1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * Copyright (c) 2006 Bernd Walter. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * driver for RealTek 8305 pseudo PHYs 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/socket.h> 46 #include <sys/bus.h> 47 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include "miidevs.h" 55 56 #include <machine/bus.h> 57 #include <pci/if_rlreg.h> 58 59 #include "miibus_if.h" 60 61 //#define RL_DEBUG 62 #define RL_VLAN 63 64 static int rlswitch_probe(device_t); 65 static int rlswitch_attach(device_t); 66 67 static device_method_t rlswitch_methods[] = { 68 /* device interface */ 69 DEVMETHOD(device_probe, rlswitch_probe), 70 DEVMETHOD(device_attach, rlswitch_attach), 71 DEVMETHOD(device_detach, mii_phy_detach), 72 DEVMETHOD(device_shutdown, bus_generic_shutdown), 73 DEVMETHOD_END 74 }; 75 76 static devclass_t rlswitch_devclass; 77 78 static driver_t rlswitch_driver = { 79 "rlswitch", 80 rlswitch_methods, 81 sizeof(struct mii_softc) 82 }; 83 84 DRIVER_MODULE(rlswitch, miibus, rlswitch_driver, rlswitch_devclass, 0, 0); 85 86 static int rlswitch_service(struct mii_softc *, struct mii_data *, int); 87 static void rlswitch_status(struct mii_softc *); 88 89 #ifdef RL_DEBUG 90 static void rlswitch_phydump(device_t dev); 91 #endif 92 93 static const struct mii_phydesc rlswitches[] = { 94 MII_PHY_DESC(REALTEK, RTL8305SC), 95 MII_PHY_END 96 }; 97 98 static const struct mii_phy_funcs rlswitch_funcs = { 99 rlswitch_service, 100 rlswitch_status, 101 mii_phy_reset 102 }; 103 104 static int 105 rlswitch_probe(device_t dev) 106 { 107 int rv; 108 109 rv = mii_phy_dev_probe(dev, rlswitches, BUS_PROBE_DEFAULT); 110 if (rv <= 0) 111 return (rv); 112 113 return (ENXIO); 114 } 115 116 static int 117 rlswitch_attach(device_t dev) 118 { 119 struct mii_softc *sc; 120 121 sc = device_get_softc(dev); 122 123 /* 124 * We handle all pseudo PHYs in a single instance. 125 */ 126 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 127 &rlswitch_funcs, 0); 128 129 sc->mii_capabilities = BMSR_100TXFDX & sc->mii_capmask; 130 device_printf(dev, " "); 131 mii_phy_add_media(sc); 132 printf("\n"); 133 #ifdef RL_DEBUG 134 rlswitch_phydump(dev); 135 #endif 136 137 #ifdef RL_VLAN 138 int val; 139 140 /* Global Control 0 */ 141 val = 0; 142 val |= 0 << 10; /* enable 802.1q VLAN Tag support */ 143 val |= 0 << 9; /* enable VLAN ingress filtering */ 144 val |= 1 << 8; /* disable VLAN tag admit control */ 145 val |= 1 << 6; /* internal use */ 146 val |= 1 << 5; /* internal use */ 147 val |= 1 << 4; /* internal use */ 148 val |= 1 << 3; /* internal use */ 149 val |= 1 << 1; /* reserved */ 150 MIIBUS_WRITEREG(sc->mii_dev, 0, 16, val); 151 152 /* Global Control 2 */ 153 val = 0; 154 val |= 1 << 15; /* reserved */ 155 val |= 0 << 14; /* enable 1552 Bytes support */ 156 val |= 1 << 13; /* enable broadcast input drop */ 157 val |= 1 << 12; /* forward reserved control frames */ 158 val |= 1 << 11; /* disable forwarding unicast frames to other VLAN's */ 159 val |= 1 << 10; /* disable forwarding ARP broadcasts to other VLAN's */ 160 val |= 1 << 9; /* enable 48 pass 1 */ 161 val |= 0 << 8; /* enable VLAN */ 162 val |= 1 << 7; /* reserved */ 163 val |= 1 << 6; /* enable defer */ 164 val |= 1 << 5; /* 43ms LED blink time */ 165 val |= 3 << 3; /* 16:1 queue weight */ 166 val |= 1 << 2; /* disable broadcast storm control */ 167 val |= 1 << 1; /* enable power-on LED blinking */ 168 val |= 1 << 0; /* reserved */ 169 MIIBUS_WRITEREG(sc->mii_dev, 0, 18, val); 170 171 /* Port 0 Control Register 0 */ 172 val = 0; 173 val |= 1 << 15; /* reserved */ 174 val |= 1 << 11; /* drop received packets with wrong VLAN tag */ 175 val |= 1 << 10; /* disable 802.1p priority classification */ 176 val |= 1 << 9; /* disable diffserv priority classification */ 177 val |= 1 << 6; /* internal use */ 178 val |= 3 << 4; /* internal use */ 179 val |= 1 << 3; /* internal use */ 180 val |= 1 << 2; /* internal use */ 181 val |= 1 << 0; /* remove VLAN tags on output */ 182 MIIBUS_WRITEREG(sc->mii_dev, 0, 22, val); 183 184 /* Port 1 Control Register 0 */ 185 val = 0; 186 val |= 1 << 15; /* reserved */ 187 val |= 1 << 11; /* drop received packets with wrong VLAN tag */ 188 val |= 1 << 10; /* disable 802.1p priority classification */ 189 val |= 1 << 9; /* disable diffserv priority classification */ 190 val |= 1 << 6; /* internal use */ 191 val |= 3 << 4; /* internal use */ 192 val |= 1 << 3; /* internal use */ 193 val |= 1 << 2; /* internal use */ 194 val |= 1 << 0; /* remove VLAN tags on output */ 195 MIIBUS_WRITEREG(sc->mii_dev, 1, 22, val); 196 197 /* Port 2 Control Register 0 */ 198 val = 0; 199 val |= 1 << 15; /* reserved */ 200 val |= 1 << 11; /* drop received packets with wrong VLAN tag */ 201 val |= 1 << 10; /* disable 802.1p priority classification */ 202 val |= 1 << 9; /* disable diffserv priority classification */ 203 val |= 1 << 6; /* internal use */ 204 val |= 3 << 4; /* internal use */ 205 val |= 1 << 3; /* internal use */ 206 val |= 1 << 2; /* internal use */ 207 val |= 1 << 0; /* remove VLAN tags on output */ 208 MIIBUS_WRITEREG(sc->mii_dev, 2, 22, val); 209 210 /* Port 3 Control Register 0 */ 211 val = 0; 212 val |= 1 << 15; /* reserved */ 213 val |= 1 << 11; /* drop received packets with wrong VLAN tag */ 214 val |= 1 << 10; /* disable 802.1p priority classification */ 215 val |= 1 << 9; /* disable diffserv priority classification */ 216 val |= 1 << 6; /* internal use */ 217 val |= 3 << 4; /* internal use */ 218 val |= 1 << 3; /* internal use */ 219 val |= 1 << 2; /* internal use */ 220 val |= 1 << 0; /* remove VLAN tags on output */ 221 MIIBUS_WRITEREG(sc->mii_dev, 3, 22, val); 222 223 /* Port 4 (system port) Control Register 0 */ 224 val = 0; 225 val |= 1 << 15; /* reserved */ 226 val |= 0 << 11; /* don't drop received packets with wrong VLAN tag */ 227 val |= 1 << 10; /* disable 802.1p priority classification */ 228 val |= 1 << 9; /* disable diffserv priority classification */ 229 val |= 1 << 6; /* internal use */ 230 val |= 3 << 4; /* internal use */ 231 val |= 1 << 3; /* internal use */ 232 val |= 1 << 2; /* internal use */ 233 val |= 2 << 0; /* add VLAN tags for untagged packets on output */ 234 MIIBUS_WRITEREG(sc->mii_dev, 4, 22, val); 235 236 /* Port 0 Control Register 1 and VLAN A */ 237 val = 0; 238 val |= 0x0 << 12; /* Port 0 VLAN Index */ 239 val |= 1 << 11; /* internal use */ 240 val |= 1 << 10; /* internal use */ 241 val |= 1 << 9; /* internal use */ 242 val |= 1 << 7; /* internal use */ 243 val |= 1 << 6; /* internal use */ 244 val |= 0x11 << 0; /* VLAN A membership */ 245 MIIBUS_WRITEREG(sc->mii_dev, 0, 24, val); 246 247 /* Port 0 Control Register 2 and VLAN A */ 248 val = 0; 249 val |= 1 << 15; /* internal use */ 250 val |= 1 << 14; /* internal use */ 251 val |= 1 << 13; /* internal use */ 252 val |= 1 << 12; /* internal use */ 253 val |= 0x100 << 0; /* VLAN A ID */ 254 MIIBUS_WRITEREG(sc->mii_dev, 0, 25, val); 255 256 /* Port 1 Control Register 1 and VLAN B */ 257 val = 0; 258 val |= 0x1 << 12; /* Port 1 VLAN Index */ 259 val |= 1 << 11; /* internal use */ 260 val |= 1 << 10; /* internal use */ 261 val |= 1 << 9; /* internal use */ 262 val |= 1 << 7; /* internal use */ 263 val |= 1 << 6; /* internal use */ 264 val |= 0x12 << 0; /* VLAN B membership */ 265 MIIBUS_WRITEREG(sc->mii_dev, 1, 24, val); 266 267 /* Port 1 Control Register 2 and VLAN B */ 268 val = 0; 269 val |= 1 << 15; /* internal use */ 270 val |= 1 << 14; /* internal use */ 271 val |= 1 << 13; /* internal use */ 272 val |= 1 << 12; /* internal use */ 273 val |= 0x101 << 0; /* VLAN B ID */ 274 MIIBUS_WRITEREG(sc->mii_dev, 1, 25, val); 275 276 /* Port 2 Control Register 1 and VLAN C */ 277 val = 0; 278 val |= 0x2 << 12; /* Port 2 VLAN Index */ 279 val |= 1 << 11; /* internal use */ 280 val |= 1 << 10; /* internal use */ 281 val |= 1 << 9; /* internal use */ 282 val |= 1 << 7; /* internal use */ 283 val |= 1 << 6; /* internal use */ 284 val |= 0x14 << 0; /* VLAN C membership */ 285 MIIBUS_WRITEREG(sc->mii_dev, 2, 24, val); 286 287 /* Port 2 Control Register 2 and VLAN C */ 288 val = 0; 289 val |= 1 << 15; /* internal use */ 290 val |= 1 << 14; /* internal use */ 291 val |= 1 << 13; /* internal use */ 292 val |= 1 << 12; /* internal use */ 293 val |= 0x102 << 0; /* VLAN C ID */ 294 MIIBUS_WRITEREG(sc->mii_dev, 2, 25, val); 295 296 /* Port 3 Control Register 1 and VLAN D */ 297 val = 0; 298 val |= 0x3 << 12; /* Port 3 VLAN Index */ 299 val |= 1 << 11; /* internal use */ 300 val |= 1 << 10; /* internal use */ 301 val |= 1 << 9; /* internal use */ 302 val |= 1 << 7; /* internal use */ 303 val |= 1 << 6; /* internal use */ 304 val |= 0x18 << 0; /* VLAN D membership */ 305 MIIBUS_WRITEREG(sc->mii_dev, 3, 24, val); 306 307 /* Port 3 Control Register 2 and VLAN D */ 308 val = 0; 309 val |= 1 << 15; /* internal use */ 310 val |= 1 << 14; /* internal use */ 311 val |= 1 << 13; /* internal use */ 312 val |= 1 << 12; /* internal use */ 313 val |= 0x103 << 0; /* VLAN D ID */ 314 MIIBUS_WRITEREG(sc->mii_dev, 3, 25, val); 315 316 /* Port 4 Control Register 1 and VLAN E */ 317 val = 0; 318 val |= 0x0 << 12; /* Port 4 VLAN Index */ 319 val |= 1 << 11; /* internal use */ 320 val |= 1 << 10; /* internal use */ 321 val |= 1 << 9; /* internal use */ 322 val |= 1 << 7; /* internal use */ 323 val |= 1 << 6; /* internal use */ 324 val |= 0 << 0; /* VLAN E membership */ 325 MIIBUS_WRITEREG(sc->mii_dev, 4, 24, val); 326 327 /* Port 4 Control Register 2 and VLAN E */ 328 val = 0; 329 val |= 1 << 15; /* internal use */ 330 val |= 1 << 14; /* internal use */ 331 val |= 1 << 13; /* internal use */ 332 val |= 1 << 12; /* internal use */ 333 val |= 0x104 << 0; /* VLAN E ID */ 334 MIIBUS_WRITEREG(sc->mii_dev, 4, 25, val); 335 #endif 336 337 #ifdef RL_DEBUG 338 rlswitch_phydump(dev); 339 #endif 340 MIIBUS_MEDIAINIT(sc->mii_dev); 341 return (0); 342 } 343 344 static int 345 rlswitch_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 346 { 347 348 switch (cmd) { 349 case MII_POLLSTAT: 350 break; 351 352 case MII_MEDIACHG: 353 break; 354 355 case MII_TICK: 356 /* 357 * Is the interface even up? 358 */ 359 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 360 return (0); 361 break; 362 } 363 364 /* Update the media status. */ 365 PHY_STATUS(sc); 366 367 /* Callback if something changed. */ 368 // mii_phy_update(sc, cmd); 369 return (0); 370 } 371 372 static void 373 rlswitch_status(struct mii_softc *phy) 374 { 375 struct mii_data *mii = phy->mii_pdata; 376 377 mii->mii_media_status = IFM_AVALID; 378 mii->mii_media_active = IFM_ETHER; 379 mii->mii_media_status |= IFM_ACTIVE; 380 mii->mii_media_active |= 381 IFM_100_TX | IFM_FDX | mii_phy_flowstatus(phy); 382 } 383 384 #ifdef RL_DEBUG 385 static void 386 rlswitch_phydump(device_t dev) { 387 int phy, reg, val; 388 struct mii_softc *sc; 389 390 sc = device_get_softc(dev); 391 device_printf(dev, "rlswitchphydump\n"); 392 for (phy = 0; phy <= 5; phy++) { 393 printf("PHY%i:", phy); 394 for (reg = 0; reg <= 31; reg++) { 395 val = MIIBUS_READREG(sc->mii_dev, phy, reg); 396 printf(" 0x%x", val); 397 } 398 printf("\n"); 399 } 400 } 401 #endif 402