1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008, 2014 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <dev/mlx4/cmd.h> 35 #include <dev/mlx4/srq.h> 36 #include <linux/module.h> 37 #include <linux/gfp.h> 38 39 #include "mlx4.h" 40 #include "icm.h" 41 42 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type) 43 { 44 struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; 45 struct mlx4_srq *srq; 46 47 spin_lock(&srq_table->lock); 48 49 srq = radix_tree_lookup(&srq_table->tree, srqn & (dev->caps.num_srqs - 1)); 50 if (srq) 51 atomic_inc(&srq->refcount); 52 53 spin_unlock(&srq_table->lock); 54 55 if (!srq) { 56 mlx4_warn(dev, "Async event for bogus SRQ %08x\n", srqn); 57 return; 58 } 59 60 srq->event(srq, event_type); 61 62 if (atomic_dec_and_test(&srq->refcount)) 63 complete(&srq->free); 64 } 65 66 static int mlx4_SW2HW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 67 int srq_num) 68 { 69 return mlx4_cmd(dev, mailbox->dma, srq_num, 0, 70 MLX4_CMD_SW2HW_SRQ, MLX4_CMD_TIME_CLASS_A, 71 MLX4_CMD_WRAPPED); 72 } 73 74 static int mlx4_HW2SW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 75 int srq_num) 76 { 77 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, srq_num, 78 mailbox ? 0 : 1, MLX4_CMD_HW2SW_SRQ, 79 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 80 } 81 82 static int mlx4_ARM_SRQ(struct mlx4_dev *dev, int srq_num, int limit_watermark) 83 { 84 return mlx4_cmd(dev, limit_watermark, srq_num, 0, MLX4_CMD_ARM_SRQ, 85 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); 86 } 87 88 static int mlx4_QUERY_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 89 int srq_num) 90 { 91 return mlx4_cmd_box(dev, 0, mailbox->dma, srq_num, 0, MLX4_CMD_QUERY_SRQ, 92 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 93 } 94 95 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn) 96 { 97 struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; 98 int err; 99 100 101 *srqn = mlx4_bitmap_alloc(&srq_table->bitmap); 102 if (*srqn == -1) 103 return -ENOMEM; 104 105 err = mlx4_table_get(dev, &srq_table->table, *srqn); 106 if (err) 107 goto err_out; 108 109 err = mlx4_table_get(dev, &srq_table->cmpt_table, *srqn); 110 if (err) 111 goto err_put; 112 return 0; 113 114 err_put: 115 mlx4_table_put(dev, &srq_table->table, *srqn); 116 117 err_out: 118 mlx4_bitmap_free(&srq_table->bitmap, *srqn, MLX4_NO_RR); 119 return err; 120 } 121 122 static int mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn) 123 { 124 u64 out_param; 125 int err; 126 127 if (mlx4_is_mfunc(dev)) { 128 err = mlx4_cmd_imm(dev, 0, &out_param, RES_SRQ, 129 RES_OP_RESERVE_AND_MAP, 130 MLX4_CMD_ALLOC_RES, 131 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 132 if (!err) 133 *srqn = get_param_l(&out_param); 134 135 return err; 136 } 137 return __mlx4_srq_alloc_icm(dev, srqn); 138 } 139 140 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn) 141 { 142 struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; 143 144 mlx4_table_put(dev, &srq_table->cmpt_table, srqn); 145 mlx4_table_put(dev, &srq_table->table, srqn); 146 mlx4_bitmap_free(&srq_table->bitmap, srqn, MLX4_NO_RR); 147 } 148 149 static void mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn) 150 { 151 u64 in_param = 0; 152 153 if (mlx4_is_mfunc(dev)) { 154 set_param_l(&in_param, srqn); 155 if (mlx4_cmd(dev, in_param, RES_SRQ, RES_OP_RESERVE_AND_MAP, 156 MLX4_CMD_FREE_RES, 157 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED)) 158 mlx4_warn(dev, "Failed freeing cq:%d\n", srqn); 159 return; 160 } 161 __mlx4_srq_free_icm(dev, srqn); 162 } 163 164 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcd, 165 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq) 166 { 167 struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; 168 struct mlx4_cmd_mailbox *mailbox; 169 struct mlx4_srq_context *srq_context; 170 u64 mtt_addr; 171 int err; 172 173 err = mlx4_srq_alloc_icm(dev, &srq->srqn); 174 if (err) 175 return err; 176 177 spin_lock_irq(&srq_table->lock); 178 err = radix_tree_insert(&srq_table->tree, srq->srqn, srq); 179 spin_unlock_irq(&srq_table->lock); 180 if (err) 181 goto err_icm; 182 183 mailbox = mlx4_alloc_cmd_mailbox(dev); 184 if (IS_ERR(mailbox)) { 185 err = PTR_ERR(mailbox); 186 goto err_radix; 187 } 188 189 srq_context = mailbox->buf; 190 memset(srq_context, 0, sizeof *srq_context); 191 192 srq_context->state_logsize_srqn = cpu_to_be32((ilog2(srq->max) << 24) | 193 srq->srqn); 194 srq_context->logstride = srq->wqe_shift - 4; 195 srq_context->xrcd = cpu_to_be16(xrcd); 196 srq_context->pg_offset_cqn = cpu_to_be32(cqn & 0xffffff); 197 srq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT; 198 199 mtt_addr = mlx4_mtt_addr(dev, mtt); 200 srq_context->mtt_base_addr_h = mtt_addr >> 32; 201 srq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 202 srq_context->pd = cpu_to_be32(pdn); 203 srq_context->db_rec_addr = cpu_to_be64(db_rec); 204 205 err = mlx4_SW2HW_SRQ(dev, mailbox, srq->srqn); 206 mlx4_free_cmd_mailbox(dev, mailbox); 207 if (err) 208 goto err_radix; 209 210 atomic_set(&srq->refcount, 1); 211 init_completion(&srq->free); 212 213 return 0; 214 215 err_radix: 216 spin_lock_irq(&srq_table->lock); 217 radix_tree_delete(&srq_table->tree, srq->srqn); 218 spin_unlock_irq(&srq_table->lock); 219 220 err_icm: 221 mlx4_srq_free_icm(dev, srq->srqn); 222 return err; 223 } 224 EXPORT_SYMBOL_GPL(mlx4_srq_alloc); 225 226 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq) 227 { 228 struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; 229 int err; 230 231 err = mlx4_HW2SW_SRQ(dev, NULL, srq->srqn); 232 if (err) 233 mlx4_warn(dev, "HW2SW_SRQ failed (%d) for SRQN %06x\n", err, srq->srqn); 234 235 spin_lock_irq(&srq_table->lock); 236 radix_tree_delete(&srq_table->tree, srq->srqn); 237 spin_unlock_irq(&srq_table->lock); 238 239 if (atomic_dec_and_test(&srq->refcount)) 240 complete(&srq->free); 241 wait_for_completion(&srq->free); 242 243 mlx4_srq_free_icm(dev, srq->srqn); 244 } 245 EXPORT_SYMBOL_GPL(mlx4_srq_free); 246 247 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark) 248 { 249 return mlx4_ARM_SRQ(dev, srq->srqn, limit_watermark); 250 } 251 EXPORT_SYMBOL_GPL(mlx4_srq_arm); 252 253 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark) 254 { 255 struct mlx4_cmd_mailbox *mailbox; 256 struct mlx4_srq_context *srq_context; 257 int err; 258 259 mailbox = mlx4_alloc_cmd_mailbox(dev); 260 if (IS_ERR(mailbox)) 261 return PTR_ERR(mailbox); 262 263 srq_context = mailbox->buf; 264 265 err = mlx4_QUERY_SRQ(dev, mailbox, srq->srqn); 266 if (err) 267 goto err_out; 268 *limit_watermark = be16_to_cpu(srq_context->limit_watermark); 269 270 err_out: 271 mlx4_free_cmd_mailbox(dev, mailbox); 272 return err; 273 } 274 EXPORT_SYMBOL_GPL(mlx4_srq_query); 275 276 int mlx4_init_srq_table(struct mlx4_dev *dev) 277 { 278 struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; 279 int err; 280 281 spin_lock_init(&srq_table->lock); 282 INIT_RADIX_TREE(&srq_table->tree, GFP_ATOMIC); 283 if (mlx4_is_slave(dev)) 284 return 0; 285 286 err = mlx4_bitmap_init(&srq_table->bitmap, dev->caps.num_srqs, 287 dev->caps.num_srqs - 1, dev->caps.reserved_srqs, 0); 288 if (err) 289 return err; 290 291 return 0; 292 } 293 294 void mlx4_cleanup_srq_table(struct mlx4_dev *dev) 295 { 296 if (mlx4_is_slave(dev)) 297 return; 298 mlx4_bitmap_cleanup(&mlx4_priv(dev)->srq_table.bitmap); 299 } 300 301 struct mlx4_srq *mlx4_srq_lookup(struct mlx4_dev *dev, u32 srqn) 302 { 303 struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; 304 struct mlx4_srq *srq; 305 unsigned long flags; 306 307 spin_lock_irqsave(&srq_table->lock, flags); 308 srq = radix_tree_lookup(&srq_table->tree, 309 srqn & (dev->caps.num_srqs - 1)); 310 spin_unlock_irqrestore(&srq_table->lock, flags); 311 312 return srq; 313 } 314 EXPORT_SYMBOL_GPL(mlx4_srq_lookup); 315