1 /* 2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/kobject.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_vlan.h> 44 #include <linux/if_ether.h> 45 #ifdef CONFIG_MLX4_EN_DCB 46 #include <linux/dcbnl.h> 47 #endif 48 49 #include <dev/mlx4/device.h> 50 #include <dev/mlx4/qp.h> 51 #include <dev/mlx4/cq.h> 52 #include <dev/mlx4/srq.h> 53 #include <dev/mlx4/doorbell.h> 54 #include <dev/mlx4/cmd.h> 55 56 #include <net/debugnet.h> 57 #include <netinet/tcp_lro.h> 58 59 #include "en_port.h" 60 #include <dev/mlx4/stats.h> 61 62 #define DRV_NAME "mlx4_en" 63 64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 65 66 /* 67 * Device constants 68 */ 69 70 71 #define MLX4_EN_PAGE_SHIFT 12 72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 73 #define MLX4_NET_IP_ALIGN 2 /* bytes */ 74 #define DEF_RX_RINGS 16 75 #define MAX_RX_RINGS 128 76 #define MIN_RX_RINGS 4 77 #define TXBB_SIZE 64 78 79 #ifndef MLX4_EN_MAX_RX_SEGS 80 #define MLX4_EN_MAX_RX_SEGS 1 /* or 8 */ 81 #endif 82 83 #ifndef MLX4_EN_MAX_RX_BYTES 84 #define MLX4_EN_MAX_RX_BYTES MCLBYTES 85 #endif 86 87 #define HEADROOM (2048 / TXBB_SIZE + 1) 88 #define INIT_OWNER_BIT 0xffffffff 89 #define STAMP_STRIDE 64 90 #define STAMP_DWORDS (STAMP_STRIDE / 4) 91 #define STAMP_SHIFT 31 92 #define STAMP_VAL 0x7fffffff 93 #define STATS_DELAY (HZ / 4) 94 #define SERVICE_TASK_DELAY (HZ / 4) 95 #define MAX_NUM_OF_FS_RULES 256 96 97 #define MLX4_EN_FILTER_HASH_SHIFT 4 98 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 99 100 #ifdef CONFIG_NET_RX_BUSY_POLL 101 #define LL_EXTENDED_STATS 102 #endif 103 104 /* vlan valid range */ 105 #define VLAN_MIN_VALUE 1 106 #define VLAN_MAX_VALUE 4094 107 108 /* 109 * OS related constants and tunables 110 */ 111 112 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 113 114 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(PAGE_SIZE) 115 #define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE) 116 117 enum mlx4_en_alloc_type { 118 MLX4_EN_ALLOC_NEW = 0, 119 MLX4_EN_ALLOC_REPLACEMENT = 1, 120 }; 121 122 /* Maximum ring sizes */ 123 #define MLX4_EN_DEF_TX_QUEUE_SIZE 4096 124 125 /* Minimum packet number till arming the CQ */ 126 #define MLX4_EN_MIN_RX_ARM 2048 127 #define MLX4_EN_MIN_TX_ARM 2048 128 129 /* Maximum ring sizes */ 130 #define MLX4_EN_MAX_TX_SIZE 8192 131 #define MLX4_EN_MAX_RX_SIZE 8192 132 133 /* Minimum ring sizes */ 134 #define MLX4_EN_MIN_RX_SIZE (4096 / TXBB_SIZE) 135 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 136 137 #define MLX4_EN_SMALL_PKT_SIZE 64 138 139 #define MLX4_EN_MAX_TX_RING_P_UP 32 140 #define MLX4_EN_NUM_UP 1 141 142 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 143 MLX4_EN_NUM_UP) 144 145 #define MLX4_EN_NO_VLAN 0xffff 146 147 #define MLX4_EN_DEF_TX_RING_SIZE 1024 148 #define MLX4_EN_DEF_RX_RING_SIZE 1024 149 150 /* Target number of bytes to coalesce with interrupt moderation */ 151 #define MLX4_EN_RX_COAL_TARGET 44 152 #define MLX4_EN_RX_COAL_TIME 0x10 153 154 #define MLX4_EN_TX_COAL_PKTS 64 155 #define MLX4_EN_TX_COAL_TIME 64 156 157 #define MLX4_EN_RX_RATE_LOW 400000 158 #define MLX4_EN_RX_COAL_TIME_LOW 0 159 #define MLX4_EN_RX_RATE_HIGH 450000 160 #define MLX4_EN_RX_COAL_TIME_HIGH 128 161 #define MLX4_EN_RX_SIZE_THRESH 1024 162 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 163 #define MLX4_EN_SAMPLE_INTERVAL 0 164 #define MLX4_EN_AVG_PKT_SMALL 256 165 166 #define MLX4_EN_AUTO_CONF 0xffff 167 168 #define MLX4_EN_DEF_RX_PAUSE 1 169 #define MLX4_EN_DEF_TX_PAUSE 1 170 171 /* Interval between successive polls in the Tx routine when polling is used 172 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 173 #define MLX4_EN_TX_POLL_MODER 16 174 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 175 176 #define MLX4_EN_64_ALIGN (64 - NET_SKB_PAD) 177 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 178 #define HEADER_COPY_SIZE (128) 179 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN) 180 181 #define MLX4_EN_MIN_MTU 46 182 #define ETH_BCAST 0xffffffffffffULL 183 184 #define MLX4_EN_LOOPBACK_RETRIES 5 185 #define MLX4_EN_LOOPBACK_TIMEOUT 100 186 187 #ifdef MLX4_EN_PERF_STAT 188 /* Number of samples to 'average' */ 189 #define AVG_SIZE 128 190 #define AVG_FACTOR 1024 191 192 #define INC_PERF_COUNTER(cnt) (++(cnt)) 193 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 194 #define AVG_PERF_COUNTER(cnt, sample) \ 195 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 196 #define GET_PERF_COUNTER(cnt) (cnt) 197 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 198 199 #else 200 201 #define INC_PERF_COUNTER(cnt) do {} while (0) 202 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 203 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 204 #define GET_PERF_COUNTER(cnt) (0) 205 #define GET_AVG_PERF_COUNTER(cnt) (0) 206 #endif /* MLX4_EN_PERF_STAT */ 207 208 /* Constants for TX flow */ 209 enum { 210 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 211 MAX_BF = 256, 212 MIN_PKT_LEN = 17, 213 }; 214 215 /* 216 * Configurables 217 */ 218 219 enum cq_type { 220 RX = 0, 221 TX = 1, 222 }; 223 224 225 /* 226 * Useful macros 227 */ 228 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 229 #define XNOR(x, y) (!(x) == !(y)) 230 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0) 231 232 struct mlx4_en_tx_info { 233 bus_dmamap_t dma_map; 234 struct mbuf *mb; 235 u32 nr_txbb; 236 u32 nr_bytes; 237 }; 238 239 240 #define MLX4_EN_BIT_DESC_OWN 0x80000000 241 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 242 #define MLX4_EN_MEMTYPE_PAD 0x100 243 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 244 245 246 struct mlx4_en_tx_desc { 247 struct mlx4_wqe_ctrl_seg ctrl; 248 union { 249 struct mlx4_wqe_data_seg data; /* at least one data segment */ 250 struct mlx4_wqe_lso_seg lso; 251 struct mlx4_wqe_inline_seg inl; 252 }; 253 }; 254 255 #define MLX4_EN_USE_SRQ 0x01000000 256 257 #define MLX4_EN_RX_BUDGET 64 258 259 #define MLX4_EN_TX_MAX_DESC_SIZE 512 /* bytes */ 260 #define MLX4_EN_TX_MAX_MBUF_SIZE 65536 /* bytes */ 261 #define MLX4_EN_TX_MAX_PAYLOAD_SIZE 65536 /* bytes */ 262 #define MLX4_EN_TX_MAX_MBUF_FRAGS \ 263 ((MLX4_EN_TX_MAX_DESC_SIZE - 128) / DS_SIZE_ALIGNMENT) /* units */ 264 #define MLX4_EN_TX_WQE_MAX_WQEBBS \ 265 (MLX4_EN_TX_MAX_DESC_SIZE / TXBB_SIZE) /* units */ 266 267 #define MLX4_EN_CX3_LOW_ID 0x1000 268 #define MLX4_EN_CX3_HIGH_ID 0x1005 269 270 struct mlx4_en_tx_ring { 271 spinlock_t tx_lock; 272 bus_dma_tag_t dma_tag; 273 struct mlx4_hwq_resources wqres; 274 u32 size ; /* number of TXBBs */ 275 u32 size_mask; 276 u16 stride; 277 u16 cqn; /* index of port CQ associated with this ring */ 278 u32 prod; 279 u32 cons; 280 u32 buf_size; 281 u32 doorbell_qpn; 282 u8 *buf; 283 u16 poll_cnt; 284 struct mlx4_en_tx_info *tx_info; 285 u8 queue_index; 286 u32 last_nr_txbb; 287 struct mlx4_qp qp; 288 struct mlx4_qp_context context; 289 int qpn; 290 enum mlx4_qp_state qp_state; 291 struct mlx4_srq dummy; 292 u64 bytes; 293 u64 packets; 294 u64 tx_csum; 295 u64 queue_stopped; 296 u64 oversized_packets; 297 u64 wake_queue; 298 u64 tso_packets; 299 u64 defrag_attempts; 300 struct mlx4_bf bf; 301 bool bf_enabled; 302 int hwtstamp_tx_type; 303 spinlock_t comp_lock; 304 int inline_thold; 305 u64 watchdog_time; 306 }; 307 308 struct mlx4_en_rx_desc { 309 struct mlx4_wqe_data_seg data[MLX4_EN_MAX_RX_SEGS]; 310 }; 311 312 /* the size of the structure above must be power of two */ 313 CTASSERT(powerof2(sizeof(struct mlx4_en_rx_desc))); 314 315 struct mlx4_en_rx_mbuf { 316 bus_dmamap_t dma_map; 317 struct mbuf *mbuf; 318 }; 319 320 struct mlx4_en_rx_spare { 321 bus_dmamap_t dma_map; 322 struct mbuf *mbuf; 323 bus_dma_segment_t segs[MLX4_EN_MAX_RX_SEGS]; 324 }; 325 326 struct mlx4_en_rx_ring { 327 struct mlx4_hwq_resources wqres; 328 bus_dma_tag_t dma_tag; 329 struct mlx4_en_rx_spare spare; 330 u32 size ; /* number of Rx descs*/ 331 u32 actual_size; 332 u32 size_mask; 333 u16 log_stride; 334 u16 cqn; /* index of port CQ associated with this ring */ 335 u32 prod; 336 u32 cons; 337 u32 buf_size; 338 u8 fcs_del; 339 u32 rx_mb_size; 340 u32 rx_mr_key_be; 341 int qpn; 342 u8 *buf; 343 struct mlx4_en_rx_mbuf *mbuf; 344 u64 errors; 345 u64 bytes; 346 u64 packets; 347 #ifdef LL_EXTENDED_STATS 348 u64 yields; 349 u64 misses; 350 u64 cleaned; 351 #endif 352 u64 csum_ok; 353 u64 csum_none; 354 int hwtstamp_rx_filter; 355 int numa_node; 356 struct lro_ctrl lro; 357 }; 358 359 static inline int mlx4_en_can_lro(__be16 status) 360 { 361 const __be16 status_all = cpu_to_be16( 362 MLX4_CQE_STATUS_IPV4 | 363 MLX4_CQE_STATUS_IPV4F | 364 MLX4_CQE_STATUS_IPV6 | 365 MLX4_CQE_STATUS_IPV4OPT | 366 MLX4_CQE_STATUS_TCP | 367 MLX4_CQE_STATUS_UDP | 368 MLX4_CQE_STATUS_IPOK); 369 const __be16 status_ipv4_ipok_tcp = cpu_to_be16( 370 MLX4_CQE_STATUS_IPV4 | 371 MLX4_CQE_STATUS_IPOK | 372 MLX4_CQE_STATUS_TCP); 373 const __be16 status_ipv6_ipok_tcp = cpu_to_be16( 374 MLX4_CQE_STATUS_IPV6 | 375 MLX4_CQE_STATUS_IPOK | 376 MLX4_CQE_STATUS_TCP); 377 378 status &= status_all; 379 return (status == status_ipv4_ipok_tcp || 380 status == status_ipv6_ipok_tcp); 381 } 382 383 struct mlx4_en_cq { 384 struct mlx4_cq mcq; 385 struct mlx4_hwq_resources wqres; 386 int ring; 387 spinlock_t lock; 388 struct net_device *dev; 389 /* Per-core Tx cq processing support */ 390 struct timer_list timer; 391 int size; 392 int buf_size; 393 unsigned vector; 394 enum cq_type is_tx; 395 u16 moder_time; 396 u16 moder_cnt; 397 struct mlx4_cqe *buf; 398 struct task cq_task; 399 struct taskqueue *tq; 400 #define MLX4_EN_OPCODE_ERROR 0x1e 401 u32 tot_rx; 402 u32 tot_tx; 403 u32 curr_poll_rx_cpu_id; 404 405 #ifdef CONFIG_NET_RX_BUSY_POLL 406 unsigned int state; 407 #define MLX4_EN_CQ_STATE_IDLE 0 408 #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */ 409 #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */ 410 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL) 411 #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */ 412 #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */ 413 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD) 414 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD) 415 spinlock_t poll_lock; /* protects from LLS/napi conflicts */ 416 #endif /* CONFIG_NET_RX_BUSY_POLL */ 417 }; 418 419 struct mlx4_en_port_profile { 420 u32 flags; 421 u32 tx_ring_num; 422 u32 rx_ring_num; 423 u32 tx_ring_size; 424 u32 rx_ring_size; 425 u8 rx_pause; 426 u8 rx_ppp; 427 u8 tx_pause; 428 u8 tx_ppp; 429 int rss_rings; 430 int inline_thold; 431 }; 432 433 struct mlx4_en_profile { 434 int rss_xor; 435 int udp_rss; 436 u8 rss_mask; 437 u32 active_ports; 438 u32 small_pkt_int; 439 u8 no_reset; 440 u8 num_tx_rings_p_up; 441 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 442 }; 443 444 struct mlx4_en_dev { 445 struct mlx4_dev *dev; 446 struct pci_dev *pdev; 447 struct mutex state_lock; 448 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 449 u32 port_cnt; 450 bool device_up; 451 struct mlx4_en_profile profile; 452 u32 LSO_support; 453 struct workqueue_struct *workqueue; 454 struct device *dma_device; 455 void __iomem *uar_map; 456 struct mlx4_uar priv_uar; 457 struct mlx4_mr mr; 458 u32 priv_pdn; 459 spinlock_t uar_lock; 460 u8 mac_removed[MLX4_MAX_PORTS + 1]; 461 unsigned long last_overflow_check; 462 unsigned long overflow_period; 463 }; 464 465 466 struct mlx4_en_rss_map { 467 int base_qpn; 468 struct mlx4_qp qps[MAX_RX_RINGS]; 469 enum mlx4_qp_state state[MAX_RX_RINGS]; 470 struct mlx4_qp indir_qp; 471 enum mlx4_qp_state indir_state; 472 }; 473 474 enum mlx4_en_port_flag { 475 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */ 476 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */ 477 }; 478 479 struct mlx4_en_port_state { 480 int link_state; 481 int link_speed; 482 int transceiver; 483 u32 flags; 484 }; 485 486 enum mlx4_en_addr_list_act { 487 MLX4_ADDR_LIST_NONE, 488 MLX4_ADDR_LIST_REM, 489 MLX4_ADDR_LIST_ADD, 490 }; 491 492 struct mlx4_en_addr_list { 493 struct list_head list; 494 enum mlx4_en_addr_list_act action; 495 u8 addr[ETH_ALEN]; 496 u64 reg_id; 497 u64 tunnel_reg_id; 498 }; 499 500 #ifdef CONFIG_MLX4_EN_DCB 501 /* Minimal TC BW - setting to 0 will block traffic */ 502 #define MLX4_EN_BW_MIN 1 503 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 504 505 #define MLX4_EN_TC_VENDOR 0 506 #define MLX4_EN_TC_ETS 7 507 508 #endif 509 510 511 enum { 512 MLX4_EN_FLAG_PROMISC = (1 << 0), 513 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 514 /* whether we need to enable hardware loopback by putting dmac 515 * in Tx WQE 516 */ 517 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 518 /* whether we need to drop packets that hardware loopback-ed */ 519 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 520 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 521 #ifdef CONFIG_MLX4_EN_DCB 522 MLX4_EN_FLAG_DCB_ENABLED = (1 << 5) 523 #endif 524 }; 525 526 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 527 #define MLX4_EN_MAC_HASH_IDX 5 528 529 struct en_port { 530 struct kobject kobj; 531 struct mlx4_dev *dev; 532 u8 port_num; 533 u8 vport_num; 534 }; 535 536 struct mlx4_en_priv { 537 struct mlx4_en_dev *mdev; 538 struct mlx4_en_port_profile *prof; 539 struct net_device *dev; 540 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 541 struct mlx4_en_port_state port_state; 542 spinlock_t stats_lock; 543 /* To allow rules removal while port is going down */ 544 struct list_head ethtool_list; 545 546 unsigned long last_moder_packets[MAX_RX_RINGS]; 547 unsigned long last_moder_tx_packets; 548 unsigned long last_moder_bytes[MAX_RX_RINGS]; 549 unsigned long last_moder_jiffies; 550 int last_moder_time[MAX_RX_RINGS]; 551 u16 rx_usecs; 552 u16 rx_frames; 553 u16 tx_usecs; 554 u16 tx_frames; 555 u32 pkt_rate_low; 556 u32 rx_usecs_low; 557 u32 pkt_rate_high; 558 u32 rx_usecs_high; 559 u32 sample_interval; 560 u32 adaptive_rx_coal; 561 u32 msg_enable; 562 u32 loopback_ok; 563 u32 validate_loopback; 564 565 struct mlx4_hwq_resources res; 566 int link_state; 567 int last_link_state; 568 bool port_up; 569 int port; 570 int registered; 571 int gone; 572 int allocated; 573 unsigned char current_mac[ETH_ALEN + 2]; 574 u64 mac; 575 int mac_index; 576 unsigned max_mtu; 577 int base_qpn; 578 int cqe_factor; 579 580 struct mlx4_en_rss_map rss_map; 581 u32 flags; 582 u8 num_tx_rings_p_up; 583 u32 tx_ring_num; 584 u32 rx_ring_num; 585 u32 rx_mb_size; 586 587 struct mlx4_en_tx_ring **tx_ring; 588 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 589 struct mlx4_en_cq **tx_cq; 590 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 591 struct mlx4_qp drop_qp; 592 struct work_struct rx_mode_task; 593 struct work_struct watchdog_task; 594 struct work_struct linkstate_task; 595 struct delayed_work stats_task; 596 struct delayed_work service_task; 597 struct mlx4_en_perf_stats pstats; 598 struct mlx4_en_pkt_stats pkstats; 599 struct mlx4_en_pkt_stats pkstats_last; 600 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES]; 601 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES]; 602 struct mlx4_en_flow_stats_rx rx_flowstats; 603 struct mlx4_en_flow_stats_tx tx_flowstats; 604 struct mlx4_en_port_stats port_stats; 605 struct mlx4_en_vport_stats vport_stats; 606 struct mlx4_en_vf_stats vf_stats; 607 struct list_head mc_list; 608 struct list_head uc_list; 609 struct list_head curr_mc_list; 610 struct list_head curr_uc_list; 611 u64 broadcast_id; 612 struct mlx4_en_stat_out_mbox hw_stats; 613 int vids[128]; 614 bool wol; 615 struct device *ddev; 616 struct dentry *dev_root; 617 u32 counter_index; 618 eventhandler_tag vlan_attach; 619 eventhandler_tag vlan_detach; 620 struct callout watchdog_timer; 621 struct ifmedia media; 622 volatile int blocked; 623 struct sysctl_oid *conf_sysctl; 624 struct sysctl_oid *stat_sysctl; 625 struct sysctl_ctx_list conf_ctx; 626 struct sysctl_ctx_list stat_ctx; 627 628 #ifdef CONFIG_MLX4_EN_DCB 629 struct ieee_ets ets; 630 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 631 u8 dcbx_cap; 632 #endif 633 #ifdef CONFIG_RFS_ACCEL 634 spinlock_t filters_lock; 635 int last_filter_id; 636 struct list_head filters; 637 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 638 #endif 639 u64 tunnel_reg_id; 640 struct en_port *vf_ports[MLX4_MAX_NUM_VF]; 641 unsigned long last_ifq_jiffies; 642 u64 if_counters_rx_errors; 643 u64 if_counters_rx_no_buffer; 644 }; 645 646 enum mlx4_en_wol { 647 MLX4_EN_WOL_MAGIC = (1ULL << 61), 648 MLX4_EN_WOL_ENABLED = (1ULL << 62), 649 }; 650 651 struct mlx4_mac_entry { 652 struct hlist_node hlist; 653 unsigned char mac[ETH_ALEN + 2]; 654 u64 reg_id; 655 }; 656 657 static inline void * 658 netdev_priv(const struct net_device *dev) 659 { 660 return (dev->if_softc); 661 } 662 663 static inline struct mlx4_cqe *mlx4_en_get_cqe(u8 *buf, int idx, int cqe_sz) 664 { 665 return (struct mlx4_cqe *)(buf + idx * cqe_sz); 666 } 667 668 #ifdef CONFIG_NET_RX_BUSY_POLL 669 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 670 { 671 spin_lock_init(&cq->poll_lock); 672 cq->state = MLX4_EN_CQ_STATE_IDLE; 673 } 674 675 /* called from the device poll rutine to get ownership of a cq */ 676 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 677 { 678 int rc = true; 679 spin_lock(&cq->poll_lock); 680 if (cq->state & MLX4_CQ_LOCKED) { 681 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI); 682 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD; 683 rc = false; 684 } else 685 /* we don't care if someone yielded */ 686 cq->state = MLX4_EN_CQ_STATE_NAPI; 687 spin_unlock(&cq->poll_lock); 688 return rc; 689 } 690 691 /* returns true is someone tried to get the cq while napi had it */ 692 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 693 { 694 int rc = false; 695 spin_lock(&cq->poll_lock); 696 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL | 697 MLX4_EN_CQ_STATE_NAPI_YIELD)); 698 699 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) 700 rc = true; 701 cq->state = MLX4_EN_CQ_STATE_IDLE; 702 spin_unlock(&cq->poll_lock); 703 return rc; 704 } 705 706 /* called from mlx4_en_low_latency_poll() */ 707 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 708 { 709 int rc = true; 710 spin_lock_bh(&cq->poll_lock); 711 if ((cq->state & MLX4_CQ_LOCKED)) { 712 struct net_device *dev = cq->dev; 713 struct mlx4_en_priv *priv = netdev_priv(dev); 714 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; 715 716 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD; 717 rc = false; 718 #ifdef LL_EXTENDED_STATS 719 rx_ring->yields++; 720 #endif 721 } else 722 /* preserve yield marks */ 723 cq->state |= MLX4_EN_CQ_STATE_POLL; 724 spin_unlock_bh(&cq->poll_lock); 725 return rc; 726 } 727 728 /* returns true if someone tried to get the cq while it was locked */ 729 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 730 { 731 int rc = false; 732 spin_lock_bh(&cq->poll_lock); 733 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI)); 734 735 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) 736 rc = true; 737 cq->state = MLX4_EN_CQ_STATE_IDLE; 738 spin_unlock_bh(&cq->poll_lock); 739 return rc; 740 } 741 742 /* true if a socket is polling, even if it did not get the lock */ 743 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) 744 { 745 WARN_ON(!(cq->state & MLX4_CQ_LOCKED)); 746 return cq->state & CQ_USER_PEND; 747 } 748 #else 749 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 750 { 751 } 752 753 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 754 { 755 return true; 756 } 757 758 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 759 { 760 return false; 761 } 762 763 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 764 { 765 return false; 766 } 767 768 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 769 { 770 return false; 771 } 772 773 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) 774 { 775 return false; 776 } 777 #endif /* CONFIG_NET_RX_BUSY_POLL */ 778 779 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 780 781 void mlx4_en_destroy_netdev(struct net_device *dev); 782 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 783 struct mlx4_en_port_profile *prof); 784 785 int mlx4_en_start_port(struct net_device *dev); 786 void mlx4_en_stop_port(struct net_device *dev); 787 788 void mlx4_en_free_resources(struct mlx4_en_priv *priv); 789 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 790 791 int mlx4_en_pre_config(struct mlx4_en_priv *priv); 792 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 793 int entries, int ring, enum cq_type mode, int node); 794 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 795 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 796 int cq_idx); 797 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 798 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 799 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 800 801 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 802 u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb); 803 804 int mlx4_en_xmit(struct mlx4_en_priv *priv, int tx_ind, struct mbuf **mbp); 805 int mlx4_en_transmit(struct ifnet *dev, struct mbuf *m); 806 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 807 struct mlx4_en_tx_ring **pring, 808 u32 size, u16 stride, int node, int queue_idx); 809 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 810 struct mlx4_en_tx_ring **pring); 811 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 812 struct mlx4_en_tx_ring *ring, 813 int cq, int user_prio); 814 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 815 struct mlx4_en_tx_ring *ring); 816 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 817 void mlx4_en_qflush(struct ifnet *dev); 818 819 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 820 struct mlx4_en_rx_ring **pring, 821 u32 size, int node); 822 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 823 struct mlx4_en_rx_ring **pring, 824 u32 size); 825 void mlx4_en_rx_que(void *context, int pending); 826 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 827 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 828 struct mlx4_en_rx_ring *ring); 829 int mlx4_en_process_rx_cq(struct net_device *dev, 830 struct mlx4_en_cq *cq, 831 int budget); 832 void mlx4_en_poll_tx_cq(unsigned long data); 833 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 834 int is_tx, int rss, int qpn, int cqn, int user_prio, 835 struct mlx4_qp_context *context); 836 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 837 int mlx4_en_map_buffer(struct mlx4_buf *buf); 838 void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 839 void mlx4_en_calc_rx_buf(struct net_device *dev); 840 841 const u32 *mlx4_en_get_rss_key(struct mlx4_en_priv *priv, u16 *keylen); 842 u8 mlx4_en_get_rss_mask(struct mlx4_en_priv *priv); 843 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 844 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 845 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 846 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 847 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 848 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 849 850 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 851 852 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 853 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 854 int mlx4_en_get_vport_stats(struct mlx4_en_dev *mdev, u8 port); 855 void mlx4_en_create_debug_files(struct mlx4_en_priv *priv); 856 void mlx4_en_delete_debug_files(struct mlx4_en_priv *priv); 857 int mlx4_en_register_debugfs(void); 858 void mlx4_en_unregister_debugfs(void); 859 860 #ifdef CONFIG_MLX4_EN_DCB 861 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 862 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 863 #endif 864 865 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 866 867 #ifdef CONFIG_RFS_ACCEL 868 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv, 869 struct mlx4_en_rx_ring *rx_ring); 870 #endif 871 872 #define MLX4_EN_NUM_SELF_TEST 5 873 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 874 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 875 876 /* 877 * Functions for time stamping 878 */ 879 #define SKBTX_HW_TSTAMP (1 << 0) 880 #define SKBTX_IN_PROGRESS (1 << 2) 881 882 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 883 884 /* Functions for caching and restoring statistics */ 885 int mlx4_en_get_sset_count(struct net_device *dev, int sset); 886 void mlx4_en_restore_ethtool_stats(struct mlx4_en_priv *priv, 887 u64 *data); 888 889 /* 890 * Globals 891 */ 892 extern const struct ethtool_ops mlx4_en_ethtool_ops; 893 894 /* 895 * Defines for link speed - needed by selftest 896 */ 897 #define MLX4_EN_LINK_SPEED_1G 1000 898 #define MLX4_EN_LINK_SPEED_10G 10000 899 #define MLX4_EN_LINK_SPEED_40G 40000 900 901 enum { 902 NETIF_MSG_DRV = 0x0001, 903 NETIF_MSG_PROBE = 0x0002, 904 NETIF_MSG_LINK = 0x0004, 905 NETIF_MSG_TIMER = 0x0008, 906 NETIF_MSG_IFDOWN = 0x0010, 907 NETIF_MSG_IFUP = 0x0020, 908 NETIF_MSG_RX_ERR = 0x0040, 909 NETIF_MSG_TX_ERR = 0x0080, 910 NETIF_MSG_TX_QUEUED = 0x0100, 911 NETIF_MSG_INTR = 0x0200, 912 NETIF_MSG_TX_DONE = 0x0400, 913 NETIF_MSG_RX_STATUS = 0x0800, 914 NETIF_MSG_PKTDATA = 0x1000, 915 NETIF_MSG_HW = 0x2000, 916 NETIF_MSG_WOL = 0x4000, 917 }; 918 919 920 /* 921 * printk / logging functions 922 */ 923 924 #define en_print(level, priv, format, arg...) \ 925 { \ 926 if ((priv)->registered) \ 927 printk(level "%s: %s: " format, DRV_NAME, \ 928 (priv)->dev->if_xname, ## arg); \ 929 else \ 930 printk(level "%s: %s: Port %d: " format, \ 931 DRV_NAME, dev_name(&(priv)->mdev->pdev->dev), \ 932 (priv)->port, ## arg); \ 933 } 934 935 936 #define en_dbg(mlevel, priv, format, arg...) \ 937 do { \ 938 if (NETIF_MSG_##mlevel & priv->msg_enable) \ 939 en_print(KERN_DEBUG, priv, format, ##arg); \ 940 } while (0) 941 #define en_warn(priv, format, arg...) \ 942 en_print(KERN_WARNING, priv, format, ##arg) 943 #define en_err(priv, format, arg...) \ 944 en_print(KERN_ERR, priv, format, ##arg) 945 #define en_info(priv, format, arg...) \ 946 en_print(KERN_INFO, priv, format, ## arg) 947 948 #define mlx4_err(mdev, format, arg...) \ 949 pr_err("%s %s: " format, DRV_NAME, \ 950 dev_name(&(mdev)->pdev->dev), ##arg) 951 #define mlx4_info(mdev, format, arg...) \ 952 pr_info("%s %s: " format, DRV_NAME, \ 953 dev_name(&(mdev)->pdev->dev), ##arg) 954 #define mlx4_warn(mdev, format, arg...) \ 955 pr_warning("%s %s: " format, DRV_NAME, \ 956 dev_name(&(mdev)->pdev->dev), ##arg) 957 958 #endif 959