1 /*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DEVICE_H 29 #define MLX5_DEVICE_H 30 31 #include <linux/types.h> 32 #include <rdma/ib_verbs.h> 33 #include <dev/mlx5/mlx5_ifc.h> 34 35 #define FW_INIT_TIMEOUT_MILI 2000 36 #define FW_INIT_WAIT_MS 2 37 #define FW_PRE_INIT_TIMEOUT_MILI 120000 38 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld) 52 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 53 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 54 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 55 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) 56 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 57 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 58 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 59 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 60 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) 61 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 62 63 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 64 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 65 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 66 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 67 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 68 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 69 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 70 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 71 72 /* insert a value to a struct */ 73 #define MLX5_SET(typ, p, fld, v) do { \ 74 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 75 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 78 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 79 << __mlx5_dw_bit_off(typ, fld))); \ 80 } while (0) 81 82 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 83 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 84 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 85 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 86 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 87 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 88 << __mlx5_dw_bit_off(typ, fld))); \ 89 } while (0) 90 91 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 92 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 93 __mlx5_mask(typ, fld)) 94 95 #define MLX5_GET_PR(typ, p, fld) ({ \ 96 u32 ___t = MLX5_GET(typ, p, fld); \ 97 pr_debug(#fld " = 0x%x\n", ___t); \ 98 ___t; \ 99 }) 100 101 #define __MLX5_SET64(typ, p, fld, v) do { \ 102 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 103 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 104 } while (0) 105 106 #define MLX5_SET64(typ, p, fld, v) do { \ 107 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 108 __MLX5_SET64(typ, p, fld, v); \ 109 } while (0) 110 111 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 112 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 113 __MLX5_SET64(typ, p, fld[idx], v); \ 114 } while (0) 115 116 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 117 118 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ 119 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 120 __mlx5_mask16(typ, fld)) 121 122 #define MLX5_SET16(typ, p, fld, v) do { \ 123 u16 _v = v; \ 124 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ 125 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ 126 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ 127 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ 128 << __mlx5_16_bit_off(typ, fld))); \ 129 } while (0) 130 131 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 132 __mlx5_64_off(typ, fld))) 133 134 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 135 type_t tmp; \ 136 switch (sizeof(tmp)) { \ 137 case sizeof(u8): \ 138 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 139 break; \ 140 case sizeof(u16): \ 141 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 142 break; \ 143 case sizeof(u32): \ 144 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 145 break; \ 146 case sizeof(u64): \ 147 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 148 break; \ 149 } \ 150 tmp; \ 151 }) 152 153 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 154 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 155 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 156 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 157 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 158 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 159 160 /* insert a value to a struct */ 161 #define MLX5_VSC_SET(typ, p, fld, v) do { \ 162 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 163 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 164 *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 165 cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 166 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 167 << __mlx5_dw_bit_off(typ, fld))); \ 168 } while (0) 169 170 #define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\ 171 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 172 __mlx5_mask(typ, fld)) 173 174 #define MLX5_VSC_GET_PR(typ, p, fld) ({ \ 175 u32 ___t = MLX5_VSC_GET(typ, p, fld); \ 176 pr_debug(#fld " = 0x%x\n", ___t); \ 177 ___t; \ 178 }) 179 180 enum { 181 MLX5_MAX_COMMANDS = 32, 182 MLX5_CMD_DATA_BLOCK_SIZE = 512, 183 MLX5_CMD_MBOX_SIZE = 1024, 184 MLX5_PCI_CMD_XPORT = 7, 185 MLX5_MKEY_BSF_OCTO_SIZE = 4, 186 MLX5_MAX_PSVS = 4, 187 }; 188 189 enum { 190 MLX5_EXTENDED_UD_AV = 0x80000000, 191 }; 192 193 enum { 194 MLX5_CQ_FLAGS_OI = 2, 195 }; 196 197 enum { 198 MLX5_STAT_RATE_OFFSET = 5, 199 }; 200 201 enum { 202 MLX5_INLINE_SEG = 0x80000000, 203 }; 204 205 enum { 206 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 207 }; 208 209 enum { 210 MLX5_MIN_PKEY_TABLE_SIZE = 128, 211 MLX5_MAX_LOG_PKEY_TABLE = 5, 212 }; 213 214 enum { 215 MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31 216 }; 217 218 enum { 219 MLX5_PERM_LOCAL_READ = 1 << 2, 220 MLX5_PERM_LOCAL_WRITE = 1 << 3, 221 MLX5_PERM_REMOTE_READ = 1 << 4, 222 MLX5_PERM_REMOTE_WRITE = 1 << 5, 223 MLX5_PERM_ATOMIC = 1 << 6, 224 MLX5_PERM_UMR_EN = 1 << 7, 225 }; 226 227 enum { 228 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 229 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 230 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 231 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 232 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 233 }; 234 235 enum { 236 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 237 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 238 MLX5_MKEY_BSF_EN = 1 << 30, 239 MLX5_MKEY_LEN64 = 1U << 31, 240 }; 241 242 enum { 243 MLX5_EN_RD = (u64)1, 244 MLX5_EN_WR = (u64)2 245 }; 246 247 enum { 248 MLX5_BF_REGS_PER_PAGE = 4, 249 MLX5_MAX_UAR_PAGES = 1 << 8, 250 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 251 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 252 }; 253 254 enum { 255 MLX5_MKEY_MASK_LEN = 1ull << 0, 256 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 257 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 258 MLX5_MKEY_MASK_PD = 1ull << 7, 259 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 260 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 261 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 262 MLX5_MKEY_MASK_KEY = 1ull << 13, 263 MLX5_MKEY_MASK_QPN = 1ull << 14, 264 MLX5_MKEY_MASK_LR = 1ull << 17, 265 MLX5_MKEY_MASK_LW = 1ull << 18, 266 MLX5_MKEY_MASK_RR = 1ull << 19, 267 MLX5_MKEY_MASK_RW = 1ull << 20, 268 MLX5_MKEY_MASK_A = 1ull << 21, 269 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 270 MLX5_MKEY_MASK_FREE = 1ull << 29, 271 }; 272 273 enum { 274 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 275 276 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 277 MLX5_UMR_CHECK_FREE = (2 << 5), 278 279 MLX5_UMR_INLINE = (1 << 7), 280 }; 281 282 #define MLX5_UMR_MTT_ALIGNMENT 0x40 283 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 284 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 285 286 enum { 287 MLX5_EVENT_QUEUE_TYPE_QP = 0, 288 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 289 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 290 }; 291 292 enum { 293 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 294 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 295 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 296 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 297 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 298 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 299 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 300 }; 301 302 enum { 303 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1, 304 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE, 305 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE, 306 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE, 307 MLX5_MAX_INLINE_RECEIVE_SIZE = 64 308 }; 309 310 enum { 311 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 312 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 313 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 314 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 315 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21, 316 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 317 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 318 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 319 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33, 320 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34, 321 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 322 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 323 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 324 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48, 325 }; 326 327 enum { 328 MLX5_ROCE_VERSION_1 = 0, 329 MLX5_ROCE_VERSION_1_5 = 1, 330 MLX5_ROCE_VERSION_2 = 2, 331 }; 332 333 enum { 334 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 335 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5, 336 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 337 }; 338 339 enum { 340 MLX5_ROCE_L3_TYPE_IPV4 = 0, 341 MLX5_ROCE_L3_TYPE_IPV6 = 1, 342 }; 343 344 enum { 345 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 346 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 347 }; 348 349 enum { 350 MLX5_OPCODE_NOP = 0x00, 351 MLX5_OPCODE_SEND_INVAL = 0x01, 352 MLX5_OPCODE_RDMA_WRITE = 0x08, 353 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 354 MLX5_OPCODE_SEND = 0x0a, 355 MLX5_OPCODE_SEND_IMM = 0x0b, 356 MLX5_OPCODE_LSO = 0x0e, 357 MLX5_OPCODE_RDMA_READ = 0x10, 358 MLX5_OPCODE_ATOMIC_CS = 0x11, 359 MLX5_OPCODE_ATOMIC_FA = 0x12, 360 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 361 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 362 MLX5_OPCODE_BIND_MW = 0x18, 363 MLX5_OPCODE_CONFIG_CMD = 0x1f, 364 MLX5_OPCODE_DUMP = 0x23, 365 366 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 367 MLX5_RECV_OPCODE_SEND = 0x01, 368 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 369 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 370 371 MLX5_CQE_OPCODE_ERROR = 0x1e, 372 MLX5_CQE_OPCODE_RESIZE = 0x16, 373 374 MLX5_OPCODE_SET_PSV = 0x20, 375 MLX5_OPCODE_GET_PSV = 0x21, 376 MLX5_OPCODE_CHECK_PSV = 0x22, 377 MLX5_OPCODE_RGET_PSV = 0x26, 378 MLX5_OPCODE_RCHECK_PSV = 0x27, 379 380 MLX5_OPCODE_UMR = 0x25, 381 382 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15), 383 }; 384 385 enum { 386 MLX5_OPCODE_MOD_UMR_UMR = 0x0, 387 MLX5_OPCODE_MOD_UMR_TLS_TIS_STATIC_PARAMS = 0x1, 388 MLX5_OPCODE_MOD_UMR_TLS_TIR_STATIC_PARAMS = 0x2, 389 }; 390 391 enum { 392 MLX5_OPCODE_MOD_PSV_PSV = 0x0, 393 MLX5_OPCODE_MOD_PSV_TLS_TIS_PROGRESS_PARAMS = 0x1, 394 MLX5_OPCODE_MOD_PSV_TLS_TIR_PROGRESS_PARAMS = 0x2, 395 }; 396 397 enum { 398 MLX5_SET_PORT_RESET_QKEY = 0, 399 MLX5_SET_PORT_GUID0 = 16, 400 MLX5_SET_PORT_NODE_GUID = 17, 401 MLX5_SET_PORT_SYS_GUID = 18, 402 MLX5_SET_PORT_GID_TABLE = 19, 403 MLX5_SET_PORT_PKEY_TABLE = 20, 404 }; 405 406 enum { 407 MLX5_MAX_PAGE_SHIFT = 31 408 }; 409 410 enum { 411 MLX5_ADAPTER_PAGE_SHIFT = 12, 412 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 413 }; 414 415 enum { 416 MLX5_CAP_OFF_CMDIF_CSUM = 46, 417 }; 418 419 enum { 420 /* 421 * Max wqe size for rdma read is 512 bytes, so this 422 * limits our max_sge_rd as the wqe needs to fit: 423 * - ctrl segment (16 bytes) 424 * - rdma segment (16 bytes) 425 * - scatter elements (16 bytes each) 426 */ 427 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 428 }; 429 430 struct mlx5_cmd_layout { 431 u8 type; 432 u8 rsvd0[3]; 433 __be32 inlen; 434 __be64 in_ptr; 435 __be32 in[4]; 436 __be32 out[4]; 437 __be64 out_ptr; 438 __be32 outlen; 439 u8 token; 440 u8 sig; 441 u8 rsvd1; 442 u8 status_own; 443 }; 444 445 enum mlx5_fatal_assert_bit_offsets { 446 MLX5_RFR_OFFSET = 31, 447 }; 448 449 struct mlx5_health_buffer { 450 __be32 assert_var[5]; 451 __be32 rsvd0[3]; 452 __be32 assert_exit_ptr; 453 __be32 assert_callra; 454 __be32 rsvd1[2]; 455 __be32 fw_ver; 456 __be32 hw_id; 457 __be32 rfr; 458 u8 irisc_index; 459 u8 synd; 460 __be16 ext_synd; 461 }; 462 463 enum mlx5_initializing_bit_offsets { 464 MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 465 }; 466 467 enum mlx5_cmd_addr_l_sz_offset { 468 MLX5_NIC_IFC_OFFSET = 8, 469 }; 470 471 struct mlx5_init_seg { 472 __be32 fw_rev; 473 __be32 cmdif_rev_fw_sub; 474 __be32 rsvd0[2]; 475 __be32 cmdq_addr_h; 476 __be32 cmdq_addr_l_sz; 477 __be32 cmd_dbell; 478 __be32 rsvd1[120]; 479 __be32 initializing; 480 struct mlx5_health_buffer health; 481 __be32 rsvd2[880]; 482 __be32 internal_timer_h; 483 __be32 internal_timer_l; 484 __be32 rsvd3[2]; 485 __be32 health_counter; 486 __be32 rsvd4[1019]; 487 __be64 ieee1588_clk; 488 __be32 ieee1588_clk_type; 489 __be32 clr_intx; 490 }; 491 492 struct mlx5_eqe_comp { 493 __be32 reserved[6]; 494 __be32 cqn; 495 }; 496 497 struct mlx5_eqe_qp_srq { 498 __be32 reserved[6]; 499 __be32 qp_srq_n; 500 }; 501 502 struct mlx5_eqe_cq_err { 503 __be32 cqn; 504 u8 reserved1[7]; 505 u8 syndrome; 506 }; 507 508 struct mlx5_eqe_port_state { 509 u8 reserved0[8]; 510 u8 port; 511 }; 512 513 struct mlx5_eqe_gpio { 514 __be32 reserved0[2]; 515 __be64 gpio_event; 516 }; 517 518 struct mlx5_eqe_congestion { 519 u8 type; 520 u8 rsvd0; 521 u8 congestion_level; 522 }; 523 524 struct mlx5_eqe_stall_vl { 525 u8 rsvd0[3]; 526 u8 port_vl; 527 }; 528 529 struct mlx5_eqe_cmd { 530 __be32 vector; 531 __be32 rsvd[6]; 532 }; 533 534 struct mlx5_eqe_page_req { 535 u8 rsvd0[2]; 536 __be16 func_id; 537 __be32 num_pages; 538 __be32 rsvd1[5]; 539 }; 540 541 struct mlx5_eqe_vport_change { 542 u8 rsvd0[2]; 543 __be16 vport_num; 544 __be32 rsvd1[6]; 545 }; 546 547 548 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 549 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 550 551 enum { 552 MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1, 553 MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 554 MLX5_MODULE_STATUS_ERROR = 0x3, 555 MLX5_MODULE_STATUS_NUM , 556 }; 557 558 enum { 559 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0, 560 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1, 561 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2, 562 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3, 563 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4, 564 MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5, 565 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6, 566 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7, 567 MLX5_MODULE_EVENT_ERROR_PMD_TYPE_NOT_ENABLED = 0x8, 568 MLX5_MODULE_EVENT_ERROR_LASTER_TEC_FAILURE = 0x9, 569 MLX5_MODULE_EVENT_ERROR_HIGH_CURRENT = 0xa, 570 MLX5_MODULE_EVENT_ERROR_HIGH_VOLTAGE = 0xb, 571 MLX5_MODULE_EVENT_ERROR_PCIE_SYS_POWER_SLOT_EXCEEDED = 0xc, 572 MLX5_MODULE_EVENT_ERROR_HIGH_POWER = 0xd, 573 MLX5_MODULE_EVENT_ERROR_MODULE_STATE_MACHINE_FAULT = 0xe, 574 MLX5_MODULE_EVENT_ERROR_NUM , 575 }; 576 577 struct mlx5_eqe_port_module_event { 578 u8 rsvd0; 579 u8 module; 580 u8 rsvd1; 581 u8 module_status; 582 u8 rsvd2[2]; 583 u8 error_type; 584 }; 585 586 struct mlx5_eqe_general_notification_event { 587 u32 rq_user_index_delay_drop; 588 u32 rsvd0[6]; 589 }; 590 591 struct mlx5_eqe_temp_warning { 592 __be64 sensor_warning_msb; 593 __be64 sensor_warning_lsb; 594 } __packed; 595 596 union ev_data { 597 __be32 raw[7]; 598 struct mlx5_eqe_cmd cmd; 599 struct mlx5_eqe_comp comp; 600 struct mlx5_eqe_qp_srq qp_srq; 601 struct mlx5_eqe_cq_err cq_err; 602 struct mlx5_eqe_port_state port; 603 struct mlx5_eqe_gpio gpio; 604 struct mlx5_eqe_congestion cong; 605 struct mlx5_eqe_stall_vl stall_vl; 606 struct mlx5_eqe_page_req req_pages; 607 struct mlx5_eqe_port_module_event port_module_event; 608 struct mlx5_eqe_vport_change vport_change; 609 struct mlx5_eqe_general_notification_event general_notifications; 610 struct mlx5_eqe_temp_warning temp_warning; 611 } __packed; 612 613 struct mlx5_eqe { 614 u8 rsvd0; 615 u8 type; 616 u8 rsvd1; 617 u8 sub_type; 618 __be32 rsvd2[7]; 619 union ev_data data; 620 __be16 rsvd3; 621 u8 signature; 622 u8 owner; 623 } __packed; 624 625 struct mlx5_cmd_prot_block { 626 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 627 u8 rsvd0[48]; 628 __be64 next; 629 __be32 block_num; 630 u8 rsvd1; 631 u8 token; 632 u8 ctrl_sig; 633 u8 sig; 634 }; 635 636 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \ 637 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE) 638 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block)); 639 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE); 640 641 enum { 642 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 643 }; 644 645 struct mlx5_err_cqe { 646 u8 rsvd0[32]; 647 __be32 srqn; 648 u8 rsvd1[18]; 649 u8 vendor_err_synd; 650 u8 syndrome; 651 __be32 s_wqe_opcode_qpn; 652 __be16 wqe_counter; 653 u8 signature; 654 u8 op_own; 655 }; 656 657 struct mlx5_cqe64 { 658 u8 tunneled_etc; 659 u8 rsvd0[3]; 660 u8 lro_tcppsh_abort_dupack; 661 u8 lro_min_ttl; 662 __be16 lro_tcp_win; 663 __be32 lro_ack_seq_num; 664 __be32 rss_hash_result; 665 u8 rss_hash_type; 666 u8 ml_path; 667 u8 rsvd20[2]; 668 __be16 check_sum; 669 __be16 slid; 670 __be32 flags_rqpn; 671 u8 hds_ip_ext; 672 u8 l4_hdr_type_etc; 673 __be16 vlan_info; 674 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 675 __be32 imm_inval_pkey; 676 u8 rsvd40[4]; 677 __be32 byte_cnt; 678 __be64 timestamp; 679 __be32 sop_drop_qpn; 680 __be16 wqe_counter; 681 u8 signature; 682 u8 op_own; 683 }; 684 685 #define MLX5_CQE_TSTMP_PTP (1ULL << 63) 686 687 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe) 688 { 689 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1; 690 } 691 692 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 693 { 694 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 695 } 696 697 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 698 { 699 return (cqe->l4_hdr_type_etc >> 4) & 0x7; 700 } 701 702 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe) 703 { 704 return be16_to_cpu(cqe->vlan_info) & 0xfff; 705 } 706 707 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac) 708 { 709 memcpy(smac, &cqe->rss_hash_type , 4); 710 memcpy(smac + 4, &cqe->slid , 2); 711 } 712 713 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 714 { 715 return cqe->l4_hdr_type_etc & 0x1; 716 } 717 718 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 719 { 720 return cqe->tunneled_etc & 0x1; 721 } 722 723 enum { 724 CQE_L4_HDR_TYPE_NONE = 0x0, 725 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 726 CQE_L4_HDR_TYPE_UDP = 0x2, 727 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 728 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 729 }; 730 731 enum { 732 /* source L3 hash types */ 733 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0, 734 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0, 735 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0, 736 737 /* destination L3 hash types */ 738 CQE_RSS_DST_HTYPE_IP = 0x3 << 2, 739 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2, 740 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2, 741 742 /* source L4 hash types */ 743 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4, 744 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4, 745 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4, 746 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4, 747 748 /* destination L4 hash types */ 749 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6, 750 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6, 751 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6, 752 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6, 753 }; 754 755 enum { 756 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 757 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 758 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 759 }; 760 761 enum { 762 CQE_L2_OK = 1 << 0, 763 CQE_L3_OK = 1 << 1, 764 CQE_L4_OK = 1 << 2, 765 }; 766 767 struct mlx5_sig_err_cqe { 768 u8 rsvd0[16]; 769 __be32 expected_trans_sig; 770 __be32 actual_trans_sig; 771 __be32 expected_reftag; 772 __be32 actual_reftag; 773 __be16 syndrome; 774 u8 rsvd22[2]; 775 __be32 mkey; 776 __be64 err_offset; 777 u8 rsvd30[8]; 778 __be32 qpn; 779 u8 rsvd38[2]; 780 u8 signature; 781 u8 op_own; 782 }; 783 784 struct mlx5_wqe_srq_next_seg { 785 u8 rsvd0[2]; 786 __be16 next_wqe_index; 787 u8 signature; 788 u8 rsvd1[11]; 789 }; 790 791 union mlx5_ext_cqe { 792 struct ib_grh grh; 793 u8 inl[64]; 794 }; 795 796 struct mlx5_cqe128 { 797 union mlx5_ext_cqe inl_grh; 798 struct mlx5_cqe64 cqe64; 799 }; 800 801 enum { 802 MLX5_MKEY_STATUS_FREE = 1 << 6, 803 }; 804 805 struct mlx5_mkey_seg { 806 /* This is a two bit field occupying bits 31-30. 807 * bit 31 is always 0, 808 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 809 */ 810 u8 status; 811 u8 pcie_control; 812 u8 flags; 813 u8 version; 814 __be32 qpn_mkey7_0; 815 u8 rsvd1[4]; 816 __be32 flags_pd; 817 __be64 start_addr; 818 __be64 len; 819 __be32 bsfs_octo_size; 820 u8 rsvd2[16]; 821 __be32 xlt_oct_size; 822 u8 rsvd3[3]; 823 u8 log2_page_size; 824 u8 rsvd4[4]; 825 }; 826 827 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 828 829 enum { 830 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 831 }; 832 833 static inline int mlx5_host_is_le(void) 834 { 835 #if defined(__LITTLE_ENDIAN) 836 return 1; 837 #elif defined(__BIG_ENDIAN) 838 return 0; 839 #else 840 #error Host endianness not defined 841 #endif 842 } 843 844 #define MLX5_CMD_OP_MAX 0x939 845 846 enum { 847 VPORT_STATE_DOWN = 0x0, 848 VPORT_STATE_UP = 0x1, 849 VPORT_STATE_FOLLOW = 0x2, 850 }; 851 852 enum { 853 MLX5_L3_PROT_TYPE_IPV4 = 0, 854 MLX5_L3_PROT_TYPE_IPV6 = 1, 855 }; 856 857 enum { 858 MLX5_L4_PROT_TYPE_TCP = 0, 859 MLX5_L4_PROT_TYPE_UDP = 1, 860 }; 861 862 enum { 863 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 864 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 865 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 866 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 867 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 868 }; 869 870 enum { 871 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 872 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 873 MLX5_MATCH_INNER_HEADERS = 1 << 2, 874 875 }; 876 877 enum { 878 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 879 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2, 880 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3, 881 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 882 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5, 883 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6, 884 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7, 885 }; 886 887 enum { 888 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0, 889 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1, 890 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2 891 }; 892 893 enum { 894 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0, 895 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1, 896 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2, 897 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3 898 }; 899 900 enum { 901 MLX5_UC_ADDR_CHANGE = (1 << 0), 902 MLX5_MC_ADDR_CHANGE = (1 << 1), 903 MLX5_VLAN_CHANGE = (1 << 2), 904 MLX5_PROMISC_CHANGE = (1 << 3), 905 MLX5_MTU_CHANGE = (1 << 4), 906 }; 907 908 enum mlx5_list_type { 909 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0, 910 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1, 911 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2, 912 }; 913 914 enum { 915 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 916 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 917 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 918 }; 919 920 /* MLX5 DEV CAPs */ 921 922 /* TODO: EAT.ME */ 923 enum mlx5_cap_mode { 924 HCA_CAP_OPMOD_GET_MAX = 0, 925 HCA_CAP_OPMOD_GET_CUR = 1, 926 }; 927 928 enum mlx5_cap_type { 929 MLX5_CAP_GENERAL = 0, 930 MLX5_CAP_ETHERNET_OFFLOADS, 931 MLX5_CAP_ODP, 932 MLX5_CAP_ATOMIC, 933 MLX5_CAP_ROCE, 934 MLX5_CAP_IPOIB_OFFLOADS, 935 MLX5_CAP_EOIB_OFFLOADS, 936 MLX5_CAP_FLOW_TABLE, 937 MLX5_CAP_ESWITCH_FLOW_TABLE, 938 MLX5_CAP_ESWITCH, 939 MLX5_CAP_SNAPSHOT, 940 MLX5_CAP_VECTOR_CALC, 941 MLX5_CAP_QOS, 942 MLX5_CAP_DEBUG, 943 MLX5_CAP_NVME, 944 MLX5_CAP_DMC, 945 MLX5_CAP_DEC, 946 MLX5_CAP_TLS, 947 /* NUM OF CAP Types */ 948 MLX5_CAP_NUM 949 }; 950 951 enum mlx5_qcam_reg_groups { 952 MLX5_QCAM_REGS_FIRST_128 = 0x0, 953 }; 954 955 enum mlx5_qcam_feature_groups { 956 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 957 }; 958 959 enum mlx5_pcam_reg_groups { 960 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 961 }; 962 963 enum mlx5_pcam_feature_groups { 964 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 965 }; 966 967 enum mlx5_mcam_reg_groups { 968 MLX5_MCAM_REGS_FIRST_128 = 0x0, 969 }; 970 971 enum mlx5_mcam_feature_groups { 972 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 973 }; 974 975 /* GET Dev Caps macros */ 976 #define MLX5_CAP_GEN(mdev, cap) \ 977 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 978 979 #define MLX5_CAP_GEN_64(mdev, cap) \ 980 MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 981 982 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 983 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 984 985 #define MLX5_CAP_ETH(mdev, cap) \ 986 MLX5_GET(per_protocol_networking_offload_caps,\ 987 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 988 989 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 990 MLX5_GET(per_protocol_networking_offload_caps,\ 991 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 992 993 #define MLX5_CAP_ROCE(mdev, cap) \ 994 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 995 996 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 997 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 998 999 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1000 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 1001 1002 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1003 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 1004 1005 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1006 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 1007 1008 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1009 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 1010 1011 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1012 MLX5_GET(flow_table_eswitch_cap, \ 1013 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1014 1015 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1016 MLX5_GET(flow_table_eswitch_cap, \ 1017 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1018 1019 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1020 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1021 1022 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1023 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1024 1025 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1026 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1027 1028 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1029 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1030 1031 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1032 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1033 1034 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1035 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1036 1037 #define MLX5_CAP_ESW(mdev, cap) \ 1038 MLX5_GET(e_switch_cap, \ 1039 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 1040 1041 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1042 MLX5_GET(e_switch_cap, \ 1043 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 1044 1045 #define MLX5_CAP_ODP(mdev, cap)\ 1046 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1047 1048 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 1049 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap) 1050 1051 #define MLX5_CAP_SNAPSHOT(mdev, cap) \ 1052 MLX5_GET(snapshot_cap, \ 1053 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap) 1054 1055 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \ 1056 MLX5_GET(snapshot_cap, \ 1057 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap) 1058 1059 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \ 1060 MLX5_GET(per_protocol_networking_offload_caps,\ 1061 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap) 1062 1063 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \ 1064 MLX5_GET(per_protocol_networking_offload_caps,\ 1065 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap) 1066 1067 #define MLX5_CAP_DEBUG(mdev, cap) \ 1068 MLX5_GET(debug_cap, \ 1069 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap) 1070 1071 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \ 1072 MLX5_GET(debug_cap, \ 1073 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap) 1074 1075 #define MLX5_CAP_QOS(mdev, cap) \ 1076 MLX5_GET(qos_cap,\ 1077 mdev->hca_caps_cur[MLX5_CAP_QOS], cap) 1078 1079 #define MLX5_CAP_QOS_MAX(mdev, cap) \ 1080 MLX5_GET(qos_cap,\ 1081 mdev->hca_caps_max[MLX5_CAP_QOS], cap) 1082 1083 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1084 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1085 1086 #define MLX5_CAP_PCAM_REG(mdev, reg) \ 1087 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) 1088 1089 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1090 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1091 1092 #define MLX5_CAP_MCAM_REG(mdev, reg) \ 1093 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg) 1094 1095 #define MLX5_CAP_QCAM_REG(mdev, fld) \ 1096 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1097 1098 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1099 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1100 1101 #define MLX5_CAP_FPGA(mdev, cap) \ 1102 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) 1103 1104 #define MLX5_CAP64_FPGA(mdev, cap) \ 1105 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) 1106 1107 #define MLX5_CAP_TLS(mdev, cap) \ 1108 MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap) 1109 1110 enum { 1111 MLX5_CMD_STAT_OK = 0x0, 1112 MLX5_CMD_STAT_INT_ERR = 0x1, 1113 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1114 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1115 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1116 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1117 MLX5_CMD_STAT_RES_BUSY = 0x6, 1118 MLX5_CMD_STAT_LIM_ERR = 0x8, 1119 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1120 MLX5_CMD_STAT_IX_ERR = 0xa, 1121 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1122 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1123 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1124 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1125 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1126 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1127 }; 1128 1129 enum { 1130 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1131 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1132 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1133 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1134 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1135 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6, 1136 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1137 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1138 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1139 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1140 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1141 }; 1142 1143 enum { 1144 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1145 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1, 1146 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2, 1147 }; 1148 1149 enum { 1150 MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE, 1151 MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE, 1152 }; 1153 1154 enum { 1155 NUM_DRIVER_UARS = 4, 1156 NUM_LOW_LAT_UUARS = 4, 1157 }; 1158 1159 enum { 1160 MLX5_CAP_PORT_TYPE_IB = 0x0, 1161 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1162 }; 1163 1164 enum { 1165 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0, 1166 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1, 1167 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2 1168 }; 1169 1170 enum mlx5_inline_modes { 1171 MLX5_INLINE_MODE_NONE, 1172 MLX5_INLINE_MODE_L2, 1173 MLX5_INLINE_MODE_IP, 1174 MLX5_INLINE_MODE_TCP_UDP, 1175 }; 1176 1177 enum { 1178 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2, 1179 }; 1180 1181 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1182 { 1183 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1184 return 0; 1185 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1186 } 1187 1188 struct mlx5_ifc_mcia_reg_bits { 1189 u8 l[0x1]; 1190 u8 reserved_0[0x7]; 1191 u8 module[0x8]; 1192 u8 reserved_1[0x8]; 1193 u8 status[0x8]; 1194 1195 u8 i2c_device_address[0x8]; 1196 u8 page_number[0x8]; 1197 u8 device_address[0x10]; 1198 1199 u8 reserved_2[0x10]; 1200 u8 size[0x10]; 1201 1202 u8 reserved_3[0x20]; 1203 1204 u8 dword_0[0x20]; 1205 u8 dword_1[0x20]; 1206 u8 dword_2[0x20]; 1207 u8 dword_3[0x20]; 1208 u8 dword_4[0x20]; 1209 u8 dword_5[0x20]; 1210 u8 dword_6[0x20]; 1211 u8 dword_7[0x20]; 1212 u8 dword_8[0x20]; 1213 u8 dword_9[0x20]; 1214 u8 dword_10[0x20]; 1215 u8 dword_11[0x20]; 1216 }; 1217 1218 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c 1219 1220 struct mlx5_mini_cqe8 { 1221 union { 1222 __be32 rx_hash_result; 1223 __be16 checksum; 1224 __be16 rsvd; 1225 struct { 1226 __be16 wqe_counter; 1227 u8 s_wqe_opcode; 1228 u8 reserved; 1229 } s_wqe_info; 1230 }; 1231 __be32 byte_cnt; 1232 }; 1233 1234 enum { 1235 MLX5_NO_INLINE_DATA, 1236 MLX5_INLINE_DATA32_SEG, 1237 MLX5_INLINE_DATA64_SEG, 1238 MLX5_COMPRESSED, 1239 }; 1240 1241 enum mlx5_exp_cqe_zip_recv_type { 1242 MLX5_CQE_FORMAT_HASH, 1243 MLX5_CQE_FORMAT_CSUM, 1244 }; 1245 1246 #define MLX5E_CQE_FORMAT_MASK 0xc 1247 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe) 1248 { 1249 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2; 1250 } 1251 1252 enum { 1253 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 1254 MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, 1255 }; 1256 1257 enum { 1258 MLX5_FRL_LEVEL3 = 0x8, 1259 MLX5_FRL_LEVEL6 = 0x40, 1260 }; 1261 1262 /* 8 regular priorities + 1 for multicast */ 1263 #define MLX5_NUM_BYPASS_FTS 9 1264 1265 #endif /* MLX5_DEVICE_H */ 1266