xref: /freebsd/sys/dev/mlx5/driver.h (revision 0957b409) 
1 /*-
2  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef MLX5_DRIVER_H
29 #define MLX5_DRIVER_H
30 
31 #include "opt_ratelimit.h"
32 
33 #include <linux/kernel.h>
34 #include <linux/completion.h>
35 #include <linux/pci.h>
36 #include <linux/cache.h>
37 #include <linux/rbtree.h>
38 #include <linux/if_ether.h>
39 #include <linux/semaphore.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/radix-tree.h>
43 #include <linux/idr.h>
44 
45 #include <dev/mlx5/device.h>
46 #include <dev/mlx5/doorbell.h>
47 #include <dev/mlx5/srq.h>
48 
49 #define MLX5_QCOUNTER_SETS_NETDEV 64
50 #define MLX5_MAX_NUMBER_OF_VFS 128
51 
52 enum {
53 	MLX5_BOARD_ID_LEN = 64,
54 	MLX5_MAX_NAME_LEN = 16,
55 };
56 
57 enum {
58 	MLX5_CMD_TIMEOUT_MSEC	= 8 * 60 * 1000,
59 	MLX5_CMD_WQ_MAX_NAME	= 32,
60 };
61 
62 enum {
63 	CMD_OWNER_SW		= 0x0,
64 	CMD_OWNER_HW		= 0x1,
65 	CMD_STATUS_SUCCESS	= 0,
66 };
67 
68 enum mlx5_sqp_t {
69 	MLX5_SQP_SMI		= 0,
70 	MLX5_SQP_GSI		= 1,
71 	MLX5_SQP_IEEE_1588	= 2,
72 	MLX5_SQP_SNIFFER	= 3,
73 	MLX5_SQP_SYNC_UMR	= 4,
74 };
75 
76 enum {
77 	MLX5_MAX_PORTS	= 2,
78 };
79 
80 enum {
81 	MLX5_EQ_VEC_PAGES	 = 0,
82 	MLX5_EQ_VEC_CMD		 = 1,
83 	MLX5_EQ_VEC_ASYNC	 = 2,
84 	MLX5_EQ_VEC_COMP_BASE,
85 };
86 
87 enum {
88 	MLX5_MAX_IRQ_NAME	= 32
89 };
90 
91 enum {
92 	MLX5_ATOMIC_MODE_OFF		= 16,
93 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
94 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
95 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
96 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
97 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
98 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
99 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
100 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
101 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
102 };
103 
104 enum {
105 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
106 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
107 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
108 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
109 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
110 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
111 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
112 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
113 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
114 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
115 };
116 
117 enum {
118 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
119 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
120 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
121 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
122 };
123 
124 enum {
125 	MLX5_REG_QPTS		 = 0x4002,
126 	MLX5_REG_QETCR		 = 0x4005,
127 	MLX5_REG_QPDP		 = 0x4007,
128 	MLX5_REG_QTCT		 = 0x400A,
129 	MLX5_REG_QPDPM		 = 0x4013,
130 	MLX5_REG_QHLL		 = 0x4016,
131 	MLX5_REG_QCAM		 = 0x4019,
132 	MLX5_REG_DCBX_PARAM	 = 0x4020,
133 	MLX5_REG_DCBX_APP	 = 0x4021,
134 	MLX5_REG_PCAP		 = 0x5001,
135 	MLX5_REG_FPGA_CAP	 = 0x4022,
136 	MLX5_REG_FPGA_CTRL	 = 0x4023,
137 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
138 	MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
139 	MLX5_REG_PMTU		 = 0x5003,
140 	MLX5_REG_PTYS		 = 0x5004,
141 	MLX5_REG_PAOS		 = 0x5006,
142 	MLX5_REG_PFCC		 = 0x5007,
143 	MLX5_REG_PPCNT		 = 0x5008,
144 	MLX5_REG_PMAOS		 = 0x5012,
145 	MLX5_REG_PUDE		 = 0x5009,
146 	MLX5_REG_PPTB		 = 0x500B,
147 	MLX5_REG_PBMC		 = 0x500C,
148 	MLX5_REG_PMPE		 = 0x5010,
149 	MLX5_REG_PELC		 = 0x500e,
150 	MLX5_REG_PVLC		 = 0x500f,
151 	MLX5_REG_PMLP		 = 0x5002,
152 	MLX5_REG_NODE_DESC	 = 0x6001,
153 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
154 	MLX5_REG_MTMP		 = 0x900a,
155 	MLX5_REG_MCIA		 = 0x9014,
156 	MLX5_REG_MPCNT		 = 0x9051,
157 };
158 
159 enum dbg_rsc_type {
160 	MLX5_DBG_RSC_QP,
161 	MLX5_DBG_RSC_EQ,
162 	MLX5_DBG_RSC_CQ,
163 };
164 
165 enum {
166 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
167 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
168 	MLX5_INTERFACE_NUMBER       = 2,
169 };
170 
171 struct mlx5_field_desc {
172 	struct dentry	       *dent;
173 	int			i;
174 };
175 
176 struct mlx5_rsc_debug {
177 	struct mlx5_core_dev   *dev;
178 	void		       *object;
179 	enum dbg_rsc_type	type;
180 	struct dentry	       *root;
181 	struct mlx5_field_desc	fields[0];
182 };
183 
184 enum mlx5_dev_event {
185 	MLX5_DEV_EVENT_SYS_ERROR,
186 	MLX5_DEV_EVENT_PORT_UP,
187 	MLX5_DEV_EVENT_PORT_DOWN,
188 	MLX5_DEV_EVENT_PORT_INITIALIZED,
189 	MLX5_DEV_EVENT_LID_CHANGE,
190 	MLX5_DEV_EVENT_PKEY_CHANGE,
191 	MLX5_DEV_EVENT_GUID_CHANGE,
192 	MLX5_DEV_EVENT_CLIENT_REREG,
193 	MLX5_DEV_EVENT_VPORT_CHANGE,
194 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
195 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
196 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
197 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
198 };
199 
200 enum mlx5_port_status {
201 	MLX5_PORT_UP        = 1 << 0,
202 	MLX5_PORT_DOWN      = 1 << 1,
203 };
204 
205 enum mlx5_link_mode {
206 	MLX5_1000BASE_CX_SGMII	= 0,
207 	MLX5_1000BASE_KX	= 1,
208 	MLX5_10GBASE_CX4	= 2,
209 	MLX5_10GBASE_KX4	= 3,
210 	MLX5_10GBASE_KR		= 4,
211 	MLX5_20GBASE_KR2	= 5,
212 	MLX5_40GBASE_CR4	= 6,
213 	MLX5_40GBASE_KR4	= 7,
214 	MLX5_56GBASE_R4		= 8,
215 	MLX5_10GBASE_CR		= 12,
216 	MLX5_10GBASE_SR		= 13,
217 	MLX5_10GBASE_ER		= 14,
218 	MLX5_40GBASE_SR4	= 15,
219 	MLX5_40GBASE_LR4	= 16,
220 	MLX5_100GBASE_CR4	= 20,
221 	MLX5_100GBASE_SR4	= 21,
222 	MLX5_100GBASE_KR4	= 22,
223 	MLX5_100GBASE_LR4	= 23,
224 	MLX5_100BASE_TX		= 24,
225 	MLX5_1000BASE_T		= 25,
226 	MLX5_10GBASE_T		= 26,
227 	MLX5_25GBASE_CR		= 27,
228 	MLX5_25GBASE_KR		= 28,
229 	MLX5_25GBASE_SR		= 29,
230 	MLX5_50GBASE_CR2	= 30,
231 	MLX5_50GBASE_KR2	= 31,
232 	MLX5_LINK_MODES_NUMBER,
233 };
234 
235 enum {
236 	MLX5_VSC_SPACE_SUPPORTED = 0x1,
237 	MLX5_VSC_SPACE_OFFSET	 = 0x4,
238 	MLX5_VSC_COUNTER_OFFSET	 = 0x8,
239 	MLX5_VSC_SEMA_OFFSET	 = 0xC,
240 	MLX5_VSC_ADDR_OFFSET	 = 0x10,
241 	MLX5_VSC_DATA_OFFSET	 = 0x14,
242 	MLX5_VSC_MAX_RETRIES	 = 0x1000,
243 };
244 
245 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
246 
247 struct mlx5_uuar_info {
248 	struct mlx5_uar	       *uars;
249 	int			num_uars;
250 	int			num_low_latency_uuars;
251 	unsigned long	       *bitmap;
252 	unsigned int	       *count;
253 	struct mlx5_bf	       *bfs;
254 
255 	/*
256 	 * protect uuar allocation data structs
257 	 */
258 	struct mutex		lock;
259 	u32			ver;
260 };
261 
262 struct mlx5_bf {
263 	void __iomem	       *reg;
264 	void __iomem	       *regreg;
265 	int			buf_size;
266 	struct mlx5_uar	       *uar;
267 	unsigned long		offset;
268 	int			need_lock;
269 	/* protect blue flame buffer selection when needed
270 	 */
271 	spinlock_t		lock;
272 
273 	/* serialize 64 bit writes when done as two 32 bit accesses
274 	 */
275 	spinlock_t		lock32;
276 	int			uuarn;
277 };
278 
279 struct mlx5_cmd_first {
280 	__be32		data[4];
281 };
282 
283 struct cache_ent;
284 struct mlx5_fw_page {
285 	union {
286 		struct rb_node rb_node;
287 		struct list_head list;
288 	};
289 	struct mlx5_cmd_first first;
290 	struct mlx5_core_dev *dev;
291 	bus_dmamap_t dma_map;
292 	bus_addr_t dma_addr;
293 	void *virt_addr;
294 	struct cache_ent *cache;
295 	u32 numpages;
296 	u16 load_done;
297 #define	MLX5_LOAD_ST_NONE 0
298 #define	MLX5_LOAD_ST_SUCCESS 1
299 #define	MLX5_LOAD_ST_FAILURE 2
300 	u16 func_id;
301 };
302 #define	mlx5_cmd_msg mlx5_fw_page
303 
304 struct mlx5_cmd_debug {
305 	struct dentry	       *dbg_root;
306 	struct dentry	       *dbg_in;
307 	struct dentry	       *dbg_out;
308 	struct dentry	       *dbg_outlen;
309 	struct dentry	       *dbg_status;
310 	struct dentry	       *dbg_run;
311 	void		       *in_msg;
312 	void		       *out_msg;
313 	u8			status;
314 	u16			inlen;
315 	u16			outlen;
316 };
317 
318 struct cache_ent {
319 	/* protect block chain allocations
320 	 */
321 	spinlock_t		lock;
322 	struct list_head	head;
323 };
324 
325 struct cmd_msg_cache {
326 	struct cache_ent	large;
327 	struct cache_ent	med;
328 
329 };
330 
331 struct mlx5_traffic_counter {
332 	u64         packets;
333 	u64         octets;
334 };
335 
336 enum mlx5_cmd_mode {
337 	MLX5_CMD_MODE_POLLING,
338 	MLX5_CMD_MODE_EVENTS
339 };
340 
341 struct mlx5_cmd_stats {
342 	u64		sum;
343 	u64		n;
344 	struct dentry  *root;
345 	struct dentry  *avg;
346 	struct dentry  *count;
347 	/* protect command average calculations */
348 	spinlock_t	lock;
349 };
350 
351 struct mlx5_cmd {
352 	struct mlx5_fw_page *cmd_page;
353 	bus_dma_tag_t dma_tag;
354 	struct sx dma_sx;
355 	struct mtx dma_mtx;
356 #define	MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
357 #define	MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
358 #define	MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
359 	struct cv dma_cv;
360 #define	MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
361 #define	MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
362 	void	       *cmd_buf;
363 	dma_addr_t	dma;
364 	u16		cmdif_rev;
365 	u8		log_sz;
366 	u8		log_stride;
367 	int		max_reg_cmds;
368 	int		events;
369 	u32 __iomem    *vector;
370 
371 	/* protect command queue allocations
372 	 */
373 	spinlock_t	alloc_lock;
374 
375 	/* protect token allocations
376 	 */
377 	spinlock_t	token_lock;
378 	u8		token;
379 	unsigned long	bitmask;
380 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
381 	struct workqueue_struct *wq;
382 	struct semaphore sem;
383 	struct semaphore pages_sem;
384 	enum mlx5_cmd_mode mode;
385 	struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
386 	volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
387 	struct mlx5_cmd_debug dbg;
388 	struct cmd_msg_cache cache;
389 	int checksum_disabled;
390 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
391 };
392 
393 struct mlx5_port_caps {
394 	int	gid_table_len;
395 	int	pkey_table_len;
396 	u8	ext_port_cap;
397 };
398 
399 struct mlx5_buf {
400 	bus_dma_tag_t		dma_tag;
401 	bus_dmamap_t		dma_map;
402 	struct mlx5_core_dev   *dev;
403 	struct {
404 		void	       *buf;
405 	} direct;
406 	u64		       *page_list;
407 	int			npages;
408 	int			size;
409 	u8			page_shift;
410 	u8			load_done;
411 };
412 
413 struct mlx5_frag_buf {
414 	struct mlx5_buf_list	*frags;
415 	int			npages;
416 	int			size;
417 	u8			page_shift;
418 };
419 
420 struct mlx5_eq {
421 	struct mlx5_core_dev   *dev;
422 	__be32 __iomem	       *doorbell;
423 	u32			cons_index;
424 	struct mlx5_buf		buf;
425 	int			size;
426 	u8			irqn;
427 	u8			eqn;
428 	int			nent;
429 	u64			mask;
430 	struct list_head	list;
431 	int			index;
432 	struct mlx5_rsc_debug	*dbg;
433 };
434 
435 struct mlx5_core_psv {
436 	u32	psv_idx;
437 	struct psv_layout {
438 		u32	pd;
439 		u16	syndrome;
440 		u16	reserved;
441 		u16	bg;
442 		u16	app_tag;
443 		u32	ref_tag;
444 	} psv;
445 };
446 
447 struct mlx5_core_sig_ctx {
448 	struct mlx5_core_psv	psv_memory;
449 	struct mlx5_core_psv	psv_wire;
450 #if (__FreeBSD_version >= 1100000)
451 	struct ib_sig_err       err_item;
452 #endif
453 	bool			sig_status_checked;
454 	bool			sig_err_exists;
455 	u32			sigerr_count;
456 };
457 
458 enum {
459 	MLX5_MKEY_MR = 1,
460 	MLX5_MKEY_MW,
461 	MLX5_MKEY_MR_USER,
462 };
463 
464 struct mlx5_core_mkey {
465 	u64			iova;
466 	u64			size;
467 	u32			key;
468 	u32			pd;
469 	u32			type;
470 };
471 
472 struct mlx5_core_mr {
473 	u64			iova;
474 	u64			size;
475 	u32			key;
476 	u32			pd;
477 };
478 
479 enum mlx5_res_type {
480 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
481 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
482 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
483 	MLX5_RES_SRQ	= 3,
484 	MLX5_RES_XSRQ	= 4,
485 	MLX5_RES_DCT	= 5,
486 };
487 
488 struct mlx5_core_rsc_common {
489 	enum mlx5_res_type	res;
490 	atomic_t		refcount;
491 	struct completion	free;
492 };
493 
494 struct mlx5_core_srq {
495 	struct mlx5_core_rsc_common	common; /* must be first */
496 	u32				srqn;
497 	int				max;
498 	size_t				max_gs;
499 	size_t				max_avail_gather;
500 	int				wqe_shift;
501 	void				(*event)(struct mlx5_core_srq *, int);
502 	atomic_t			refcount;
503 	struct completion		free;
504 };
505 
506 struct mlx5_eq_table {
507 	void __iomem	       *update_ci;
508 	void __iomem	       *update_arm_ci;
509 	struct list_head	comp_eqs_list;
510 	struct mlx5_eq		pages_eq;
511 	struct mlx5_eq		async_eq;
512 	struct mlx5_eq		cmd_eq;
513 	int			num_comp_vectors;
514 	/* protect EQs list
515 	 */
516 	spinlock_t		lock;
517 };
518 
519 struct mlx5_uar {
520 	u32			index;
521 	void __iomem	       *bf_map;
522 	void __iomem	       *map;
523 };
524 
525 
526 struct mlx5_core_health {
527 	struct mlx5_health_buffer __iomem	*health;
528 	__be32 __iomem		       *health_counter;
529 	struct timer_list		timer;
530 	u32				prev;
531 	int				miss_counter;
532 	u32				fatal_error;
533 	/* wq spinlock to synchronize draining */
534 	spinlock_t			wq_lock;
535 	struct workqueue_struct	       *wq;
536 	unsigned long			flags;
537 	struct work_struct		work;
538 	struct delayed_work		recover_work;
539 };
540 
541 #ifdef RATELIMIT
542 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	(128 * 1024)
543 #else
544 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
545 #endif
546 
547 struct mlx5_cq_linear_array_entry {
548 	spinlock_t	lock;
549 	struct mlx5_core_cq * volatile cq;
550 };
551 
552 struct mlx5_cq_table {
553 	/* protect radix tree
554 	 */
555 	spinlock_t		lock;
556 	struct radix_tree_root	tree;
557 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
558 };
559 
560 struct mlx5_qp_table {
561 	/* protect radix tree
562 	 */
563 	spinlock_t		lock;
564 	struct radix_tree_root	tree;
565 };
566 
567 struct mlx5_srq_table {
568 	/* protect radix tree
569 	 */
570 	spinlock_t		lock;
571 	struct radix_tree_root	tree;
572 };
573 
574 struct mlx5_mr_table {
575 	/* protect radix tree
576 	 */
577 	spinlock_t		lock;
578 	struct radix_tree_root	tree;
579 };
580 
581 struct mlx5_irq_info {
582 	char name[MLX5_MAX_IRQ_NAME];
583 };
584 
585 #ifdef RATELIMIT
586 struct mlx5_rl_entry {
587 	u32			rate;
588 	u16			burst;
589 	u16			index;
590 	u32			refcount;
591 };
592 
593 struct mlx5_rl_table {
594 	struct mutex		rl_lock;
595 	u16			max_size;
596 	u32			max_rate;
597 	u32			min_rate;
598 	struct mlx5_rl_entry   *rl_entry;
599 };
600 #endif
601 
602 struct mlx5_priv {
603 	char			name[MLX5_MAX_NAME_LEN];
604 	struct mlx5_eq_table	eq_table;
605 	struct msix_entry	*msix_arr;
606 	struct mlx5_irq_info	*irq_info;
607 	struct mlx5_uuar_info	uuari;
608 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
609 
610 	struct io_mapping	*bf_mapping;
611 
612 	/* pages stuff */
613 	struct workqueue_struct *pg_wq;
614 	struct rb_root		page_root;
615 	s64			fw_pages;
616 	atomic_t		reg_pages;
617 	s64			pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
618 	struct mlx5_core_health health;
619 
620 	struct mlx5_srq_table	srq_table;
621 
622 	/* start: qp staff */
623 	struct mlx5_qp_table	qp_table;
624 	struct dentry	       *qp_debugfs;
625 	struct dentry	       *eq_debugfs;
626 	struct dentry	       *cq_debugfs;
627 	struct dentry	       *cmdif_debugfs;
628 	/* end: qp staff */
629 
630 	/* start: cq staff */
631 	struct mlx5_cq_table	cq_table;
632 	/* end: cq staff */
633 
634 	/* start: mr staff */
635 	struct mlx5_mr_table	mr_table;
636 	/* end: mr staff */
637 
638 	/* start: alloc staff */
639 	int			numa_node;
640 
641 	struct mutex   pgdir_mutex;
642 	struct list_head        pgdir_list;
643 	/* end: alloc staff */
644 	struct dentry	       *dbg_root;
645 
646 	/* protect mkey key part */
647 	spinlock_t		mkey_lock;
648 	u8			mkey_key;
649 
650 	struct list_head        dev_list;
651 	struct list_head        ctx_list;
652 	spinlock_t              ctx_lock;
653 	unsigned long		pci_dev_data;
654 #ifdef RATELIMIT
655 	struct mlx5_rl_table	rl_table;
656 #endif
657 };
658 
659 enum mlx5_device_state {
660 	MLX5_DEVICE_STATE_UP,
661 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
662 };
663 
664 enum mlx5_interface_state {
665 	MLX5_INTERFACE_STATE_DOWN = BIT(0),
666 	MLX5_INTERFACE_STATE_UP = BIT(1),
667 	MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
668 };
669 
670 enum mlx5_pci_status {
671 	MLX5_PCI_STATUS_DISABLED,
672 	MLX5_PCI_STATUS_ENABLED,
673 };
674 
675 #define	MLX5_MAX_RESERVED_GIDS	8
676 
677 struct mlx5_rsvd_gids {
678 	unsigned int start;
679 	unsigned int count;
680 	struct ida ida;
681 };
682 
683 struct mlx5_special_contexts {
684 	int resd_lkey;
685 };
686 
687 struct mlx5_flow_root_namespace;
688 struct mlx5_dump_data;
689 struct mlx5_core_dev {
690 	struct pci_dev	       *pdev;
691 	/* sync pci state */
692 	struct mutex		pci_status_mutex;
693 	enum mlx5_pci_status	pci_status;
694 	char			board_id[MLX5_BOARD_ID_LEN];
695 	struct mlx5_cmd		cmd;
696 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
697 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
698 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
699 	struct {
700 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
701 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
702 	} caps;
703 	phys_addr_t		iseg_base;
704 	struct mlx5_init_seg __iomem *iseg;
705 	enum mlx5_device_state	state;
706 	/* sync interface state */
707 	struct mutex		intf_state_mutex;
708 	unsigned long		intf_state;
709 	void			(*event) (struct mlx5_core_dev *dev,
710 					  enum mlx5_dev_event event,
711 					  unsigned long param);
712 	struct mlx5_priv	priv;
713 	struct mlx5_profile	*profile;
714 	atomic_t		num_qps;
715 	u32			vsc_addr;
716 	u32			issi;
717 	struct mlx5_special_contexts special_contexts;
718 	unsigned int module_status[MLX5_MAX_PORTS];
719 	struct mlx5_flow_root_namespace *root_ns;
720 	struct mlx5_flow_root_namespace *fdb_root_ns;
721 	struct mlx5_flow_root_namespace *esw_egress_root_ns;
722 	struct mlx5_flow_root_namespace *esw_ingress_root_ns;
723 	struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
724 	struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
725 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
726 	struct mlx5_dump_data	*dump_data;
727 
728 	struct sysctl_ctx_list	sysctl_ctx;
729 	int			msix_eqvec;
730 
731 	struct {
732 		struct mlx5_rsvd_gids	reserved_gids;
733 		atomic_t		roce_en;
734 	} roce;
735 #ifdef CONFIG_MLX5_FPGA
736 	struct mlx5_fpga_device	*fpga;
737 #endif
738 };
739 
740 enum {
741 	MLX5_WOL_DISABLE       = 0,
742 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
743 	MLX5_WOL_MAGIC         = 1 << 2,
744 	MLX5_WOL_ARP           = 1 << 3,
745 	MLX5_WOL_BROADCAST     = 1 << 4,
746 	MLX5_WOL_MULTICAST     = 1 << 5,
747 	MLX5_WOL_UNICAST       = 1 << 6,
748 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
749 };
750 
751 struct mlx5_db {
752 	__be32			*db;
753 	union {
754 		struct mlx5_db_pgdir		*pgdir;
755 		struct mlx5_ib_user_db_page	*user_page;
756 	}			u;
757 	dma_addr_t		dma;
758 	int			index;
759 };
760 
761 struct mlx5_net_counters {
762 	u64	packets;
763 	u64	octets;
764 };
765 
766 struct mlx5_ptys_reg {
767 	u8	an_dis_admin;
768 	u8	an_dis_ap;
769 	u8	local_port;
770 	u8	proto_mask;
771 	u32	eth_proto_cap;
772 	u16	ib_link_width_cap;
773 	u16	ib_proto_cap;
774 	u32	eth_proto_admin;
775 	u16	ib_link_width_admin;
776 	u16	ib_proto_admin;
777 	u32	eth_proto_oper;
778 	u16	ib_link_width_oper;
779 	u16	ib_proto_oper;
780 	u32	eth_proto_lp_advertise;
781 };
782 
783 struct mlx5_pvlc_reg {
784 	u8	local_port;
785 	u8	vl_hw_cap;
786 	u8	vl_admin;
787 	u8	vl_operational;
788 };
789 
790 struct mlx5_pmtu_reg {
791 	u8	local_port;
792 	u16	max_mtu;
793 	u16	admin_mtu;
794 	u16	oper_mtu;
795 };
796 
797 struct mlx5_vport_counters {
798 	struct mlx5_net_counters	received_errors;
799 	struct mlx5_net_counters	transmit_errors;
800 	struct mlx5_net_counters	received_ib_unicast;
801 	struct mlx5_net_counters	transmitted_ib_unicast;
802 	struct mlx5_net_counters	received_ib_multicast;
803 	struct mlx5_net_counters	transmitted_ib_multicast;
804 	struct mlx5_net_counters	received_eth_broadcast;
805 	struct mlx5_net_counters	transmitted_eth_broadcast;
806 	struct mlx5_net_counters	received_eth_unicast;
807 	struct mlx5_net_counters	transmitted_eth_unicast;
808 	struct mlx5_net_counters	received_eth_multicast;
809 	struct mlx5_net_counters	transmitted_eth_multicast;
810 };
811 
812 enum {
813 	MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
814 };
815 
816 struct mlx5_core_dct {
817 	struct mlx5_core_rsc_common	common; /* must be first */
818 	void (*event)(struct mlx5_core_dct *, int);
819 	int			dctn;
820 	struct completion	drained;
821 	struct mlx5_rsc_debug	*dbg;
822 	int			pid;
823 };
824 
825 enum {
826 	MLX5_COMP_EQ_SIZE = 1024,
827 };
828 
829 enum {
830 	MLX5_PTYS_IB = 1 << 0,
831 	MLX5_PTYS_EN = 1 << 2,
832 };
833 
834 struct mlx5_db_pgdir {
835 	struct list_head	list;
836 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
837 	struct mlx5_fw_page    *fw_page;
838 	__be32		       *db_page;
839 	dma_addr_t		db_dma;
840 };
841 
842 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
843 
844 struct mlx5_cmd_work_ent {
845 	struct mlx5_cmd_msg    *in;
846 	struct mlx5_cmd_msg    *out;
847 	int			uin_size;
848 	void		       *uout;
849 	int			uout_size;
850 	mlx5_cmd_cbk_t		callback;
851         struct delayed_work     cb_timeout_work;
852 	void		       *context;
853 	int			idx;
854 	struct completion	done;
855 	struct mlx5_cmd        *cmd;
856 	struct work_struct	work;
857 	struct mlx5_cmd_layout *lay;
858 	int			ret;
859 	int			page_queue;
860 	u8			status;
861 	u8			token;
862 	u64			ts1;
863 	u64			ts2;
864 	u16			op;
865 	u8			busy;
866 	bool			polling;
867 };
868 
869 struct mlx5_pas {
870 	u64	pa;
871 	u8	log_sz;
872 };
873 
874 enum port_state_policy {
875 	MLX5_POLICY_DOWN        = 0,
876 	MLX5_POLICY_UP          = 1,
877 	MLX5_POLICY_FOLLOW      = 2,
878 	MLX5_POLICY_INVALID     = 0xffffffff
879 };
880 
881 static inline void *
882 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
883 {
884 	return ((char *)buf->direct.buf + offset);
885 }
886 
887 
888 extern struct workqueue_struct *mlx5_core_wq;
889 
890 #define STRUCT_FIELD(header, field) \
891 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
892 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
893 
894 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
895 {
896 	return pci_get_drvdata(pdev);
897 }
898 
899 extern struct dentry *mlx5_debugfs_root;
900 
901 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
902 {
903 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
904 }
905 
906 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
907 {
908 	return ioread32be(&dev->iseg->fw_rev) >> 16;
909 }
910 
911 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
912 {
913 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
914 }
915 
916 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
917 {
918 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
919 }
920 
921 static inline int mlx5_get_gid_table_len(u16 param)
922 {
923 	if (param > 4) {
924 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
925 		return 0;
926 	}
927 
928 	return 8 * (1 << param);
929 }
930 
931 static inline void *mlx5_vzalloc(unsigned long size)
932 {
933 	void *rtn;
934 
935 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
936 	return rtn;
937 }
938 
939 static inline void *mlx5_vmalloc(unsigned long size)
940 {
941 	void *rtn;
942 
943 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
944 	if (!rtn)
945 		rtn = vmalloc(size);
946 	return rtn;
947 }
948 
949 static inline u32 mlx5_base_mkey(const u32 key)
950 {
951 	return key & 0xffffff00u;
952 }
953 
954 int mlx5_cmd_init(struct mlx5_core_dev *dev);
955 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
956 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
957 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
958 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
959 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
960 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
961 		  int out_size);
962 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
963 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
964 		     void *context);
965 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
966 			  void *out, int out_size);
967 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
968 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
969 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
970 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
971 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
972 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
973 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
974 int mlx5_health_init(struct mlx5_core_dev *dev);
975 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
976 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
977 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
978 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
979 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
980 
981 #define	mlx5_buf_alloc_node(dev, size, direct, buf, node) \
982 	mlx5_buf_alloc(dev, size, direct, buf)
983 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
984 		   struct mlx5_buf *buf);
985 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
986 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
987 			 struct mlx5_srq_attr *in);
988 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
989 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
990 			struct mlx5_srq_attr *out);
991 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
992 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
993 		      u16 lwm, int is_srq);
994 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
995 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
996 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
997 			     struct mlx5_core_mr *mkey,
998 			     u32 *in, int inlen,
999 			     u32 *out, int outlen,
1000 			     mlx5_cmd_cbk_t callback, void *context);
1001 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1002 			  struct mlx5_core_mr *mr,
1003 			  u32 *in, int inlen);
1004 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
1005 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
1006 			 u32 *out, int outlen);
1007 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
1008 			     u32 *mkey);
1009 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1010 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1011 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1012 		      u16 opmod, u8 port);
1013 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
1014 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
1015 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
1016 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1017 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1018 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1019 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1020 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1021 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1022 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1023 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1024 				 s32 npages);
1025 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1026 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1027 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1028 void mlx5_register_debugfs(void);
1029 void mlx5_unregister_debugfs(void);
1030 int mlx5_eq_init(struct mlx5_core_dev *dev);
1031 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1032 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1033 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1034 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1035 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1036 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1037 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1038 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1039 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1040 		       int nent, u64 mask, const char *name, struct mlx5_uar *uar);
1041 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1042 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1043 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1044 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1045 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1046 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1047 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1048 				u64 addr);
1049 
1050 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1051 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1052 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1053 			 int size_in, void *data_out, int size_out,
1054 			 u16 reg_num, int arg, int write);
1055 
1056 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1057 
1058 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1059 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1060 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1061 		       u32 *out, int outlen);
1062 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1063 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1064 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1065 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1066 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1067 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1068 		       int node);
1069 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1070 
1071 const char *mlx5_command_str(int command);
1072 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1073 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1074 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1075 			 int npsvs, u32 *sig_index);
1076 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1077 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1078 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1079 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1080 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1081 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1082 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1083 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1084 			  struct mlx5_pvlc_reg *pvlc, int write);
1085 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1086 			  struct mlx5_ptys_reg *ptys, int write);
1087 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1088 			  struct mlx5_pmtu_reg *pmtu, int write);
1089 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1090 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1091 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1092 				int priority, int *is_enable);
1093 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1094 				 int priority, int enable);
1095 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1096 				void *out, int out_size);
1097 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1098 				 void *in, int in_size);
1099 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1100 				    void *out, int out_size);
1101 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1102 			       int in_size);
1103 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1104 				   u8 num_of_samples, u16 sample_index,
1105 				   void *out, int out_size);
1106 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1107 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1108 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1109 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1110 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1111 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1112 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1113 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1114 
1115 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1116 {
1117 	return mkey >> 8;
1118 }
1119 
1120 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1121 {
1122 	return mkey_idx << 8;
1123 }
1124 
1125 static inline u8 mlx5_mkey_variant(u32 mkey)
1126 {
1127 	return mkey & 0xff;
1128 }
1129 
1130 enum {
1131 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1132 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1133 };
1134 
1135 enum {
1136 	MAX_MR_CACHE_ENTRIES    = 15,
1137 };
1138 
1139 struct mlx5_interface {
1140 	void *			(*add)(struct mlx5_core_dev *dev);
1141 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1142 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1143 					 enum mlx5_dev_event event, unsigned long param);
1144 	void *                  (*get_dev)(void *context);
1145 	int			protocol;
1146 	struct list_head	list;
1147 };
1148 
1149 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1150 int mlx5_register_interface(struct mlx5_interface *intf);
1151 void mlx5_unregister_interface(struct mlx5_interface *intf);
1152 
1153 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1154 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1155     u8 roce_version, u8 roce_l3_type, const u8 *gid,
1156     const u8 *mac, bool vlan, u16 vlan_id);
1157 
1158 struct mlx5_profile {
1159 	u64	mask;
1160 	u8	log_max_qp;
1161 	struct {
1162 		int	size;
1163 		int	limit;
1164 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1165 };
1166 
1167 enum {
1168 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1169 };
1170 
1171 enum {
1172 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1173 };
1174 
1175 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1176 {
1177 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1178 }
1179 #ifdef RATELIMIT
1180 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1181 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1182 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1183 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1184 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1185 
1186 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1187 {
1188 	return !!(dev->priv.rl_table.max_size);
1189 }
1190 #endif
1191 
1192 #endif /* MLX5_DRIVER_H */
1193