1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/module.h> 29 #include <linux/errno.h> 30 #include <linux/pci.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/slab.h> 33 #include <linux/delay.h> 34 #include <linux/random.h> 35 #include <linux/io-mapping.h> 36 #include <linux/hardirq.h> 37 #include <linux/ktime.h> 38 #include <dev/mlx5/driver.h> 39 #include <dev/mlx5/cmd.h> 40 41 #include "mlx5_core.h" 42 43 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size); 44 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev, 45 struct mlx5_cmd_msg *msg); 46 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg); 47 48 enum { 49 CMD_IF_REV = 5, 50 }; 51 52 enum { 53 NUM_LONG_LISTS = 2, 54 NUM_MED_LISTS = 64, 55 LONG_LIST_SIZE = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 + 56 MLX5_CMD_DATA_BLOCK_SIZE, 57 MED_LIST_SIZE = 16 + MLX5_CMD_DATA_BLOCK_SIZE, 58 }; 59 60 enum { 61 MLX5_CMD_DELIVERY_STAT_OK = 0x0, 62 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1, 63 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2, 64 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3, 65 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4, 66 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5, 67 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6, 68 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7, 69 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8, 70 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9, 71 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10, 72 }; 73 74 struct mlx5_ifc_mbox_out_bits { 75 u8 status[0x8]; 76 u8 reserved_at_8[0x18]; 77 78 u8 syndrome[0x20]; 79 80 u8 reserved_at_40[0x40]; 81 }; 82 83 struct mlx5_ifc_mbox_in_bits { 84 u8 opcode[0x10]; 85 u8 reserved_at_10[0x10]; 86 87 u8 reserved_at_20[0x10]; 88 u8 op_mod[0x10]; 89 90 u8 reserved_at_40[0x40]; 91 }; 92 93 94 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd, 95 struct mlx5_cmd_msg *in, 96 int uin_size, 97 struct mlx5_cmd_msg *out, 98 void *uout, int uout_size, 99 mlx5_cmd_cbk_t cbk, 100 void *context, int page_queue) 101 { 102 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL; 103 struct mlx5_cmd_work_ent *ent; 104 105 ent = kzalloc(sizeof(*ent), alloc_flags); 106 if (!ent) 107 return ERR_PTR(-ENOMEM); 108 109 ent->in = in; 110 ent->uin_size = uin_size; 111 ent->out = out; 112 ent->uout = uout; 113 ent->uout_size = uout_size; 114 ent->callback = cbk; 115 ent->context = context; 116 ent->cmd = cmd; 117 ent->page_queue = page_queue; 118 119 return ent; 120 } 121 122 static u8 alloc_token(struct mlx5_cmd *cmd) 123 { 124 u8 token; 125 126 spin_lock(&cmd->token_lock); 127 cmd->token++; 128 if (cmd->token == 0) 129 cmd->token++; 130 token = cmd->token; 131 spin_unlock(&cmd->token_lock); 132 133 return token; 134 } 135 136 static int alloc_ent(struct mlx5_cmd_work_ent *ent) 137 { 138 unsigned long flags; 139 struct mlx5_cmd *cmd = ent->cmd; 140 struct mlx5_core_dev *dev = 141 container_of(cmd, struct mlx5_core_dev, cmd); 142 int ret = cmd->max_reg_cmds; 143 144 spin_lock_irqsave(&cmd->alloc_lock, flags); 145 if (!ent->page_queue) { 146 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds); 147 if (ret >= cmd->max_reg_cmds) 148 ret = -1; 149 } 150 151 if (dev->state != MLX5_DEVICE_STATE_UP) 152 ret = -1; 153 154 if (ret != -1) { 155 ent->busy = 1; 156 ent->idx = ret; 157 clear_bit(ent->idx, &cmd->bitmask); 158 cmd->ent_mode[ent->idx] = 159 ent->polling ? MLX5_CMD_MODE_POLLING : MLX5_CMD_MODE_EVENTS; 160 cmd->ent_arr[ent->idx] = ent; 161 } 162 spin_unlock_irqrestore(&cmd->alloc_lock, flags); 163 164 return ret; 165 } 166 167 static void free_ent(struct mlx5_cmd *cmd, int idx) 168 { 169 unsigned long flags; 170 171 spin_lock_irqsave(&cmd->alloc_lock, flags); 172 cmd->ent_arr[idx] = NULL; /* safety clear */ 173 cmd->ent_mode[idx] = MLX5_CMD_MODE_POLLING; /* reset mode */ 174 set_bit(idx, &cmd->bitmask); 175 spin_unlock_irqrestore(&cmd->alloc_lock, flags); 176 } 177 178 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx) 179 { 180 return cmd->cmd_buf + (idx << cmd->log_stride); 181 } 182 183 static u8 xor8_buf(void *buf, int len) 184 { 185 u8 *ptr = buf; 186 u8 sum = 0; 187 int i; 188 189 for (i = 0; i < len; i++) 190 sum ^= ptr[i]; 191 192 return sum; 193 } 194 195 static int verify_block_sig(struct mlx5_cmd_prot_block *block) 196 { 197 if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff) 198 return -EINVAL; 199 200 if (xor8_buf(block, sizeof(*block)) != 0xff) 201 return -EINVAL; 202 203 return 0; 204 } 205 206 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token, 207 int csum) 208 { 209 block->token = token; 210 if (csum) { 211 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) - 212 sizeof(block->data) - 2); 213 block->sig = ~xor8_buf(block, sizeof(*block) - 1); 214 } 215 } 216 217 static void 218 calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum) 219 { 220 size_t i; 221 222 for (i = 0; i != (msg->numpages * MLX5_NUM_CMDS_IN_ADAPTER_PAGE); i++) { 223 struct mlx5_cmd_prot_block *block; 224 225 block = mlx5_fwp_get_virt(msg, i * MLX5_CMD_MBOX_SIZE); 226 227 /* compute signature */ 228 calc_block_sig(block, token, csum); 229 230 /* check for last block */ 231 if (block->next == 0) 232 break; 233 } 234 235 /* make sure data gets written to RAM */ 236 mlx5_fwp_flush(msg); 237 } 238 239 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum) 240 { 241 ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay)); 242 calc_chain_sig(ent->in, ent->token, csum); 243 calc_chain_sig(ent->out, ent->token, csum); 244 } 245 246 static void poll_timeout(struct mlx5_cmd_work_ent *ent) 247 { 248 struct mlx5_core_dev *dev = container_of(ent->cmd, 249 struct mlx5_core_dev, cmd); 250 int poll_end = jiffies + 251 msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000); 252 u8 own; 253 254 do { 255 own = ent->lay->status_own; 256 if (!(own & CMD_OWNER_HW) || 257 dev->state != MLX5_DEVICE_STATE_UP) { 258 ent->ret = 0; 259 return; 260 } 261 usleep_range(5000, 10000); 262 } while (time_before(jiffies, poll_end)); 263 264 ent->ret = -ETIMEDOUT; 265 } 266 267 static void free_cmd(struct mlx5_cmd_work_ent *ent) 268 { 269 cancel_delayed_work_sync(&ent->cb_timeout_work); 270 kfree(ent); 271 } 272 273 static int 274 verify_signature(struct mlx5_cmd_work_ent *ent) 275 { 276 struct mlx5_cmd_msg *msg = ent->out; 277 size_t i; 278 int err; 279 u8 sig; 280 281 sig = xor8_buf(ent->lay, sizeof(*ent->lay)); 282 if (sig != 0xff) 283 return -EINVAL; 284 285 for (i = 0; i != (msg->numpages * MLX5_NUM_CMDS_IN_ADAPTER_PAGE); i++) { 286 struct mlx5_cmd_prot_block *block; 287 288 block = mlx5_fwp_get_virt(msg, i * MLX5_CMD_MBOX_SIZE); 289 290 /* compute signature */ 291 err = verify_block_sig(block); 292 if (err != 0) 293 return (err); 294 295 /* check for last block */ 296 if (block->next == 0) 297 break; 298 } 299 return (0); 300 } 301 302 static void dump_buf(void *buf, int size, int data_only, int offset) 303 { 304 __be32 *p = buf; 305 int i; 306 307 for (i = 0; i < size; i += 16) { 308 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]), 309 be32_to_cpu(p[1]), be32_to_cpu(p[2]), 310 be32_to_cpu(p[3])); 311 p += 4; 312 offset += 16; 313 } 314 if (!data_only) 315 pr_debug("\n"); 316 } 317 318 enum { 319 MLX5_DRIVER_STATUS_ABORTED = 0xfe, 320 MLX5_DRIVER_SYND = 0xbadd00de, 321 }; 322 323 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, 324 u32 *synd, u8 *status) 325 { 326 *synd = 0; 327 *status = 0; 328 329 switch (op) { 330 case MLX5_CMD_OP_TEARDOWN_HCA: 331 case MLX5_CMD_OP_DISABLE_HCA: 332 case MLX5_CMD_OP_MANAGE_PAGES: 333 case MLX5_CMD_OP_DESTROY_MKEY: 334 case MLX5_CMD_OP_DESTROY_EQ: 335 case MLX5_CMD_OP_DESTROY_CQ: 336 case MLX5_CMD_OP_DESTROY_QP: 337 case MLX5_CMD_OP_DESTROY_PSV: 338 case MLX5_CMD_OP_DESTROY_SRQ: 339 case MLX5_CMD_OP_DESTROY_XRC_SRQ: 340 case MLX5_CMD_OP_DESTROY_DCT: 341 case MLX5_CMD_OP_DEALLOC_Q_COUNTER: 342 case MLX5_CMD_OP_DEALLOC_PD: 343 case MLX5_CMD_OP_DEALLOC_UAR: 344 case MLX5_CMD_OP_DETACH_FROM_MCG: 345 case MLX5_CMD_OP_DEALLOC_XRCD: 346 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN: 347 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT: 348 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY: 349 case MLX5_CMD_OP_DESTROY_TIR: 350 case MLX5_CMD_OP_DESTROY_SQ: 351 case MLX5_CMD_OP_DESTROY_RQ: 352 case MLX5_CMD_OP_DESTROY_RMP: 353 case MLX5_CMD_OP_DESTROY_TIS: 354 case MLX5_CMD_OP_DESTROY_RQT: 355 case MLX5_CMD_OP_DESTROY_FLOW_TABLE: 356 case MLX5_CMD_OP_DESTROY_FLOW_GROUP: 357 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY: 358 case MLX5_CMD_OP_2ERR_QP: 359 case MLX5_CMD_OP_2RST_QP: 360 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT: 361 case MLX5_CMD_OP_MODIFY_FLOW_TABLE: 362 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 363 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT: 364 return MLX5_CMD_STAT_OK; 365 366 case MLX5_CMD_OP_QUERY_HCA_CAP: 367 case MLX5_CMD_OP_QUERY_ADAPTER: 368 case MLX5_CMD_OP_INIT_HCA: 369 case MLX5_CMD_OP_ENABLE_HCA: 370 case MLX5_CMD_OP_QUERY_PAGES: 371 case MLX5_CMD_OP_SET_HCA_CAP: 372 case MLX5_CMD_OP_QUERY_ISSI: 373 case MLX5_CMD_OP_SET_ISSI: 374 case MLX5_CMD_OP_CREATE_MKEY: 375 case MLX5_CMD_OP_QUERY_MKEY: 376 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS: 377 case MLX5_CMD_OP_PAGE_FAULT_RESUME: 378 case MLX5_CMD_OP_CREATE_EQ: 379 case MLX5_CMD_OP_QUERY_EQ: 380 case MLX5_CMD_OP_GEN_EQE: 381 case MLX5_CMD_OP_CREATE_CQ: 382 case MLX5_CMD_OP_QUERY_CQ: 383 case MLX5_CMD_OP_MODIFY_CQ: 384 case MLX5_CMD_OP_CREATE_QP: 385 case MLX5_CMD_OP_RST2INIT_QP: 386 case MLX5_CMD_OP_INIT2RTR_QP: 387 case MLX5_CMD_OP_RTR2RTS_QP: 388 case MLX5_CMD_OP_RTS2RTS_QP: 389 case MLX5_CMD_OP_SQERR2RTS_QP: 390 case MLX5_CMD_OP_QUERY_QP: 391 case MLX5_CMD_OP_SQD_RTS_QP: 392 case MLX5_CMD_OP_INIT2INIT_QP: 393 case MLX5_CMD_OP_CREATE_PSV: 394 case MLX5_CMD_OP_CREATE_SRQ: 395 case MLX5_CMD_OP_QUERY_SRQ: 396 case MLX5_CMD_OP_ARM_RQ: 397 case MLX5_CMD_OP_CREATE_XRC_SRQ: 398 case MLX5_CMD_OP_QUERY_XRC_SRQ: 399 case MLX5_CMD_OP_ARM_XRC_SRQ: 400 case MLX5_CMD_OP_CREATE_DCT: 401 case MLX5_CMD_OP_DRAIN_DCT: 402 case MLX5_CMD_OP_QUERY_DCT: 403 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION: 404 case MLX5_CMD_OP_QUERY_VPORT_STATE: 405 case MLX5_CMD_OP_MODIFY_VPORT_STATE: 406 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT: 407 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT: 408 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT: 409 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS: 410 case MLX5_CMD_OP_SET_ROCE_ADDRESS: 411 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT: 412 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT: 413 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID: 414 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY: 415 case MLX5_CMD_OP_QUERY_VPORT_COUNTER: 416 case MLX5_CMD_OP_ALLOC_Q_COUNTER: 417 case MLX5_CMD_OP_QUERY_Q_COUNTER: 418 case MLX5_CMD_OP_ALLOC_PD: 419 case MLX5_CMD_OP_ALLOC_UAR: 420 case MLX5_CMD_OP_CONFIG_INT_MODERATION: 421 case MLX5_CMD_OP_ACCESS_REG: 422 case MLX5_CMD_OP_ATTACH_TO_MCG: 423 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG: 424 case MLX5_CMD_OP_MAD_IFC: 425 case MLX5_CMD_OP_QUERY_MAD_DEMUX: 426 case MLX5_CMD_OP_SET_MAD_DEMUX: 427 case MLX5_CMD_OP_NOP: 428 case MLX5_CMD_OP_ALLOC_XRCD: 429 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN: 430 case MLX5_CMD_OP_QUERY_CONG_STATUS: 431 case MLX5_CMD_OP_MODIFY_CONG_STATUS: 432 case MLX5_CMD_OP_QUERY_CONG_PARAMS: 433 case MLX5_CMD_OP_MODIFY_CONG_PARAMS: 434 case MLX5_CMD_OP_QUERY_CONG_STATISTICS: 435 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 436 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 437 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY: 438 case MLX5_CMD_OP_CREATE_TIR: 439 case MLX5_CMD_OP_MODIFY_TIR: 440 case MLX5_CMD_OP_QUERY_TIR: 441 case MLX5_CMD_OP_CREATE_SQ: 442 case MLX5_CMD_OP_MODIFY_SQ: 443 case MLX5_CMD_OP_QUERY_SQ: 444 case MLX5_CMD_OP_CREATE_RQ: 445 case MLX5_CMD_OP_MODIFY_RQ: 446 case MLX5_CMD_OP_QUERY_RQ: 447 case MLX5_CMD_OP_CREATE_RMP: 448 case MLX5_CMD_OP_MODIFY_RMP: 449 case MLX5_CMD_OP_QUERY_RMP: 450 case MLX5_CMD_OP_CREATE_TIS: 451 case MLX5_CMD_OP_MODIFY_TIS: 452 case MLX5_CMD_OP_QUERY_TIS: 453 case MLX5_CMD_OP_CREATE_RQT: 454 case MLX5_CMD_OP_MODIFY_RQT: 455 case MLX5_CMD_OP_QUERY_RQT: 456 case MLX5_CMD_OP_CREATE_FLOW_TABLE: 457 case MLX5_CMD_OP_QUERY_FLOW_TABLE: 458 case MLX5_CMD_OP_CREATE_FLOW_GROUP: 459 case MLX5_CMD_OP_QUERY_FLOW_GROUP: 460 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY: 461 *status = MLX5_DRIVER_STATUS_ABORTED; 462 *synd = MLX5_DRIVER_SYND; 463 return -EIO; 464 default: 465 mlx5_core_err(dev, "Unknown FW command (%d)\n", op); 466 return -EINVAL; 467 } 468 } 469 470 const char *mlx5_command_str(int command) 471 { 472 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd 473 474 switch (command) { 475 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP); 476 MLX5_COMMAND_STR_CASE(SET_HCA_CAP); 477 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER); 478 MLX5_COMMAND_STR_CASE(INIT_HCA); 479 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA); 480 MLX5_COMMAND_STR_CASE(ENABLE_HCA); 481 MLX5_COMMAND_STR_CASE(DISABLE_HCA); 482 MLX5_COMMAND_STR_CASE(QUERY_PAGES); 483 MLX5_COMMAND_STR_CASE(MANAGE_PAGES); 484 MLX5_COMMAND_STR_CASE(QUERY_ISSI); 485 MLX5_COMMAND_STR_CASE(SET_ISSI); 486 MLX5_COMMAND_STR_CASE(CREATE_MKEY); 487 MLX5_COMMAND_STR_CASE(QUERY_MKEY); 488 MLX5_COMMAND_STR_CASE(DESTROY_MKEY); 489 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS); 490 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME); 491 MLX5_COMMAND_STR_CASE(CREATE_EQ); 492 MLX5_COMMAND_STR_CASE(DESTROY_EQ); 493 MLX5_COMMAND_STR_CASE(QUERY_EQ); 494 MLX5_COMMAND_STR_CASE(GEN_EQE); 495 MLX5_COMMAND_STR_CASE(CREATE_CQ); 496 MLX5_COMMAND_STR_CASE(DESTROY_CQ); 497 MLX5_COMMAND_STR_CASE(QUERY_CQ); 498 MLX5_COMMAND_STR_CASE(MODIFY_CQ); 499 MLX5_COMMAND_STR_CASE(CREATE_QP); 500 MLX5_COMMAND_STR_CASE(DESTROY_QP); 501 MLX5_COMMAND_STR_CASE(RST2INIT_QP); 502 MLX5_COMMAND_STR_CASE(INIT2RTR_QP); 503 MLX5_COMMAND_STR_CASE(RTR2RTS_QP); 504 MLX5_COMMAND_STR_CASE(RTS2RTS_QP); 505 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP); 506 MLX5_COMMAND_STR_CASE(2ERR_QP); 507 MLX5_COMMAND_STR_CASE(2RST_QP); 508 MLX5_COMMAND_STR_CASE(QUERY_QP); 509 MLX5_COMMAND_STR_CASE(SQD_RTS_QP); 510 MLX5_COMMAND_STR_CASE(MAD_IFC); 511 MLX5_COMMAND_STR_CASE(INIT2INIT_QP); 512 MLX5_COMMAND_STR_CASE(CREATE_PSV); 513 MLX5_COMMAND_STR_CASE(DESTROY_PSV); 514 MLX5_COMMAND_STR_CASE(CREATE_SRQ); 515 MLX5_COMMAND_STR_CASE(DESTROY_SRQ); 516 MLX5_COMMAND_STR_CASE(QUERY_SRQ); 517 MLX5_COMMAND_STR_CASE(ARM_RQ); 518 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ); 519 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ); 520 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ); 521 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ); 522 MLX5_COMMAND_STR_CASE(CREATE_DCT); 523 MLX5_COMMAND_STR_CASE(SET_DC_CNAK_TRACE); 524 MLX5_COMMAND_STR_CASE(DESTROY_DCT); 525 MLX5_COMMAND_STR_CASE(DRAIN_DCT); 526 MLX5_COMMAND_STR_CASE(QUERY_DCT); 527 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION); 528 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE); 529 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE); 530 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT); 531 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT); 532 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT); 533 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT); 534 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS); 535 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS); 536 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT); 537 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT); 538 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID); 539 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY); 540 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER); 541 MLX5_COMMAND_STR_CASE(SET_WOL_ROL); 542 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL); 543 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER); 544 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER); 545 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER); 546 MLX5_COMMAND_STR_CASE(ALLOC_PD); 547 MLX5_COMMAND_STR_CASE(DEALLOC_PD); 548 MLX5_COMMAND_STR_CASE(ALLOC_UAR); 549 MLX5_COMMAND_STR_CASE(DEALLOC_UAR); 550 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION); 551 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG); 552 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG); 553 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG); 554 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX); 555 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX); 556 MLX5_COMMAND_STR_CASE(NOP); 557 MLX5_COMMAND_STR_CASE(ALLOC_XRCD); 558 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD); 559 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN); 560 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN); 561 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS); 562 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS); 563 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS); 564 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS); 565 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS); 566 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT); 567 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT); 568 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY); 569 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY); 570 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY); 571 MLX5_COMMAND_STR_CASE(CREATE_RMP); 572 MLX5_COMMAND_STR_CASE(MODIFY_RMP); 573 MLX5_COMMAND_STR_CASE(DESTROY_RMP); 574 MLX5_COMMAND_STR_CASE(QUERY_RMP); 575 MLX5_COMMAND_STR_CASE(CREATE_RQT); 576 MLX5_COMMAND_STR_CASE(MODIFY_RQT); 577 MLX5_COMMAND_STR_CASE(DESTROY_RQT); 578 MLX5_COMMAND_STR_CASE(QUERY_RQT); 579 MLX5_COMMAND_STR_CASE(ACCESS_REG); 580 MLX5_COMMAND_STR_CASE(CREATE_SQ); 581 MLX5_COMMAND_STR_CASE(MODIFY_SQ); 582 MLX5_COMMAND_STR_CASE(DESTROY_SQ); 583 MLX5_COMMAND_STR_CASE(QUERY_SQ); 584 MLX5_COMMAND_STR_CASE(CREATE_RQ); 585 MLX5_COMMAND_STR_CASE(MODIFY_RQ); 586 MLX5_COMMAND_STR_CASE(DESTROY_RQ); 587 MLX5_COMMAND_STR_CASE(QUERY_RQ); 588 MLX5_COMMAND_STR_CASE(CREATE_TIR); 589 MLX5_COMMAND_STR_CASE(MODIFY_TIR); 590 MLX5_COMMAND_STR_CASE(DESTROY_TIR); 591 MLX5_COMMAND_STR_CASE(QUERY_TIR); 592 MLX5_COMMAND_STR_CASE(CREATE_TIS); 593 MLX5_COMMAND_STR_CASE(MODIFY_TIS); 594 MLX5_COMMAND_STR_CASE(DESTROY_TIS); 595 MLX5_COMMAND_STR_CASE(QUERY_TIS); 596 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE); 597 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE); 598 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE); 599 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP); 600 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP); 601 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP); 602 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY); 603 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY); 604 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY); 605 MLX5_COMMAND_STR_CASE(SET_DIAGNOSTICS); 606 MLX5_COMMAND_STR_CASE(QUERY_DIAGNOSTICS); 607 default: return "unknown command opcode"; 608 } 609 } 610 611 static const char *cmd_status_str(u8 status) 612 { 613 switch (status) { 614 case MLX5_CMD_STAT_OK: 615 return "OK"; 616 case MLX5_CMD_STAT_INT_ERR: 617 return "internal error"; 618 case MLX5_CMD_STAT_BAD_OP_ERR: 619 return "bad operation"; 620 case MLX5_CMD_STAT_BAD_PARAM_ERR: 621 return "bad parameter"; 622 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: 623 return "bad system state"; 624 case MLX5_CMD_STAT_BAD_RES_ERR: 625 return "bad resource"; 626 case MLX5_CMD_STAT_RES_BUSY: 627 return "resource busy"; 628 case MLX5_CMD_STAT_LIM_ERR: 629 return "limits exceeded"; 630 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: 631 return "bad resource state"; 632 case MLX5_CMD_STAT_IX_ERR: 633 return "bad index"; 634 case MLX5_CMD_STAT_NO_RES_ERR: 635 return "no resources"; 636 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: 637 return "bad input length"; 638 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: 639 return "bad output length"; 640 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: 641 return "bad QP state"; 642 case MLX5_CMD_STAT_BAD_PKT_ERR: 643 return "bad packet (discarded)"; 644 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: 645 return "bad size too many outstanding CQEs"; 646 default: 647 return "unknown status"; 648 } 649 } 650 651 static int cmd_status_to_err_helper(u8 status) 652 { 653 switch (status) { 654 case MLX5_CMD_STAT_OK: return 0; 655 case MLX5_CMD_STAT_INT_ERR: return -EIO; 656 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL; 657 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL; 658 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO; 659 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL; 660 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY; 661 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM; 662 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL; 663 case MLX5_CMD_STAT_IX_ERR: return -EINVAL; 664 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN; 665 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO; 666 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO; 667 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL; 668 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL; 669 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL; 670 default: return -EIO; 671 } 672 } 673 674 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome) 675 { 676 *status = MLX5_GET(mbox_out, out, status); 677 *syndrome = MLX5_GET(mbox_out, out, syndrome); 678 } 679 680 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out) 681 { 682 u32 syndrome; 683 u8 status; 684 u16 opcode; 685 u16 op_mod; 686 687 mlx5_cmd_mbox_status(out, &status, &syndrome); 688 if (!status) 689 return 0; 690 691 opcode = MLX5_GET(mbox_in, in, opcode); 692 op_mod = MLX5_GET(mbox_in, in, op_mod); 693 694 mlx5_core_err(dev, 695 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n", 696 mlx5_command_str(opcode), 697 opcode, op_mod, 698 cmd_status_str(status), 699 status, 700 syndrome); 701 702 return cmd_status_to_err_helper(status); 703 } 704 705 static void dump_command(struct mlx5_core_dev *dev, 706 struct mlx5_cmd_work_ent *ent, int input) 707 { 708 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out; 709 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode); 710 size_t i; 711 int data_only; 712 int offset = 0; 713 int msg_len = input ? ent->uin_size : ent->uout_size; 714 int dump_len; 715 716 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA)); 717 718 if (data_only) 719 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA, 720 "dump command data %s(0x%x) %s\n", 721 mlx5_command_str(op), op, 722 input ? "INPUT" : "OUTPUT"); 723 else 724 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n", 725 mlx5_command_str(op), op, 726 input ? "INPUT" : "OUTPUT"); 727 728 if (data_only) { 729 if (input) { 730 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset); 731 offset += sizeof(ent->lay->in); 732 } else { 733 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset); 734 offset += sizeof(ent->lay->out); 735 } 736 } else { 737 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset); 738 offset += sizeof(*ent->lay); 739 } 740 741 for (i = 0; i != (msg->numpages * MLX5_NUM_CMDS_IN_ADAPTER_PAGE); i++) { 742 struct mlx5_cmd_prot_block *block; 743 744 block = mlx5_fwp_get_virt(msg, i * MLX5_CMD_MBOX_SIZE); 745 746 if (data_only) { 747 if (offset >= msg_len) 748 break; 749 dump_len = min_t(int, 750 MLX5_CMD_DATA_BLOCK_SIZE, msg_len - offset); 751 752 dump_buf(block->data, dump_len, 1, offset); 753 offset += MLX5_CMD_DATA_BLOCK_SIZE; 754 } else { 755 mlx5_core_dbg(dev, "command block:\n"); 756 dump_buf(block, sizeof(*block), 0, offset); 757 offset += sizeof(*block); 758 } 759 760 /* check for last block */ 761 if (block->next == 0) 762 break; 763 } 764 765 if (data_only) 766 pr_debug("\n"); 767 } 768 769 static u16 msg_to_opcode(struct mlx5_cmd_msg *in) 770 { 771 return MLX5_GET(mbox_in, in->first.data, opcode); 772 } 773 774 static void cb_timeout_handler(struct work_struct *work) 775 { 776 struct delayed_work *dwork = container_of(work, struct delayed_work, 777 work); 778 struct mlx5_cmd_work_ent *ent = container_of(dwork, 779 struct mlx5_cmd_work_ent, 780 cb_timeout_work); 781 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev, 782 cmd); 783 784 ent->ret = -ETIMEDOUT; 785 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n", 786 mlx5_command_str(msg_to_opcode(ent->in)), 787 msg_to_opcode(ent->in)); 788 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, MLX5_CMD_MODE_EVENTS); 789 } 790 791 static void complete_command(struct mlx5_cmd_work_ent *ent) 792 { 793 struct mlx5_cmd *cmd = ent->cmd; 794 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, 795 cmd); 796 mlx5_cmd_cbk_t callback; 797 void *context; 798 799 s64 ds; 800 struct mlx5_cmd_stats *stats; 801 unsigned long flags; 802 int err; 803 struct semaphore *sem; 804 805 if (ent->page_queue) 806 sem = &cmd->pages_sem; 807 else 808 sem = &cmd->sem; 809 810 if (dev->state != MLX5_DEVICE_STATE_UP) { 811 u8 status = 0; 812 u32 drv_synd; 813 814 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status); 815 MLX5_SET(mbox_out, ent->out, status, status); 816 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd); 817 } 818 819 if (ent->callback) { 820 ds = ent->ts2 - ent->ts1; 821 if (ent->op < ARRAY_SIZE(cmd->stats)) { 822 stats = &cmd->stats[ent->op]; 823 spin_lock_irqsave(&stats->lock, flags); 824 stats->sum += ds; 825 ++stats->n; 826 spin_unlock_irqrestore(&stats->lock, flags); 827 } 828 829 callback = ent->callback; 830 context = ent->context; 831 err = ent->ret; 832 if (!err) { 833 err = mlx5_copy_from_msg(ent->uout, 834 ent->out, 835 ent->uout_size); 836 err = err ? err : mlx5_cmd_check(dev, 837 ent->in->first.data, 838 ent->uout); 839 } 840 841 mlx5_free_cmd_msg(dev, ent->out); 842 free_msg(dev, ent->in); 843 844 err = err ? err : ent->status; 845 free_cmd(ent); 846 callback(err, context); 847 } else { 848 complete(&ent->done); 849 } 850 up(sem); 851 } 852 853 static void cmd_work_handler(struct work_struct *work) 854 { 855 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work); 856 struct mlx5_cmd *cmd = ent->cmd; 857 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd); 858 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC); 859 struct mlx5_cmd_layout *lay; 860 struct semaphore *sem; 861 bool poll_cmd = ent->polling; 862 863 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem; 864 down(sem); 865 866 if (alloc_ent(ent) < 0) { 867 complete_command(ent); 868 return; 869 } 870 871 ent->token = alloc_token(cmd); 872 lay = get_inst(cmd, ent->idx); 873 ent->lay = lay; 874 memset(lay, 0, sizeof(*lay)); 875 memcpy(lay->in, ent->in->first.data, sizeof(lay->in)); 876 ent->op = be32_to_cpu(lay->in[0]) >> 16; 877 if (ent->in->numpages != 0) 878 lay->in_ptr = cpu_to_be64(mlx5_fwp_get_dma(ent->in, 0)); 879 if (ent->out->numpages != 0) 880 lay->out_ptr = cpu_to_be64(mlx5_fwp_get_dma(ent->out, 0)); 881 lay->inlen = cpu_to_be32(ent->uin_size); 882 lay->outlen = cpu_to_be32(ent->uout_size); 883 lay->type = MLX5_PCI_CMD_XPORT; 884 lay->token = ent->token; 885 lay->status_own = CMD_OWNER_HW; 886 set_signature(ent, !cmd->checksum_disabled); 887 dump_command(dev, ent, 1); 888 ent->ts1 = ktime_get_ns(); 889 ent->busy = 0; 890 if (ent->callback) 891 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout); 892 893 /* ring doorbell after the descriptor is valid */ 894 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx); 895 /* make sure data is written to RAM */ 896 mlx5_fwp_flush(cmd->cmd_page); 897 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell); 898 mmiowb(); 899 900 /* if not in polling don't use ent after this point */ 901 if (poll_cmd) { 902 poll_timeout(ent); 903 /* make sure we read the descriptor after ownership is SW */ 904 mlx5_cmd_comp_handler(dev, 1U << ent->idx, MLX5_CMD_MODE_POLLING); 905 } 906 } 907 908 static const char *deliv_status_to_str(u8 status) 909 { 910 switch (status) { 911 case MLX5_CMD_DELIVERY_STAT_OK: 912 return "no errors"; 913 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR: 914 return "signature error"; 915 case MLX5_CMD_DELIVERY_STAT_TOK_ERR: 916 return "token error"; 917 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR: 918 return "bad block number"; 919 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR: 920 return "output pointer not aligned to block size"; 921 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR: 922 return "input pointer not aligned to block size"; 923 case MLX5_CMD_DELIVERY_STAT_FW_ERR: 924 return "firmware internal error"; 925 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR: 926 return "command input length error"; 927 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR: 928 return "command ouput length error"; 929 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR: 930 return "reserved fields not cleared"; 931 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR: 932 return "bad command descriptor type"; 933 default: 934 return "unknown status code"; 935 } 936 } 937 938 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent) 939 { 940 int timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC); 941 int err; 942 943 if (ent->polling) { 944 wait_for_completion(&ent->done); 945 } else if (!wait_for_completion_timeout(&ent->done, timeout)) { 946 ent->ret = -ETIMEDOUT; 947 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, MLX5_CMD_MODE_EVENTS); 948 } 949 950 err = ent->ret; 951 952 if (err == -ETIMEDOUT) { 953 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n", 954 mlx5_command_str(msg_to_opcode(ent->in)), 955 msg_to_opcode(ent->in)); 956 } 957 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n", 958 err, deliv_status_to_str(ent->status), ent->status); 959 960 return err; 961 } 962 963 /* Notes: 964 * 1. Callback functions may not sleep 965 * 2. page queue commands do not support asynchrous completion 966 */ 967 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in, 968 int uin_size, 969 struct mlx5_cmd_msg *out, void *uout, int uout_size, 970 mlx5_cmd_cbk_t callback, 971 void *context, int page_queue, u8 *status, 972 bool force_polling) 973 { 974 struct mlx5_cmd *cmd = &dev->cmd; 975 struct mlx5_cmd_work_ent *ent; 976 struct mlx5_cmd_stats *stats; 977 int err = 0; 978 s64 ds; 979 u16 op; 980 981 if (callback && page_queue) 982 return -EINVAL; 983 984 ent = alloc_cmd(cmd, in, uin_size, out, uout, uout_size, callback, 985 context, page_queue); 986 if (IS_ERR(ent)) 987 return PTR_ERR(ent); 988 989 ent->polling = force_polling || (cmd->mode == MLX5_CMD_MODE_POLLING); 990 991 if (!callback) 992 init_completion(&ent->done); 993 994 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler); 995 INIT_WORK(&ent->work, cmd_work_handler); 996 if (page_queue) { 997 cmd_work_handler(&ent->work); 998 } else if (!queue_work(cmd->wq, &ent->work)) { 999 mlx5_core_warn(dev, "failed to queue work\n"); 1000 err = -ENOMEM; 1001 goto out_free; 1002 } 1003 1004 if (callback) 1005 goto out; 1006 1007 err = wait_func(dev, ent); 1008 if (err == -ETIMEDOUT) 1009 goto out; 1010 1011 ds = ent->ts2 - ent->ts1; 1012 op = MLX5_GET(mbox_in, in->first.data, opcode); 1013 if (op < ARRAY_SIZE(cmd->stats)) { 1014 stats = &cmd->stats[op]; 1015 spin_lock_irq(&stats->lock); 1016 stats->sum += ds; 1017 ++stats->n; 1018 spin_unlock_irq(&stats->lock); 1019 } 1020 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME, 1021 "fw exec time for %s is %lld nsec\n", 1022 mlx5_command_str(op), (long long)ds); 1023 *status = ent->status; 1024 free_cmd(ent); 1025 1026 return err; 1027 1028 out_free: 1029 free_cmd(ent); 1030 out: 1031 return err; 1032 } 1033 1034 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, size_t size) 1035 { 1036 size_t delta; 1037 size_t i; 1038 1039 if (to == NULL || from == NULL) 1040 return (-ENOMEM); 1041 1042 delta = min_t(size_t, size, sizeof(to->first.data)); 1043 memcpy(to->first.data, from, delta); 1044 from = (char *)from + delta; 1045 size -= delta; 1046 1047 for (i = 0; size != 0; i++) { 1048 struct mlx5_cmd_prot_block *block; 1049 1050 block = mlx5_fwp_get_virt(to, i * MLX5_CMD_MBOX_SIZE); 1051 1052 delta = min_t(size_t, size, MLX5_CMD_DATA_BLOCK_SIZE); 1053 memcpy(block->data, from, delta); 1054 from = (char *)from + delta; 1055 size -= delta; 1056 } 1057 return (0); 1058 } 1059 1060 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size) 1061 { 1062 size_t delta; 1063 size_t i; 1064 1065 if (to == NULL || from == NULL) 1066 return (-ENOMEM); 1067 1068 delta = min_t(size_t, size, sizeof(from->first.data)); 1069 memcpy(to, from->first.data, delta); 1070 to = (char *)to + delta; 1071 size -= delta; 1072 1073 for (i = 0; size != 0; i++) { 1074 struct mlx5_cmd_prot_block *block; 1075 1076 block = mlx5_fwp_get_virt(from, i * MLX5_CMD_MBOX_SIZE); 1077 1078 delta = min_t(size_t, size, MLX5_CMD_DATA_BLOCK_SIZE); 1079 memcpy(to, block->data, delta); 1080 to = (char *)to + delta; 1081 size -= delta; 1082 } 1083 return (0); 1084 } 1085 1086 static struct mlx5_cmd_msg * 1087 mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev, gfp_t flags, size_t size) 1088 { 1089 struct mlx5_cmd_msg *msg; 1090 size_t blen; 1091 size_t n; 1092 size_t i; 1093 1094 blen = size - min_t(size_t, sizeof(msg->first.data), size); 1095 n = howmany(blen, MLX5_CMD_DATA_BLOCK_SIZE); 1096 1097 msg = mlx5_fwp_alloc(dev, flags, howmany(n, MLX5_NUM_CMDS_IN_ADAPTER_PAGE)); 1098 if (msg == NULL) 1099 return (ERR_PTR(-ENOMEM)); 1100 1101 for (i = 0; i != n; i++) { 1102 struct mlx5_cmd_prot_block *block; 1103 1104 block = mlx5_fwp_get_virt(msg, i * MLX5_CMD_MBOX_SIZE); 1105 1106 memset(block, 0, MLX5_CMD_MBOX_SIZE); 1107 1108 if (i != (n - 1)) { 1109 u64 dma = mlx5_fwp_get_dma(msg, (i + 1) * MLX5_CMD_MBOX_SIZE); 1110 block->next = cpu_to_be64(dma); 1111 } 1112 block->block_num = cpu_to_be32(i); 1113 } 1114 1115 /* make sure initial data is written to RAM */ 1116 mlx5_fwp_flush(msg); 1117 1118 return (msg); 1119 } 1120 1121 static void 1122 mlx5_free_cmd_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg) 1123 { 1124 1125 mlx5_fwp_free(msg); 1126 } 1127 1128 static void set_wqname(struct mlx5_core_dev *dev) 1129 { 1130 struct mlx5_cmd *cmd = &dev->cmd; 1131 1132 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s", 1133 dev_name(&dev->pdev->dev)); 1134 } 1135 1136 static void clean_debug_files(struct mlx5_core_dev *dev) 1137 { 1138 } 1139 1140 1141 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode) 1142 { 1143 struct mlx5_cmd *cmd = &dev->cmd; 1144 int i; 1145 1146 if (cmd->mode == mode) 1147 return; 1148 1149 for (i = 0; i < cmd->max_reg_cmds; i++) 1150 down(&cmd->sem); 1151 1152 down(&cmd->pages_sem); 1153 cmd->mode = mode; 1154 1155 up(&cmd->pages_sem); 1156 for (i = 0; i < cmd->max_reg_cmds; i++) 1157 up(&cmd->sem); 1158 } 1159 1160 void mlx5_cmd_use_events(struct mlx5_core_dev *dev) 1161 { 1162 mlx5_cmd_change_mod(dev, MLX5_CMD_MODE_EVENTS); 1163 } 1164 1165 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev) 1166 { 1167 mlx5_cmd_change_mod(dev, MLX5_CMD_MODE_POLLING); 1168 } 1169 1170 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg) 1171 { 1172 unsigned long flags; 1173 1174 if (msg->cache) { 1175 spin_lock_irqsave(&msg->cache->lock, flags); 1176 list_add_tail(&msg->list, &msg->cache->head); 1177 spin_unlock_irqrestore(&msg->cache->lock, flags); 1178 } else { 1179 mlx5_free_cmd_msg(dev, msg); 1180 } 1181 } 1182 1183 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector_flags, 1184 enum mlx5_cmd_mode cmd_mode) 1185 { 1186 struct mlx5_cmd *cmd = &dev->cmd; 1187 struct mlx5_cmd_work_ent *ent; 1188 bool triggered = (vector_flags & MLX5_TRIGGERED_CMD_COMP) ? 1 : 0; 1189 u32 vector = vector_flags; /* discard flags in the upper dword */ 1190 int i; 1191 1192 /* make sure data gets read from RAM */ 1193 mlx5_fwp_invalidate(cmd->cmd_page); 1194 1195 while (vector != 0) { 1196 i = ffs(vector) - 1; 1197 vector &= ~(1U << i); 1198 /* check command mode */ 1199 if (cmd->ent_mode[i] != cmd_mode) 1200 continue; 1201 ent = cmd->ent_arr[i]; 1202 /* check if command was already handled */ 1203 if (ent == NULL) 1204 continue; 1205 if (ent->callback) 1206 cancel_delayed_work(&ent->cb_timeout_work); 1207 ent->ts2 = ktime_get_ns(); 1208 memcpy(ent->out->first.data, ent->lay->out, 1209 sizeof(ent->lay->out)); 1210 /* make sure data gets read from RAM */ 1211 mlx5_fwp_invalidate(ent->out); 1212 dump_command(dev, ent, 0); 1213 if (!ent->ret) { 1214 if (!cmd->checksum_disabled) 1215 ent->ret = verify_signature(ent); 1216 else 1217 ent->ret = 0; 1218 1219 if (triggered) 1220 ent->status = MLX5_DRIVER_STATUS_ABORTED; 1221 else 1222 ent->status = ent->lay->status_own >> 1; 1223 1224 mlx5_core_dbg(dev, 1225 "FW command ret 0x%x, status %s(0x%x)\n", 1226 ent->ret, 1227 deliv_status_to_str(ent->status), 1228 ent->status); 1229 } 1230 free_ent(cmd, ent->idx); 1231 complete_command(ent); 1232 } 1233 } 1234 EXPORT_SYMBOL(mlx5_cmd_comp_handler); 1235 1236 static int status_to_err(u8 status) 1237 { 1238 return status ? -EIO : 0; /* TBD more meaningful codes */ 1239 } 1240 1241 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size, 1242 gfp_t gfp) 1243 { 1244 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM); 1245 struct mlx5_cmd *cmd = &dev->cmd; 1246 struct cache_ent *ent = NULL; 1247 1248 if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE) 1249 ent = &cmd->cache.large; 1250 else if (in_size > 16 && in_size <= MED_LIST_SIZE) 1251 ent = &cmd->cache.med; 1252 1253 if (ent) { 1254 spin_lock_irq(&ent->lock); 1255 if (!list_empty(&ent->head)) { 1256 msg = list_entry(ent->head.next, struct mlx5_cmd_msg, 1257 list); 1258 list_del(&msg->list); 1259 } 1260 spin_unlock_irq(&ent->lock); 1261 } 1262 1263 if (IS_ERR(msg)) 1264 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size); 1265 1266 return msg; 1267 } 1268 1269 static int is_manage_pages(void *in) 1270 { 1271 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES; 1272 } 1273 1274 static int cmd_exec_helper(struct mlx5_core_dev *dev, 1275 void *in, int in_size, 1276 void *out, int out_size, 1277 mlx5_cmd_cbk_t callback, void *context, 1278 bool force_polling) 1279 { 1280 struct mlx5_cmd_msg *inb; 1281 struct mlx5_cmd_msg *outb; 1282 int pages_queue; 1283 const gfp_t gfp = GFP_KERNEL; 1284 int err; 1285 u8 status = 0; 1286 u32 drv_synd; 1287 1288 if (pci_channel_offline(dev->pdev) || 1289 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1290 u16 opcode = MLX5_GET(mbox_in, in, opcode); 1291 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status); 1292 MLX5_SET(mbox_out, out, status, status); 1293 MLX5_SET(mbox_out, out, syndrome, drv_synd); 1294 return err; 1295 } 1296 1297 pages_queue = is_manage_pages(in); 1298 1299 inb = alloc_msg(dev, in_size, gfp); 1300 if (IS_ERR(inb)) { 1301 err = PTR_ERR(inb); 1302 return err; 1303 } 1304 1305 err = mlx5_copy_to_msg(inb, in, in_size); 1306 if (err) { 1307 mlx5_core_warn(dev, "err %d\n", err); 1308 goto out_in; 1309 } 1310 1311 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size); 1312 if (IS_ERR(outb)) { 1313 err = PTR_ERR(outb); 1314 goto out_in; 1315 } 1316 1317 err = mlx5_cmd_invoke(dev, inb, in_size, outb, out, out_size, callback, 1318 context, pages_queue, &status, force_polling); 1319 if (err) { 1320 if (err == -ETIMEDOUT) 1321 return err; 1322 goto out_out; 1323 } 1324 1325 mlx5_core_dbg(dev, "err %d, status %d\n", err, status); 1326 if (status) { 1327 err = status_to_err(status); 1328 goto out_out; 1329 } 1330 1331 if (callback) 1332 return err; 1333 1334 err = mlx5_copy_from_msg(out, outb, out_size); 1335 1336 out_out: 1337 mlx5_free_cmd_msg(dev, outb); 1338 1339 out_in: 1340 free_msg(dev, inb); 1341 return err; 1342 } 1343 1344 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 1345 int out_size) 1346 { 1347 int err; 1348 1349 err = cmd_exec_helper(dev, in, in_size, out, out_size, NULL, NULL, false); 1350 return err ? : mlx5_cmd_check(dev, in, out); 1351 } 1352 EXPORT_SYMBOL(mlx5_cmd_exec); 1353 1354 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 1355 void *out, int out_size, mlx5_cmd_cbk_t callback, 1356 void *context) 1357 { 1358 return cmd_exec_helper(dev, in, in_size, out, out_size, callback, context, false); 1359 } 1360 EXPORT_SYMBOL(mlx5_cmd_exec_cb); 1361 1362 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 1363 void *out, int out_size) 1364 { 1365 int err; 1366 1367 err = cmd_exec_helper(dev, in, in_size, out, out_size, NULL, NULL, true); 1368 return err ? : mlx5_cmd_check(dev, in, out); 1369 } 1370 EXPORT_SYMBOL(mlx5_cmd_exec_polling); 1371 1372 static void destroy_msg_cache(struct mlx5_core_dev *dev) 1373 { 1374 struct mlx5_cmd *cmd = &dev->cmd; 1375 struct mlx5_cmd_msg *msg; 1376 struct mlx5_cmd_msg *n; 1377 1378 list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) { 1379 list_del(&msg->list); 1380 mlx5_free_cmd_msg(dev, msg); 1381 } 1382 1383 list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) { 1384 list_del(&msg->list); 1385 mlx5_free_cmd_msg(dev, msg); 1386 } 1387 } 1388 1389 static int create_msg_cache(struct mlx5_core_dev *dev) 1390 { 1391 struct mlx5_cmd *cmd = &dev->cmd; 1392 struct mlx5_cmd_msg *msg; 1393 int err; 1394 int i; 1395 1396 spin_lock_init(&cmd->cache.large.lock); 1397 INIT_LIST_HEAD(&cmd->cache.large.head); 1398 spin_lock_init(&cmd->cache.med.lock); 1399 INIT_LIST_HEAD(&cmd->cache.med.head); 1400 1401 for (i = 0; i < NUM_LONG_LISTS; i++) { 1402 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE); 1403 if (IS_ERR(msg)) { 1404 err = PTR_ERR(msg); 1405 goto ex_err; 1406 } 1407 msg->cache = &cmd->cache.large; 1408 list_add_tail(&msg->list, &cmd->cache.large.head); 1409 } 1410 1411 for (i = 0; i < NUM_MED_LISTS; i++) { 1412 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE); 1413 if (IS_ERR(msg)) { 1414 err = PTR_ERR(msg); 1415 goto ex_err; 1416 } 1417 msg->cache = &cmd->cache.med; 1418 list_add_tail(&msg->list, &cmd->cache.med.head); 1419 } 1420 1421 return 0; 1422 1423 ex_err: 1424 destroy_msg_cache(dev); 1425 return err; 1426 } 1427 1428 static int 1429 alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd) 1430 { 1431 int err; 1432 1433 sx_init(&cmd->dma_sx, "MLX5-DMA-SX"); 1434 mtx_init(&cmd->dma_mtx, "MLX5-DMA-MTX", NULL, MTX_DEF); 1435 cv_init(&cmd->dma_cv, "MLX5-DMA-CV"); 1436 1437 /* 1438 * Create global DMA descriptor tag for allocating 1439 * 4K firmware pages: 1440 */ 1441 err = -bus_dma_tag_create( 1442 bus_get_dma_tag(dev->pdev->dev.bsddev), 1443 MLX5_ADAPTER_PAGE_SIZE, /* alignment */ 1444 0, /* no boundary */ 1445 BUS_SPACE_MAXADDR, /* lowaddr */ 1446 BUS_SPACE_MAXADDR, /* highaddr */ 1447 NULL, NULL, /* filter, filterarg */ 1448 MLX5_ADAPTER_PAGE_SIZE, /* maxsize */ 1449 1, /* nsegments */ 1450 MLX5_ADAPTER_PAGE_SIZE, /* maxsegsize */ 1451 0, /* flags */ 1452 NULL, NULL, /* lockfunc, lockfuncarg */ 1453 &cmd->dma_tag); 1454 if (err != 0) 1455 goto failure_destroy_sx; 1456 1457 cmd->cmd_page = mlx5_fwp_alloc(dev, GFP_KERNEL, 1); 1458 if (cmd->cmd_page == NULL) { 1459 err = -ENOMEM; 1460 goto failure_alloc_page; 1461 } 1462 cmd->dma = mlx5_fwp_get_dma(cmd->cmd_page, 0); 1463 cmd->cmd_buf = mlx5_fwp_get_virt(cmd->cmd_page, 0); 1464 return (0); 1465 1466 failure_alloc_page: 1467 bus_dma_tag_destroy(cmd->dma_tag); 1468 1469 failure_destroy_sx: 1470 cv_destroy(&cmd->dma_cv); 1471 mtx_destroy(&cmd->dma_mtx); 1472 sx_destroy(&cmd->dma_sx); 1473 return (err); 1474 } 1475 1476 static void 1477 free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd) 1478 { 1479 1480 mlx5_fwp_free(cmd->cmd_page); 1481 bus_dma_tag_destroy(cmd->dma_tag); 1482 cv_destroy(&cmd->dma_cv); 1483 mtx_destroy(&cmd->dma_mtx); 1484 sx_destroy(&cmd->dma_sx); 1485 } 1486 1487 int mlx5_cmd_init(struct mlx5_core_dev *dev) 1488 { 1489 struct mlx5_cmd *cmd = &dev->cmd; 1490 u32 cmd_h, cmd_l; 1491 u16 cmd_if_rev; 1492 int err; 1493 int i; 1494 1495 memset(cmd, 0, sizeof(*cmd)); 1496 cmd_if_rev = cmdif_rev_get(dev); 1497 if (cmd_if_rev != CMD_IF_REV) { 1498 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Driver cmdif rev(%d) differs from firmware's(%d)\n", CMD_IF_REV, cmd_if_rev); 1499 return -EINVAL; 1500 } 1501 1502 err = alloc_cmd_page(dev, cmd); 1503 if (err) 1504 goto err_free_pool; 1505 1506 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff; 1507 cmd->log_sz = cmd_l >> 4 & 0xf; 1508 cmd->log_stride = cmd_l & 0xf; 1509 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) { 1510 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""firmware reports too many outstanding commands %d\n", 1 << cmd->log_sz); 1511 err = -EINVAL; 1512 goto err_free_page; 1513 } 1514 1515 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) { 1516 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""command queue size overflow\n"); 1517 err = -EINVAL; 1518 goto err_free_page; 1519 } 1520 1521 cmd->checksum_disabled = 1; 1522 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1; 1523 cmd->bitmask = (1 << cmd->max_reg_cmds) - 1; 1524 1525 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 1526 if (cmd->cmdif_rev > CMD_IF_REV) { 1527 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""driver does not support command interface version. driver %d, firmware %d\n", CMD_IF_REV, cmd->cmdif_rev); 1528 err = -ENOTSUPP; 1529 goto err_free_page; 1530 } 1531 1532 spin_lock_init(&cmd->alloc_lock); 1533 spin_lock_init(&cmd->token_lock); 1534 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++) 1535 spin_lock_init(&cmd->stats[i].lock); 1536 1537 sema_init(&cmd->sem, cmd->max_reg_cmds); 1538 sema_init(&cmd->pages_sem, 1); 1539 1540 cmd_h = (u32)((u64)(cmd->dma) >> 32); 1541 cmd_l = (u32)(cmd->dma); 1542 if (cmd_l & 0xfff) { 1543 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""invalid command queue address\n"); 1544 err = -ENOMEM; 1545 goto err_free_page; 1546 } 1547 1548 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h); 1549 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz); 1550 1551 /* Make sure firmware sees the complete address before we proceed */ 1552 wmb(); 1553 1554 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma)); 1555 1556 cmd->mode = MLX5_CMD_MODE_POLLING; 1557 1558 err = create_msg_cache(dev); 1559 if (err) { 1560 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""failed to create command cache\n"); 1561 goto err_free_page; 1562 } 1563 1564 set_wqname(dev); 1565 cmd->wq = create_singlethread_workqueue(cmd->wq_name); 1566 if (!cmd->wq) { 1567 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""failed to create command workqueue\n"); 1568 err = -ENOMEM; 1569 goto err_cache; 1570 } 1571 1572 return 0; 1573 1574 err_cache: 1575 destroy_msg_cache(dev); 1576 1577 err_free_page: 1578 free_cmd_page(dev, cmd); 1579 1580 err_free_pool: 1581 return err; 1582 } 1583 EXPORT_SYMBOL(mlx5_cmd_init); 1584 1585 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev) 1586 { 1587 struct mlx5_cmd *cmd = &dev->cmd; 1588 1589 clean_debug_files(dev); 1590 destroy_workqueue(cmd->wq); 1591 destroy_msg_cache(dev); 1592 free_cmd_page(dev, cmd); 1593 } 1594 EXPORT_SYMBOL(mlx5_cmd_cleanup); 1595 1596 int mlx5_cmd_query_cong_counter(struct mlx5_core_dev *dev, 1597 bool reset, void *out, int out_size) 1598 { 1599 u32 in[MLX5_ST_SZ_DW(query_cong_statistics_in)] = { }; 1600 1601 MLX5_SET(query_cong_statistics_in, in, opcode, 1602 MLX5_CMD_OP_QUERY_CONG_STATISTICS); 1603 MLX5_SET(query_cong_statistics_in, in, clear, reset); 1604 return mlx5_cmd_exec(dev, in, sizeof(in), out, out_size); 1605 } 1606 EXPORT_SYMBOL(mlx5_cmd_query_cong_counter); 1607 1608 int mlx5_cmd_query_cong_params(struct mlx5_core_dev *dev, int cong_point, 1609 void *out, int out_size) 1610 { 1611 u32 in[MLX5_ST_SZ_DW(query_cong_params_in)] = { }; 1612 1613 MLX5_SET(query_cong_params_in, in, opcode, 1614 MLX5_CMD_OP_QUERY_CONG_PARAMS); 1615 MLX5_SET(query_cong_params_in, in, cong_protocol, cong_point); 1616 1617 return mlx5_cmd_exec(dev, in, sizeof(in), out, out_size); 1618 } 1619 EXPORT_SYMBOL(mlx5_cmd_query_cong_params); 1620 1621 int mlx5_cmd_modify_cong_params(struct mlx5_core_dev *dev, 1622 void *in, int in_size) 1623 { 1624 u32 out[MLX5_ST_SZ_DW(modify_cong_params_out)] = { }; 1625 1626 return mlx5_cmd_exec(dev, in, in_size, out, sizeof(out)); 1627 } 1628 EXPORT_SYMBOL(mlx5_cmd_modify_cong_params); 1629