1 /*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "opt_rss.h" 29 #include "opt_ratelimit.h" 30 31 #include <linux/module.h> 32 #include <linux/errno.h> 33 #include <linux/pci.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/slab.h> 36 #include <linux/delay.h> 37 #include <linux/random.h> 38 #include <linux/io-mapping.h> 39 #include <linux/hardirq.h> 40 #include <linux/ktime.h> 41 #include <dev/mlx5/driver.h> 42 #include <dev/mlx5/cmd.h> 43 44 #include "mlx5_core.h" 45 46 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size); 47 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev, 48 struct mlx5_cmd_msg *msg); 49 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg); 50 51 enum { 52 CMD_IF_REV = 5, 53 }; 54 55 enum { 56 NUM_LONG_LISTS = 2, 57 NUM_MED_LISTS = 64, 58 LONG_LIST_SIZE = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 + 59 MLX5_CMD_DATA_BLOCK_SIZE, 60 MED_LIST_SIZE = 16 + MLX5_CMD_DATA_BLOCK_SIZE, 61 }; 62 63 enum { 64 MLX5_CMD_DELIVERY_STAT_OK = 0x0, 65 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1, 66 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2, 67 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3, 68 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4, 69 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5, 70 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6, 71 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7, 72 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8, 73 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9, 74 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10, 75 }; 76 77 struct mlx5_ifc_mbox_out_bits { 78 u8 status[0x8]; 79 u8 reserved_at_8[0x18]; 80 81 u8 syndrome[0x20]; 82 83 u8 reserved_at_40[0x40]; 84 }; 85 86 struct mlx5_ifc_mbox_in_bits { 87 u8 opcode[0x10]; 88 u8 reserved_at_10[0x10]; 89 90 u8 reserved_at_20[0x10]; 91 u8 op_mod[0x10]; 92 93 u8 reserved_at_40[0x40]; 94 }; 95 96 97 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd, 98 struct mlx5_cmd_msg *in, 99 int uin_size, 100 struct mlx5_cmd_msg *out, 101 void *uout, int uout_size, 102 mlx5_cmd_cbk_t cbk, 103 void *context, int page_queue) 104 { 105 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL; 106 struct mlx5_cmd_work_ent *ent; 107 108 ent = kzalloc(sizeof(*ent), alloc_flags); 109 if (!ent) 110 return ERR_PTR(-ENOMEM); 111 112 ent->in = in; 113 ent->uin_size = uin_size; 114 ent->out = out; 115 ent->uout = uout; 116 ent->uout_size = uout_size; 117 ent->callback = cbk; 118 ent->context = context; 119 ent->cmd = cmd; 120 ent->page_queue = page_queue; 121 122 return ent; 123 } 124 125 static u8 alloc_token(struct mlx5_cmd *cmd) 126 { 127 u8 token; 128 129 spin_lock(&cmd->token_lock); 130 cmd->token++; 131 if (cmd->token == 0) 132 cmd->token++; 133 token = cmd->token; 134 spin_unlock(&cmd->token_lock); 135 136 return token; 137 } 138 139 static int alloc_ent(struct mlx5_cmd_work_ent *ent) 140 { 141 unsigned long flags; 142 struct mlx5_cmd *cmd = ent->cmd; 143 struct mlx5_core_dev *dev = 144 container_of(cmd, struct mlx5_core_dev, cmd); 145 int ret = cmd->max_reg_cmds; 146 147 spin_lock_irqsave(&cmd->alloc_lock, flags); 148 if (!ent->page_queue) { 149 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds); 150 if (ret >= cmd->max_reg_cmds) 151 ret = -1; 152 } 153 154 if (dev->state != MLX5_DEVICE_STATE_UP) 155 ret = -1; 156 157 if (ret != -1) { 158 ent->busy = 1; 159 ent->idx = ret; 160 clear_bit(ent->idx, &cmd->bitmask); 161 cmd->ent_mode[ent->idx] = 162 ent->polling ? MLX5_CMD_MODE_POLLING : MLX5_CMD_MODE_EVENTS; 163 cmd->ent_arr[ent->idx] = ent; 164 } 165 spin_unlock_irqrestore(&cmd->alloc_lock, flags); 166 167 return ret; 168 } 169 170 static void free_ent(struct mlx5_cmd *cmd, int idx) 171 { 172 unsigned long flags; 173 174 spin_lock_irqsave(&cmd->alloc_lock, flags); 175 cmd->ent_arr[idx] = NULL; /* safety clear */ 176 cmd->ent_mode[idx] = MLX5_CMD_MODE_POLLING; /* reset mode */ 177 set_bit(idx, &cmd->bitmask); 178 spin_unlock_irqrestore(&cmd->alloc_lock, flags); 179 } 180 181 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx) 182 { 183 return cmd->cmd_buf + (idx << cmd->log_stride); 184 } 185 186 static u8 xor8_buf(void *buf, int len) 187 { 188 u8 *ptr = buf; 189 u8 sum = 0; 190 int i; 191 192 for (i = 0; i < len; i++) 193 sum ^= ptr[i]; 194 195 return sum; 196 } 197 198 static int verify_block_sig(struct mlx5_cmd_prot_block *block) 199 { 200 if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff) 201 return -EINVAL; 202 203 if (xor8_buf(block, sizeof(*block)) != 0xff) 204 return -EINVAL; 205 206 return 0; 207 } 208 209 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token, 210 int csum) 211 { 212 block->token = token; 213 if (csum) { 214 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) - 215 sizeof(block->data) - 2); 216 block->sig = ~xor8_buf(block, sizeof(*block) - 1); 217 } 218 } 219 220 static void 221 calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum) 222 { 223 size_t i; 224 225 for (i = 0; i != (msg->numpages * MLX5_NUM_CMDS_IN_ADAPTER_PAGE); i++) { 226 struct mlx5_cmd_prot_block *block; 227 228 block = mlx5_fwp_get_virt(msg, i * MLX5_CMD_MBOX_SIZE); 229 230 /* compute signature */ 231 calc_block_sig(block, token, csum); 232 233 /* check for last block */ 234 if (block->next == 0) 235 break; 236 } 237 238 /* make sure data gets written to RAM */ 239 mlx5_fwp_flush(msg); 240 } 241 242 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum) 243 { 244 ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay)); 245 calc_chain_sig(ent->in, ent->token, csum); 246 calc_chain_sig(ent->out, ent->token, csum); 247 } 248 249 static void poll_timeout(struct mlx5_cmd_work_ent *ent) 250 { 251 struct mlx5_core_dev *dev = container_of(ent->cmd, 252 struct mlx5_core_dev, cmd); 253 int poll_end = jiffies + 254 msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000); 255 u8 own; 256 257 do { 258 own = ent->lay->status_own; 259 if (!(own & CMD_OWNER_HW) || 260 dev->state != MLX5_DEVICE_STATE_UP) { 261 ent->ret = 0; 262 return; 263 } 264 usleep_range(5000, 10000); 265 } while (time_before(jiffies, poll_end)); 266 267 ent->ret = -ETIMEDOUT; 268 } 269 270 static void free_cmd(struct mlx5_cmd_work_ent *ent) 271 { 272 cancel_delayed_work_sync(&ent->cb_timeout_work); 273 kfree(ent); 274 } 275 276 static int 277 verify_signature(struct mlx5_cmd_work_ent *ent) 278 { 279 struct mlx5_cmd_msg *msg = ent->out; 280 size_t i; 281 int err; 282 u8 sig; 283 284 sig = xor8_buf(ent->lay, sizeof(*ent->lay)); 285 if (sig != 0xff) 286 return -EINVAL; 287 288 for (i = 0; i != (msg->numpages * MLX5_NUM_CMDS_IN_ADAPTER_PAGE); i++) { 289 struct mlx5_cmd_prot_block *block; 290 291 block = mlx5_fwp_get_virt(msg, i * MLX5_CMD_MBOX_SIZE); 292 293 /* compute signature */ 294 err = verify_block_sig(block); 295 if (err != 0) 296 return (err); 297 298 /* check for last block */ 299 if (block->next == 0) 300 break; 301 } 302 return (0); 303 } 304 305 static void dump_buf(void *buf, int size, int data_only, int offset) 306 { 307 __be32 *p = buf; 308 int i; 309 310 for (i = 0; i < size; i += 16) { 311 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]), 312 be32_to_cpu(p[1]), be32_to_cpu(p[2]), 313 be32_to_cpu(p[3])); 314 p += 4; 315 offset += 16; 316 } 317 if (!data_only) 318 pr_debug("\n"); 319 } 320 321 enum { 322 MLX5_DRIVER_STATUS_ABORTED = 0xfe, 323 MLX5_DRIVER_SYND = 0xbadd00de, 324 }; 325 326 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, 327 u32 *synd, u8 *status) 328 { 329 *synd = 0; 330 *status = 0; 331 332 switch (op) { 333 case MLX5_CMD_OP_TEARDOWN_HCA: 334 case MLX5_CMD_OP_DISABLE_HCA: 335 case MLX5_CMD_OP_MANAGE_PAGES: 336 case MLX5_CMD_OP_DESTROY_MKEY: 337 case MLX5_CMD_OP_DESTROY_EQ: 338 case MLX5_CMD_OP_DESTROY_CQ: 339 case MLX5_CMD_OP_DESTROY_QP: 340 case MLX5_CMD_OP_DESTROY_PSV: 341 case MLX5_CMD_OP_DESTROY_SRQ: 342 case MLX5_CMD_OP_DESTROY_XRC_SRQ: 343 case MLX5_CMD_OP_DESTROY_DCT: 344 case MLX5_CMD_OP_DEALLOC_Q_COUNTER: 345 case MLX5_CMD_OP_DEALLOC_PD: 346 case MLX5_CMD_OP_DEALLOC_UAR: 347 case MLX5_CMD_OP_DETACH_FROM_MCG: 348 case MLX5_CMD_OP_DEALLOC_XRCD: 349 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN: 350 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT: 351 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY: 352 case MLX5_CMD_OP_DESTROY_TIR: 353 case MLX5_CMD_OP_DESTROY_SQ: 354 case MLX5_CMD_OP_DESTROY_RQ: 355 case MLX5_CMD_OP_DESTROY_RMP: 356 case MLX5_CMD_OP_DESTROY_TIS: 357 case MLX5_CMD_OP_DESTROY_RQT: 358 case MLX5_CMD_OP_DESTROY_FLOW_TABLE: 359 case MLX5_CMD_OP_DESTROY_FLOW_GROUP: 360 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY: 361 case MLX5_CMD_OP_2ERR_QP: 362 case MLX5_CMD_OP_2RST_QP: 363 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT: 364 case MLX5_CMD_OP_MODIFY_FLOW_TABLE: 365 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 366 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT: 367 case MLX5_CMD_OP_DESTROY_GENERAL_OBJ: 368 return MLX5_CMD_STAT_OK; 369 370 case MLX5_CMD_OP_QUERY_HCA_CAP: 371 case MLX5_CMD_OP_QUERY_ADAPTER: 372 case MLX5_CMD_OP_INIT_HCA: 373 case MLX5_CMD_OP_ENABLE_HCA: 374 case MLX5_CMD_OP_QUERY_PAGES: 375 case MLX5_CMD_OP_SET_HCA_CAP: 376 case MLX5_CMD_OP_QUERY_ISSI: 377 case MLX5_CMD_OP_SET_ISSI: 378 case MLX5_CMD_OP_CREATE_MKEY: 379 case MLX5_CMD_OP_QUERY_MKEY: 380 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS: 381 case MLX5_CMD_OP_PAGE_FAULT_RESUME: 382 case MLX5_CMD_OP_CREATE_EQ: 383 case MLX5_CMD_OP_QUERY_EQ: 384 case MLX5_CMD_OP_GEN_EQE: 385 case MLX5_CMD_OP_CREATE_CQ: 386 case MLX5_CMD_OP_QUERY_CQ: 387 case MLX5_CMD_OP_MODIFY_CQ: 388 case MLX5_CMD_OP_CREATE_QP: 389 case MLX5_CMD_OP_RST2INIT_QP: 390 case MLX5_CMD_OP_INIT2RTR_QP: 391 case MLX5_CMD_OP_RTR2RTS_QP: 392 case MLX5_CMD_OP_RTS2RTS_QP: 393 case MLX5_CMD_OP_SQERR2RTS_QP: 394 case MLX5_CMD_OP_QUERY_QP: 395 case MLX5_CMD_OP_SQD_RTS_QP: 396 case MLX5_CMD_OP_INIT2INIT_QP: 397 case MLX5_CMD_OP_CREATE_PSV: 398 case MLX5_CMD_OP_CREATE_SRQ: 399 case MLX5_CMD_OP_QUERY_SRQ: 400 case MLX5_CMD_OP_ARM_RQ: 401 case MLX5_CMD_OP_CREATE_XRC_SRQ: 402 case MLX5_CMD_OP_QUERY_XRC_SRQ: 403 case MLX5_CMD_OP_ARM_XRC_SRQ: 404 case MLX5_CMD_OP_CREATE_DCT: 405 case MLX5_CMD_OP_DRAIN_DCT: 406 case MLX5_CMD_OP_QUERY_DCT: 407 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION: 408 case MLX5_CMD_OP_QUERY_VPORT_STATE: 409 case MLX5_CMD_OP_MODIFY_VPORT_STATE: 410 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT: 411 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT: 412 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT: 413 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS: 414 case MLX5_CMD_OP_SET_ROCE_ADDRESS: 415 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT: 416 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT: 417 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID: 418 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY: 419 case MLX5_CMD_OP_QUERY_VNIC_ENV: 420 case MLX5_CMD_OP_QUERY_VPORT_COUNTER: 421 case MLX5_CMD_OP_ALLOC_Q_COUNTER: 422 case MLX5_CMD_OP_QUERY_Q_COUNTER: 423 case MLX5_CMD_OP_ALLOC_PD: 424 case MLX5_CMD_OP_ALLOC_UAR: 425 case MLX5_CMD_OP_CONFIG_INT_MODERATION: 426 case MLX5_CMD_OP_ACCESS_REG: 427 case MLX5_CMD_OP_ATTACH_TO_MCG: 428 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG: 429 case MLX5_CMD_OP_MAD_IFC: 430 case MLX5_CMD_OP_QUERY_MAD_DEMUX: 431 case MLX5_CMD_OP_SET_MAD_DEMUX: 432 case MLX5_CMD_OP_NOP: 433 case MLX5_CMD_OP_ALLOC_XRCD: 434 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN: 435 case MLX5_CMD_OP_QUERY_CONG_STATUS: 436 case MLX5_CMD_OP_MODIFY_CONG_STATUS: 437 case MLX5_CMD_OP_QUERY_CONG_PARAMS: 438 case MLX5_CMD_OP_MODIFY_CONG_PARAMS: 439 case MLX5_CMD_OP_QUERY_CONG_STATISTICS: 440 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 441 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 442 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY: 443 case MLX5_CMD_OP_CREATE_TIR: 444 case MLX5_CMD_OP_MODIFY_TIR: 445 case MLX5_CMD_OP_QUERY_TIR: 446 case MLX5_CMD_OP_CREATE_SQ: 447 case MLX5_CMD_OP_MODIFY_SQ: 448 case MLX5_CMD_OP_QUERY_SQ: 449 case MLX5_CMD_OP_CREATE_RQ: 450 case MLX5_CMD_OP_MODIFY_RQ: 451 case MLX5_CMD_OP_QUERY_RQ: 452 case MLX5_CMD_OP_CREATE_RMP: 453 case MLX5_CMD_OP_MODIFY_RMP: 454 case MLX5_CMD_OP_QUERY_RMP: 455 case MLX5_CMD_OP_CREATE_TIS: 456 case MLX5_CMD_OP_MODIFY_TIS: 457 case MLX5_CMD_OP_QUERY_TIS: 458 case MLX5_CMD_OP_CREATE_RQT: 459 case MLX5_CMD_OP_MODIFY_RQT: 460 case MLX5_CMD_OP_QUERY_RQT: 461 case MLX5_CMD_OP_CREATE_FLOW_TABLE: 462 case MLX5_CMD_OP_QUERY_FLOW_TABLE: 463 case MLX5_CMD_OP_CREATE_FLOW_GROUP: 464 case MLX5_CMD_OP_QUERY_FLOW_GROUP: 465 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY: 466 case MLX5_CMD_OP_CREATE_GENERAL_OBJ: 467 case MLX5_CMD_OP_MODIFY_GENERAL_OBJ: 468 case MLX5_CMD_OP_QUERY_GENERAL_OBJ: 469 *status = MLX5_DRIVER_STATUS_ABORTED; 470 *synd = MLX5_DRIVER_SYND; 471 return -EIO; 472 default: 473 mlx5_core_err(dev, "Unknown FW command (%d)\n", op); 474 return -EINVAL; 475 } 476 } 477 478 const char *mlx5_command_str(int command) 479 { 480 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd 481 482 switch (command) { 483 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP); 484 MLX5_COMMAND_STR_CASE(SET_HCA_CAP); 485 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER); 486 MLX5_COMMAND_STR_CASE(INIT_HCA); 487 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA); 488 MLX5_COMMAND_STR_CASE(ENABLE_HCA); 489 MLX5_COMMAND_STR_CASE(DISABLE_HCA); 490 MLX5_COMMAND_STR_CASE(QUERY_PAGES); 491 MLX5_COMMAND_STR_CASE(MANAGE_PAGES); 492 MLX5_COMMAND_STR_CASE(QUERY_ISSI); 493 MLX5_COMMAND_STR_CASE(SET_ISSI); 494 MLX5_COMMAND_STR_CASE(CREATE_MKEY); 495 MLX5_COMMAND_STR_CASE(QUERY_MKEY); 496 MLX5_COMMAND_STR_CASE(DESTROY_MKEY); 497 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS); 498 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME); 499 MLX5_COMMAND_STR_CASE(CREATE_EQ); 500 MLX5_COMMAND_STR_CASE(DESTROY_EQ); 501 MLX5_COMMAND_STR_CASE(QUERY_EQ); 502 MLX5_COMMAND_STR_CASE(GEN_EQE); 503 MLX5_COMMAND_STR_CASE(CREATE_CQ); 504 MLX5_COMMAND_STR_CASE(DESTROY_CQ); 505 MLX5_COMMAND_STR_CASE(QUERY_CQ); 506 MLX5_COMMAND_STR_CASE(MODIFY_CQ); 507 MLX5_COMMAND_STR_CASE(CREATE_QP); 508 MLX5_COMMAND_STR_CASE(DESTROY_QP); 509 MLX5_COMMAND_STR_CASE(RST2INIT_QP); 510 MLX5_COMMAND_STR_CASE(INIT2RTR_QP); 511 MLX5_COMMAND_STR_CASE(RTR2RTS_QP); 512 MLX5_COMMAND_STR_CASE(RTS2RTS_QP); 513 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP); 514 MLX5_COMMAND_STR_CASE(2ERR_QP); 515 MLX5_COMMAND_STR_CASE(2RST_QP); 516 MLX5_COMMAND_STR_CASE(QUERY_QP); 517 MLX5_COMMAND_STR_CASE(SQD_RTS_QP); 518 MLX5_COMMAND_STR_CASE(MAD_IFC); 519 MLX5_COMMAND_STR_CASE(INIT2INIT_QP); 520 MLX5_COMMAND_STR_CASE(CREATE_PSV); 521 MLX5_COMMAND_STR_CASE(DESTROY_PSV); 522 MLX5_COMMAND_STR_CASE(CREATE_SRQ); 523 MLX5_COMMAND_STR_CASE(DESTROY_SRQ); 524 MLX5_COMMAND_STR_CASE(QUERY_SRQ); 525 MLX5_COMMAND_STR_CASE(ARM_RQ); 526 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ); 527 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ); 528 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ); 529 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ); 530 MLX5_COMMAND_STR_CASE(CREATE_DCT); 531 MLX5_COMMAND_STR_CASE(SET_DC_CNAK_TRACE); 532 MLX5_COMMAND_STR_CASE(DESTROY_DCT); 533 MLX5_COMMAND_STR_CASE(DRAIN_DCT); 534 MLX5_COMMAND_STR_CASE(QUERY_DCT); 535 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION); 536 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE); 537 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE); 538 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT); 539 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT); 540 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT); 541 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT); 542 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS); 543 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS); 544 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT); 545 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT); 546 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID); 547 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY); 548 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV); 549 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER); 550 MLX5_COMMAND_STR_CASE(SET_WOL_ROL); 551 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL); 552 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER); 553 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER); 554 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER); 555 MLX5_COMMAND_STR_CASE(ALLOC_PD); 556 MLX5_COMMAND_STR_CASE(DEALLOC_PD); 557 MLX5_COMMAND_STR_CASE(ALLOC_UAR); 558 MLX5_COMMAND_STR_CASE(DEALLOC_UAR); 559 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION); 560 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG); 561 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG); 562 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG); 563 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX); 564 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX); 565 MLX5_COMMAND_STR_CASE(NOP); 566 MLX5_COMMAND_STR_CASE(ALLOC_XRCD); 567 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD); 568 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN); 569 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN); 570 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS); 571 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS); 572 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS); 573 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS); 574 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS); 575 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT); 576 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT); 577 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY); 578 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY); 579 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY); 580 MLX5_COMMAND_STR_CASE(CREATE_RMP); 581 MLX5_COMMAND_STR_CASE(MODIFY_RMP); 582 MLX5_COMMAND_STR_CASE(DESTROY_RMP); 583 MLX5_COMMAND_STR_CASE(QUERY_RMP); 584 MLX5_COMMAND_STR_CASE(CREATE_RQT); 585 MLX5_COMMAND_STR_CASE(MODIFY_RQT); 586 MLX5_COMMAND_STR_CASE(DESTROY_RQT); 587 MLX5_COMMAND_STR_CASE(QUERY_RQT); 588 MLX5_COMMAND_STR_CASE(ACCESS_REG); 589 MLX5_COMMAND_STR_CASE(CREATE_SQ); 590 MLX5_COMMAND_STR_CASE(MODIFY_SQ); 591 MLX5_COMMAND_STR_CASE(DESTROY_SQ); 592 MLX5_COMMAND_STR_CASE(QUERY_SQ); 593 MLX5_COMMAND_STR_CASE(CREATE_RQ); 594 MLX5_COMMAND_STR_CASE(MODIFY_RQ); 595 MLX5_COMMAND_STR_CASE(DESTROY_RQ); 596 MLX5_COMMAND_STR_CASE(QUERY_RQ); 597 MLX5_COMMAND_STR_CASE(CREATE_TIR); 598 MLX5_COMMAND_STR_CASE(MODIFY_TIR); 599 MLX5_COMMAND_STR_CASE(DESTROY_TIR); 600 MLX5_COMMAND_STR_CASE(QUERY_TIR); 601 MLX5_COMMAND_STR_CASE(CREATE_TIS); 602 MLX5_COMMAND_STR_CASE(MODIFY_TIS); 603 MLX5_COMMAND_STR_CASE(DESTROY_TIS); 604 MLX5_COMMAND_STR_CASE(QUERY_TIS); 605 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE); 606 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE); 607 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE); 608 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP); 609 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP); 610 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP); 611 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY); 612 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY); 613 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY); 614 MLX5_COMMAND_STR_CASE(SET_DIAGNOSTICS); 615 MLX5_COMMAND_STR_CASE(QUERY_DIAGNOSTICS); 616 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJ); 617 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJ); 618 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJ); 619 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJ); 620 default: return "unknown command opcode"; 621 } 622 } 623 624 static const char *cmd_status_str(u8 status) 625 { 626 switch (status) { 627 case MLX5_CMD_STAT_OK: 628 return "OK"; 629 case MLX5_CMD_STAT_INT_ERR: 630 return "internal error"; 631 case MLX5_CMD_STAT_BAD_OP_ERR: 632 return "bad operation"; 633 case MLX5_CMD_STAT_BAD_PARAM_ERR: 634 return "bad parameter"; 635 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: 636 return "bad system state"; 637 case MLX5_CMD_STAT_BAD_RES_ERR: 638 return "bad resource"; 639 case MLX5_CMD_STAT_RES_BUSY: 640 return "resource busy"; 641 case MLX5_CMD_STAT_LIM_ERR: 642 return "limits exceeded"; 643 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: 644 return "bad resource state"; 645 case MLX5_CMD_STAT_IX_ERR: 646 return "bad index"; 647 case MLX5_CMD_STAT_NO_RES_ERR: 648 return "no resources"; 649 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: 650 return "bad input length"; 651 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: 652 return "bad output length"; 653 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: 654 return "bad QP state"; 655 case MLX5_CMD_STAT_BAD_PKT_ERR: 656 return "bad packet (discarded)"; 657 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: 658 return "bad size too many outstanding CQEs"; 659 default: 660 return "unknown status"; 661 } 662 } 663 664 static int cmd_status_to_err_helper(u8 status) 665 { 666 switch (status) { 667 case MLX5_CMD_STAT_OK: return 0; 668 case MLX5_CMD_STAT_INT_ERR: return -EIO; 669 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL; 670 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL; 671 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO; 672 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL; 673 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY; 674 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM; 675 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL; 676 case MLX5_CMD_STAT_IX_ERR: return -EINVAL; 677 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN; 678 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO; 679 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO; 680 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL; 681 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL; 682 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL; 683 default: return -EIO; 684 } 685 } 686 687 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome) 688 { 689 *status = MLX5_GET(mbox_out, out, status); 690 *syndrome = MLX5_GET(mbox_out, out, syndrome); 691 } 692 693 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out) 694 { 695 u32 syndrome; 696 u8 status; 697 u16 opcode; 698 u16 op_mod; 699 700 mlx5_cmd_mbox_status(out, &status, &syndrome); 701 if (!status) 702 return 0; 703 704 opcode = MLX5_GET(mbox_in, in, opcode); 705 op_mod = MLX5_GET(mbox_in, in, op_mod); 706 707 mlx5_core_err(dev, 708 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n", 709 mlx5_command_str(opcode), 710 opcode, op_mod, 711 cmd_status_str(status), 712 status, 713 syndrome); 714 715 return cmd_status_to_err_helper(status); 716 } 717 718 static void dump_command(struct mlx5_core_dev *dev, 719 struct mlx5_cmd_work_ent *ent, int input) 720 { 721 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out; 722 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode); 723 size_t i; 724 int data_only; 725 int offset = 0; 726 int msg_len = input ? ent->uin_size : ent->uout_size; 727 int dump_len; 728 729 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA)); 730 731 if (data_only) 732 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA, 733 "dump command data %s(0x%x) %s\n", 734 mlx5_command_str(op), op, 735 input ? "INPUT" : "OUTPUT"); 736 else 737 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n", 738 mlx5_command_str(op), op, 739 input ? "INPUT" : "OUTPUT"); 740 741 if (data_only) { 742 if (input) { 743 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset); 744 offset += sizeof(ent->lay->in); 745 } else { 746 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset); 747 offset += sizeof(ent->lay->out); 748 } 749 } else { 750 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset); 751 offset += sizeof(*ent->lay); 752 } 753 754 for (i = 0; i != (msg->numpages * MLX5_NUM_CMDS_IN_ADAPTER_PAGE); i++) { 755 struct mlx5_cmd_prot_block *block; 756 757 block = mlx5_fwp_get_virt(msg, i * MLX5_CMD_MBOX_SIZE); 758 759 if (data_only) { 760 if (offset >= msg_len) 761 break; 762 dump_len = min_t(int, 763 MLX5_CMD_DATA_BLOCK_SIZE, msg_len - offset); 764 765 dump_buf(block->data, dump_len, 1, offset); 766 offset += MLX5_CMD_DATA_BLOCK_SIZE; 767 } else { 768 mlx5_core_dbg(dev, "command block:\n"); 769 dump_buf(block, sizeof(*block), 0, offset); 770 offset += sizeof(*block); 771 } 772 773 /* check for last block */ 774 if (block->next == 0) 775 break; 776 } 777 778 if (data_only) 779 pr_debug("\n"); 780 } 781 782 static u16 msg_to_opcode(struct mlx5_cmd_msg *in) 783 { 784 return MLX5_GET(mbox_in, in->first.data, opcode); 785 } 786 787 static void cb_timeout_handler(struct work_struct *work) 788 { 789 struct delayed_work *dwork = container_of(work, struct delayed_work, 790 work); 791 struct mlx5_cmd_work_ent *ent = container_of(dwork, 792 struct mlx5_cmd_work_ent, 793 cb_timeout_work); 794 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev, 795 cmd); 796 797 ent->ret = -ETIMEDOUT; 798 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n", 799 mlx5_command_str(msg_to_opcode(ent->in)), 800 msg_to_opcode(ent->in)); 801 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, MLX5_CMD_MODE_EVENTS); 802 } 803 804 static void complete_command(struct mlx5_cmd_work_ent *ent) 805 { 806 struct mlx5_cmd *cmd = ent->cmd; 807 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, 808 cmd); 809 mlx5_cmd_cbk_t callback; 810 void *context; 811 812 s64 ds; 813 struct mlx5_cmd_stats *stats; 814 unsigned long flags; 815 int err; 816 struct semaphore *sem; 817 818 if (ent->page_queue) 819 sem = &cmd->pages_sem; 820 else 821 sem = &cmd->sem; 822 823 if (dev->state != MLX5_DEVICE_STATE_UP) { 824 u8 status = 0; 825 u32 drv_synd; 826 827 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status); 828 MLX5_SET(mbox_out, ent->out, status, status); 829 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd); 830 } 831 832 if (ent->callback) { 833 ds = ent->ts2 - ent->ts1; 834 if (ent->op < ARRAY_SIZE(cmd->stats)) { 835 stats = &cmd->stats[ent->op]; 836 spin_lock_irqsave(&stats->lock, flags); 837 stats->sum += ds; 838 ++stats->n; 839 spin_unlock_irqrestore(&stats->lock, flags); 840 } 841 842 callback = ent->callback; 843 context = ent->context; 844 err = ent->ret; 845 if (!err) { 846 err = mlx5_copy_from_msg(ent->uout, 847 ent->out, 848 ent->uout_size); 849 err = err ? err : mlx5_cmd_check(dev, 850 ent->in->first.data, 851 ent->uout); 852 } 853 854 mlx5_free_cmd_msg(dev, ent->out); 855 free_msg(dev, ent->in); 856 857 err = err ? err : ent->status; 858 free_cmd(ent); 859 callback(err, context); 860 } else { 861 complete(&ent->done); 862 } 863 up(sem); 864 } 865 866 static void cmd_work_handler(struct work_struct *work) 867 { 868 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work); 869 struct mlx5_cmd *cmd = ent->cmd; 870 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd); 871 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC); 872 struct mlx5_cmd_layout *lay; 873 struct semaphore *sem; 874 bool poll_cmd = ent->polling; 875 876 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem; 877 down(sem); 878 879 if (alloc_ent(ent) < 0) { 880 complete_command(ent); 881 return; 882 } 883 884 ent->token = alloc_token(cmd); 885 lay = get_inst(cmd, ent->idx); 886 ent->lay = lay; 887 memset(lay, 0, sizeof(*lay)); 888 memcpy(lay->in, ent->in->first.data, sizeof(lay->in)); 889 ent->op = be32_to_cpu(lay->in[0]) >> 16; 890 if (ent->in->numpages != 0) 891 lay->in_ptr = cpu_to_be64(mlx5_fwp_get_dma(ent->in, 0)); 892 if (ent->out->numpages != 0) 893 lay->out_ptr = cpu_to_be64(mlx5_fwp_get_dma(ent->out, 0)); 894 lay->inlen = cpu_to_be32(ent->uin_size); 895 lay->outlen = cpu_to_be32(ent->uout_size); 896 lay->type = MLX5_PCI_CMD_XPORT; 897 lay->token = ent->token; 898 lay->status_own = CMD_OWNER_HW; 899 set_signature(ent, !cmd->checksum_disabled); 900 dump_command(dev, ent, 1); 901 ent->ts1 = ktime_get_ns(); 902 ent->busy = 0; 903 if (ent->callback) 904 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout); 905 906 /* ring doorbell after the descriptor is valid */ 907 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx); 908 /* make sure data is written to RAM */ 909 mlx5_fwp_flush(cmd->cmd_page); 910 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell); 911 mmiowb(); 912 913 /* if not in polling don't use ent after this point */ 914 if (poll_cmd) { 915 poll_timeout(ent); 916 /* make sure we read the descriptor after ownership is SW */ 917 mlx5_cmd_comp_handler(dev, 1U << ent->idx, MLX5_CMD_MODE_POLLING); 918 } 919 } 920 921 static const char *deliv_status_to_str(u8 status) 922 { 923 switch (status) { 924 case MLX5_CMD_DELIVERY_STAT_OK: 925 return "no errors"; 926 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR: 927 return "signature error"; 928 case MLX5_CMD_DELIVERY_STAT_TOK_ERR: 929 return "token error"; 930 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR: 931 return "bad block number"; 932 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR: 933 return "output pointer not aligned to block size"; 934 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR: 935 return "input pointer not aligned to block size"; 936 case MLX5_CMD_DELIVERY_STAT_FW_ERR: 937 return "firmware internal error"; 938 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR: 939 return "command input length error"; 940 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR: 941 return "command ouput length error"; 942 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR: 943 return "reserved fields not cleared"; 944 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR: 945 return "bad command descriptor type"; 946 default: 947 return "unknown status code"; 948 } 949 } 950 951 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent) 952 { 953 int timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC); 954 int err; 955 956 if (ent->polling) { 957 wait_for_completion(&ent->done); 958 } else if (!wait_for_completion_timeout(&ent->done, timeout)) { 959 ent->ret = -ETIMEDOUT; 960 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, MLX5_CMD_MODE_EVENTS); 961 } 962 963 err = ent->ret; 964 965 if (err == -ETIMEDOUT) { 966 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n", 967 mlx5_command_str(msg_to_opcode(ent->in)), 968 msg_to_opcode(ent->in)); 969 } 970 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n", 971 err, deliv_status_to_str(ent->status), ent->status); 972 973 return err; 974 } 975 976 /* Notes: 977 * 1. Callback functions may not sleep 978 * 2. page queue commands do not support asynchrous completion 979 */ 980 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in, 981 int uin_size, 982 struct mlx5_cmd_msg *out, void *uout, int uout_size, 983 mlx5_cmd_cbk_t callback, 984 void *context, int page_queue, u8 *status, 985 bool force_polling) 986 { 987 struct mlx5_cmd *cmd = &dev->cmd; 988 struct mlx5_cmd_work_ent *ent; 989 struct mlx5_cmd_stats *stats; 990 int err = 0; 991 s64 ds; 992 u16 op; 993 994 if (callback && page_queue) 995 return -EINVAL; 996 997 ent = alloc_cmd(cmd, in, uin_size, out, uout, uout_size, callback, 998 context, page_queue); 999 if (IS_ERR(ent)) 1000 return PTR_ERR(ent); 1001 1002 ent->polling = force_polling || (cmd->mode == MLX5_CMD_MODE_POLLING); 1003 1004 if (!callback) 1005 init_completion(&ent->done); 1006 1007 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler); 1008 INIT_WORK(&ent->work, cmd_work_handler); 1009 if (page_queue) { 1010 cmd_work_handler(&ent->work); 1011 } else if (!queue_work(dev->priv.health.wq_cmd, &ent->work)) { 1012 mlx5_core_warn(dev, "failed to queue work\n"); 1013 err = -ENOMEM; 1014 goto out_free; 1015 } 1016 1017 if (callback) 1018 goto out; 1019 1020 err = wait_func(dev, ent); 1021 if (err == -ETIMEDOUT) 1022 goto out; 1023 1024 ds = ent->ts2 - ent->ts1; 1025 op = MLX5_GET(mbox_in, in->first.data, opcode); 1026 if (op < ARRAY_SIZE(cmd->stats)) { 1027 stats = &cmd->stats[op]; 1028 spin_lock_irq(&stats->lock); 1029 stats->sum += ds; 1030 ++stats->n; 1031 spin_unlock_irq(&stats->lock); 1032 } 1033 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME, 1034 "fw exec time for %s is %lld nsec\n", 1035 mlx5_command_str(op), (long long)ds); 1036 *status = ent->status; 1037 free_cmd(ent); 1038 1039 return err; 1040 1041 out_free: 1042 free_cmd(ent); 1043 out: 1044 return err; 1045 } 1046 1047 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, size_t size) 1048 { 1049 size_t delta; 1050 size_t i; 1051 1052 if (to == NULL || from == NULL) 1053 return (-ENOMEM); 1054 1055 delta = min_t(size_t, size, sizeof(to->first.data)); 1056 memcpy(to->first.data, from, delta); 1057 from = (char *)from + delta; 1058 size -= delta; 1059 1060 for (i = 0; size != 0; i++) { 1061 struct mlx5_cmd_prot_block *block; 1062 1063 block = mlx5_fwp_get_virt(to, i * MLX5_CMD_MBOX_SIZE); 1064 1065 delta = min_t(size_t, size, MLX5_CMD_DATA_BLOCK_SIZE); 1066 memcpy(block->data, from, delta); 1067 from = (char *)from + delta; 1068 size -= delta; 1069 } 1070 return (0); 1071 } 1072 1073 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size) 1074 { 1075 size_t delta; 1076 size_t i; 1077 1078 if (to == NULL || from == NULL) 1079 return (-ENOMEM); 1080 1081 delta = min_t(size_t, size, sizeof(from->first.data)); 1082 memcpy(to, from->first.data, delta); 1083 to = (char *)to + delta; 1084 size -= delta; 1085 1086 for (i = 0; size != 0; i++) { 1087 struct mlx5_cmd_prot_block *block; 1088 1089 block = mlx5_fwp_get_virt(from, i * MLX5_CMD_MBOX_SIZE); 1090 1091 delta = min_t(size_t, size, MLX5_CMD_DATA_BLOCK_SIZE); 1092 memcpy(to, block->data, delta); 1093 to = (char *)to + delta; 1094 size -= delta; 1095 } 1096 return (0); 1097 } 1098 1099 static struct mlx5_cmd_msg * 1100 mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev, gfp_t flags, size_t size) 1101 { 1102 struct mlx5_cmd_msg *msg; 1103 size_t blen; 1104 size_t n; 1105 size_t i; 1106 1107 blen = size - min_t(size_t, sizeof(msg->first.data), size); 1108 n = howmany(blen, MLX5_CMD_DATA_BLOCK_SIZE); 1109 1110 msg = mlx5_fwp_alloc(dev, flags, howmany(n, MLX5_NUM_CMDS_IN_ADAPTER_PAGE)); 1111 if (msg == NULL) 1112 return (ERR_PTR(-ENOMEM)); 1113 1114 for (i = 0; i != n; i++) { 1115 struct mlx5_cmd_prot_block *block; 1116 1117 block = mlx5_fwp_get_virt(msg, i * MLX5_CMD_MBOX_SIZE); 1118 1119 memset(block, 0, MLX5_CMD_MBOX_SIZE); 1120 1121 if (i != (n - 1)) { 1122 u64 dma = mlx5_fwp_get_dma(msg, (i + 1) * MLX5_CMD_MBOX_SIZE); 1123 block->next = cpu_to_be64(dma); 1124 } 1125 block->block_num = cpu_to_be32(i); 1126 } 1127 1128 /* make sure initial data is written to RAM */ 1129 mlx5_fwp_flush(msg); 1130 1131 return (msg); 1132 } 1133 1134 static void 1135 mlx5_free_cmd_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg) 1136 { 1137 1138 mlx5_fwp_free(msg); 1139 } 1140 1141 static void clean_debug_files(struct mlx5_core_dev *dev) 1142 { 1143 } 1144 1145 1146 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode) 1147 { 1148 struct mlx5_cmd *cmd = &dev->cmd; 1149 int i; 1150 1151 if (cmd->mode == mode) 1152 return; 1153 1154 for (i = 0; i < cmd->max_reg_cmds; i++) 1155 down(&cmd->sem); 1156 1157 down(&cmd->pages_sem); 1158 cmd->mode = mode; 1159 1160 up(&cmd->pages_sem); 1161 for (i = 0; i < cmd->max_reg_cmds; i++) 1162 up(&cmd->sem); 1163 } 1164 1165 void mlx5_cmd_use_events(struct mlx5_core_dev *dev) 1166 { 1167 mlx5_cmd_change_mod(dev, MLX5_CMD_MODE_EVENTS); 1168 } 1169 1170 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev) 1171 { 1172 mlx5_cmd_change_mod(dev, MLX5_CMD_MODE_POLLING); 1173 } 1174 1175 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg) 1176 { 1177 unsigned long flags; 1178 1179 if (msg->cache) { 1180 spin_lock_irqsave(&msg->cache->lock, flags); 1181 list_add_tail(&msg->list, &msg->cache->head); 1182 spin_unlock_irqrestore(&msg->cache->lock, flags); 1183 } else { 1184 mlx5_free_cmd_msg(dev, msg); 1185 } 1186 } 1187 1188 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector_flags, 1189 enum mlx5_cmd_mode cmd_mode) 1190 { 1191 struct mlx5_cmd *cmd = &dev->cmd; 1192 struct mlx5_cmd_work_ent *ent; 1193 bool triggered = (vector_flags & MLX5_TRIGGERED_CMD_COMP) ? 1 : 0; 1194 u32 vector = vector_flags; /* discard flags in the upper dword */ 1195 int i; 1196 1197 /* make sure data gets read from RAM */ 1198 mlx5_fwp_invalidate(cmd->cmd_page); 1199 1200 while (vector != 0) { 1201 i = ffs(vector) - 1; 1202 vector &= ~(1U << i); 1203 /* check command mode */ 1204 if (cmd->ent_mode[i] != cmd_mode) 1205 continue; 1206 ent = cmd->ent_arr[i]; 1207 /* check if command was already handled */ 1208 if (ent == NULL) 1209 continue; 1210 if (ent->callback) 1211 cancel_delayed_work(&ent->cb_timeout_work); 1212 ent->ts2 = ktime_get_ns(); 1213 memcpy(ent->out->first.data, ent->lay->out, 1214 sizeof(ent->lay->out)); 1215 /* make sure data gets read from RAM */ 1216 mlx5_fwp_invalidate(ent->out); 1217 dump_command(dev, ent, 0); 1218 if (!ent->ret) { 1219 if (!cmd->checksum_disabled) 1220 ent->ret = verify_signature(ent); 1221 else 1222 ent->ret = 0; 1223 1224 if (triggered) 1225 ent->status = MLX5_DRIVER_STATUS_ABORTED; 1226 else 1227 ent->status = ent->lay->status_own >> 1; 1228 1229 mlx5_core_dbg(dev, 1230 "FW command ret 0x%x, status %s(0x%x)\n", 1231 ent->ret, 1232 deliv_status_to_str(ent->status), 1233 ent->status); 1234 } 1235 free_ent(cmd, ent->idx); 1236 complete_command(ent); 1237 } 1238 } 1239 EXPORT_SYMBOL(mlx5_cmd_comp_handler); 1240 1241 static int status_to_err(u8 status) 1242 { 1243 return status ? -EIO : 0; /* TBD more meaningful codes */ 1244 } 1245 1246 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size, 1247 gfp_t gfp) 1248 { 1249 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM); 1250 struct mlx5_cmd *cmd = &dev->cmd; 1251 struct cache_ent *ent = NULL; 1252 1253 if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE) 1254 ent = &cmd->cache.large; 1255 else if (in_size > 16 && in_size <= MED_LIST_SIZE) 1256 ent = &cmd->cache.med; 1257 1258 if (ent) { 1259 spin_lock_irq(&ent->lock); 1260 if (!list_empty(&ent->head)) { 1261 msg = list_entry(ent->head.next, struct mlx5_cmd_msg, 1262 list); 1263 list_del(&msg->list); 1264 } 1265 spin_unlock_irq(&ent->lock); 1266 } 1267 1268 if (IS_ERR(msg)) 1269 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size); 1270 1271 return msg; 1272 } 1273 1274 static int is_manage_pages(void *in) 1275 { 1276 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES; 1277 } 1278 1279 static int cmd_exec_helper(struct mlx5_core_dev *dev, 1280 void *in, int in_size, 1281 void *out, int out_size, 1282 mlx5_cmd_cbk_t callback, void *context, 1283 bool force_polling) 1284 { 1285 struct mlx5_cmd_msg *inb; 1286 struct mlx5_cmd_msg *outb; 1287 int pages_queue; 1288 const gfp_t gfp = GFP_KERNEL; 1289 int err; 1290 u8 status = 0; 1291 u32 drv_synd; 1292 1293 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1294 u16 opcode = MLX5_GET(mbox_in, in, opcode); 1295 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status); 1296 MLX5_SET(mbox_out, out, status, status); 1297 MLX5_SET(mbox_out, out, syndrome, drv_synd); 1298 return err; 1299 } 1300 1301 pages_queue = is_manage_pages(in); 1302 1303 inb = alloc_msg(dev, in_size, gfp); 1304 if (IS_ERR(inb)) { 1305 err = PTR_ERR(inb); 1306 return err; 1307 } 1308 1309 err = mlx5_copy_to_msg(inb, in, in_size); 1310 if (err) { 1311 mlx5_core_warn(dev, "err %d\n", err); 1312 goto out_in; 1313 } 1314 1315 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size); 1316 if (IS_ERR(outb)) { 1317 err = PTR_ERR(outb); 1318 goto out_in; 1319 } 1320 1321 err = mlx5_cmd_invoke(dev, inb, in_size, outb, out, out_size, callback, 1322 context, pages_queue, &status, force_polling); 1323 if (err) { 1324 if (err == -ETIMEDOUT) 1325 return err; 1326 goto out_out; 1327 } 1328 1329 mlx5_core_dbg(dev, "err %d, status %d\n", err, status); 1330 if (status) { 1331 err = status_to_err(status); 1332 goto out_out; 1333 } 1334 1335 if (callback) 1336 return err; 1337 1338 err = mlx5_copy_from_msg(out, outb, out_size); 1339 1340 out_out: 1341 mlx5_free_cmd_msg(dev, outb); 1342 1343 out_in: 1344 free_msg(dev, inb); 1345 return err; 1346 } 1347 1348 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 1349 int out_size) 1350 { 1351 int err; 1352 1353 err = cmd_exec_helper(dev, in, in_size, out, out_size, NULL, NULL, false); 1354 return err ? : mlx5_cmd_check(dev, in, out); 1355 } 1356 EXPORT_SYMBOL(mlx5_cmd_exec); 1357 1358 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, 1359 struct mlx5_async_ctx *ctx) 1360 { 1361 ctx->dev = dev; 1362 /* Starts at 1 to avoid doing wake_up if we are not cleaning up */ 1363 atomic_set(&ctx->num_inflight, 1); 1364 init_waitqueue_head(&ctx->wait); 1365 } 1366 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx); 1367 1368 /** 1369 * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx 1370 * @ctx: The ctx to clean 1371 * 1372 * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The 1373 * caller must ensure that mlx5_cmd_exec_cb() is not called during or after 1374 * the call mlx5_cleanup_async_ctx(). 1375 */ 1376 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx) 1377 { 1378 atomic_dec(&ctx->num_inflight); 1379 wait_event(ctx->wait, atomic_read(&ctx->num_inflight) == 0); 1380 } 1381 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx); 1382 1383 static void mlx5_cmd_exec_cb_handler(int status, void *_work) 1384 { 1385 struct mlx5_async_work *work = _work; 1386 struct mlx5_async_ctx *ctx = work->ctx; 1387 1388 work->user_callback(status, work); 1389 if (atomic_dec_and_test(&ctx->num_inflight)) 1390 wake_up(&ctx->wait); 1391 } 1392 1393 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, 1394 void *out, int out_size, mlx5_async_cbk_t callback, 1395 struct mlx5_async_work *work) 1396 { 1397 int ret; 1398 1399 work->ctx = ctx; 1400 work->user_callback = callback; 1401 if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight))) 1402 return -EIO; 1403 ret = cmd_exec_helper(ctx->dev, in, in_size, out, out_size, 1404 mlx5_cmd_exec_cb_handler, work, false); 1405 if (ret && atomic_dec_and_test(&ctx->num_inflight)) 1406 wake_up(&ctx->wait); 1407 1408 return ret; 1409 } 1410 EXPORT_SYMBOL(mlx5_cmd_exec_cb); 1411 1412 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 1413 void *out, int out_size) 1414 { 1415 int err; 1416 1417 err = cmd_exec_helper(dev, in, in_size, out, out_size, NULL, NULL, true); 1418 return err ? : mlx5_cmd_check(dev, in, out); 1419 } 1420 EXPORT_SYMBOL(mlx5_cmd_exec_polling); 1421 1422 static void destroy_msg_cache(struct mlx5_core_dev *dev) 1423 { 1424 struct mlx5_cmd *cmd = &dev->cmd; 1425 struct mlx5_cmd_msg *msg; 1426 struct mlx5_cmd_msg *n; 1427 1428 list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) { 1429 list_del(&msg->list); 1430 mlx5_free_cmd_msg(dev, msg); 1431 } 1432 1433 list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) { 1434 list_del(&msg->list); 1435 mlx5_free_cmd_msg(dev, msg); 1436 } 1437 } 1438 1439 static int create_msg_cache(struct mlx5_core_dev *dev) 1440 { 1441 struct mlx5_cmd *cmd = &dev->cmd; 1442 struct mlx5_cmd_msg *msg; 1443 int err; 1444 int i; 1445 1446 spin_lock_init(&cmd->cache.large.lock); 1447 INIT_LIST_HEAD(&cmd->cache.large.head); 1448 spin_lock_init(&cmd->cache.med.lock); 1449 INIT_LIST_HEAD(&cmd->cache.med.head); 1450 1451 for (i = 0; i < NUM_LONG_LISTS; i++) { 1452 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE); 1453 if (IS_ERR(msg)) { 1454 err = PTR_ERR(msg); 1455 goto ex_err; 1456 } 1457 msg->cache = &cmd->cache.large; 1458 list_add_tail(&msg->list, &cmd->cache.large.head); 1459 } 1460 1461 for (i = 0; i < NUM_MED_LISTS; i++) { 1462 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE); 1463 if (IS_ERR(msg)) { 1464 err = PTR_ERR(msg); 1465 goto ex_err; 1466 } 1467 msg->cache = &cmd->cache.med; 1468 list_add_tail(&msg->list, &cmd->cache.med.head); 1469 } 1470 1471 return 0; 1472 1473 ex_err: 1474 destroy_msg_cache(dev); 1475 return err; 1476 } 1477 1478 static int 1479 alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd) 1480 { 1481 int err; 1482 1483 sx_init(&cmd->dma_sx, "MLX5-DMA-SX"); 1484 mtx_init(&cmd->dma_mtx, "MLX5-DMA-MTX", NULL, MTX_DEF); 1485 cv_init(&cmd->dma_cv, "MLX5-DMA-CV"); 1486 1487 /* 1488 * Create global DMA descriptor tag for allocating 1489 * 4K firmware pages: 1490 */ 1491 err = -bus_dma_tag_create( 1492 bus_get_dma_tag(dev->pdev->dev.bsddev), 1493 MLX5_ADAPTER_PAGE_SIZE, /* alignment */ 1494 0, /* no boundary */ 1495 BUS_SPACE_MAXADDR, /* lowaddr */ 1496 BUS_SPACE_MAXADDR, /* highaddr */ 1497 NULL, NULL, /* filter, filterarg */ 1498 MLX5_ADAPTER_PAGE_SIZE, /* maxsize */ 1499 1, /* nsegments */ 1500 MLX5_ADAPTER_PAGE_SIZE, /* maxsegsize */ 1501 0, /* flags */ 1502 NULL, NULL, /* lockfunc, lockfuncarg */ 1503 &cmd->dma_tag); 1504 if (err != 0) 1505 goto failure_destroy_sx; 1506 1507 cmd->cmd_page = mlx5_fwp_alloc(dev, GFP_KERNEL, 1); 1508 if (cmd->cmd_page == NULL) { 1509 err = -ENOMEM; 1510 goto failure_alloc_page; 1511 } 1512 cmd->dma = mlx5_fwp_get_dma(cmd->cmd_page, 0); 1513 cmd->cmd_buf = mlx5_fwp_get_virt(cmd->cmd_page, 0); 1514 return (0); 1515 1516 failure_alloc_page: 1517 bus_dma_tag_destroy(cmd->dma_tag); 1518 1519 failure_destroy_sx: 1520 cv_destroy(&cmd->dma_cv); 1521 mtx_destroy(&cmd->dma_mtx); 1522 sx_destroy(&cmd->dma_sx); 1523 return (err); 1524 } 1525 1526 static void 1527 free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd) 1528 { 1529 1530 mlx5_fwp_free(cmd->cmd_page); 1531 bus_dma_tag_destroy(cmd->dma_tag); 1532 cv_destroy(&cmd->dma_cv); 1533 mtx_destroy(&cmd->dma_mtx); 1534 sx_destroy(&cmd->dma_sx); 1535 } 1536 1537 int mlx5_cmd_init(struct mlx5_core_dev *dev) 1538 { 1539 struct mlx5_cmd *cmd = &dev->cmd; 1540 u32 cmd_h, cmd_l; 1541 u16 cmd_if_rev; 1542 int err; 1543 int i; 1544 1545 memset(cmd, 0, sizeof(*cmd)); 1546 cmd_if_rev = cmdif_rev_get(dev); 1547 if (cmd_if_rev != CMD_IF_REV) { 1548 mlx5_core_err(dev, 1549 "Driver cmdif rev(%d) differs from firmware's(%d)\n", 1550 CMD_IF_REV, cmd_if_rev); 1551 return -EINVAL; 1552 } 1553 1554 err = alloc_cmd_page(dev, cmd); 1555 if (err) 1556 goto err_free_pool; 1557 1558 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff; 1559 cmd->log_sz = cmd_l >> 4 & 0xf; 1560 cmd->log_stride = cmd_l & 0xf; 1561 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) { 1562 mlx5_core_err(dev, 1563 "firmware reports too many outstanding commands %d\n", 1564 1 << cmd->log_sz); 1565 err = -EINVAL; 1566 goto err_free_page; 1567 } 1568 1569 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) { 1570 mlx5_core_err(dev, 1571 "command queue size overflow\n"); 1572 err = -EINVAL; 1573 goto err_free_page; 1574 } 1575 1576 cmd->checksum_disabled = 1; 1577 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1; 1578 cmd->bitmask = (1 << cmd->max_reg_cmds) - 1; 1579 1580 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 1581 if (cmd->cmdif_rev > CMD_IF_REV) { 1582 mlx5_core_err(dev, 1583 "driver does not support command interface version. driver %d, firmware %d\n", 1584 CMD_IF_REV, cmd->cmdif_rev); 1585 err = -ENOTSUPP; 1586 goto err_free_page; 1587 } 1588 1589 spin_lock_init(&cmd->alloc_lock); 1590 spin_lock_init(&cmd->token_lock); 1591 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++) 1592 spin_lock_init(&cmd->stats[i].lock); 1593 1594 sema_init(&cmd->sem, cmd->max_reg_cmds); 1595 sema_init(&cmd->pages_sem, 1); 1596 1597 cmd_h = (u32)((u64)(cmd->dma) >> 32); 1598 cmd_l = (u32)(cmd->dma); 1599 if (cmd_l & 0xfff) { 1600 mlx5_core_err(dev, "invalid command queue address\n"); 1601 err = -ENOMEM; 1602 goto err_free_page; 1603 } 1604 1605 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h); 1606 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz); 1607 1608 /* Make sure firmware sees the complete address before we proceed */ 1609 wmb(); 1610 1611 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma)); 1612 1613 cmd->mode = MLX5_CMD_MODE_POLLING; 1614 1615 err = create_msg_cache(dev); 1616 if (err) { 1617 mlx5_core_err(dev, "failed to create command cache\n"); 1618 goto err_free_page; 1619 } 1620 return 0; 1621 1622 err_free_page: 1623 free_cmd_page(dev, cmd); 1624 1625 err_free_pool: 1626 return err; 1627 } 1628 EXPORT_SYMBOL(mlx5_cmd_init); 1629 1630 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev) 1631 { 1632 struct mlx5_cmd *cmd = &dev->cmd; 1633 1634 clean_debug_files(dev); 1635 flush_workqueue(dev->priv.health.wq_cmd); 1636 destroy_msg_cache(dev); 1637 free_cmd_page(dev, cmd); 1638 } 1639 EXPORT_SYMBOL(mlx5_cmd_cleanup); 1640 1641 int mlx5_cmd_query_cong_counter(struct mlx5_core_dev *dev, 1642 bool reset, void *out, int out_size) 1643 { 1644 u32 in[MLX5_ST_SZ_DW(query_cong_statistics_in)] = { }; 1645 1646 MLX5_SET(query_cong_statistics_in, in, opcode, 1647 MLX5_CMD_OP_QUERY_CONG_STATISTICS); 1648 MLX5_SET(query_cong_statistics_in, in, clear, reset); 1649 return mlx5_cmd_exec(dev, in, sizeof(in), out, out_size); 1650 } 1651 EXPORT_SYMBOL(mlx5_cmd_query_cong_counter); 1652 1653 int mlx5_cmd_query_cong_params(struct mlx5_core_dev *dev, int cong_point, 1654 void *out, int out_size) 1655 { 1656 u32 in[MLX5_ST_SZ_DW(query_cong_params_in)] = { }; 1657 1658 MLX5_SET(query_cong_params_in, in, opcode, 1659 MLX5_CMD_OP_QUERY_CONG_PARAMS); 1660 MLX5_SET(query_cong_params_in, in, cong_protocol, cong_point); 1661 1662 return mlx5_cmd_exec(dev, in, sizeof(in), out, out_size); 1663 } 1664 EXPORT_SYMBOL(mlx5_cmd_query_cong_params); 1665 1666 int mlx5_cmd_modify_cong_params(struct mlx5_core_dev *dev, 1667 void *in, int in_size) 1668 { 1669 u32 out[MLX5_ST_SZ_DW(modify_cong_params_out)] = { }; 1670 1671 return mlx5_cmd_exec(dev, in, in_size, out, sizeof(out)); 1672 } 1673 EXPORT_SYMBOL(mlx5_cmd_modify_cong_params); 1674 1675 int mlx5_cmd_query_cong_status(struct mlx5_core_dev *dev, int cong_point, 1676 int prio, void *out, int out_size) 1677 { 1678 u32 in[MLX5_ST_SZ_DW(query_cong_status_in)] = { }; 1679 1680 MLX5_SET(query_cong_status_in, in, opcode, 1681 MLX5_CMD_OP_QUERY_CONG_STATUS); 1682 MLX5_SET(query_cong_status_in, in, priority, prio); 1683 MLX5_SET(query_cong_status_in, in, cong_protocol, cong_point); 1684 1685 return mlx5_cmd_exec(dev, in, sizeof(in), out, out_size); 1686 } 1687 EXPORT_SYMBOL(mlx5_cmd_query_cong_status); 1688 1689 int mlx5_cmd_modify_cong_status(struct mlx5_core_dev *dev, 1690 void *in, int in_size) 1691 { 1692 u32 out[MLX5_ST_SZ_DW(modify_cong_status_out)] = { }; 1693 1694 return mlx5_cmd_exec(dev, in, in_size, out, sizeof(out)); 1695 } 1696 EXPORT_SYMBOL(mlx5_cmd_modify_cong_status); 1697