1dc7e38acSHans Petter Selasky /*-
2b633e08cSHans Petter Selasky * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved.
3dc7e38acSHans Petter Selasky *
4dc7e38acSHans Petter Selasky * Redistribution and use in source and binary forms, with or without
5dc7e38acSHans Petter Selasky * modification, are permitted provided that the following conditions
6dc7e38acSHans Petter Selasky * are met:
7dc7e38acSHans Petter Selasky * 1. Redistributions of source code must retain the above copyright
8dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer.
9dc7e38acSHans Petter Selasky * 2. Redistributions in binary form must reproduce the above copyright
10dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer in the
11dc7e38acSHans Petter Selasky * documentation and/or other materials provided with the distribution.
12dc7e38acSHans Petter Selasky *
13dc7e38acSHans Petter Selasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14dc7e38acSHans Petter Selasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15dc7e38acSHans Petter Selasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16dc7e38acSHans Petter Selasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17dc7e38acSHans Petter Selasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18dc7e38acSHans Petter Selasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19dc7e38acSHans Petter Selasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20dc7e38acSHans Petter Selasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21dc7e38acSHans Petter Selasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22dc7e38acSHans Petter Selasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23dc7e38acSHans Petter Selasky * SUCH DAMAGE.
24dc7e38acSHans Petter Selasky */
25dc7e38acSHans Petter Selasky
26ee9d634bSKonstantin Belousov #include "opt_rss.h"
27ee9d634bSKonstantin Belousov #include "opt_ratelimit.h"
28ee9d634bSKonstantin Belousov
29dc7e38acSHans Petter Selasky #include <linux/interrupt.h>
30dc7e38acSHans Petter Selasky #include <linux/module.h>
31d9142151SHans Petter Selasky #include <dev/mlx5/port.h>
32dc7e38acSHans Petter Selasky #include <dev/mlx5/mlx5_ifc.h>
33e5eae1dcSHans Petter Selasky #include <dev/mlx5/mlx5_fpga/core.h>
3412c56d7dSHans Petter Selasky #include <dev/mlx5/mlx5_core/mlx5_core.h>
3512c56d7dSHans Petter Selasky #include <dev/mlx5/mlx5_core/eswitch.h>
36dc7e38acSHans Petter Selasky
37278ce1c9SHans Petter Selasky #ifdef RSS
38278ce1c9SHans Petter Selasky #include <net/rss_config.h>
39278ce1c9SHans Petter Selasky #include <netinet/in_rss.h>
40278ce1c9SHans Petter Selasky #endif
41278ce1c9SHans Petter Selasky
42dc7e38acSHans Petter Selasky enum {
43dc7e38acSHans Petter Selasky MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
44dc7e38acSHans Petter Selasky MLX5_EQE_OWNER_INIT_VAL = 0x1,
45dc7e38acSHans Petter Selasky };
46dc7e38acSHans Petter Selasky
47dc7e38acSHans Petter Selasky enum {
48dc7e38acSHans Petter Selasky MLX5_NUM_SPARE_EQE = 0x80,
49dc7e38acSHans Petter Selasky MLX5_NUM_ASYNC_EQE = 0x100,
50dc7e38acSHans Petter Selasky MLX5_NUM_CMD_EQE = 32,
51dc7e38acSHans Petter Selasky };
52dc7e38acSHans Petter Selasky
53dc7e38acSHans Petter Selasky enum {
54dc7e38acSHans Petter Selasky MLX5_EQ_DOORBEL_OFFSET = 0x40,
55dc7e38acSHans Petter Selasky };
56dc7e38acSHans Petter Selasky
57dc7e38acSHans Petter Selasky #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
58dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
59dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
60dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
61dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
62dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
63dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
64dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
65dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
66dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
67dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
68bbcb656aSKonstantin Belousov (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT) | \
69bbcb656aSKonstantin Belousov (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE))
70dc7e38acSHans Petter Selasky
71dc7e38acSHans Petter Selasky struct map_eq_in {
72dc7e38acSHans Petter Selasky u64 mask;
73dc7e38acSHans Petter Selasky u32 reserved;
74dc7e38acSHans Petter Selasky u32 unmap_eqn;
75dc7e38acSHans Petter Selasky };
76dc7e38acSHans Petter Selasky
77dc7e38acSHans Petter Selasky struct cre_des_eq {
78dc7e38acSHans Petter Selasky u8 reserved[15];
79dc7e38acSHans Petter Selasky u8 eqn;
80dc7e38acSHans Petter Selasky };
81dc7e38acSHans Petter Selasky
82dc7e38acSHans Petter Selasky /*Function prototype*/
83dc7e38acSHans Petter Selasky static void mlx5_port_module_event(struct mlx5_core_dev *dev,
84dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe);
856c7057f7SHans Petter Selasky static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev,
866c7057f7SHans Petter Selasky struct mlx5_eqe *eqe);
87dc7e38acSHans Petter Selasky
mlx5_cmd_destroy_eq(struct mlx5_core_dev * dev,u8 eqn)88dc7e38acSHans Petter Selasky static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
89dc7e38acSHans Petter Selasky {
90788333d9SHans Petter Selasky u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0};
91788333d9SHans Petter Selasky u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
92dc7e38acSHans Petter Selasky
93dc7e38acSHans Petter Selasky MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
94dc7e38acSHans Petter Selasky MLX5_SET(destroy_eq_in, in, eq_number, eqn);
95dc7e38acSHans Petter Selasky
96788333d9SHans Petter Selasky return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
97dc7e38acSHans Petter Selasky }
98dc7e38acSHans Petter Selasky
get_eqe(struct mlx5_eq * eq,u32 entry)99dc7e38acSHans Petter Selasky static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
100dc7e38acSHans Petter Selasky {
101dc7e38acSHans Petter Selasky return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
102dc7e38acSHans Petter Selasky }
103dc7e38acSHans Petter Selasky
next_eqe_sw(struct mlx5_eq * eq)104dc7e38acSHans Petter Selasky static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
105dc7e38acSHans Petter Selasky {
106dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
107dc7e38acSHans Petter Selasky
108dc7e38acSHans Petter Selasky return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
109dc7e38acSHans Petter Selasky }
110dc7e38acSHans Petter Selasky
eqe_type_str(u8 type)111dc7e38acSHans Petter Selasky static const char *eqe_type_str(u8 type)
112dc7e38acSHans Petter Selasky {
113dc7e38acSHans Petter Selasky switch (type) {
114dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMP:
115dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_COMP";
116dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG:
117dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PATH_MIG";
118dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMM_EST:
119dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_COMM_EST";
120dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SQ_DRAINED:
121dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SQ_DRAINED";
122dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
123dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
124dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
125dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
126dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CQ_ERROR:
127dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_CQ_ERROR";
128dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
129dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
130dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
131dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
132dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
133dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
134dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
135dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
136dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
137dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
138dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_INTERNAL_ERROR:
139dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
140dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PORT_CHANGE:
141dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PORT_CHANGE";
142dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_GPIO_EVENT:
143dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_GPIO_EVENT";
144dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
145dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
146983026eaSHans Petter Selasky case MLX5_EVENT_TYPE_TEMP_WARN_EVENT:
147983026eaSHans Petter Selasky return "MLX5_EVENT_TYPE_TEMP_WARN_EVENT";
148dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_REMOTE_CONFIG:
149dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
150dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
151dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
152dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_STALL_EVENT:
153dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_STALL_EVENT";
154dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CMD:
155dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_CMD";
156dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PAGE_REQUEST:
157dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PAGE_REQUEST";
158dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
159dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
160e5eae1dcSHans Petter Selasky case MLX5_EVENT_TYPE_FPGA_ERROR:
161e5eae1dcSHans Petter Selasky return "MLX5_EVENT_TYPE_FPGA_ERROR";
162e5eae1dcSHans Petter Selasky case MLX5_EVENT_TYPE_FPGA_QP_ERROR:
163e5eae1dcSHans Petter Selasky return "MLX5_EVENT_TYPE_FPGA_QP_ERROR";
164cb4e4a6eSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT:
165cb4e4a6eSHans Petter Selasky return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT";
1666c7057f7SHans Petter Selasky case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT:
1676c7057f7SHans Petter Selasky return "MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT";
168dc7e38acSHans Petter Selasky default:
169dc7e38acSHans Petter Selasky return "Unrecognized event";
170dc7e38acSHans Petter Selasky }
171dc7e38acSHans Petter Selasky }
172dc7e38acSHans Petter Selasky
port_subtype_event(u8 subtype)173dc7e38acSHans Petter Selasky static enum mlx5_dev_event port_subtype_event(u8 subtype)
174dc7e38acSHans Petter Selasky {
175dc7e38acSHans Petter Selasky switch (subtype) {
176dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
177dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_DOWN;
178dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
179dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_UP;
180dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
181dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_INITIALIZED;
182dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_LID:
183dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_LID_CHANGE;
184dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
185dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PKEY_CHANGE;
186dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_GUID:
187dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_GUID_CHANGE;
188dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
189dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_CLIENT_REREG;
190dc7e38acSHans Petter Selasky }
191dc7e38acSHans Petter Selasky return -1;
192dc7e38acSHans Petter Selasky }
193dc7e38acSHans Petter Selasky
dcbx_subevent(u8 subtype)194cb4e4a6eSHans Petter Selasky static enum mlx5_dev_event dcbx_subevent(u8 subtype)
195cb4e4a6eSHans Petter Selasky {
196cb4e4a6eSHans Petter Selasky switch (subtype) {
197cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX:
198cb4e4a6eSHans Petter Selasky return MLX5_DEV_EVENT_ERROR_STATE_DCBX;
199cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE:
200cb4e4a6eSHans Petter Selasky return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE;
201cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE:
202cb4e4a6eSHans Petter Selasky return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE;
203cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE:
204cb4e4a6eSHans Petter Selasky return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE;
205cb4e4a6eSHans Petter Selasky }
206cb4e4a6eSHans Petter Selasky return -1;
207cb4e4a6eSHans Petter Selasky }
208cb4e4a6eSHans Petter Selasky
eq_update_ci(struct mlx5_eq * eq,int arm)209dc7e38acSHans Petter Selasky static void eq_update_ci(struct mlx5_eq *eq, int arm)
210dc7e38acSHans Petter Selasky {
211dc7e38acSHans Petter Selasky __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
212dc7e38acSHans Petter Selasky u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
213dc7e38acSHans Petter Selasky __raw_writel((__force u32) cpu_to_be32(val), addr);
214dc7e38acSHans Petter Selasky /* We still want ordering, just not swabbing, so add a barrier */
215dc7e38acSHans Petter Selasky mb();
216dc7e38acSHans Petter Selasky }
217dc7e38acSHans Petter Selasky
218983026eaSHans Petter Selasky static void
mlx5_temp_warning_event(struct mlx5_core_dev * dev,struct mlx5_eqe * eqe)219983026eaSHans Petter Selasky mlx5_temp_warning_event(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe)
220983026eaSHans Petter Selasky {
221983026eaSHans Petter Selasky
222983026eaSHans Petter Selasky mlx5_core_warn(dev,
22395c05e05SHans Petter Selasky "High temperature on sensors with bit set %#jx %#jx\n",
224983026eaSHans Petter Selasky (uintmax_t)be64_to_cpu(eqe->data.temp_warning.sensor_warning_msb),
225983026eaSHans Petter Selasky (uintmax_t)be64_to_cpu(eqe->data.temp_warning.sensor_warning_lsb));
226983026eaSHans Petter Selasky }
227983026eaSHans Petter Selasky
mlx5_eq_int(struct mlx5_core_dev * dev,struct mlx5_eq * eq)228dc7e38acSHans Petter Selasky static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
229dc7e38acSHans Petter Selasky {
230dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe;
231dc7e38acSHans Petter Selasky int eqes_found = 0;
232dc7e38acSHans Petter Selasky int set_ci = 0;
233dc7e38acSHans Petter Selasky u32 cqn;
234dc7e38acSHans Petter Selasky u32 rsn;
235dc7e38acSHans Petter Selasky u8 port;
236dc7e38acSHans Petter Selasky
237dc7e38acSHans Petter Selasky while ((eqe = next_eqe_sw(eq))) {
238dc7e38acSHans Petter Selasky /*
239dc7e38acSHans Petter Selasky * Make sure we read EQ entry contents after we've
240dc7e38acSHans Petter Selasky * checked the ownership bit.
241dc7e38acSHans Petter Selasky */
24292d8df2fSKonstantin Belousov atomic_thread_fence_acq();
243dc7e38acSHans Petter Selasky
244dc7e38acSHans Petter Selasky mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
245dc7e38acSHans Petter Selasky eq->eqn, eqe_type_str(eqe->type));
246b633e08cSHans Petter Selasky
247b633e08cSHans Petter Selasky if (dev->priv.eq_table.cb != NULL &&
248b633e08cSHans Petter Selasky dev->priv.eq_table.cb(dev, eqe->type, &eqe->data)) {
249b633e08cSHans Petter Selasky /* FALLTHROUGH */
250b633e08cSHans Petter Selasky } else switch (eqe->type) {
251dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMP:
252f34f0a65SHans Petter Selasky mlx5_cq_completion(dev, eqe);
253dc7e38acSHans Petter Selasky break;
254dc7e38acSHans Petter Selasky
255dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG:
256dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMM_EST:
257dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SQ_DRAINED:
258dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
259dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
260dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
261dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
262dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
263dc7e38acSHans Petter Selasky rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
264dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
265dc7e38acSHans Petter Selasky eqe_type_str(eqe->type), eqe->type, rsn);
266dc7e38acSHans Petter Selasky mlx5_rsc_event(dev, rsn, eqe->type);
267dc7e38acSHans Petter Selasky break;
268dc7e38acSHans Petter Selasky
269dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
270dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
271dc7e38acSHans Petter Selasky rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
272dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
273dc7e38acSHans Petter Selasky eqe_type_str(eqe->type), eqe->type, rsn);
274dc7e38acSHans Petter Selasky mlx5_srq_event(dev, rsn, eqe->type);
275dc7e38acSHans Petter Selasky break;
276dc7e38acSHans Petter Selasky
277dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CMD:
278721a1a6aSSlava Shwartsman if (dev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
279721a1a6aSSlava Shwartsman mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector),
280721a1a6aSSlava Shwartsman MLX5_CMD_MODE_EVENTS);
281721a1a6aSSlava Shwartsman }
282dc7e38acSHans Petter Selasky break;
283dc7e38acSHans Petter Selasky
284dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PORT_CHANGE:
285dc7e38acSHans Petter Selasky port = (eqe->data.port.port >> 4) & 0xf;
286dc7e38acSHans Petter Selasky switch (eqe->sub_type) {
287dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
288dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
289dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_LID:
290dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
291dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_GUID:
292dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
293dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
294dc7e38acSHans Petter Selasky if (dev->event)
295dc7e38acSHans Petter Selasky dev->event(dev, port_subtype_event(eqe->sub_type),
296dc7e38acSHans Petter Selasky (unsigned long)port);
297dc7e38acSHans Petter Selasky break;
298dc7e38acSHans Petter Selasky default:
299dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
300dc7e38acSHans Petter Selasky port, eqe->sub_type);
301dc7e38acSHans Petter Selasky }
302dc7e38acSHans Petter Selasky break;
303cb4e4a6eSHans Petter Selasky
304cb4e4a6eSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT:
305cb4e4a6eSHans Petter Selasky port = (eqe->data.port.port >> 4) & 0xf;
306cb4e4a6eSHans Petter Selasky switch (eqe->sub_type) {
307cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX:
308cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE:
309cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE:
310cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE:
311cb4e4a6eSHans Petter Selasky if (dev->event)
312cb4e4a6eSHans Petter Selasky dev->event(dev,
313cb4e4a6eSHans Petter Selasky dcbx_subevent(eqe->sub_type),
314cb4e4a6eSHans Petter Selasky 0);
315cb4e4a6eSHans Petter Selasky break;
316cb4e4a6eSHans Petter Selasky default:
317cb4e4a6eSHans Petter Selasky mlx5_core_warn(dev,
318cb4e4a6eSHans Petter Selasky "dcbx event with unrecognized subtype: port %d, sub_type %d\n",
319cb4e4a6eSHans Petter Selasky port, eqe->sub_type);
320cb4e4a6eSHans Petter Selasky }
321cb4e4a6eSHans Petter Selasky break;
322cb4e4a6eSHans Petter Selasky
3236c7057f7SHans Petter Selasky case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT:
3246c7057f7SHans Petter Selasky mlx5_port_general_notification_event(dev, eqe);
3256c7057f7SHans Petter Selasky break;
3266c7057f7SHans Petter Selasky
327dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CQ_ERROR:
328dc7e38acSHans Petter Selasky cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
329dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
330dc7e38acSHans Petter Selasky cqn, eqe->data.cq_err.syndrome);
331dc7e38acSHans Petter Selasky mlx5_cq_event(dev, cqn, eqe->type);
332dc7e38acSHans Petter Selasky break;
333dc7e38acSHans Petter Selasky
334dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PAGE_REQUEST:
335dc7e38acSHans Petter Selasky {
336dc7e38acSHans Petter Selasky u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
337dc7e38acSHans Petter Selasky s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
338dc7e38acSHans Petter Selasky
339dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
340dc7e38acSHans Petter Selasky func_id, npages);
341dc7e38acSHans Petter Selasky mlx5_core_req_pages_handler(dev, func_id, npages);
342dc7e38acSHans Petter Selasky }
343dc7e38acSHans Petter Selasky break;
344dc7e38acSHans Petter Selasky
345dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
346dc7e38acSHans Petter Selasky mlx5_port_module_event(dev, eqe);
347dc7e38acSHans Petter Selasky break;
348dc7e38acSHans Petter Selasky
349dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
350dc7e38acSHans Petter Selasky {
351dc7e38acSHans Petter Selasky struct mlx5_eqe_vport_change *vc_eqe =
352dc7e38acSHans Petter Selasky &eqe->data.vport_change;
353dc7e38acSHans Petter Selasky u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
354dc7e38acSHans Petter Selasky
355dc7e38acSHans Petter Selasky if (dev->event)
356dc7e38acSHans Petter Selasky dev->event(dev,
357dc7e38acSHans Petter Selasky MLX5_DEV_EVENT_VPORT_CHANGE,
358dc7e38acSHans Petter Selasky (unsigned long)vport_num);
359dc7e38acSHans Petter Selasky }
360bbcb656aSKonstantin Belousov if (dev->priv.eswitch != NULL)
361bbcb656aSKonstantin Belousov mlx5_eswitch_vport_event(dev->priv.eswitch,
362bbcb656aSKonstantin Belousov eqe);
363dc7e38acSHans Petter Selasky break;
364dc7e38acSHans Petter Selasky
365e5eae1dcSHans Petter Selasky case MLX5_EVENT_TYPE_FPGA_ERROR:
366e5eae1dcSHans Petter Selasky case MLX5_EVENT_TYPE_FPGA_QP_ERROR:
367e5eae1dcSHans Petter Selasky mlx5_fpga_event(dev, eqe->type, &eqe->data.raw);
368e5eae1dcSHans Petter Selasky break;
369983026eaSHans Petter Selasky case MLX5_EVENT_TYPE_TEMP_WARN_EVENT:
370983026eaSHans Petter Selasky mlx5_temp_warning_event(dev, eqe);
371983026eaSHans Petter Selasky break;
372e5eae1dcSHans Petter Selasky
373dc7e38acSHans Petter Selasky default:
374dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
375dc7e38acSHans Petter Selasky eqe->type, eq->eqn);
376dc7e38acSHans Petter Selasky break;
377dc7e38acSHans Petter Selasky }
378dc7e38acSHans Petter Selasky
379dc7e38acSHans Petter Selasky ++eq->cons_index;
380dc7e38acSHans Petter Selasky eqes_found = 1;
381dc7e38acSHans Petter Selasky ++set_ci;
382dc7e38acSHans Petter Selasky
383dc7e38acSHans Petter Selasky /* The HCA will think the queue has overflowed if we
384dc7e38acSHans Petter Selasky * don't tell it we've been processing events. We
385dc7e38acSHans Petter Selasky * create our EQs with MLX5_NUM_SPARE_EQE extra
386dc7e38acSHans Petter Selasky * entries, so we must update our consumer index at
387dc7e38acSHans Petter Selasky * least that often.
388dc7e38acSHans Petter Selasky */
389dc7e38acSHans Petter Selasky if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
390dc7e38acSHans Petter Selasky eq_update_ci(eq, 0);
391dc7e38acSHans Petter Selasky set_ci = 0;
392dc7e38acSHans Petter Selasky }
393dc7e38acSHans Petter Selasky }
394dc7e38acSHans Petter Selasky
395dc7e38acSHans Petter Selasky eq_update_ci(eq, 1);
396dc7e38acSHans Petter Selasky
397dc7e38acSHans Petter Selasky return eqes_found;
398dc7e38acSHans Petter Selasky }
399dc7e38acSHans Petter Selasky
mlx5_msix_handler(int irq,void * eq_ptr)400dc7e38acSHans Petter Selasky static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
401dc7e38acSHans Petter Selasky {
402dc7e38acSHans Petter Selasky struct mlx5_eq *eq = eq_ptr;
403dc7e38acSHans Petter Selasky struct mlx5_core_dev *dev = eq->dev;
404dc7e38acSHans Petter Selasky
405192fc18dSHans Petter Selasky /* check if IRQs are not disabled */
406192fc18dSHans Petter Selasky if (likely(dev->priv.disable_irqs == 0))
407dc7e38acSHans Petter Selasky mlx5_eq_int(dev, eq);
408dc7e38acSHans Petter Selasky
409dc7e38acSHans Petter Selasky /* MSI-X vectors always belong to us */
410dc7e38acSHans Petter Selasky return IRQ_HANDLED;
411dc7e38acSHans Petter Selasky }
412dc7e38acSHans Petter Selasky
init_eq_buf(struct mlx5_eq * eq)413dc7e38acSHans Petter Selasky static void init_eq_buf(struct mlx5_eq *eq)
414dc7e38acSHans Petter Selasky {
415dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe;
416dc7e38acSHans Petter Selasky int i;
417dc7e38acSHans Petter Selasky
418dc7e38acSHans Petter Selasky for (i = 0; i < eq->nent; i++) {
419dc7e38acSHans Petter Selasky eqe = get_eqe(eq, i);
420dc7e38acSHans Petter Selasky eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
421dc7e38acSHans Petter Selasky }
422dc7e38acSHans Petter Selasky }
423dc7e38acSHans Petter Selasky
mlx5_create_map_eq(struct mlx5_core_dev * dev,struct mlx5_eq * eq,u8 vecidx,int nent,u64 mask)424dc7e38acSHans Petter Selasky int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
425f8f5b459SHans Petter Selasky int nent, u64 mask)
426dc7e38acSHans Petter Selasky {
427788333d9SHans Petter Selasky u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
428dc7e38acSHans Petter Selasky struct mlx5_priv *priv = &dev->priv;
429788333d9SHans Petter Selasky __be64 *pas;
430788333d9SHans Petter Selasky void *eqc;
431dc7e38acSHans Petter Selasky int inlen;
432788333d9SHans Petter Selasky u32 *in;
433788333d9SHans Petter Selasky int err;
434dc7e38acSHans Petter Selasky
435dc7e38acSHans Petter Selasky eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
436a2485fe5SHans Petter Selasky eq->cons_index = 0;
437dc7e38acSHans Petter Selasky err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE,
438dc7e38acSHans Petter Selasky &eq->buf);
439dc7e38acSHans Petter Selasky if (err)
440dc7e38acSHans Petter Selasky return err;
441dc7e38acSHans Petter Selasky
442dc7e38acSHans Petter Selasky init_eq_buf(eq);
443dc7e38acSHans Petter Selasky
444788333d9SHans Petter Selasky inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
445788333d9SHans Petter Selasky MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
446dc7e38acSHans Petter Selasky in = mlx5_vzalloc(inlen);
447dc7e38acSHans Petter Selasky if (!in) {
448dc7e38acSHans Petter Selasky err = -ENOMEM;
449dc7e38acSHans Petter Selasky goto err_buf;
450dc7e38acSHans Petter Selasky }
451dc7e38acSHans Petter Selasky
452788333d9SHans Petter Selasky pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
453788333d9SHans Petter Selasky mlx5_fill_page_array(&eq->buf, pas);
454dc7e38acSHans Petter Selasky
455788333d9SHans Petter Selasky MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
456788333d9SHans Petter Selasky MLX5_SET64(create_eq_in, in, event_bitmask, mask);
457dc7e38acSHans Petter Selasky
458788333d9SHans Petter Selasky eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
459788333d9SHans Petter Selasky MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
460f8f5b459SHans Petter Selasky MLX5_SET(eqc, eqc, uar_page, priv->uar->index);
461788333d9SHans Petter Selasky MLX5_SET(eqc, eqc, intr, vecidx);
462788333d9SHans Petter Selasky MLX5_SET(eqc, eqc, log_page_size,
463788333d9SHans Petter Selasky eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
464788333d9SHans Petter Selasky
465788333d9SHans Petter Selasky err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
466dc7e38acSHans Petter Selasky if (err)
467dc7e38acSHans Petter Selasky goto err_in;
468dc7e38acSHans Petter Selasky
469788333d9SHans Petter Selasky eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
470dc7e38acSHans Petter Selasky eq->irqn = vecidx;
471dc7e38acSHans Petter Selasky eq->dev = dev;
472f8f5b459SHans Petter Selasky eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
473dc7e38acSHans Petter Selasky err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0,
4746226306bSHans Petter Selasky "mlx5_core", eq);
475dc7e38acSHans Petter Selasky if (err)
476dc7e38acSHans Petter Selasky goto err_eq;
477278ce1c9SHans Petter Selasky #ifdef RSS
478278ce1c9SHans Petter Selasky if (vecidx >= MLX5_EQ_VEC_COMP_BASE) {
479278ce1c9SHans Petter Selasky u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE;
480278ce1c9SHans Petter Selasky err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector,
481278ce1c9SHans Petter Selasky rss_getcpu(bucket % rss_getnumbuckets()));
482278ce1c9SHans Petter Selasky if (err)
483278ce1c9SHans Petter Selasky goto err_irq;
484278ce1c9SHans Petter Selasky }
485278ce1c9SHans Petter Selasky #else
486278ce1c9SHans Petter Selasky if (0)
487278ce1c9SHans Petter Selasky goto err_irq;
488278ce1c9SHans Petter Selasky #endif
489dc7e38acSHans Petter Selasky
490dc7e38acSHans Petter Selasky
491dc7e38acSHans Petter Selasky /* EQs are created in ARMED state
492dc7e38acSHans Petter Selasky */
493dc7e38acSHans Petter Selasky eq_update_ci(eq, 1);
494dc7e38acSHans Petter Selasky
495dc7e38acSHans Petter Selasky kvfree(in);
496dc7e38acSHans Petter Selasky return 0;
497dc7e38acSHans Petter Selasky
498278ce1c9SHans Petter Selasky err_irq:
499278ce1c9SHans Petter Selasky free_irq(priv->msix_arr[vecidx].vector, eq);
500dc7e38acSHans Petter Selasky
501dc7e38acSHans Petter Selasky err_eq:
502dc7e38acSHans Petter Selasky mlx5_cmd_destroy_eq(dev, eq->eqn);
503dc7e38acSHans Petter Selasky
504dc7e38acSHans Petter Selasky err_in:
505dc7e38acSHans Petter Selasky kvfree(in);
506dc7e38acSHans Petter Selasky
507dc7e38acSHans Petter Selasky err_buf:
508dc7e38acSHans Petter Selasky mlx5_buf_free(dev, &eq->buf);
509dc7e38acSHans Petter Selasky return err;
510dc7e38acSHans Petter Selasky }
511dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
512dc7e38acSHans Petter Selasky
mlx5_destroy_unmap_eq(struct mlx5_core_dev * dev,struct mlx5_eq * eq)513dc7e38acSHans Petter Selasky int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
514dc7e38acSHans Petter Selasky {
515dc7e38acSHans Petter Selasky int err;
516dc7e38acSHans Petter Selasky
517dc7e38acSHans Petter Selasky free_irq(dev->priv.msix_arr[eq->irqn].vector, eq);
518dc7e38acSHans Petter Selasky err = mlx5_cmd_destroy_eq(dev, eq->eqn);
519dc7e38acSHans Petter Selasky if (err)
520dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
521dc7e38acSHans Petter Selasky eq->eqn);
522dc7e38acSHans Petter Selasky mlx5_buf_free(dev, &eq->buf);
523dc7e38acSHans Petter Selasky
524dc7e38acSHans Petter Selasky return err;
525dc7e38acSHans Petter Selasky }
526dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
527dc7e38acSHans Petter Selasky
mlx5_eq_init(struct mlx5_core_dev * dev)528dc7e38acSHans Petter Selasky int mlx5_eq_init(struct mlx5_core_dev *dev)
529dc7e38acSHans Petter Selasky {
530dc7e38acSHans Petter Selasky int err;
531dc7e38acSHans Petter Selasky
532dc7e38acSHans Petter Selasky spin_lock_init(&dev->priv.eq_table.lock);
533dc7e38acSHans Petter Selasky
534dc7e38acSHans Petter Selasky err = 0;
535dc7e38acSHans Petter Selasky
536dc7e38acSHans Petter Selasky return err;
537dc7e38acSHans Petter Selasky }
538dc7e38acSHans Petter Selasky
539dc7e38acSHans Petter Selasky
mlx5_eq_cleanup(struct mlx5_core_dev * dev)540dc7e38acSHans Petter Selasky void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
541dc7e38acSHans Petter Selasky {
542dc7e38acSHans Petter Selasky }
543dc7e38acSHans Petter Selasky
mlx5_start_eqs(struct mlx5_core_dev * dev)544dc7e38acSHans Petter Selasky int mlx5_start_eqs(struct mlx5_core_dev *dev)
545dc7e38acSHans Petter Selasky {
546dc7e38acSHans Petter Selasky struct mlx5_eq_table *table = &dev->priv.eq_table;
547a4d6b007SHans Petter Selasky u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
548dc7e38acSHans Petter Selasky int err;
549dc7e38acSHans Petter Selasky
550dc7e38acSHans Petter Selasky if (MLX5_CAP_GEN(dev, port_module_event))
551dc7e38acSHans Petter Selasky async_event_mask |= (1ull <<
552dc7e38acSHans Petter Selasky MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT);
553dc7e38acSHans Petter Selasky
55498a998d5SHans Petter Selasky if (MLX5_CAP_GEN(dev, nic_vport_change_event))
55598a998d5SHans Petter Selasky async_event_mask |= (1ull <<
55698a998d5SHans Petter Selasky MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
55798a998d5SHans Petter Selasky
558cb4e4a6eSHans Petter Selasky if (MLX5_CAP_GEN(dev, dcbx))
559cb4e4a6eSHans Petter Selasky async_event_mask |= (1ull <<
560cb4e4a6eSHans Petter Selasky MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT);
561cb4e4a6eSHans Petter Selasky
562e5eae1dcSHans Petter Selasky if (MLX5_CAP_GEN(dev, fpga))
563e5eae1dcSHans Petter Selasky async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) |
564e5eae1dcSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR);
565e5eae1dcSHans Petter Selasky
566983026eaSHans Petter Selasky if (MLX5_CAP_GEN(dev, temp_warn_event))
567983026eaSHans Petter Selasky async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT);
568983026eaSHans Petter Selasky
569adb6fd50SHans Petter Selasky if (MLX5_CAP_GEN(dev, general_notification_event)) {
570adb6fd50SHans Petter Selasky async_event_mask |= (1ull <<
571adb6fd50SHans Petter Selasky MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT);
572adb6fd50SHans Petter Selasky }
573adb6fd50SHans Petter Selasky
574dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
575f8f5b459SHans Petter Selasky MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD);
576dc7e38acSHans Petter Selasky if (err) {
577dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
578dc7e38acSHans Petter Selasky return err;
579dc7e38acSHans Petter Selasky }
580dc7e38acSHans Petter Selasky
581dc7e38acSHans Petter Selasky mlx5_cmd_use_events(dev);
582dc7e38acSHans Petter Selasky
583dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
584f8f5b459SHans Petter Selasky MLX5_NUM_ASYNC_EQE, async_event_mask);
585dc7e38acSHans Petter Selasky if (err) {
586dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
587dc7e38acSHans Petter Selasky goto err1;
588dc7e38acSHans Petter Selasky }
589dc7e38acSHans Petter Selasky
590dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->pages_eq,
591dc7e38acSHans Petter Selasky MLX5_EQ_VEC_PAGES,
592dc7e38acSHans Petter Selasky /* TODO: sriov max_vf + */ 1,
593f8f5b459SHans Petter Selasky 1 << MLX5_EVENT_TYPE_PAGE_REQUEST);
594dc7e38acSHans Petter Selasky if (err) {
595dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
596dc7e38acSHans Petter Selasky goto err2;
597dc7e38acSHans Petter Selasky }
598dc7e38acSHans Petter Selasky
599dc7e38acSHans Petter Selasky return err;
600dc7e38acSHans Petter Selasky
601dc7e38acSHans Petter Selasky err2:
602dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->async_eq);
603dc7e38acSHans Petter Selasky
604dc7e38acSHans Petter Selasky err1:
605dc7e38acSHans Petter Selasky mlx5_cmd_use_polling(dev);
606dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
607dc7e38acSHans Petter Selasky return err;
608dc7e38acSHans Petter Selasky }
609dc7e38acSHans Petter Selasky
mlx5_stop_eqs(struct mlx5_core_dev * dev)610dc7e38acSHans Petter Selasky int mlx5_stop_eqs(struct mlx5_core_dev *dev)
611dc7e38acSHans Petter Selasky {
612dc7e38acSHans Petter Selasky struct mlx5_eq_table *table = &dev->priv.eq_table;
613dc7e38acSHans Petter Selasky int err;
614dc7e38acSHans Petter Selasky
615dc7e38acSHans Petter Selasky err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
616dc7e38acSHans Petter Selasky if (err)
617dc7e38acSHans Petter Selasky return err;
618dc7e38acSHans Petter Selasky
619dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->async_eq);
620dc7e38acSHans Petter Selasky mlx5_cmd_use_polling(dev);
621dc7e38acSHans Petter Selasky
622dc7e38acSHans Petter Selasky err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
623dc7e38acSHans Petter Selasky if (err)
624dc7e38acSHans Petter Selasky mlx5_cmd_use_events(dev);
625dc7e38acSHans Petter Selasky
626dc7e38acSHans Petter Selasky return err;
627dc7e38acSHans Petter Selasky }
628dc7e38acSHans Petter Selasky
mlx5_core_eq_query(struct mlx5_core_dev * dev,struct mlx5_eq * eq,u32 * out,int outlen)629dc7e38acSHans Petter Selasky int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
630788333d9SHans Petter Selasky u32 *out, int outlen)
631dc7e38acSHans Petter Selasky {
632788333d9SHans Petter Selasky u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
633dc7e38acSHans Petter Selasky
634dc7e38acSHans Petter Selasky memset(out, 0, outlen);
635788333d9SHans Petter Selasky MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ);
636788333d9SHans Petter Selasky MLX5_SET(query_eq_in, in, eq_number, eq->eqn);
637dc7e38acSHans Petter Selasky
638788333d9SHans Petter Selasky return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
639dc7e38acSHans Petter Selasky }
640dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_core_eq_query);
641dc7e38acSHans Petter Selasky
mlx5_port_module_event_error_type_to_string(u8 error_type)642dc7e38acSHans Petter Selasky static const char *mlx5_port_module_event_error_type_to_string(u8 error_type)
643dc7e38acSHans Petter Selasky {
644dc7e38acSHans Petter Selasky switch (error_type) {
645dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED:
646111b57c3SHans Petter Selasky return "Power budget exceeded";
647dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE:
648111b57c3SHans Petter Selasky return "Long Range for non MLNX cable";
649dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_BUS_STUCK:
650dc7e38acSHans Petter Selasky return "Bus stuck(I2C or data shorted)";
651dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT:
652dc7e38acSHans Petter Selasky return "No EEPROM/retry timeout";
653dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST:
654dc7e38acSHans Petter Selasky return "Enforce part number list";
655ecb4fcc4SHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE:
656111b57c3SHans Petter Selasky return "Unknown identifier";
657dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE:
658dc7e38acSHans Petter Selasky return "High Temperature";
659cb4e4a6eSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED:
660111b57c3SHans Petter Selasky return "Bad or shorted cable/module";
6616418350cSKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_PMD_TYPE_NOT_ENABLED:
6626418350cSKonstantin Belousov return "PMD type is not enabled";
663d0a40683SKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_LASTER_TEC_FAILURE:
664d0a40683SKonstantin Belousov return "Laster_TEC_failure";
665d0a40683SKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_HIGH_CURRENT:
666d0a40683SKonstantin Belousov return "High_current";
667d0a40683SKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_HIGH_VOLTAGE:
668d0a40683SKonstantin Belousov return "High_voltage";
669d0a40683SKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_PCIE_SYS_POWER_SLOT_EXCEEDED:
670d0a40683SKonstantin Belousov return "pcie_system_power_slot_Exceeded";
671d0a40683SKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_HIGH_POWER:
672d0a40683SKonstantin Belousov return "High_power";
673d0a40683SKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_MODULE_STATE_MACHINE_FAULT:
674d0a40683SKonstantin Belousov return "Module_state_machine_fault";
675dc7e38acSHans Petter Selasky default:
676dc7e38acSHans Petter Selasky return "Unknown error type";
677dc7e38acSHans Petter Selasky }
678dc7e38acSHans Petter Selasky }
679dc7e38acSHans Petter Selasky
mlx5_query_module_status(struct mlx5_core_dev * dev,int module_num)68021dd6527SHans Petter Selasky unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num)
68121dd6527SHans Petter Selasky {
68221dd6527SHans Petter Selasky if (module_num < 0 || module_num >= MLX5_MAX_PORTS)
68321dd6527SHans Petter Selasky return 0; /* undefined */
68421dd6527SHans Petter Selasky return dev->module_status[module_num];
68521dd6527SHans Petter Selasky }
68621dd6527SHans Petter Selasky
mlx5_port_module_event(struct mlx5_core_dev * dev,struct mlx5_eqe * eqe)687dc7e38acSHans Petter Selasky static void mlx5_port_module_event(struct mlx5_core_dev *dev,
688dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe)
689dc7e38acSHans Petter Selasky {
690dc7e38acSHans Petter Selasky unsigned int module_num;
691dc7e38acSHans Petter Selasky unsigned int module_status;
692dc7e38acSHans Petter Selasky unsigned int error_type;
693dc7e38acSHans Petter Selasky struct mlx5_eqe_port_module_event *module_event_eqe;
694dc7e38acSHans Petter Selasky
695dc7e38acSHans Petter Selasky module_event_eqe = &eqe->data.port_module_event;
696dc7e38acSHans Petter Selasky
697dc7e38acSHans Petter Selasky module_num = (unsigned int)module_event_eqe->module;
698dc7e38acSHans Petter Selasky module_status = (unsigned int)module_event_eqe->module_status &
699dc7e38acSHans Petter Selasky PORT_MODULE_EVENT_MODULE_STATUS_MASK;
700dc7e38acSHans Petter Selasky error_type = (unsigned int)module_event_eqe->error_type &
701dc7e38acSHans Petter Selasky PORT_MODULE_EVENT_ERROR_TYPE_MASK;
702dc7e38acSHans Petter Selasky
703111b57c3SHans Petter Selasky if (module_status < MLX5_MODULE_STATUS_NUM)
704111b57c3SHans Petter Selasky dev->priv.pme_stats.status_counters[module_status]++;
705dc7e38acSHans Petter Selasky switch (module_status) {
706ecb4fcc4SHans Petter Selasky case MLX5_MODULE_STATUS_PLUGGED_ENABLED:
707a2f4f59cSHans Petter Selasky mlx5_core_info(dev,
708a2f4f59cSHans Petter Selasky "Module %u, status: plugged and enabled\n",
709111b57c3SHans Petter Selasky module_num);
710dc7e38acSHans Petter Selasky break;
711dc7e38acSHans Petter Selasky
712dc7e38acSHans Petter Selasky case MLX5_MODULE_STATUS_UNPLUGGED:
713a2f4f59cSHans Petter Selasky mlx5_core_info(dev,
714a2f4f59cSHans Petter Selasky "Module %u, status: unplugged\n", module_num);
715dc7e38acSHans Petter Selasky break;
716dc7e38acSHans Petter Selasky
717dc7e38acSHans Petter Selasky case MLX5_MODULE_STATUS_ERROR:
718a2f4f59cSHans Petter Selasky mlx5_core_err(dev,
719fedc7bd2SHans Petter Selasky "Module %u, status: error, %s (%d)\n",
720111b57c3SHans Petter Selasky module_num,
721fedc7bd2SHans Petter Selasky mlx5_port_module_event_error_type_to_string(error_type),
722fedc7bd2SHans Petter Selasky error_type);
723111b57c3SHans Petter Selasky if (error_type < MLX5_MODULE_EVENT_ERROR_NUM)
724111b57c3SHans Petter Selasky dev->priv.pme_stats.error_counters[error_type]++;
725ecb4fcc4SHans Petter Selasky break;
726ecb4fcc4SHans Petter Selasky
727dc7e38acSHans Petter Selasky default:
728a2f4f59cSHans Petter Selasky mlx5_core_info(dev,
729fedc7bd2SHans Petter Selasky "Module %u, unknown status %d\n", module_num, module_status);
730dc7e38acSHans Petter Selasky }
73121dd6527SHans Petter Selasky /* store module status */
73221dd6527SHans Petter Selasky if (module_num < MLX5_MAX_PORTS)
73321dd6527SHans Petter Selasky dev->module_status[module_num] = module_status;
734dc7e38acSHans Petter Selasky }
735dc7e38acSHans Petter Selasky
mlx5_port_general_notification_event(struct mlx5_core_dev * dev,struct mlx5_eqe * eqe)7366c7057f7SHans Petter Selasky static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev,
7376c7057f7SHans Petter Selasky struct mlx5_eqe *eqe)
7386c7057f7SHans Petter Selasky {
7396c7057f7SHans Petter Selasky u8 port = (eqe->data.port.port >> 4) & 0xf;
7406c7057f7SHans Petter Selasky
7416c7057f7SHans Petter Selasky switch (eqe->sub_type) {
7426c7057f7SHans Petter Selasky case MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT:
7436c7057f7SHans Petter Selasky break;
744adb6fd50SHans Petter Selasky case MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT:
745adb6fd50SHans Petter Selasky mlx5_trigger_health_watchdog(dev);
746adb6fd50SHans Petter Selasky break;
7476c7057f7SHans Petter Selasky default:
7486c7057f7SHans Petter Selasky mlx5_core_warn(dev,
7496c7057f7SHans Petter Selasky "general event with unrecognized subtype: port %d, sub_type %d\n",
7506c7057f7SHans Petter Selasky port, eqe->sub_type);
7516c7057f7SHans Petter Selasky break;
7526c7057f7SHans Petter Selasky }
7536c7057f7SHans Petter Selasky }
7546c7057f7SHans Petter Selasky
755f14d8498SHans Petter Selasky void
mlx5_disable_interrupts(struct mlx5_core_dev * dev)756f14d8498SHans Petter Selasky mlx5_disable_interrupts(struct mlx5_core_dev *dev)
757f14d8498SHans Petter Selasky {
758f14d8498SHans Petter Selasky int nvec = dev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE;
759f14d8498SHans Petter Selasky int x;
760f14d8498SHans Petter Selasky
761f14d8498SHans Petter Selasky for (x = 0; x != nvec; x++)
762f14d8498SHans Petter Selasky disable_irq(dev->priv.msix_arr[x].vector);
763f14d8498SHans Petter Selasky }
764f14d8498SHans Petter Selasky
765f14d8498SHans Petter Selasky void
mlx5_poll_interrupts(struct mlx5_core_dev * dev)766f14d8498SHans Petter Selasky mlx5_poll_interrupts(struct mlx5_core_dev *dev)
767f14d8498SHans Petter Selasky {
768f14d8498SHans Petter Selasky struct mlx5_eq *eq;
769f14d8498SHans Petter Selasky
770f14d8498SHans Petter Selasky if (unlikely(dev->priv.disable_irqs != 0))
771f14d8498SHans Petter Selasky return;
772f14d8498SHans Petter Selasky
773f14d8498SHans Petter Selasky mlx5_eq_int(dev, &dev->priv.eq_table.cmd_eq);
774f14d8498SHans Petter Selasky mlx5_eq_int(dev, &dev->priv.eq_table.async_eq);
775f14d8498SHans Petter Selasky mlx5_eq_int(dev, &dev->priv.eq_table.pages_eq);
776f14d8498SHans Petter Selasky
777f14d8498SHans Petter Selasky list_for_each_entry(eq, &dev->priv.eq_table.comp_eqs_list, list)
778f14d8498SHans Petter Selasky mlx5_eq_int(dev, eq);
779f14d8498SHans Petter Selasky }
780