1dc7e38acSHans Petter Selasky /*- 2dc7e38acSHans Petter Selasky * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3dc7e38acSHans Petter Selasky * 4dc7e38acSHans Petter Selasky * Redistribution and use in source and binary forms, with or without 5dc7e38acSHans Petter Selasky * modification, are permitted provided that the following conditions 6dc7e38acSHans Petter Selasky * are met: 7dc7e38acSHans Petter Selasky * 1. Redistributions of source code must retain the above copyright 8dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer. 9dc7e38acSHans Petter Selasky * 2. Redistributions in binary form must reproduce the above copyright 10dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer in the 11dc7e38acSHans Petter Selasky * documentation and/or other materials provided with the distribution. 12dc7e38acSHans Petter Selasky * 13dc7e38acSHans Petter Selasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14dc7e38acSHans Petter Selasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15dc7e38acSHans Petter Selasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16dc7e38acSHans Petter Selasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17dc7e38acSHans Petter Selasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18dc7e38acSHans Petter Selasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19dc7e38acSHans Petter Selasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20dc7e38acSHans Petter Selasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21dc7e38acSHans Petter Selasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22dc7e38acSHans Petter Selasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23dc7e38acSHans Petter Selasky * SUCH DAMAGE. 24dc7e38acSHans Petter Selasky * 25dc7e38acSHans Petter Selasky * $FreeBSD$ 26dc7e38acSHans Petter Selasky */ 27dc7e38acSHans Petter Selasky 28dc7e38acSHans Petter Selasky #include <linux/interrupt.h> 29dc7e38acSHans Petter Selasky #include <linux/module.h> 30dc7e38acSHans Petter Selasky #include <dev/mlx5/driver.h> 31dc7e38acSHans Petter Selasky #include <dev/mlx5/mlx5_ifc.h> 32dc7e38acSHans Petter Selasky #include "mlx5_core.h" 33dc7e38acSHans Petter Selasky 34278ce1c9SHans Petter Selasky #include "opt_rss.h" 35278ce1c9SHans Petter Selasky 36278ce1c9SHans Petter Selasky #ifdef RSS 37278ce1c9SHans Petter Selasky #include <net/rss_config.h> 38278ce1c9SHans Petter Selasky #include <netinet/in_rss.h> 39278ce1c9SHans Petter Selasky #endif 40278ce1c9SHans Petter Selasky 41dc7e38acSHans Petter Selasky enum { 42dc7e38acSHans Petter Selasky MLX5_EQE_SIZE = sizeof(struct mlx5_eqe), 43dc7e38acSHans Petter Selasky MLX5_EQE_OWNER_INIT_VAL = 0x1, 44dc7e38acSHans Petter Selasky }; 45dc7e38acSHans Petter Selasky 46dc7e38acSHans Petter Selasky enum { 47dc7e38acSHans Petter Selasky MLX5_NUM_SPARE_EQE = 0x80, 48dc7e38acSHans Petter Selasky MLX5_NUM_ASYNC_EQE = 0x100, 49dc7e38acSHans Petter Selasky MLX5_NUM_CMD_EQE = 32, 50dc7e38acSHans Petter Selasky }; 51dc7e38acSHans Petter Selasky 52dc7e38acSHans Petter Selasky enum { 53dc7e38acSHans Petter Selasky MLX5_EQ_DOORBEL_OFFSET = 0x40, 54dc7e38acSHans Petter Selasky }; 55dc7e38acSHans Petter Selasky 56dc7e38acSHans Petter Selasky #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \ 57dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_COMM_EST) | \ 58dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \ 59dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \ 60dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \ 61dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \ 62dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 63dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 64dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \ 65dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE) | \ 66dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 67dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \ 68dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT)) 69dc7e38acSHans Petter Selasky 70dc7e38acSHans Petter Selasky struct map_eq_in { 71dc7e38acSHans Petter Selasky u64 mask; 72dc7e38acSHans Petter Selasky u32 reserved; 73dc7e38acSHans Petter Selasky u32 unmap_eqn; 74dc7e38acSHans Petter Selasky }; 75dc7e38acSHans Petter Selasky 76dc7e38acSHans Petter Selasky struct cre_des_eq { 77dc7e38acSHans Petter Selasky u8 reserved[15]; 78dc7e38acSHans Petter Selasky u8 eqn; 79dc7e38acSHans Petter Selasky }; 80dc7e38acSHans Petter Selasky 81dc7e38acSHans Petter Selasky /*Function prototype*/ 82dc7e38acSHans Petter Selasky static void mlx5_port_module_event(struct mlx5_core_dev *dev, 83dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe); 84dc7e38acSHans Petter Selasky 85dc7e38acSHans Petter Selasky static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn) 86dc7e38acSHans Petter Selasky { 87dc7e38acSHans Petter Selasky u32 in[MLX5_ST_SZ_DW(destroy_eq_in)]; 88dc7e38acSHans Petter Selasky u32 out[MLX5_ST_SZ_DW(destroy_eq_out)]; 89dc7e38acSHans Petter Selasky 90dc7e38acSHans Petter Selasky memset(in, 0, sizeof(in)); 91dc7e38acSHans Petter Selasky 92dc7e38acSHans Petter Selasky MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ); 93dc7e38acSHans Petter Selasky MLX5_SET(destroy_eq_in, in, eq_number, eqn); 94dc7e38acSHans Petter Selasky 95dc7e38acSHans Petter Selasky memset(out, 0, sizeof(out)); 96dc7e38acSHans Petter Selasky return mlx5_cmd_exec_check_status(dev, in, sizeof(in), 97dc7e38acSHans Petter Selasky out, sizeof(out)); 98dc7e38acSHans Petter Selasky } 99dc7e38acSHans Petter Selasky 100dc7e38acSHans Petter Selasky static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) 101dc7e38acSHans Petter Selasky { 102dc7e38acSHans Petter Selasky return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE); 103dc7e38acSHans Petter Selasky } 104dc7e38acSHans Petter Selasky 105dc7e38acSHans Petter Selasky static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) 106dc7e38acSHans Petter Selasky { 107dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1)); 108dc7e38acSHans Petter Selasky 109dc7e38acSHans Petter Selasky return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe; 110dc7e38acSHans Petter Selasky } 111dc7e38acSHans Petter Selasky 112dc7e38acSHans Petter Selasky static const char *eqe_type_str(u8 type) 113dc7e38acSHans Petter Selasky { 114dc7e38acSHans Petter Selasky switch (type) { 115dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMP: 116dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_COMP"; 117dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG: 118dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PATH_MIG"; 119dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMM_EST: 120dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_COMM_EST"; 121dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SQ_DRAINED: 122dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SQ_DRAINED"; 123dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 124dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_LAST_WQE"; 125dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 126dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT"; 127dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CQ_ERROR: 128dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_CQ_ERROR"; 129dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 130dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR"; 131dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 132dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PATH_MIG_FAILED"; 133dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 134dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR"; 135dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 136dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR"; 137dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 138dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR"; 139dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_INTERNAL_ERROR: 140dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_INTERNAL_ERROR"; 141dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PORT_CHANGE: 142dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PORT_CHANGE"; 143dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_GPIO_EVENT: 144dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_GPIO_EVENT"; 145dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 146dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT"; 147dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_REMOTE_CONFIG: 148dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_REMOTE_CONFIG"; 149dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_DB_BF_CONGESTION: 150dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_DB_BF_CONGESTION"; 151dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_STALL_EVENT: 152dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_STALL_EVENT"; 153dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CMD: 154dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_CMD"; 155dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PAGE_REQUEST: 156dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PAGE_REQUEST"; 157dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 158dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE"; 159dc7e38acSHans Petter Selasky default: 160dc7e38acSHans Petter Selasky return "Unrecognized event"; 161dc7e38acSHans Petter Selasky } 162dc7e38acSHans Petter Selasky } 163dc7e38acSHans Petter Selasky 164dc7e38acSHans Petter Selasky static enum mlx5_dev_event port_subtype_event(u8 subtype) 165dc7e38acSHans Petter Selasky { 166dc7e38acSHans Petter Selasky switch (subtype) { 167dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 168dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_DOWN; 169dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 170dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_UP; 171dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 172dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_INITIALIZED; 173dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_LID: 174dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_LID_CHANGE; 175dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 176dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PKEY_CHANGE; 177dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_GUID: 178dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_GUID_CHANGE; 179dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 180dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_CLIENT_REREG; 181dc7e38acSHans Petter Selasky } 182dc7e38acSHans Petter Selasky return -1; 183dc7e38acSHans Petter Selasky } 184dc7e38acSHans Petter Selasky 185dc7e38acSHans Petter Selasky static void eq_update_ci(struct mlx5_eq *eq, int arm) 186dc7e38acSHans Petter Selasky { 187dc7e38acSHans Petter Selasky __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); 188dc7e38acSHans Petter Selasky u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); 189dc7e38acSHans Petter Selasky __raw_writel((__force u32) cpu_to_be32(val), addr); 190dc7e38acSHans Petter Selasky /* We still want ordering, just not swabbing, so add a barrier */ 191dc7e38acSHans Petter Selasky mb(); 192dc7e38acSHans Petter Selasky } 193dc7e38acSHans Petter Selasky 194dc7e38acSHans Petter Selasky static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 195dc7e38acSHans Petter Selasky { 196dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe; 197dc7e38acSHans Petter Selasky int eqes_found = 0; 198dc7e38acSHans Petter Selasky int set_ci = 0; 199dc7e38acSHans Petter Selasky u32 cqn; 200dc7e38acSHans Petter Selasky u32 rsn; 201dc7e38acSHans Petter Selasky u8 port; 202dc7e38acSHans Petter Selasky 203dc7e38acSHans Petter Selasky while ((eqe = next_eqe_sw(eq))) { 204dc7e38acSHans Petter Selasky /* 205dc7e38acSHans Petter Selasky * Make sure we read EQ entry contents after we've 206dc7e38acSHans Petter Selasky * checked the ownership bit. 207dc7e38acSHans Petter Selasky */ 208dc7e38acSHans Petter Selasky rmb(); 209dc7e38acSHans Petter Selasky 210dc7e38acSHans Petter Selasky mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", 211dc7e38acSHans Petter Selasky eq->eqn, eqe_type_str(eqe->type)); 212dc7e38acSHans Petter Selasky switch (eqe->type) { 213dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMP: 214dc7e38acSHans Petter Selasky cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; 215dc7e38acSHans Petter Selasky mlx5_cq_completion(dev, cqn); 216dc7e38acSHans Petter Selasky break; 217dc7e38acSHans Petter Selasky 218dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG: 219dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMM_EST: 220dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SQ_DRAINED: 221dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 222dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 223dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 224dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 225dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 226dc7e38acSHans Petter Selasky rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 227dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n", 228dc7e38acSHans Petter Selasky eqe_type_str(eqe->type), eqe->type, rsn); 229dc7e38acSHans Petter Selasky mlx5_rsc_event(dev, rsn, eqe->type); 230dc7e38acSHans Petter Selasky break; 231dc7e38acSHans Petter Selasky 232dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 233dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 234dc7e38acSHans Petter Selasky rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 235dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n", 236dc7e38acSHans Petter Selasky eqe_type_str(eqe->type), eqe->type, rsn); 237dc7e38acSHans Petter Selasky mlx5_srq_event(dev, rsn, eqe->type); 238dc7e38acSHans Petter Selasky break; 239dc7e38acSHans Petter Selasky 240dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CMD: 241dc7e38acSHans Petter Selasky mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector)); 242dc7e38acSHans Petter Selasky break; 243dc7e38acSHans Petter Selasky 244dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PORT_CHANGE: 245dc7e38acSHans Petter Selasky port = (eqe->data.port.port >> 4) & 0xf; 246dc7e38acSHans Petter Selasky switch (eqe->sub_type) { 247dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 248dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 249dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_LID: 250dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 251dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_GUID: 252dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 253dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 254dc7e38acSHans Petter Selasky if (dev->event) 255dc7e38acSHans Petter Selasky dev->event(dev, port_subtype_event(eqe->sub_type), 256dc7e38acSHans Petter Selasky (unsigned long)port); 257dc7e38acSHans Petter Selasky break; 258dc7e38acSHans Petter Selasky default: 259dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n", 260dc7e38acSHans Petter Selasky port, eqe->sub_type); 261dc7e38acSHans Petter Selasky } 262dc7e38acSHans Petter Selasky break; 263dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CQ_ERROR: 264dc7e38acSHans Petter Selasky cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 265dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n", 266dc7e38acSHans Petter Selasky cqn, eqe->data.cq_err.syndrome); 267dc7e38acSHans Petter Selasky mlx5_cq_event(dev, cqn, eqe->type); 268dc7e38acSHans Petter Selasky break; 269dc7e38acSHans Petter Selasky 270dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PAGE_REQUEST: 271dc7e38acSHans Petter Selasky { 272dc7e38acSHans Petter Selasky u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id); 273dc7e38acSHans Petter Selasky s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages); 274dc7e38acSHans Petter Selasky 275dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n", 276dc7e38acSHans Petter Selasky func_id, npages); 277dc7e38acSHans Petter Selasky mlx5_core_req_pages_handler(dev, func_id, npages); 278dc7e38acSHans Petter Selasky } 279dc7e38acSHans Petter Selasky break; 280dc7e38acSHans Petter Selasky 281dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 282dc7e38acSHans Petter Selasky mlx5_port_module_event(dev, eqe); 283dc7e38acSHans Petter Selasky break; 284dc7e38acSHans Petter Selasky 285dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 286dc7e38acSHans Petter Selasky { 287dc7e38acSHans Petter Selasky struct mlx5_eqe_vport_change *vc_eqe = 288dc7e38acSHans Petter Selasky &eqe->data.vport_change; 289dc7e38acSHans Petter Selasky u16 vport_num = be16_to_cpu(vc_eqe->vport_num); 290dc7e38acSHans Petter Selasky 291dc7e38acSHans Petter Selasky if (dev->event) 292dc7e38acSHans Petter Selasky dev->event(dev, 293dc7e38acSHans Petter Selasky MLX5_DEV_EVENT_VPORT_CHANGE, 294dc7e38acSHans Petter Selasky (unsigned long)vport_num); 295dc7e38acSHans Petter Selasky } 296dc7e38acSHans Petter Selasky break; 297dc7e38acSHans Petter Selasky 298dc7e38acSHans Petter Selasky default: 299dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n", 300dc7e38acSHans Petter Selasky eqe->type, eq->eqn); 301dc7e38acSHans Petter Selasky break; 302dc7e38acSHans Petter Selasky } 303dc7e38acSHans Petter Selasky 304dc7e38acSHans Petter Selasky ++eq->cons_index; 305dc7e38acSHans Petter Selasky eqes_found = 1; 306dc7e38acSHans Petter Selasky ++set_ci; 307dc7e38acSHans Petter Selasky 308dc7e38acSHans Petter Selasky /* The HCA will think the queue has overflowed if we 309dc7e38acSHans Petter Selasky * don't tell it we've been processing events. We 310dc7e38acSHans Petter Selasky * create our EQs with MLX5_NUM_SPARE_EQE extra 311dc7e38acSHans Petter Selasky * entries, so we must update our consumer index at 312dc7e38acSHans Petter Selasky * least that often. 313dc7e38acSHans Petter Selasky */ 314dc7e38acSHans Petter Selasky if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) { 315dc7e38acSHans Petter Selasky eq_update_ci(eq, 0); 316dc7e38acSHans Petter Selasky set_ci = 0; 317dc7e38acSHans Petter Selasky } 318dc7e38acSHans Petter Selasky } 319dc7e38acSHans Petter Selasky 320dc7e38acSHans Petter Selasky eq_update_ci(eq, 1); 321dc7e38acSHans Petter Selasky 322dc7e38acSHans Petter Selasky return eqes_found; 323dc7e38acSHans Petter Selasky } 324dc7e38acSHans Petter Selasky 325dc7e38acSHans Petter Selasky static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr) 326dc7e38acSHans Petter Selasky { 327dc7e38acSHans Petter Selasky struct mlx5_eq *eq = eq_ptr; 328dc7e38acSHans Petter Selasky struct mlx5_core_dev *dev = eq->dev; 329dc7e38acSHans Petter Selasky 330dc7e38acSHans Petter Selasky mlx5_eq_int(dev, eq); 331dc7e38acSHans Petter Selasky 332dc7e38acSHans Petter Selasky /* MSI-X vectors always belong to us */ 333dc7e38acSHans Petter Selasky return IRQ_HANDLED; 334dc7e38acSHans Petter Selasky } 335dc7e38acSHans Petter Selasky 336dc7e38acSHans Petter Selasky static void init_eq_buf(struct mlx5_eq *eq) 337dc7e38acSHans Petter Selasky { 338dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe; 339dc7e38acSHans Petter Selasky int i; 340dc7e38acSHans Petter Selasky 341dc7e38acSHans Petter Selasky for (i = 0; i < eq->nent; i++) { 342dc7e38acSHans Petter Selasky eqe = get_eqe(eq, i); 343dc7e38acSHans Petter Selasky eqe->owner = MLX5_EQE_OWNER_INIT_VAL; 344dc7e38acSHans Petter Selasky } 345dc7e38acSHans Petter Selasky } 346dc7e38acSHans Petter Selasky 347dc7e38acSHans Petter Selasky int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 348dc7e38acSHans Petter Selasky int nent, u64 mask, const char *name, struct mlx5_uar *uar) 349dc7e38acSHans Petter Selasky { 350dc7e38acSHans Petter Selasky struct mlx5_priv *priv = &dev->priv; 351dc7e38acSHans Petter Selasky struct mlx5_create_eq_mbox_in *in; 352dc7e38acSHans Petter Selasky struct mlx5_create_eq_mbox_out out; 353dc7e38acSHans Petter Selasky int err; 354dc7e38acSHans Petter Selasky int inlen; 355dc7e38acSHans Petter Selasky 356dc7e38acSHans Petter Selasky eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE); 357dc7e38acSHans Petter Selasky err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE, 358dc7e38acSHans Petter Selasky &eq->buf); 359dc7e38acSHans Petter Selasky if (err) 360dc7e38acSHans Petter Selasky return err; 361dc7e38acSHans Petter Selasky 362dc7e38acSHans Petter Selasky init_eq_buf(eq); 363dc7e38acSHans Petter Selasky 364dc7e38acSHans Petter Selasky inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages; 365dc7e38acSHans Petter Selasky in = mlx5_vzalloc(inlen); 366dc7e38acSHans Petter Selasky if (!in) { 367dc7e38acSHans Petter Selasky err = -ENOMEM; 368dc7e38acSHans Petter Selasky goto err_buf; 369dc7e38acSHans Petter Selasky } 370dc7e38acSHans Petter Selasky memset(&out, 0, sizeof(out)); 371dc7e38acSHans Petter Selasky 372dc7e38acSHans Petter Selasky mlx5_fill_page_array(&eq->buf, in->pas); 373dc7e38acSHans Petter Selasky 374dc7e38acSHans Petter Selasky in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ); 375dc7e38acSHans Petter Selasky in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index); 376dc7e38acSHans Petter Selasky in->ctx.intr = vecidx; 377dc7e38acSHans Petter Selasky in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT; 378dc7e38acSHans Petter Selasky in->events_mask = cpu_to_be64(mask); 379dc7e38acSHans Petter Selasky 380dc7e38acSHans Petter Selasky err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out)); 381dc7e38acSHans Petter Selasky if (err) 382dc7e38acSHans Petter Selasky goto err_in; 383dc7e38acSHans Petter Selasky 384dc7e38acSHans Petter Selasky if (out.hdr.status) { 385dc7e38acSHans Petter Selasky err = mlx5_cmd_status_to_err(&out.hdr); 386dc7e38acSHans Petter Selasky goto err_in; 387dc7e38acSHans Petter Selasky } 388dc7e38acSHans Petter Selasky 389dc7e38acSHans Petter Selasky eq->eqn = out.eq_number; 390dc7e38acSHans Petter Selasky eq->irqn = vecidx; 391dc7e38acSHans Petter Selasky eq->dev = dev; 392dc7e38acSHans Petter Selasky eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET; 393dc7e38acSHans Petter Selasky snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s", 394dc7e38acSHans Petter Selasky name, pci_name(dev->pdev)); 395dc7e38acSHans Petter Selasky err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0, 396dc7e38acSHans Petter Selasky priv->irq_info[vecidx].name, eq); 397dc7e38acSHans Petter Selasky if (err) 398dc7e38acSHans Petter Selasky goto err_eq; 399278ce1c9SHans Petter Selasky #ifdef RSS 400278ce1c9SHans Petter Selasky if (vecidx >= MLX5_EQ_VEC_COMP_BASE) { 401278ce1c9SHans Petter Selasky u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE; 402278ce1c9SHans Petter Selasky err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector, 403278ce1c9SHans Petter Selasky rss_getcpu(bucket % rss_getnumbuckets())); 404278ce1c9SHans Petter Selasky if (err) 405278ce1c9SHans Petter Selasky goto err_irq; 406278ce1c9SHans Petter Selasky } 407278ce1c9SHans Petter Selasky #else 408278ce1c9SHans Petter Selasky if (0) 409278ce1c9SHans Petter Selasky goto err_irq; 410278ce1c9SHans Petter Selasky #endif 411dc7e38acSHans Petter Selasky 412dc7e38acSHans Petter Selasky 413dc7e38acSHans Petter Selasky /* EQs are created in ARMED state 414dc7e38acSHans Petter Selasky */ 415dc7e38acSHans Petter Selasky eq_update_ci(eq, 1); 416dc7e38acSHans Petter Selasky 417dc7e38acSHans Petter Selasky kvfree(in); 418dc7e38acSHans Petter Selasky return 0; 419dc7e38acSHans Petter Selasky 420278ce1c9SHans Petter Selasky err_irq: 421278ce1c9SHans Petter Selasky free_irq(priv->msix_arr[vecidx].vector, eq); 422dc7e38acSHans Petter Selasky 423dc7e38acSHans Petter Selasky err_eq: 424dc7e38acSHans Petter Selasky mlx5_cmd_destroy_eq(dev, eq->eqn); 425dc7e38acSHans Petter Selasky 426dc7e38acSHans Petter Selasky err_in: 427dc7e38acSHans Petter Selasky kvfree(in); 428dc7e38acSHans Petter Selasky 429dc7e38acSHans Petter Selasky err_buf: 430dc7e38acSHans Petter Selasky mlx5_buf_free(dev, &eq->buf); 431dc7e38acSHans Petter Selasky return err; 432dc7e38acSHans Petter Selasky } 433dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_create_map_eq); 434dc7e38acSHans Petter Selasky 435dc7e38acSHans Petter Selasky int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 436dc7e38acSHans Petter Selasky { 437dc7e38acSHans Petter Selasky int err; 438dc7e38acSHans Petter Selasky 439dc7e38acSHans Petter Selasky free_irq(dev->priv.msix_arr[eq->irqn].vector, eq); 440dc7e38acSHans Petter Selasky err = mlx5_cmd_destroy_eq(dev, eq->eqn); 441dc7e38acSHans Petter Selasky if (err) 442dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n", 443dc7e38acSHans Petter Selasky eq->eqn); 444dc7e38acSHans Petter Selasky mlx5_buf_free(dev, &eq->buf); 445dc7e38acSHans Petter Selasky 446dc7e38acSHans Petter Selasky return err; 447dc7e38acSHans Petter Selasky } 448dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq); 449dc7e38acSHans Petter Selasky 450dc7e38acSHans Petter Selasky int mlx5_eq_init(struct mlx5_core_dev *dev) 451dc7e38acSHans Petter Selasky { 452dc7e38acSHans Petter Selasky int err; 453dc7e38acSHans Petter Selasky 454dc7e38acSHans Petter Selasky spin_lock_init(&dev->priv.eq_table.lock); 455dc7e38acSHans Petter Selasky 456dc7e38acSHans Petter Selasky err = 0; 457dc7e38acSHans Petter Selasky 458dc7e38acSHans Petter Selasky return err; 459dc7e38acSHans Petter Selasky } 460dc7e38acSHans Petter Selasky 461dc7e38acSHans Petter Selasky 462dc7e38acSHans Petter Selasky void mlx5_eq_cleanup(struct mlx5_core_dev *dev) 463dc7e38acSHans Petter Selasky { 464dc7e38acSHans Petter Selasky } 465dc7e38acSHans Petter Selasky 466dc7e38acSHans Petter Selasky int mlx5_start_eqs(struct mlx5_core_dev *dev) 467dc7e38acSHans Petter Selasky { 468dc7e38acSHans Petter Selasky struct mlx5_eq_table *table = &dev->priv.eq_table; 469dc7e38acSHans Petter Selasky u32 async_event_mask = MLX5_ASYNC_EVENT_MASK; 470dc7e38acSHans Petter Selasky int err; 471dc7e38acSHans Petter Selasky 472dc7e38acSHans Petter Selasky if (MLX5_CAP_GEN(dev, port_module_event)) 473dc7e38acSHans Petter Selasky async_event_mask |= (1ull << 474dc7e38acSHans Petter Selasky MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT); 475dc7e38acSHans Petter Selasky 476dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, 477dc7e38acSHans Petter Selasky MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, 478dc7e38acSHans Petter Selasky "mlx5_cmd_eq", &dev->priv.uuari.uars[0]); 479dc7e38acSHans Petter Selasky if (err) { 480dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err); 481dc7e38acSHans Petter Selasky return err; 482dc7e38acSHans Petter Selasky } 483dc7e38acSHans Petter Selasky 484dc7e38acSHans Petter Selasky mlx5_cmd_use_events(dev); 485dc7e38acSHans Petter Selasky 486dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC, 487dc7e38acSHans Petter Selasky MLX5_NUM_ASYNC_EQE, async_event_mask, 488dc7e38acSHans Petter Selasky "mlx5_async_eq", &dev->priv.uuari.uars[0]); 489dc7e38acSHans Petter Selasky if (err) { 490dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create async EQ %d\n", err); 491dc7e38acSHans Petter Selasky goto err1; 492dc7e38acSHans Petter Selasky } 493dc7e38acSHans Petter Selasky 494dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->pages_eq, 495dc7e38acSHans Petter Selasky MLX5_EQ_VEC_PAGES, 496dc7e38acSHans Petter Selasky /* TODO: sriov max_vf + */ 1, 497dc7e38acSHans Petter Selasky 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq", 498dc7e38acSHans Petter Selasky &dev->priv.uuari.uars[0]); 499dc7e38acSHans Petter Selasky if (err) { 500dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create pages EQ %d\n", err); 501dc7e38acSHans Petter Selasky goto err2; 502dc7e38acSHans Petter Selasky } 503dc7e38acSHans Petter Selasky 504dc7e38acSHans Petter Selasky return err; 505dc7e38acSHans Petter Selasky 506dc7e38acSHans Petter Selasky err2: 507dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->async_eq); 508dc7e38acSHans Petter Selasky 509dc7e38acSHans Petter Selasky err1: 510dc7e38acSHans Petter Selasky mlx5_cmd_use_polling(dev); 511dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 512dc7e38acSHans Petter Selasky return err; 513dc7e38acSHans Petter Selasky } 514dc7e38acSHans Petter Selasky 515dc7e38acSHans Petter Selasky int mlx5_stop_eqs(struct mlx5_core_dev *dev) 516dc7e38acSHans Petter Selasky { 517dc7e38acSHans Petter Selasky struct mlx5_eq_table *table = &dev->priv.eq_table; 518dc7e38acSHans Petter Selasky int err; 519dc7e38acSHans Petter Selasky 520dc7e38acSHans Petter Selasky err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); 521dc7e38acSHans Petter Selasky if (err) 522dc7e38acSHans Petter Selasky return err; 523dc7e38acSHans Petter Selasky 524dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->async_eq); 525dc7e38acSHans Petter Selasky mlx5_cmd_use_polling(dev); 526dc7e38acSHans Petter Selasky 527dc7e38acSHans Petter Selasky err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 528dc7e38acSHans Petter Selasky if (err) 529dc7e38acSHans Petter Selasky mlx5_cmd_use_events(dev); 530dc7e38acSHans Petter Selasky 531dc7e38acSHans Petter Selasky return err; 532dc7e38acSHans Petter Selasky } 533dc7e38acSHans Petter Selasky 534dc7e38acSHans Petter Selasky int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 535dc7e38acSHans Petter Selasky struct mlx5_query_eq_mbox_out *out, int outlen) 536dc7e38acSHans Petter Selasky { 537dc7e38acSHans Petter Selasky struct mlx5_query_eq_mbox_in in; 538dc7e38acSHans Petter Selasky int err; 539dc7e38acSHans Petter Selasky 540dc7e38acSHans Petter Selasky memset(&in, 0, sizeof(in)); 541dc7e38acSHans Petter Selasky memset(out, 0, outlen); 542dc7e38acSHans Petter Selasky in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ); 543dc7e38acSHans Petter Selasky in.eqn = eq->eqn; 544dc7e38acSHans Petter Selasky err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen); 545dc7e38acSHans Petter Selasky if (err) 546dc7e38acSHans Petter Selasky return err; 547dc7e38acSHans Petter Selasky 548dc7e38acSHans Petter Selasky if (out->hdr.status) 549dc7e38acSHans Petter Selasky err = mlx5_cmd_status_to_err(&out->hdr); 550dc7e38acSHans Petter Selasky 551dc7e38acSHans Petter Selasky return err; 552dc7e38acSHans Petter Selasky } 553dc7e38acSHans Petter Selasky 554dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_core_eq_query); 555dc7e38acSHans Petter Selasky 556dc7e38acSHans Petter Selasky static const char *mlx5_port_module_event_error_type_to_string(u8 error_type) 557dc7e38acSHans Petter Selasky { 558dc7e38acSHans Petter Selasky switch (error_type) { 559dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED: 560dc7e38acSHans Petter Selasky return "Power Budget Exceeded"; 561dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE: 562dc7e38acSHans Petter Selasky return "Long Range for non MLNX cable/module"; 563dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_BUS_STUCK: 564dc7e38acSHans Petter Selasky return "Bus stuck(I2C or data shorted)"; 565dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT: 566dc7e38acSHans Petter Selasky return "No EEPROM/retry timeout"; 567dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST: 568dc7e38acSHans Petter Selasky return "Enforce part number list"; 569dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER: 570dc7e38acSHans Petter Selasky return "Unknown identifier"; 571dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE: 572dc7e38acSHans Petter Selasky return "High Temperature"; 573dc7e38acSHans Petter Selasky 574dc7e38acSHans Petter Selasky default: 575dc7e38acSHans Petter Selasky return "Unknown error type"; 576dc7e38acSHans Petter Selasky } 577dc7e38acSHans Petter Selasky } 578dc7e38acSHans Petter Selasky 579dc7e38acSHans Petter Selasky static void mlx5_port_module_event(struct mlx5_core_dev *dev, 580dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe) 581dc7e38acSHans Petter Selasky { 582dc7e38acSHans Petter Selasky unsigned int module_num; 583dc7e38acSHans Petter Selasky unsigned int module_status; 584dc7e38acSHans Petter Selasky unsigned int error_type; 585dc7e38acSHans Petter Selasky struct mlx5_eqe_port_module_event *module_event_eqe; 586dc7e38acSHans Petter Selasky struct pci_dev *pdev = dev->pdev; 587dc7e38acSHans Petter Selasky 588dc7e38acSHans Petter Selasky module_event_eqe = &eqe->data.port_module_event; 589dc7e38acSHans Petter Selasky 590dc7e38acSHans Petter Selasky module_num = (unsigned int)module_event_eqe->module; 591dc7e38acSHans Petter Selasky module_status = (unsigned int)module_event_eqe->module_status & 592dc7e38acSHans Petter Selasky PORT_MODULE_EVENT_MODULE_STATUS_MASK; 593dc7e38acSHans Petter Selasky error_type = (unsigned int)module_event_eqe->error_type & 594dc7e38acSHans Petter Selasky PORT_MODULE_EVENT_ERROR_TYPE_MASK; 595dc7e38acSHans Petter Selasky 596dc7e38acSHans Petter Selasky switch (module_status) { 597dc7e38acSHans Petter Selasky case MLX5_MODULE_STATUS_PLUGGED: 598dc7e38acSHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged", module_num); 599dc7e38acSHans Petter Selasky break; 600dc7e38acSHans Petter Selasky 601dc7e38acSHans Petter Selasky case MLX5_MODULE_STATUS_UNPLUGGED: 602dc7e38acSHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged", module_num); 603dc7e38acSHans Petter Selasky break; 604dc7e38acSHans Petter Selasky 605dc7e38acSHans Petter Selasky case MLX5_MODULE_STATUS_ERROR: 606dc7e38acSHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s", module_num, mlx5_port_module_event_error_type_to_string(error_type)); 607dc7e38acSHans Petter Selasky break; 608dc7e38acSHans Petter Selasky 609dc7e38acSHans Petter Selasky default: 610dc7e38acSHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status", module_num); 611dc7e38acSHans Petter Selasky } 612dc7e38acSHans Petter Selasky } 613dc7e38acSHans Petter Selasky 614