1dc7e38acSHans Petter Selasky /*- 26c7057f7SHans Petter Selasky * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3dc7e38acSHans Petter Selasky * 4dc7e38acSHans Petter Selasky * Redistribution and use in source and binary forms, with or without 5dc7e38acSHans Petter Selasky * modification, are permitted provided that the following conditions 6dc7e38acSHans Petter Selasky * are met: 7dc7e38acSHans Petter Selasky * 1. Redistributions of source code must retain the above copyright 8dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer. 9dc7e38acSHans Petter Selasky * 2. Redistributions in binary form must reproduce the above copyright 10dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer in the 11dc7e38acSHans Petter Selasky * documentation and/or other materials provided with the distribution. 12dc7e38acSHans Petter Selasky * 13dc7e38acSHans Petter Selasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14dc7e38acSHans Petter Selasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15dc7e38acSHans Petter Selasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16dc7e38acSHans Petter Selasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17dc7e38acSHans Petter Selasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18dc7e38acSHans Petter Selasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19dc7e38acSHans Petter Selasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20dc7e38acSHans Petter Selasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21dc7e38acSHans Petter Selasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22dc7e38acSHans Petter Selasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23dc7e38acSHans Petter Selasky * SUCH DAMAGE. 24dc7e38acSHans Petter Selasky * 25dc7e38acSHans Petter Selasky * $FreeBSD$ 26dc7e38acSHans Petter Selasky */ 27dc7e38acSHans Petter Selasky 28dc7e38acSHans Petter Selasky #include <linux/interrupt.h> 29dc7e38acSHans Petter Selasky #include <linux/module.h> 30d9142151SHans Petter Selasky #include <dev/mlx5/port.h> 31dc7e38acSHans Petter Selasky #include <dev/mlx5/mlx5_ifc.h> 32e5eae1dcSHans Petter Selasky #include <dev/mlx5/mlx5_fpga/core.h> 33dc7e38acSHans Petter Selasky #include "mlx5_core.h" 34bbcb656aSKonstantin Belousov #include "eswitch.h" 35dc7e38acSHans Petter Selasky 36278ce1c9SHans Petter Selasky #include "opt_rss.h" 37278ce1c9SHans Petter Selasky 38278ce1c9SHans Petter Selasky #ifdef RSS 39278ce1c9SHans Petter Selasky #include <net/rss_config.h> 40278ce1c9SHans Petter Selasky #include <netinet/in_rss.h> 41278ce1c9SHans Petter Selasky #endif 42278ce1c9SHans Petter Selasky 43dc7e38acSHans Petter Selasky enum { 44dc7e38acSHans Petter Selasky MLX5_EQE_SIZE = sizeof(struct mlx5_eqe), 45dc7e38acSHans Petter Selasky MLX5_EQE_OWNER_INIT_VAL = 0x1, 46dc7e38acSHans Petter Selasky }; 47dc7e38acSHans Petter Selasky 48dc7e38acSHans Petter Selasky enum { 49dc7e38acSHans Petter Selasky MLX5_NUM_SPARE_EQE = 0x80, 50dc7e38acSHans Petter Selasky MLX5_NUM_ASYNC_EQE = 0x100, 51dc7e38acSHans Petter Selasky MLX5_NUM_CMD_EQE = 32, 52dc7e38acSHans Petter Selasky }; 53dc7e38acSHans Petter Selasky 54dc7e38acSHans Petter Selasky enum { 55dc7e38acSHans Petter Selasky MLX5_EQ_DOORBEL_OFFSET = 0x40, 56dc7e38acSHans Petter Selasky }; 57dc7e38acSHans Petter Selasky 58dc7e38acSHans Petter Selasky #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \ 59dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_COMM_EST) | \ 60dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \ 61dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \ 62dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \ 63dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \ 64dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 65dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 66dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \ 67dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 68dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \ 69bbcb656aSKonstantin Belousov (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT) | \ 70bbcb656aSKonstantin Belousov (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE)) 71dc7e38acSHans Petter Selasky 72dc7e38acSHans Petter Selasky struct map_eq_in { 73dc7e38acSHans Petter Selasky u64 mask; 74dc7e38acSHans Petter Selasky u32 reserved; 75dc7e38acSHans Petter Selasky u32 unmap_eqn; 76dc7e38acSHans Petter Selasky }; 77dc7e38acSHans Petter Selasky 78dc7e38acSHans Petter Selasky struct cre_des_eq { 79dc7e38acSHans Petter Selasky u8 reserved[15]; 80dc7e38acSHans Petter Selasky u8 eqn; 81dc7e38acSHans Petter Selasky }; 82dc7e38acSHans Petter Selasky 83dc7e38acSHans Petter Selasky /*Function prototype*/ 84dc7e38acSHans Petter Selasky static void mlx5_port_module_event(struct mlx5_core_dev *dev, 85dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe); 866c7057f7SHans Petter Selasky static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 876c7057f7SHans Petter Selasky struct mlx5_eqe *eqe); 88dc7e38acSHans Petter Selasky 89dc7e38acSHans Petter Selasky static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn) 90dc7e38acSHans Petter Selasky { 91788333d9SHans Petter Selasky u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0}; 92788333d9SHans Petter Selasky u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0}; 93dc7e38acSHans Petter Selasky 94dc7e38acSHans Petter Selasky MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ); 95dc7e38acSHans Petter Selasky MLX5_SET(destroy_eq_in, in, eq_number, eqn); 96dc7e38acSHans Petter Selasky 97788333d9SHans Petter Selasky return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 98dc7e38acSHans Petter Selasky } 99dc7e38acSHans Petter Selasky 100dc7e38acSHans Petter Selasky static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) 101dc7e38acSHans Petter Selasky { 102dc7e38acSHans Petter Selasky return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE); 103dc7e38acSHans Petter Selasky } 104dc7e38acSHans Petter Selasky 105dc7e38acSHans Petter Selasky static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) 106dc7e38acSHans Petter Selasky { 107dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1)); 108dc7e38acSHans Petter Selasky 109dc7e38acSHans Petter Selasky return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe; 110dc7e38acSHans Petter Selasky } 111dc7e38acSHans Petter Selasky 112dc7e38acSHans Petter Selasky static const char *eqe_type_str(u8 type) 113dc7e38acSHans Petter Selasky { 114dc7e38acSHans Petter Selasky switch (type) { 115dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMP: 116dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_COMP"; 117dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG: 118dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PATH_MIG"; 119dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMM_EST: 120dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_COMM_EST"; 121dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SQ_DRAINED: 122dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SQ_DRAINED"; 123dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 124dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_LAST_WQE"; 125dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 126dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT"; 127dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CQ_ERROR: 128dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_CQ_ERROR"; 129dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 130dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR"; 131dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 132dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PATH_MIG_FAILED"; 133dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 134dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR"; 135dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 136dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR"; 137dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 138dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR"; 139dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_INTERNAL_ERROR: 140dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_INTERNAL_ERROR"; 141dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PORT_CHANGE: 142dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PORT_CHANGE"; 143dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_GPIO_EVENT: 144dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_GPIO_EVENT"; 145dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 146dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT"; 147983026eaSHans Petter Selasky case MLX5_EVENT_TYPE_TEMP_WARN_EVENT: 148983026eaSHans Petter Selasky return "MLX5_EVENT_TYPE_TEMP_WARN_EVENT"; 149dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_REMOTE_CONFIG: 150dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_REMOTE_CONFIG"; 151dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_DB_BF_CONGESTION: 152dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_DB_BF_CONGESTION"; 153dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_STALL_EVENT: 154dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_STALL_EVENT"; 155dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CMD: 156dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_CMD"; 157dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PAGE_REQUEST: 158dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PAGE_REQUEST"; 159dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 160dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE"; 161e5eae1dcSHans Petter Selasky case MLX5_EVENT_TYPE_FPGA_ERROR: 162e5eae1dcSHans Petter Selasky return "MLX5_EVENT_TYPE_FPGA_ERROR"; 163e5eae1dcSHans Petter Selasky case MLX5_EVENT_TYPE_FPGA_QP_ERROR: 164e5eae1dcSHans Petter Selasky return "MLX5_EVENT_TYPE_FPGA_QP_ERROR"; 165cb4e4a6eSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 166cb4e4a6eSHans Petter Selasky return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT"; 1676c7057f7SHans Petter Selasky case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 1686c7057f7SHans Petter Selasky return "MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT"; 169dc7e38acSHans Petter Selasky default: 170dc7e38acSHans Petter Selasky return "Unrecognized event"; 171dc7e38acSHans Petter Selasky } 172dc7e38acSHans Petter Selasky } 173dc7e38acSHans Petter Selasky 174dc7e38acSHans Petter Selasky static enum mlx5_dev_event port_subtype_event(u8 subtype) 175dc7e38acSHans Petter Selasky { 176dc7e38acSHans Petter Selasky switch (subtype) { 177dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 178dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_DOWN; 179dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 180dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_UP; 181dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 182dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_INITIALIZED; 183dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_LID: 184dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_LID_CHANGE; 185dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 186dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PKEY_CHANGE; 187dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_GUID: 188dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_GUID_CHANGE; 189dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 190dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_CLIENT_REREG; 191dc7e38acSHans Petter Selasky } 192dc7e38acSHans Petter Selasky return -1; 193dc7e38acSHans Petter Selasky } 194dc7e38acSHans Petter Selasky 195cb4e4a6eSHans Petter Selasky static enum mlx5_dev_event dcbx_subevent(u8 subtype) 196cb4e4a6eSHans Petter Selasky { 197cb4e4a6eSHans Petter Selasky switch (subtype) { 198cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 199cb4e4a6eSHans Petter Selasky return MLX5_DEV_EVENT_ERROR_STATE_DCBX; 200cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 201cb4e4a6eSHans Petter Selasky return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE; 202cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 203cb4e4a6eSHans Petter Selasky return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE; 204cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 205cb4e4a6eSHans Petter Selasky return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE; 206cb4e4a6eSHans Petter Selasky } 207cb4e4a6eSHans Petter Selasky return -1; 208cb4e4a6eSHans Petter Selasky } 209cb4e4a6eSHans Petter Selasky 210dc7e38acSHans Petter Selasky static void eq_update_ci(struct mlx5_eq *eq, int arm) 211dc7e38acSHans Petter Selasky { 212dc7e38acSHans Petter Selasky __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); 213dc7e38acSHans Petter Selasky u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); 214dc7e38acSHans Petter Selasky __raw_writel((__force u32) cpu_to_be32(val), addr); 215dc7e38acSHans Petter Selasky /* We still want ordering, just not swabbing, so add a barrier */ 216dc7e38acSHans Petter Selasky mb(); 217dc7e38acSHans Petter Selasky } 218dc7e38acSHans Petter Selasky 219983026eaSHans Petter Selasky static void 220983026eaSHans Petter Selasky mlx5_temp_warning_event(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe) 221983026eaSHans Petter Selasky { 222983026eaSHans Petter Selasky 223983026eaSHans Petter Selasky mlx5_core_warn(dev, 22495c05e05SHans Petter Selasky "High temperature on sensors with bit set %#jx %#jx\n", 225983026eaSHans Petter Selasky (uintmax_t)be64_to_cpu(eqe->data.temp_warning.sensor_warning_msb), 226983026eaSHans Petter Selasky (uintmax_t)be64_to_cpu(eqe->data.temp_warning.sensor_warning_lsb)); 227983026eaSHans Petter Selasky } 228983026eaSHans Petter Selasky 229dc7e38acSHans Petter Selasky static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 230dc7e38acSHans Petter Selasky { 231dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe; 232dc7e38acSHans Petter Selasky int eqes_found = 0; 233dc7e38acSHans Petter Selasky int set_ci = 0; 234dc7e38acSHans Petter Selasky u32 cqn; 235dc7e38acSHans Petter Selasky u32 rsn; 236dc7e38acSHans Petter Selasky u8 port; 237dc7e38acSHans Petter Selasky 238dc7e38acSHans Petter Selasky while ((eqe = next_eqe_sw(eq))) { 239dc7e38acSHans Petter Selasky /* 240dc7e38acSHans Petter Selasky * Make sure we read EQ entry contents after we've 241dc7e38acSHans Petter Selasky * checked the ownership bit. 242dc7e38acSHans Petter Selasky */ 24392d8df2fSKonstantin Belousov atomic_thread_fence_acq(); 244dc7e38acSHans Petter Selasky 245dc7e38acSHans Petter Selasky mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", 246dc7e38acSHans Petter Selasky eq->eqn, eqe_type_str(eqe->type)); 247dc7e38acSHans Petter Selasky switch (eqe->type) { 248dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMP: 249dc7e38acSHans Petter Selasky cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; 250dc7e38acSHans Petter Selasky mlx5_cq_completion(dev, cqn); 251dc7e38acSHans Petter Selasky break; 252dc7e38acSHans Petter Selasky 253dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG: 254dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMM_EST: 255dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SQ_DRAINED: 256dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 257dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 258dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 259dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 260dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 261dc7e38acSHans Petter Selasky rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 262dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n", 263dc7e38acSHans Petter Selasky eqe_type_str(eqe->type), eqe->type, rsn); 264dc7e38acSHans Petter Selasky mlx5_rsc_event(dev, rsn, eqe->type); 265dc7e38acSHans Petter Selasky break; 266dc7e38acSHans Petter Selasky 267dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 268dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 269dc7e38acSHans Petter Selasky rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 270dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n", 271dc7e38acSHans Petter Selasky eqe_type_str(eqe->type), eqe->type, rsn); 272dc7e38acSHans Petter Selasky mlx5_srq_event(dev, rsn, eqe->type); 273dc7e38acSHans Petter Selasky break; 274dc7e38acSHans Petter Selasky 275dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CMD: 276721a1a6aSSlava Shwartsman if (dev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 277721a1a6aSSlava Shwartsman mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), 278721a1a6aSSlava Shwartsman MLX5_CMD_MODE_EVENTS); 279721a1a6aSSlava Shwartsman } 280dc7e38acSHans Petter Selasky break; 281dc7e38acSHans Petter Selasky 282dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PORT_CHANGE: 283dc7e38acSHans Petter Selasky port = (eqe->data.port.port >> 4) & 0xf; 284dc7e38acSHans Petter Selasky switch (eqe->sub_type) { 285dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 286dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 287dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_LID: 288dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 289dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_GUID: 290dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 291dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 292dc7e38acSHans Petter Selasky if (dev->event) 293dc7e38acSHans Petter Selasky dev->event(dev, port_subtype_event(eqe->sub_type), 294dc7e38acSHans Petter Selasky (unsigned long)port); 295dc7e38acSHans Petter Selasky break; 296dc7e38acSHans Petter Selasky default: 297dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n", 298dc7e38acSHans Petter Selasky port, eqe->sub_type); 299dc7e38acSHans Petter Selasky } 300dc7e38acSHans Petter Selasky break; 301cb4e4a6eSHans Petter Selasky 302cb4e4a6eSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 303cb4e4a6eSHans Petter Selasky port = (eqe->data.port.port >> 4) & 0xf; 304cb4e4a6eSHans Petter Selasky switch (eqe->sub_type) { 305cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 306cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 307cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 308cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 309cb4e4a6eSHans Petter Selasky if (dev->event) 310cb4e4a6eSHans Petter Selasky dev->event(dev, 311cb4e4a6eSHans Petter Selasky dcbx_subevent(eqe->sub_type), 312cb4e4a6eSHans Petter Selasky 0); 313cb4e4a6eSHans Petter Selasky break; 314cb4e4a6eSHans Petter Selasky default: 315cb4e4a6eSHans Petter Selasky mlx5_core_warn(dev, 316cb4e4a6eSHans Petter Selasky "dcbx event with unrecognized subtype: port %d, sub_type %d\n", 317cb4e4a6eSHans Petter Selasky port, eqe->sub_type); 318cb4e4a6eSHans Petter Selasky } 319cb4e4a6eSHans Petter Selasky break; 320cb4e4a6eSHans Petter Selasky 3216c7057f7SHans Petter Selasky case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 3226c7057f7SHans Petter Selasky mlx5_port_general_notification_event(dev, eqe); 3236c7057f7SHans Petter Selasky break; 3246c7057f7SHans Petter Selasky 325dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CQ_ERROR: 326dc7e38acSHans Petter Selasky cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 327dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n", 328dc7e38acSHans Petter Selasky cqn, eqe->data.cq_err.syndrome); 329dc7e38acSHans Petter Selasky mlx5_cq_event(dev, cqn, eqe->type); 330dc7e38acSHans Petter Selasky break; 331dc7e38acSHans Petter Selasky 332dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PAGE_REQUEST: 333dc7e38acSHans Petter Selasky { 334dc7e38acSHans Petter Selasky u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id); 335dc7e38acSHans Petter Selasky s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages); 336dc7e38acSHans Petter Selasky 337dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n", 338dc7e38acSHans Petter Selasky func_id, npages); 339dc7e38acSHans Petter Selasky mlx5_core_req_pages_handler(dev, func_id, npages); 340dc7e38acSHans Petter Selasky } 341dc7e38acSHans Petter Selasky break; 342dc7e38acSHans Petter Selasky 343dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 344dc7e38acSHans Petter Selasky mlx5_port_module_event(dev, eqe); 345dc7e38acSHans Petter Selasky break; 346dc7e38acSHans Petter Selasky 347dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 348dc7e38acSHans Petter Selasky { 349dc7e38acSHans Petter Selasky struct mlx5_eqe_vport_change *vc_eqe = 350dc7e38acSHans Petter Selasky &eqe->data.vport_change; 351dc7e38acSHans Petter Selasky u16 vport_num = be16_to_cpu(vc_eqe->vport_num); 352dc7e38acSHans Petter Selasky 353dc7e38acSHans Petter Selasky if (dev->event) 354dc7e38acSHans Petter Selasky dev->event(dev, 355dc7e38acSHans Petter Selasky MLX5_DEV_EVENT_VPORT_CHANGE, 356dc7e38acSHans Petter Selasky (unsigned long)vport_num); 357dc7e38acSHans Petter Selasky } 358bbcb656aSKonstantin Belousov if (dev->priv.eswitch != NULL) 359bbcb656aSKonstantin Belousov mlx5_eswitch_vport_event(dev->priv.eswitch, 360bbcb656aSKonstantin Belousov eqe); 361dc7e38acSHans Petter Selasky break; 362dc7e38acSHans Petter Selasky 363e5eae1dcSHans Petter Selasky case MLX5_EVENT_TYPE_FPGA_ERROR: 364e5eae1dcSHans Petter Selasky case MLX5_EVENT_TYPE_FPGA_QP_ERROR: 365e5eae1dcSHans Petter Selasky mlx5_fpga_event(dev, eqe->type, &eqe->data.raw); 366e5eae1dcSHans Petter Selasky break; 367983026eaSHans Petter Selasky case MLX5_EVENT_TYPE_TEMP_WARN_EVENT: 368983026eaSHans Petter Selasky mlx5_temp_warning_event(dev, eqe); 369983026eaSHans Petter Selasky break; 370e5eae1dcSHans Petter Selasky 371dc7e38acSHans Petter Selasky default: 372dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n", 373dc7e38acSHans Petter Selasky eqe->type, eq->eqn); 374dc7e38acSHans Petter Selasky break; 375dc7e38acSHans Petter Selasky } 376dc7e38acSHans Petter Selasky 377dc7e38acSHans Petter Selasky ++eq->cons_index; 378dc7e38acSHans Petter Selasky eqes_found = 1; 379dc7e38acSHans Petter Selasky ++set_ci; 380dc7e38acSHans Petter Selasky 381dc7e38acSHans Petter Selasky /* The HCA will think the queue has overflowed if we 382dc7e38acSHans Petter Selasky * don't tell it we've been processing events. We 383dc7e38acSHans Petter Selasky * create our EQs with MLX5_NUM_SPARE_EQE extra 384dc7e38acSHans Petter Selasky * entries, so we must update our consumer index at 385dc7e38acSHans Petter Selasky * least that often. 386dc7e38acSHans Petter Selasky */ 387dc7e38acSHans Petter Selasky if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) { 388dc7e38acSHans Petter Selasky eq_update_ci(eq, 0); 389dc7e38acSHans Petter Selasky set_ci = 0; 390dc7e38acSHans Petter Selasky } 391dc7e38acSHans Petter Selasky } 392dc7e38acSHans Petter Selasky 393dc7e38acSHans Petter Selasky eq_update_ci(eq, 1); 394dc7e38acSHans Petter Selasky 395dc7e38acSHans Petter Selasky return eqes_found; 396dc7e38acSHans Petter Selasky } 397dc7e38acSHans Petter Selasky 398dc7e38acSHans Petter Selasky static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr) 399dc7e38acSHans Petter Selasky { 400dc7e38acSHans Petter Selasky struct mlx5_eq *eq = eq_ptr; 401dc7e38acSHans Petter Selasky struct mlx5_core_dev *dev = eq->dev; 402dc7e38acSHans Petter Selasky 403192fc18dSHans Petter Selasky /* check if IRQs are not disabled */ 404192fc18dSHans Petter Selasky if (likely(dev->priv.disable_irqs == 0)) 405dc7e38acSHans Petter Selasky mlx5_eq_int(dev, eq); 406dc7e38acSHans Petter Selasky 407dc7e38acSHans Petter Selasky /* MSI-X vectors always belong to us */ 408dc7e38acSHans Petter Selasky return IRQ_HANDLED; 409dc7e38acSHans Petter Selasky } 410dc7e38acSHans Petter Selasky 411dc7e38acSHans Petter Selasky static void init_eq_buf(struct mlx5_eq *eq) 412dc7e38acSHans Petter Selasky { 413dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe; 414dc7e38acSHans Petter Selasky int i; 415dc7e38acSHans Petter Selasky 416dc7e38acSHans Petter Selasky for (i = 0; i < eq->nent; i++) { 417dc7e38acSHans Petter Selasky eqe = get_eqe(eq, i); 418dc7e38acSHans Petter Selasky eqe->owner = MLX5_EQE_OWNER_INIT_VAL; 419dc7e38acSHans Petter Selasky } 420dc7e38acSHans Petter Selasky } 421dc7e38acSHans Petter Selasky 422dc7e38acSHans Petter Selasky int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 4236226306bSHans Petter Selasky int nent, u64 mask, struct mlx5_uar *uar) 424dc7e38acSHans Petter Selasky { 425788333d9SHans Petter Selasky u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0}; 426dc7e38acSHans Petter Selasky struct mlx5_priv *priv = &dev->priv; 427788333d9SHans Petter Selasky __be64 *pas; 428788333d9SHans Petter Selasky void *eqc; 429dc7e38acSHans Petter Selasky int inlen; 430788333d9SHans Petter Selasky u32 *in; 431788333d9SHans Petter Selasky int err; 432dc7e38acSHans Petter Selasky 433dc7e38acSHans Petter Selasky eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE); 434a2485fe5SHans Petter Selasky eq->cons_index = 0; 435dc7e38acSHans Petter Selasky err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE, 436dc7e38acSHans Petter Selasky &eq->buf); 437dc7e38acSHans Petter Selasky if (err) 438dc7e38acSHans Petter Selasky return err; 439dc7e38acSHans Petter Selasky 440dc7e38acSHans Petter Selasky init_eq_buf(eq); 441dc7e38acSHans Petter Selasky 442788333d9SHans Petter Selasky inlen = MLX5_ST_SZ_BYTES(create_eq_in) + 443788333d9SHans Petter Selasky MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages; 444dc7e38acSHans Petter Selasky in = mlx5_vzalloc(inlen); 445dc7e38acSHans Petter Selasky if (!in) { 446dc7e38acSHans Petter Selasky err = -ENOMEM; 447dc7e38acSHans Petter Selasky goto err_buf; 448dc7e38acSHans Petter Selasky } 449dc7e38acSHans Petter Selasky 450788333d9SHans Petter Selasky pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas); 451788333d9SHans Petter Selasky mlx5_fill_page_array(&eq->buf, pas); 452dc7e38acSHans Petter Selasky 453788333d9SHans Petter Selasky MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ); 454788333d9SHans Petter Selasky MLX5_SET64(create_eq_in, in, event_bitmask, mask); 455dc7e38acSHans Petter Selasky 456788333d9SHans Petter Selasky eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry); 457788333d9SHans Petter Selasky MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent)); 458788333d9SHans Petter Selasky MLX5_SET(eqc, eqc, uar_page, uar->index); 459788333d9SHans Petter Selasky MLX5_SET(eqc, eqc, intr, vecidx); 460788333d9SHans Petter Selasky MLX5_SET(eqc, eqc, log_page_size, 461788333d9SHans Petter Selasky eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 462788333d9SHans Petter Selasky 463788333d9SHans Petter Selasky err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out)); 464dc7e38acSHans Petter Selasky if (err) 465dc7e38acSHans Petter Selasky goto err_in; 466dc7e38acSHans Petter Selasky 467788333d9SHans Petter Selasky eq->eqn = MLX5_GET(create_eq_out, out, eq_number); 468dc7e38acSHans Petter Selasky eq->irqn = vecidx; 469dc7e38acSHans Petter Selasky eq->dev = dev; 470dc7e38acSHans Petter Selasky eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET; 471dc7e38acSHans Petter Selasky err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0, 4726226306bSHans Petter Selasky "mlx5_core", eq); 473dc7e38acSHans Petter Selasky if (err) 474dc7e38acSHans Petter Selasky goto err_eq; 475278ce1c9SHans Petter Selasky #ifdef RSS 476278ce1c9SHans Petter Selasky if (vecidx >= MLX5_EQ_VEC_COMP_BASE) { 477278ce1c9SHans Petter Selasky u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE; 478278ce1c9SHans Petter Selasky err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector, 479278ce1c9SHans Petter Selasky rss_getcpu(bucket % rss_getnumbuckets())); 480278ce1c9SHans Petter Selasky if (err) 481278ce1c9SHans Petter Selasky goto err_irq; 482278ce1c9SHans Petter Selasky } 483278ce1c9SHans Petter Selasky #else 484278ce1c9SHans Petter Selasky if (0) 485278ce1c9SHans Petter Selasky goto err_irq; 486278ce1c9SHans Petter Selasky #endif 487dc7e38acSHans Petter Selasky 488dc7e38acSHans Petter Selasky 489dc7e38acSHans Petter Selasky /* EQs are created in ARMED state 490dc7e38acSHans Petter Selasky */ 491dc7e38acSHans Petter Selasky eq_update_ci(eq, 1); 492dc7e38acSHans Petter Selasky 493dc7e38acSHans Petter Selasky kvfree(in); 494dc7e38acSHans Petter Selasky return 0; 495dc7e38acSHans Petter Selasky 496278ce1c9SHans Petter Selasky err_irq: 497278ce1c9SHans Petter Selasky free_irq(priv->msix_arr[vecidx].vector, eq); 498dc7e38acSHans Petter Selasky 499dc7e38acSHans Petter Selasky err_eq: 500dc7e38acSHans Petter Selasky mlx5_cmd_destroy_eq(dev, eq->eqn); 501dc7e38acSHans Petter Selasky 502dc7e38acSHans Petter Selasky err_in: 503dc7e38acSHans Petter Selasky kvfree(in); 504dc7e38acSHans Petter Selasky 505dc7e38acSHans Petter Selasky err_buf: 506dc7e38acSHans Petter Selasky mlx5_buf_free(dev, &eq->buf); 507dc7e38acSHans Petter Selasky return err; 508dc7e38acSHans Petter Selasky } 509dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_create_map_eq); 510dc7e38acSHans Petter Selasky 511dc7e38acSHans Petter Selasky int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 512dc7e38acSHans Petter Selasky { 513dc7e38acSHans Petter Selasky int err; 514dc7e38acSHans Petter Selasky 515dc7e38acSHans Petter Selasky free_irq(dev->priv.msix_arr[eq->irqn].vector, eq); 516dc7e38acSHans Petter Selasky err = mlx5_cmd_destroy_eq(dev, eq->eqn); 517dc7e38acSHans Petter Selasky if (err) 518dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n", 519dc7e38acSHans Petter Selasky eq->eqn); 520dc7e38acSHans Petter Selasky mlx5_buf_free(dev, &eq->buf); 521dc7e38acSHans Petter Selasky 522dc7e38acSHans Petter Selasky return err; 523dc7e38acSHans Petter Selasky } 524dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq); 525dc7e38acSHans Petter Selasky 526dc7e38acSHans Petter Selasky int mlx5_eq_init(struct mlx5_core_dev *dev) 527dc7e38acSHans Petter Selasky { 528dc7e38acSHans Petter Selasky int err; 529dc7e38acSHans Petter Selasky 530dc7e38acSHans Petter Selasky spin_lock_init(&dev->priv.eq_table.lock); 531dc7e38acSHans Petter Selasky 532dc7e38acSHans Petter Selasky err = 0; 533dc7e38acSHans Petter Selasky 534dc7e38acSHans Petter Selasky return err; 535dc7e38acSHans Petter Selasky } 536dc7e38acSHans Petter Selasky 537dc7e38acSHans Petter Selasky 538dc7e38acSHans Petter Selasky void mlx5_eq_cleanup(struct mlx5_core_dev *dev) 539dc7e38acSHans Petter Selasky { 540dc7e38acSHans Petter Selasky } 541dc7e38acSHans Petter Selasky 542dc7e38acSHans Petter Selasky int mlx5_start_eqs(struct mlx5_core_dev *dev) 543dc7e38acSHans Petter Selasky { 544dc7e38acSHans Petter Selasky struct mlx5_eq_table *table = &dev->priv.eq_table; 545a4d6b007SHans Petter Selasky u64 async_event_mask = MLX5_ASYNC_EVENT_MASK; 546dc7e38acSHans Petter Selasky int err; 547dc7e38acSHans Petter Selasky 548dc7e38acSHans Petter Selasky if (MLX5_CAP_GEN(dev, port_module_event)) 549dc7e38acSHans Petter Selasky async_event_mask |= (1ull << 550dc7e38acSHans Petter Selasky MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT); 551dc7e38acSHans Petter Selasky 55298a998d5SHans Petter Selasky if (MLX5_CAP_GEN(dev, nic_vport_change_event)) 55398a998d5SHans Petter Selasky async_event_mask |= (1ull << 55498a998d5SHans Petter Selasky MLX5_EVENT_TYPE_NIC_VPORT_CHANGE); 55598a998d5SHans Petter Selasky 556cb4e4a6eSHans Petter Selasky if (MLX5_CAP_GEN(dev, dcbx)) 557cb4e4a6eSHans Petter Selasky async_event_mask |= (1ull << 558cb4e4a6eSHans Petter Selasky MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT); 559cb4e4a6eSHans Petter Selasky 560e5eae1dcSHans Petter Selasky if (MLX5_CAP_GEN(dev, fpga)) 561e5eae1dcSHans Petter Selasky async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) | 562e5eae1dcSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR); 563e5eae1dcSHans Petter Selasky 564983026eaSHans Petter Selasky if (MLX5_CAP_GEN(dev, temp_warn_event)) 565983026eaSHans Petter Selasky async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT); 566983026eaSHans Petter Selasky 567adb6fd50SHans Petter Selasky if (MLX5_CAP_GEN(dev, general_notification_event)) { 568adb6fd50SHans Petter Selasky async_event_mask |= (1ull << 569adb6fd50SHans Petter Selasky MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT); 570adb6fd50SHans Petter Selasky } 571adb6fd50SHans Petter Selasky 572dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, 573dc7e38acSHans Petter Selasky MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, 5746226306bSHans Petter Selasky &dev->priv.uuari.uars[0]); 575dc7e38acSHans Petter Selasky if (err) { 576dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err); 577dc7e38acSHans Petter Selasky return err; 578dc7e38acSHans Petter Selasky } 579dc7e38acSHans Petter Selasky 580dc7e38acSHans Petter Selasky mlx5_cmd_use_events(dev); 581dc7e38acSHans Petter Selasky 582dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC, 583dc7e38acSHans Petter Selasky MLX5_NUM_ASYNC_EQE, async_event_mask, 5846226306bSHans Petter Selasky &dev->priv.uuari.uars[0]); 585dc7e38acSHans Petter Selasky if (err) { 586dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create async EQ %d\n", err); 587dc7e38acSHans Petter Selasky goto err1; 588dc7e38acSHans Petter Selasky } 589dc7e38acSHans Petter Selasky 590dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->pages_eq, 591dc7e38acSHans Petter Selasky MLX5_EQ_VEC_PAGES, 592dc7e38acSHans Petter Selasky /* TODO: sriov max_vf + */ 1, 5936226306bSHans Petter Selasky 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, 594dc7e38acSHans Petter Selasky &dev->priv.uuari.uars[0]); 595dc7e38acSHans Petter Selasky if (err) { 596dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create pages EQ %d\n", err); 597dc7e38acSHans Petter Selasky goto err2; 598dc7e38acSHans Petter Selasky } 599dc7e38acSHans Petter Selasky 600dc7e38acSHans Petter Selasky return err; 601dc7e38acSHans Petter Selasky 602dc7e38acSHans Petter Selasky err2: 603dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->async_eq); 604dc7e38acSHans Petter Selasky 605dc7e38acSHans Petter Selasky err1: 606dc7e38acSHans Petter Selasky mlx5_cmd_use_polling(dev); 607dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 608dc7e38acSHans Petter Selasky return err; 609dc7e38acSHans Petter Selasky } 610dc7e38acSHans Petter Selasky 611dc7e38acSHans Petter Selasky int mlx5_stop_eqs(struct mlx5_core_dev *dev) 612dc7e38acSHans Petter Selasky { 613dc7e38acSHans Petter Selasky struct mlx5_eq_table *table = &dev->priv.eq_table; 614dc7e38acSHans Petter Selasky int err; 615dc7e38acSHans Petter Selasky 616dc7e38acSHans Petter Selasky err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); 617dc7e38acSHans Petter Selasky if (err) 618dc7e38acSHans Petter Selasky return err; 619dc7e38acSHans Petter Selasky 620dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->async_eq); 621dc7e38acSHans Petter Selasky mlx5_cmd_use_polling(dev); 622dc7e38acSHans Petter Selasky 623dc7e38acSHans Petter Selasky err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 624dc7e38acSHans Petter Selasky if (err) 625dc7e38acSHans Petter Selasky mlx5_cmd_use_events(dev); 626dc7e38acSHans Petter Selasky 627dc7e38acSHans Petter Selasky return err; 628dc7e38acSHans Petter Selasky } 629dc7e38acSHans Petter Selasky 630dc7e38acSHans Petter Selasky int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 631788333d9SHans Petter Selasky u32 *out, int outlen) 632dc7e38acSHans Petter Selasky { 633788333d9SHans Petter Selasky u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0}; 634dc7e38acSHans Petter Selasky 635dc7e38acSHans Petter Selasky memset(out, 0, outlen); 636788333d9SHans Petter Selasky MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ); 637788333d9SHans Petter Selasky MLX5_SET(query_eq_in, in, eq_number, eq->eqn); 638dc7e38acSHans Petter Selasky 639788333d9SHans Petter Selasky return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); 640dc7e38acSHans Petter Selasky } 641dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_core_eq_query); 642dc7e38acSHans Petter Selasky 643dc7e38acSHans Petter Selasky static const char *mlx5_port_module_event_error_type_to_string(u8 error_type) 644dc7e38acSHans Petter Selasky { 645dc7e38acSHans Petter Selasky switch (error_type) { 646dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED: 647111b57c3SHans Petter Selasky return "Power budget exceeded"; 648dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE: 649111b57c3SHans Petter Selasky return "Long Range for non MLNX cable"; 650dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_BUS_STUCK: 651dc7e38acSHans Petter Selasky return "Bus stuck(I2C or data shorted)"; 652dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT: 653dc7e38acSHans Petter Selasky return "No EEPROM/retry timeout"; 654dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST: 655dc7e38acSHans Petter Selasky return "Enforce part number list"; 656ecb4fcc4SHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE: 657111b57c3SHans Petter Selasky return "Unknown identifier"; 658dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE: 659dc7e38acSHans Petter Selasky return "High Temperature"; 660cb4e4a6eSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED: 661111b57c3SHans Petter Selasky return "Bad or shorted cable/module"; 6626418350cSKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_PMD_TYPE_NOT_ENABLED: 6636418350cSKonstantin Belousov return "PMD type is not enabled"; 664d0a40683SKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_LASTER_TEC_FAILURE: 665d0a40683SKonstantin Belousov return "Laster_TEC_failure"; 666d0a40683SKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_HIGH_CURRENT: 667d0a40683SKonstantin Belousov return "High_current"; 668d0a40683SKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_HIGH_VOLTAGE: 669d0a40683SKonstantin Belousov return "High_voltage"; 670d0a40683SKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_PCIE_SYS_POWER_SLOT_EXCEEDED: 671d0a40683SKonstantin Belousov return "pcie_system_power_slot_Exceeded"; 672d0a40683SKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_HIGH_POWER: 673d0a40683SKonstantin Belousov return "High_power"; 674d0a40683SKonstantin Belousov case MLX5_MODULE_EVENT_ERROR_MODULE_STATE_MACHINE_FAULT: 675d0a40683SKonstantin Belousov return "Module_state_machine_fault"; 676dc7e38acSHans Petter Selasky default: 677dc7e38acSHans Petter Selasky return "Unknown error type"; 678dc7e38acSHans Petter Selasky } 679dc7e38acSHans Petter Selasky } 680dc7e38acSHans Petter Selasky 68121dd6527SHans Petter Selasky unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num) 68221dd6527SHans Petter Selasky { 68321dd6527SHans Petter Selasky if (module_num < 0 || module_num >= MLX5_MAX_PORTS) 68421dd6527SHans Petter Selasky return 0; /* undefined */ 68521dd6527SHans Petter Selasky return dev->module_status[module_num]; 68621dd6527SHans Petter Selasky } 68721dd6527SHans Petter Selasky 688dc7e38acSHans Petter Selasky static void mlx5_port_module_event(struct mlx5_core_dev *dev, 689dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe) 690dc7e38acSHans Petter Selasky { 691dc7e38acSHans Petter Selasky unsigned int module_num; 692dc7e38acSHans Petter Selasky unsigned int module_status; 693dc7e38acSHans Petter Selasky unsigned int error_type; 694dc7e38acSHans Petter Selasky struct mlx5_eqe_port_module_event *module_event_eqe; 695dc7e38acSHans Petter Selasky 696dc7e38acSHans Petter Selasky module_event_eqe = &eqe->data.port_module_event; 697dc7e38acSHans Petter Selasky 698dc7e38acSHans Petter Selasky module_num = (unsigned int)module_event_eqe->module; 699dc7e38acSHans Petter Selasky module_status = (unsigned int)module_event_eqe->module_status & 700dc7e38acSHans Petter Selasky PORT_MODULE_EVENT_MODULE_STATUS_MASK; 701dc7e38acSHans Petter Selasky error_type = (unsigned int)module_event_eqe->error_type & 702dc7e38acSHans Petter Selasky PORT_MODULE_EVENT_ERROR_TYPE_MASK; 703dc7e38acSHans Petter Selasky 704111b57c3SHans Petter Selasky if (module_status < MLX5_MODULE_STATUS_NUM) 705111b57c3SHans Petter Selasky dev->priv.pme_stats.status_counters[module_status]++; 706dc7e38acSHans Petter Selasky switch (module_status) { 707ecb4fcc4SHans Petter Selasky case MLX5_MODULE_STATUS_PLUGGED_ENABLED: 708a2f4f59cSHans Petter Selasky mlx5_core_info(dev, 709a2f4f59cSHans Petter Selasky "Module %u, status: plugged and enabled\n", 710111b57c3SHans Petter Selasky module_num); 711dc7e38acSHans Petter Selasky break; 712dc7e38acSHans Petter Selasky 713dc7e38acSHans Petter Selasky case MLX5_MODULE_STATUS_UNPLUGGED: 714a2f4f59cSHans Petter Selasky mlx5_core_info(dev, 715a2f4f59cSHans Petter Selasky "Module %u, status: unplugged\n", module_num); 716dc7e38acSHans Petter Selasky break; 717dc7e38acSHans Petter Selasky 718dc7e38acSHans Petter Selasky case MLX5_MODULE_STATUS_ERROR: 719a2f4f59cSHans Petter Selasky mlx5_core_err(dev, 720fedc7bd2SHans Petter Selasky "Module %u, status: error, %s (%d)\n", 721111b57c3SHans Petter Selasky module_num, 722fedc7bd2SHans Petter Selasky mlx5_port_module_event_error_type_to_string(error_type), 723fedc7bd2SHans Petter Selasky error_type); 724111b57c3SHans Petter Selasky if (error_type < MLX5_MODULE_EVENT_ERROR_NUM) 725111b57c3SHans Petter Selasky dev->priv.pme_stats.error_counters[error_type]++; 726ecb4fcc4SHans Petter Selasky break; 727ecb4fcc4SHans Petter Selasky 728dc7e38acSHans Petter Selasky default: 729a2f4f59cSHans Petter Selasky mlx5_core_info(dev, 730fedc7bd2SHans Petter Selasky "Module %u, unknown status %d\n", module_num, module_status); 731dc7e38acSHans Petter Selasky } 73221dd6527SHans Petter Selasky /* store module status */ 73321dd6527SHans Petter Selasky if (module_num < MLX5_MAX_PORTS) 73421dd6527SHans Petter Selasky dev->module_status[module_num] = module_status; 735dc7e38acSHans Petter Selasky } 736dc7e38acSHans Petter Selasky 7376c7057f7SHans Petter Selasky static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 7386c7057f7SHans Petter Selasky struct mlx5_eqe *eqe) 7396c7057f7SHans Petter Selasky { 7406c7057f7SHans Petter Selasky u8 port = (eqe->data.port.port >> 4) & 0xf; 741adb6fd50SHans Petter Selasky u32 rqn; 742adb6fd50SHans Petter Selasky struct mlx5_eqe_general_notification_event *general_event; 7436c7057f7SHans Petter Selasky 7446c7057f7SHans Petter Selasky switch (eqe->sub_type) { 7456c7057f7SHans Petter Selasky case MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT: 7466c7057f7SHans Petter Selasky general_event = &eqe->data.general_notifications; 7476c7057f7SHans Petter Selasky rqn = be32_to_cpu(general_event->rq_user_index_delay_drop) & 7486c7057f7SHans Petter Selasky 0xffffff; 7496c7057f7SHans Petter Selasky break; 750adb6fd50SHans Petter Selasky case MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT: 751adb6fd50SHans Petter Selasky mlx5_trigger_health_watchdog(dev); 752adb6fd50SHans Petter Selasky break; 7536c7057f7SHans Petter Selasky default: 7546c7057f7SHans Petter Selasky mlx5_core_warn(dev, 7556c7057f7SHans Petter Selasky "general event with unrecognized subtype: port %d, sub_type %d\n", 7566c7057f7SHans Petter Selasky port, eqe->sub_type); 7576c7057f7SHans Petter Selasky break; 7586c7057f7SHans Petter Selasky } 7596c7057f7SHans Petter Selasky } 7606c7057f7SHans Petter Selasky 761f14d8498SHans Petter Selasky void 762f14d8498SHans Petter Selasky mlx5_disable_interrupts(struct mlx5_core_dev *dev) 763f14d8498SHans Petter Selasky { 764f14d8498SHans Petter Selasky int nvec = dev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE; 765f14d8498SHans Petter Selasky int x; 766f14d8498SHans Petter Selasky 767f14d8498SHans Petter Selasky for (x = 0; x != nvec; x++) 768f14d8498SHans Petter Selasky disable_irq(dev->priv.msix_arr[x].vector); 769f14d8498SHans Petter Selasky } 770f14d8498SHans Petter Selasky 771f14d8498SHans Petter Selasky void 772f14d8498SHans Petter Selasky mlx5_poll_interrupts(struct mlx5_core_dev *dev) 773f14d8498SHans Petter Selasky { 774f14d8498SHans Petter Selasky struct mlx5_eq *eq; 775f14d8498SHans Petter Selasky 776f14d8498SHans Petter Selasky if (unlikely(dev->priv.disable_irqs != 0)) 777f14d8498SHans Petter Selasky return; 778f14d8498SHans Petter Selasky 779f14d8498SHans Petter Selasky mlx5_eq_int(dev, &dev->priv.eq_table.cmd_eq); 780f14d8498SHans Petter Selasky mlx5_eq_int(dev, &dev->priv.eq_table.async_eq); 781f14d8498SHans Petter Selasky mlx5_eq_int(dev, &dev->priv.eq_table.pages_eq); 782f14d8498SHans Petter Selasky 783f14d8498SHans Petter Selasky list_for_each_entry(eq, &dev->priv.eq_table.comp_eqs_list, list) 784f14d8498SHans Petter Selasky mlx5_eq_int(dev, eq); 785f14d8498SHans Petter Selasky } 786