1dc7e38acSHans Petter Selasky /*- 2dc7e38acSHans Petter Selasky * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3dc7e38acSHans Petter Selasky * 4dc7e38acSHans Petter Selasky * Redistribution and use in source and binary forms, with or without 5dc7e38acSHans Petter Selasky * modification, are permitted provided that the following conditions 6dc7e38acSHans Petter Selasky * are met: 7dc7e38acSHans Petter Selasky * 1. Redistributions of source code must retain the above copyright 8dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer. 9dc7e38acSHans Petter Selasky * 2. Redistributions in binary form must reproduce the above copyright 10dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer in the 11dc7e38acSHans Petter Selasky * documentation and/or other materials provided with the distribution. 12dc7e38acSHans Petter Selasky * 13dc7e38acSHans Petter Selasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14dc7e38acSHans Petter Selasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15dc7e38acSHans Petter Selasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16dc7e38acSHans Petter Selasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17dc7e38acSHans Petter Selasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18dc7e38acSHans Petter Selasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19dc7e38acSHans Petter Selasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20dc7e38acSHans Petter Selasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21dc7e38acSHans Petter Selasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22dc7e38acSHans Petter Selasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23dc7e38acSHans Petter Selasky * SUCH DAMAGE. 24dc7e38acSHans Petter Selasky * 25dc7e38acSHans Petter Selasky * $FreeBSD$ 26dc7e38acSHans Petter Selasky */ 27dc7e38acSHans Petter Selasky 28dc7e38acSHans Petter Selasky #include <linux/interrupt.h> 29dc7e38acSHans Petter Selasky #include <linux/module.h> 30dc7e38acSHans Petter Selasky #include <dev/mlx5/driver.h> 31dc7e38acSHans Petter Selasky #include <dev/mlx5/mlx5_ifc.h> 32dc7e38acSHans Petter Selasky #include "mlx5_core.h" 33dc7e38acSHans Petter Selasky 34278ce1c9SHans Petter Selasky #include "opt_rss.h" 35278ce1c9SHans Petter Selasky 36278ce1c9SHans Petter Selasky #ifdef RSS 37278ce1c9SHans Petter Selasky #include <net/rss_config.h> 38278ce1c9SHans Petter Selasky #include <netinet/in_rss.h> 39278ce1c9SHans Petter Selasky #endif 40278ce1c9SHans Petter Selasky 41dc7e38acSHans Petter Selasky enum { 42dc7e38acSHans Petter Selasky MLX5_EQE_SIZE = sizeof(struct mlx5_eqe), 43dc7e38acSHans Petter Selasky MLX5_EQE_OWNER_INIT_VAL = 0x1, 44dc7e38acSHans Petter Selasky }; 45dc7e38acSHans Petter Selasky 46dc7e38acSHans Petter Selasky enum { 47dc7e38acSHans Petter Selasky MLX5_NUM_SPARE_EQE = 0x80, 48dc7e38acSHans Petter Selasky MLX5_NUM_ASYNC_EQE = 0x100, 49dc7e38acSHans Petter Selasky MLX5_NUM_CMD_EQE = 32, 50dc7e38acSHans Petter Selasky }; 51dc7e38acSHans Petter Selasky 52dc7e38acSHans Petter Selasky enum { 53dc7e38acSHans Petter Selasky MLX5_EQ_DOORBEL_OFFSET = 0x40, 54dc7e38acSHans Petter Selasky }; 55dc7e38acSHans Petter Selasky 56dc7e38acSHans Petter Selasky #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \ 57dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_COMM_EST) | \ 58dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \ 59dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \ 60dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \ 61dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \ 62dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 63dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 64dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \ 65dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 66dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \ 67dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT)) 68dc7e38acSHans Petter Selasky 69dc7e38acSHans Petter Selasky struct map_eq_in { 70dc7e38acSHans Petter Selasky u64 mask; 71dc7e38acSHans Petter Selasky u32 reserved; 72dc7e38acSHans Petter Selasky u32 unmap_eqn; 73dc7e38acSHans Petter Selasky }; 74dc7e38acSHans Petter Selasky 75dc7e38acSHans Petter Selasky struct cre_des_eq { 76dc7e38acSHans Petter Selasky u8 reserved[15]; 77dc7e38acSHans Petter Selasky u8 eqn; 78dc7e38acSHans Petter Selasky }; 79dc7e38acSHans Petter Selasky 80dc7e38acSHans Petter Selasky /*Function prototype*/ 81dc7e38acSHans Petter Selasky static void mlx5_port_module_event(struct mlx5_core_dev *dev, 82dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe); 83dc7e38acSHans Petter Selasky 84dc7e38acSHans Petter Selasky static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn) 85dc7e38acSHans Petter Selasky { 86dc7e38acSHans Petter Selasky u32 in[MLX5_ST_SZ_DW(destroy_eq_in)]; 87dc7e38acSHans Petter Selasky u32 out[MLX5_ST_SZ_DW(destroy_eq_out)]; 88dc7e38acSHans Petter Selasky 89dc7e38acSHans Petter Selasky memset(in, 0, sizeof(in)); 90dc7e38acSHans Petter Selasky 91dc7e38acSHans Petter Selasky MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ); 92dc7e38acSHans Petter Selasky MLX5_SET(destroy_eq_in, in, eq_number, eqn); 93dc7e38acSHans Petter Selasky 94dc7e38acSHans Petter Selasky memset(out, 0, sizeof(out)); 95dc7e38acSHans Petter Selasky return mlx5_cmd_exec_check_status(dev, in, sizeof(in), 96dc7e38acSHans Petter Selasky out, sizeof(out)); 97dc7e38acSHans Petter Selasky } 98dc7e38acSHans Petter Selasky 99dc7e38acSHans Petter Selasky static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) 100dc7e38acSHans Petter Selasky { 101dc7e38acSHans Petter Selasky return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE); 102dc7e38acSHans Petter Selasky } 103dc7e38acSHans Petter Selasky 104dc7e38acSHans Petter Selasky static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) 105dc7e38acSHans Petter Selasky { 106dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1)); 107dc7e38acSHans Petter Selasky 108dc7e38acSHans Petter Selasky return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe; 109dc7e38acSHans Petter Selasky } 110dc7e38acSHans Petter Selasky 111dc7e38acSHans Petter Selasky static const char *eqe_type_str(u8 type) 112dc7e38acSHans Petter Selasky { 113dc7e38acSHans Petter Selasky switch (type) { 114dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMP: 115dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_COMP"; 116dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG: 117dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PATH_MIG"; 118dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMM_EST: 119dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_COMM_EST"; 120dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SQ_DRAINED: 121dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SQ_DRAINED"; 122dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 123dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_LAST_WQE"; 124dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 125dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT"; 126dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CQ_ERROR: 127dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_CQ_ERROR"; 128dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 129dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR"; 130dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 131dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PATH_MIG_FAILED"; 132dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 133dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR"; 134dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 135dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR"; 136dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 137dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR"; 138dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_INTERNAL_ERROR: 139dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_INTERNAL_ERROR"; 140dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PORT_CHANGE: 141dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PORT_CHANGE"; 142dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_GPIO_EVENT: 143dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_GPIO_EVENT"; 144dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 145dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT"; 146dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_REMOTE_CONFIG: 147dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_REMOTE_CONFIG"; 148dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_DB_BF_CONGESTION: 149dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_DB_BF_CONGESTION"; 150dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_STALL_EVENT: 151dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_STALL_EVENT"; 152dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CMD: 153dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_CMD"; 154dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PAGE_REQUEST: 155dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PAGE_REQUEST"; 156dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 157dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE"; 158dc7e38acSHans Petter Selasky default: 159dc7e38acSHans Petter Selasky return "Unrecognized event"; 160dc7e38acSHans Petter Selasky } 161dc7e38acSHans Petter Selasky } 162dc7e38acSHans Petter Selasky 163dc7e38acSHans Petter Selasky static enum mlx5_dev_event port_subtype_event(u8 subtype) 164dc7e38acSHans Petter Selasky { 165dc7e38acSHans Petter Selasky switch (subtype) { 166dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 167dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_DOWN; 168dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 169dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_UP; 170dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 171dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_INITIALIZED; 172dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_LID: 173dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_LID_CHANGE; 174dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 175dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PKEY_CHANGE; 176dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_GUID: 177dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_GUID_CHANGE; 178dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 179dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_CLIENT_REREG; 180dc7e38acSHans Petter Selasky } 181dc7e38acSHans Petter Selasky return -1; 182dc7e38acSHans Petter Selasky } 183dc7e38acSHans Petter Selasky 184dc7e38acSHans Petter Selasky static void eq_update_ci(struct mlx5_eq *eq, int arm) 185dc7e38acSHans Petter Selasky { 186dc7e38acSHans Petter Selasky __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); 187dc7e38acSHans Petter Selasky u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); 188dc7e38acSHans Petter Selasky __raw_writel((__force u32) cpu_to_be32(val), addr); 189dc7e38acSHans Petter Selasky /* We still want ordering, just not swabbing, so add a barrier */ 190dc7e38acSHans Petter Selasky mb(); 191dc7e38acSHans Petter Selasky } 192dc7e38acSHans Petter Selasky 193dc7e38acSHans Petter Selasky static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 194dc7e38acSHans Petter Selasky { 195dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe; 196dc7e38acSHans Petter Selasky int eqes_found = 0; 197dc7e38acSHans Petter Selasky int set_ci = 0; 198dc7e38acSHans Petter Selasky u32 cqn; 199dc7e38acSHans Petter Selasky u32 rsn; 200dc7e38acSHans Petter Selasky u8 port; 201dc7e38acSHans Petter Selasky 202dc7e38acSHans Petter Selasky while ((eqe = next_eqe_sw(eq))) { 203dc7e38acSHans Petter Selasky /* 204dc7e38acSHans Petter Selasky * Make sure we read EQ entry contents after we've 205dc7e38acSHans Petter Selasky * checked the ownership bit. 206dc7e38acSHans Petter Selasky */ 207dc7e38acSHans Petter Selasky rmb(); 208dc7e38acSHans Petter Selasky 209dc7e38acSHans Petter Selasky mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", 210dc7e38acSHans Petter Selasky eq->eqn, eqe_type_str(eqe->type)); 211dc7e38acSHans Petter Selasky switch (eqe->type) { 212dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMP: 213dc7e38acSHans Petter Selasky cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; 214dc7e38acSHans Petter Selasky mlx5_cq_completion(dev, cqn); 215dc7e38acSHans Petter Selasky break; 216dc7e38acSHans Petter Selasky 217dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG: 218dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMM_EST: 219dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SQ_DRAINED: 220dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 221dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 222dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 223dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 224dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 225dc7e38acSHans Petter Selasky rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 226dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n", 227dc7e38acSHans Petter Selasky eqe_type_str(eqe->type), eqe->type, rsn); 228dc7e38acSHans Petter Selasky mlx5_rsc_event(dev, rsn, eqe->type); 229dc7e38acSHans Petter Selasky break; 230dc7e38acSHans Petter Selasky 231dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 232dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 233dc7e38acSHans Petter Selasky rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 234dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n", 235dc7e38acSHans Petter Selasky eqe_type_str(eqe->type), eqe->type, rsn); 236dc7e38acSHans Petter Selasky mlx5_srq_event(dev, rsn, eqe->type); 237dc7e38acSHans Petter Selasky break; 238dc7e38acSHans Petter Selasky 239dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CMD: 240dc7e38acSHans Petter Selasky mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector)); 241dc7e38acSHans Petter Selasky break; 242dc7e38acSHans Petter Selasky 243dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PORT_CHANGE: 244dc7e38acSHans Petter Selasky port = (eqe->data.port.port >> 4) & 0xf; 245dc7e38acSHans Petter Selasky switch (eqe->sub_type) { 246dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 247dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 248dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_LID: 249dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 250dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_GUID: 251dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 252dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 253dc7e38acSHans Petter Selasky if (dev->event) 254dc7e38acSHans Petter Selasky dev->event(dev, port_subtype_event(eqe->sub_type), 255dc7e38acSHans Petter Selasky (unsigned long)port); 256dc7e38acSHans Petter Selasky break; 257dc7e38acSHans Petter Selasky default: 258dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n", 259dc7e38acSHans Petter Selasky port, eqe->sub_type); 260dc7e38acSHans Petter Selasky } 261dc7e38acSHans Petter Selasky break; 262dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CQ_ERROR: 263dc7e38acSHans Petter Selasky cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 264dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n", 265dc7e38acSHans Petter Selasky cqn, eqe->data.cq_err.syndrome); 266dc7e38acSHans Petter Selasky mlx5_cq_event(dev, cqn, eqe->type); 267dc7e38acSHans Petter Selasky break; 268dc7e38acSHans Petter Selasky 269dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PAGE_REQUEST: 270dc7e38acSHans Petter Selasky { 271dc7e38acSHans Petter Selasky u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id); 272dc7e38acSHans Petter Selasky s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages); 273dc7e38acSHans Petter Selasky 274dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n", 275dc7e38acSHans Petter Selasky func_id, npages); 276dc7e38acSHans Petter Selasky mlx5_core_req_pages_handler(dev, func_id, npages); 277dc7e38acSHans Petter Selasky } 278dc7e38acSHans Petter Selasky break; 279dc7e38acSHans Petter Selasky 280dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 281dc7e38acSHans Petter Selasky mlx5_port_module_event(dev, eqe); 282dc7e38acSHans Petter Selasky break; 283dc7e38acSHans Petter Selasky 284dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 285dc7e38acSHans Petter Selasky { 286dc7e38acSHans Petter Selasky struct mlx5_eqe_vport_change *vc_eqe = 287dc7e38acSHans Petter Selasky &eqe->data.vport_change; 288dc7e38acSHans Petter Selasky u16 vport_num = be16_to_cpu(vc_eqe->vport_num); 289dc7e38acSHans Petter Selasky 290dc7e38acSHans Petter Selasky if (dev->event) 291dc7e38acSHans Petter Selasky dev->event(dev, 292dc7e38acSHans Petter Selasky MLX5_DEV_EVENT_VPORT_CHANGE, 293dc7e38acSHans Petter Selasky (unsigned long)vport_num); 294dc7e38acSHans Petter Selasky } 295dc7e38acSHans Petter Selasky break; 296dc7e38acSHans Petter Selasky 297dc7e38acSHans Petter Selasky default: 298dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n", 299dc7e38acSHans Petter Selasky eqe->type, eq->eqn); 300dc7e38acSHans Petter Selasky break; 301dc7e38acSHans Petter Selasky } 302dc7e38acSHans Petter Selasky 303dc7e38acSHans Petter Selasky ++eq->cons_index; 304dc7e38acSHans Petter Selasky eqes_found = 1; 305dc7e38acSHans Petter Selasky ++set_ci; 306dc7e38acSHans Petter Selasky 307dc7e38acSHans Petter Selasky /* The HCA will think the queue has overflowed if we 308dc7e38acSHans Petter Selasky * don't tell it we've been processing events. We 309dc7e38acSHans Petter Selasky * create our EQs with MLX5_NUM_SPARE_EQE extra 310dc7e38acSHans Petter Selasky * entries, so we must update our consumer index at 311dc7e38acSHans Petter Selasky * least that often. 312dc7e38acSHans Petter Selasky */ 313dc7e38acSHans Petter Selasky if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) { 314dc7e38acSHans Petter Selasky eq_update_ci(eq, 0); 315dc7e38acSHans Petter Selasky set_ci = 0; 316dc7e38acSHans Petter Selasky } 317dc7e38acSHans Petter Selasky } 318dc7e38acSHans Petter Selasky 319dc7e38acSHans Petter Selasky eq_update_ci(eq, 1); 320dc7e38acSHans Petter Selasky 321dc7e38acSHans Petter Selasky return eqes_found; 322dc7e38acSHans Petter Selasky } 323dc7e38acSHans Petter Selasky 324dc7e38acSHans Petter Selasky static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr) 325dc7e38acSHans Petter Selasky { 326dc7e38acSHans Petter Selasky struct mlx5_eq *eq = eq_ptr; 327dc7e38acSHans Petter Selasky struct mlx5_core_dev *dev = eq->dev; 328dc7e38acSHans Petter Selasky 329dc7e38acSHans Petter Selasky mlx5_eq_int(dev, eq); 330dc7e38acSHans Petter Selasky 331dc7e38acSHans Petter Selasky /* MSI-X vectors always belong to us */ 332dc7e38acSHans Petter Selasky return IRQ_HANDLED; 333dc7e38acSHans Petter Selasky } 334dc7e38acSHans Petter Selasky 335dc7e38acSHans Petter Selasky static void init_eq_buf(struct mlx5_eq *eq) 336dc7e38acSHans Petter Selasky { 337dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe; 338dc7e38acSHans Petter Selasky int i; 339dc7e38acSHans Petter Selasky 340dc7e38acSHans Petter Selasky for (i = 0; i < eq->nent; i++) { 341dc7e38acSHans Petter Selasky eqe = get_eqe(eq, i); 342dc7e38acSHans Petter Selasky eqe->owner = MLX5_EQE_OWNER_INIT_VAL; 343dc7e38acSHans Petter Selasky } 344dc7e38acSHans Petter Selasky } 345dc7e38acSHans Petter Selasky 346dc7e38acSHans Petter Selasky int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 347dc7e38acSHans Petter Selasky int nent, u64 mask, const char *name, struct mlx5_uar *uar) 348dc7e38acSHans Petter Selasky { 349dc7e38acSHans Petter Selasky struct mlx5_priv *priv = &dev->priv; 350dc7e38acSHans Petter Selasky struct mlx5_create_eq_mbox_in *in; 351dc7e38acSHans Petter Selasky struct mlx5_create_eq_mbox_out out; 352dc7e38acSHans Petter Selasky int err; 353dc7e38acSHans Petter Selasky int inlen; 354dc7e38acSHans Petter Selasky 355dc7e38acSHans Petter Selasky eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE); 356dc7e38acSHans Petter Selasky err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE, 357dc7e38acSHans Petter Selasky &eq->buf); 358dc7e38acSHans Petter Selasky if (err) 359dc7e38acSHans Petter Selasky return err; 360dc7e38acSHans Petter Selasky 361dc7e38acSHans Petter Selasky init_eq_buf(eq); 362dc7e38acSHans Petter Selasky 363dc7e38acSHans Petter Selasky inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages; 364dc7e38acSHans Petter Selasky in = mlx5_vzalloc(inlen); 365dc7e38acSHans Petter Selasky if (!in) { 366dc7e38acSHans Petter Selasky err = -ENOMEM; 367dc7e38acSHans Petter Selasky goto err_buf; 368dc7e38acSHans Petter Selasky } 369dc7e38acSHans Petter Selasky memset(&out, 0, sizeof(out)); 370dc7e38acSHans Petter Selasky 371dc7e38acSHans Petter Selasky mlx5_fill_page_array(&eq->buf, in->pas); 372dc7e38acSHans Petter Selasky 373dc7e38acSHans Petter Selasky in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ); 374dc7e38acSHans Petter Selasky in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index); 375dc7e38acSHans Petter Selasky in->ctx.intr = vecidx; 376dc7e38acSHans Petter Selasky in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT; 377dc7e38acSHans Petter Selasky in->events_mask = cpu_to_be64(mask); 378dc7e38acSHans Petter Selasky 379dc7e38acSHans Petter Selasky err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out)); 380dc7e38acSHans Petter Selasky if (err) 381dc7e38acSHans Petter Selasky goto err_in; 382dc7e38acSHans Petter Selasky 383dc7e38acSHans Petter Selasky if (out.hdr.status) { 384dc7e38acSHans Petter Selasky err = mlx5_cmd_status_to_err(&out.hdr); 385dc7e38acSHans Petter Selasky goto err_in; 386dc7e38acSHans Petter Selasky } 387dc7e38acSHans Petter Selasky 388dc7e38acSHans Petter Selasky eq->eqn = out.eq_number; 389dc7e38acSHans Petter Selasky eq->irqn = vecidx; 390dc7e38acSHans Petter Selasky eq->dev = dev; 391dc7e38acSHans Petter Selasky eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET; 392dc7e38acSHans Petter Selasky snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s", 393dc7e38acSHans Petter Selasky name, pci_name(dev->pdev)); 394dc7e38acSHans Petter Selasky err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0, 395dc7e38acSHans Petter Selasky priv->irq_info[vecidx].name, eq); 396dc7e38acSHans Petter Selasky if (err) 397dc7e38acSHans Petter Selasky goto err_eq; 398278ce1c9SHans Petter Selasky #ifdef RSS 399278ce1c9SHans Petter Selasky if (vecidx >= MLX5_EQ_VEC_COMP_BASE) { 400278ce1c9SHans Petter Selasky u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE; 401278ce1c9SHans Petter Selasky err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector, 402278ce1c9SHans Petter Selasky rss_getcpu(bucket % rss_getnumbuckets())); 403278ce1c9SHans Petter Selasky if (err) 404278ce1c9SHans Petter Selasky goto err_irq; 405278ce1c9SHans Petter Selasky } 406278ce1c9SHans Petter Selasky #else 407278ce1c9SHans Petter Selasky if (0) 408278ce1c9SHans Petter Selasky goto err_irq; 409278ce1c9SHans Petter Selasky #endif 410dc7e38acSHans Petter Selasky 411dc7e38acSHans Petter Selasky 412dc7e38acSHans Petter Selasky /* EQs are created in ARMED state 413dc7e38acSHans Petter Selasky */ 414dc7e38acSHans Petter Selasky eq_update_ci(eq, 1); 415dc7e38acSHans Petter Selasky 416dc7e38acSHans Petter Selasky kvfree(in); 417dc7e38acSHans Petter Selasky return 0; 418dc7e38acSHans Petter Selasky 419278ce1c9SHans Petter Selasky err_irq: 420278ce1c9SHans Petter Selasky free_irq(priv->msix_arr[vecidx].vector, eq); 421dc7e38acSHans Petter Selasky 422dc7e38acSHans Petter Selasky err_eq: 423dc7e38acSHans Petter Selasky mlx5_cmd_destroy_eq(dev, eq->eqn); 424dc7e38acSHans Petter Selasky 425dc7e38acSHans Petter Selasky err_in: 426dc7e38acSHans Petter Selasky kvfree(in); 427dc7e38acSHans Petter Selasky 428dc7e38acSHans Petter Selasky err_buf: 429dc7e38acSHans Petter Selasky mlx5_buf_free(dev, &eq->buf); 430dc7e38acSHans Petter Selasky return err; 431dc7e38acSHans Petter Selasky } 432dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_create_map_eq); 433dc7e38acSHans Petter Selasky 434dc7e38acSHans Petter Selasky int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 435dc7e38acSHans Petter Selasky { 436dc7e38acSHans Petter Selasky int err; 437dc7e38acSHans Petter Selasky 438dc7e38acSHans Petter Selasky free_irq(dev->priv.msix_arr[eq->irqn].vector, eq); 439dc7e38acSHans Petter Selasky err = mlx5_cmd_destroy_eq(dev, eq->eqn); 440dc7e38acSHans Petter Selasky if (err) 441dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n", 442dc7e38acSHans Petter Selasky eq->eqn); 443dc7e38acSHans Petter Selasky mlx5_buf_free(dev, &eq->buf); 444dc7e38acSHans Petter Selasky 445dc7e38acSHans Petter Selasky return err; 446dc7e38acSHans Petter Selasky } 447dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq); 448dc7e38acSHans Petter Selasky 449dc7e38acSHans Petter Selasky int mlx5_eq_init(struct mlx5_core_dev *dev) 450dc7e38acSHans Petter Selasky { 451dc7e38acSHans Petter Selasky int err; 452dc7e38acSHans Petter Selasky 453dc7e38acSHans Petter Selasky spin_lock_init(&dev->priv.eq_table.lock); 454dc7e38acSHans Petter Selasky 455dc7e38acSHans Petter Selasky err = 0; 456dc7e38acSHans Petter Selasky 457dc7e38acSHans Petter Selasky return err; 458dc7e38acSHans Petter Selasky } 459dc7e38acSHans Petter Selasky 460dc7e38acSHans Petter Selasky 461dc7e38acSHans Petter Selasky void mlx5_eq_cleanup(struct mlx5_core_dev *dev) 462dc7e38acSHans Petter Selasky { 463dc7e38acSHans Petter Selasky } 464dc7e38acSHans Petter Selasky 465dc7e38acSHans Petter Selasky int mlx5_start_eqs(struct mlx5_core_dev *dev) 466dc7e38acSHans Petter Selasky { 467dc7e38acSHans Petter Selasky struct mlx5_eq_table *table = &dev->priv.eq_table; 468dc7e38acSHans Petter Selasky u32 async_event_mask = MLX5_ASYNC_EVENT_MASK; 469dc7e38acSHans Petter Selasky int err; 470dc7e38acSHans Petter Selasky 471dc7e38acSHans Petter Selasky if (MLX5_CAP_GEN(dev, port_module_event)) 472dc7e38acSHans Petter Selasky async_event_mask |= (1ull << 473dc7e38acSHans Petter Selasky MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT); 474dc7e38acSHans Petter Selasky 47598a998d5SHans Petter Selasky if (MLX5_CAP_GEN(dev, nic_vport_change_event)) 47698a998d5SHans Petter Selasky async_event_mask |= (1ull << 47798a998d5SHans Petter Selasky MLX5_EVENT_TYPE_NIC_VPORT_CHANGE); 47898a998d5SHans Petter Selasky 479dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, 480dc7e38acSHans Petter Selasky MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, 481dc7e38acSHans Petter Selasky "mlx5_cmd_eq", &dev->priv.uuari.uars[0]); 482dc7e38acSHans Petter Selasky if (err) { 483dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err); 484dc7e38acSHans Petter Selasky return err; 485dc7e38acSHans Petter Selasky } 486dc7e38acSHans Petter Selasky 487dc7e38acSHans Petter Selasky mlx5_cmd_use_events(dev); 488dc7e38acSHans Petter Selasky 489dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC, 490dc7e38acSHans Petter Selasky MLX5_NUM_ASYNC_EQE, async_event_mask, 491dc7e38acSHans Petter Selasky "mlx5_async_eq", &dev->priv.uuari.uars[0]); 492dc7e38acSHans Petter Selasky if (err) { 493dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create async EQ %d\n", err); 494dc7e38acSHans Petter Selasky goto err1; 495dc7e38acSHans Petter Selasky } 496dc7e38acSHans Petter Selasky 497dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->pages_eq, 498dc7e38acSHans Petter Selasky MLX5_EQ_VEC_PAGES, 499dc7e38acSHans Petter Selasky /* TODO: sriov max_vf + */ 1, 500dc7e38acSHans Petter Selasky 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq", 501dc7e38acSHans Petter Selasky &dev->priv.uuari.uars[0]); 502dc7e38acSHans Petter Selasky if (err) { 503dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create pages EQ %d\n", err); 504dc7e38acSHans Petter Selasky goto err2; 505dc7e38acSHans Petter Selasky } 506dc7e38acSHans Petter Selasky 507dc7e38acSHans Petter Selasky return err; 508dc7e38acSHans Petter Selasky 509dc7e38acSHans Petter Selasky err2: 510dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->async_eq); 511dc7e38acSHans Petter Selasky 512dc7e38acSHans Petter Selasky err1: 513dc7e38acSHans Petter Selasky mlx5_cmd_use_polling(dev); 514dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 515dc7e38acSHans Petter Selasky return err; 516dc7e38acSHans Petter Selasky } 517dc7e38acSHans Petter Selasky 518dc7e38acSHans Petter Selasky int mlx5_stop_eqs(struct mlx5_core_dev *dev) 519dc7e38acSHans Petter Selasky { 520dc7e38acSHans Petter Selasky struct mlx5_eq_table *table = &dev->priv.eq_table; 521dc7e38acSHans Petter Selasky int err; 522dc7e38acSHans Petter Selasky 523dc7e38acSHans Petter Selasky err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); 524dc7e38acSHans Petter Selasky if (err) 525dc7e38acSHans Petter Selasky return err; 526dc7e38acSHans Petter Selasky 527dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->async_eq); 528dc7e38acSHans Petter Selasky mlx5_cmd_use_polling(dev); 529dc7e38acSHans Petter Selasky 530dc7e38acSHans Petter Selasky err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 531dc7e38acSHans Petter Selasky if (err) 532dc7e38acSHans Petter Selasky mlx5_cmd_use_events(dev); 533dc7e38acSHans Petter Selasky 534dc7e38acSHans Petter Selasky return err; 535dc7e38acSHans Petter Selasky } 536dc7e38acSHans Petter Selasky 537dc7e38acSHans Petter Selasky int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 538dc7e38acSHans Petter Selasky struct mlx5_query_eq_mbox_out *out, int outlen) 539dc7e38acSHans Petter Selasky { 540dc7e38acSHans Petter Selasky struct mlx5_query_eq_mbox_in in; 541dc7e38acSHans Petter Selasky int err; 542dc7e38acSHans Petter Selasky 543dc7e38acSHans Petter Selasky memset(&in, 0, sizeof(in)); 544dc7e38acSHans Petter Selasky memset(out, 0, outlen); 545dc7e38acSHans Petter Selasky in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ); 546dc7e38acSHans Petter Selasky in.eqn = eq->eqn; 547dc7e38acSHans Petter Selasky err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen); 548dc7e38acSHans Petter Selasky if (err) 549dc7e38acSHans Petter Selasky return err; 550dc7e38acSHans Petter Selasky 551dc7e38acSHans Petter Selasky if (out->hdr.status) 552dc7e38acSHans Petter Selasky err = mlx5_cmd_status_to_err(&out->hdr); 553dc7e38acSHans Petter Selasky 554dc7e38acSHans Petter Selasky return err; 555dc7e38acSHans Petter Selasky } 556dc7e38acSHans Petter Selasky 557dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_core_eq_query); 558dc7e38acSHans Petter Selasky 559dc7e38acSHans Petter Selasky static const char *mlx5_port_module_event_error_type_to_string(u8 error_type) 560dc7e38acSHans Petter Selasky { 561dc7e38acSHans Petter Selasky switch (error_type) { 562dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED: 563dc7e38acSHans Petter Selasky return "Power Budget Exceeded"; 564dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE: 565dc7e38acSHans Petter Selasky return "Long Range for non MLNX cable/module"; 566dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_BUS_STUCK: 567dc7e38acSHans Petter Selasky return "Bus stuck(I2C or data shorted)"; 568dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT: 569dc7e38acSHans Petter Selasky return "No EEPROM/retry timeout"; 570dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST: 571dc7e38acSHans Petter Selasky return "Enforce part number list"; 572dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER: 573dc7e38acSHans Petter Selasky return "Unknown identifier"; 574dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE: 575dc7e38acSHans Petter Selasky return "High Temperature"; 576dc7e38acSHans Petter Selasky 577dc7e38acSHans Petter Selasky default: 578dc7e38acSHans Petter Selasky return "Unknown error type"; 579dc7e38acSHans Petter Selasky } 580dc7e38acSHans Petter Selasky } 581dc7e38acSHans Petter Selasky 582dc7e38acSHans Petter Selasky static void mlx5_port_module_event(struct mlx5_core_dev *dev, 583dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe) 584dc7e38acSHans Petter Selasky { 585dc7e38acSHans Petter Selasky unsigned int module_num; 586dc7e38acSHans Petter Selasky unsigned int module_status; 587dc7e38acSHans Petter Selasky unsigned int error_type; 588dc7e38acSHans Petter Selasky struct mlx5_eqe_port_module_event *module_event_eqe; 589dc7e38acSHans Petter Selasky struct pci_dev *pdev = dev->pdev; 590dc7e38acSHans Petter Selasky 591dc7e38acSHans Petter Selasky module_event_eqe = &eqe->data.port_module_event; 592dc7e38acSHans Petter Selasky 593dc7e38acSHans Petter Selasky module_num = (unsigned int)module_event_eqe->module; 594dc7e38acSHans Petter Selasky module_status = (unsigned int)module_event_eqe->module_status & 595dc7e38acSHans Petter Selasky PORT_MODULE_EVENT_MODULE_STATUS_MASK; 596dc7e38acSHans Petter Selasky error_type = (unsigned int)module_event_eqe->error_type & 597dc7e38acSHans Petter Selasky PORT_MODULE_EVENT_ERROR_TYPE_MASK; 598dc7e38acSHans Petter Selasky 599dc7e38acSHans Petter Selasky switch (module_status) { 600dc7e38acSHans Petter Selasky case MLX5_MODULE_STATUS_PLUGGED: 601dc7e38acSHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged", module_num); 602dc7e38acSHans Petter Selasky break; 603dc7e38acSHans Petter Selasky 604dc7e38acSHans Petter Selasky case MLX5_MODULE_STATUS_UNPLUGGED: 605dc7e38acSHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged", module_num); 606dc7e38acSHans Petter Selasky break; 607dc7e38acSHans Petter Selasky 608dc7e38acSHans Petter Selasky case MLX5_MODULE_STATUS_ERROR: 609dc7e38acSHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s", module_num, mlx5_port_module_event_error_type_to_string(error_type)); 610dc7e38acSHans Petter Selasky break; 611dc7e38acSHans Petter Selasky 612dc7e38acSHans Petter Selasky default: 613dc7e38acSHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status", module_num); 614dc7e38acSHans Petter Selasky } 615dc7e38acSHans Petter Selasky } 616dc7e38acSHans Petter Selasky 617