1dc7e38acSHans Petter Selasky /*- 26c7057f7SHans Petter Selasky * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3dc7e38acSHans Petter Selasky * 4dc7e38acSHans Petter Selasky * Redistribution and use in source and binary forms, with or without 5dc7e38acSHans Petter Selasky * modification, are permitted provided that the following conditions 6dc7e38acSHans Petter Selasky * are met: 7dc7e38acSHans Petter Selasky * 1. Redistributions of source code must retain the above copyright 8dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer. 9dc7e38acSHans Petter Selasky * 2. Redistributions in binary form must reproduce the above copyright 10dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer in the 11dc7e38acSHans Petter Selasky * documentation and/or other materials provided with the distribution. 12dc7e38acSHans Petter Selasky * 13dc7e38acSHans Petter Selasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14dc7e38acSHans Petter Selasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15dc7e38acSHans Petter Selasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16dc7e38acSHans Petter Selasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17dc7e38acSHans Petter Selasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18dc7e38acSHans Petter Selasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19dc7e38acSHans Petter Selasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20dc7e38acSHans Petter Selasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21dc7e38acSHans Petter Selasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22dc7e38acSHans Petter Selasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23dc7e38acSHans Petter Selasky * SUCH DAMAGE. 24dc7e38acSHans Petter Selasky * 25dc7e38acSHans Petter Selasky * $FreeBSD$ 26dc7e38acSHans Petter Selasky */ 27dc7e38acSHans Petter Selasky 28dc7e38acSHans Petter Selasky #include <linux/interrupt.h> 29dc7e38acSHans Petter Selasky #include <linux/module.h> 30d9142151SHans Petter Selasky #include <dev/mlx5/port.h> 31dc7e38acSHans Petter Selasky #include <dev/mlx5/mlx5_ifc.h> 32e5eae1dcSHans Petter Selasky #include <dev/mlx5/mlx5_fpga/core.h> 33dc7e38acSHans Petter Selasky #include "mlx5_core.h" 34dc7e38acSHans Petter Selasky 35278ce1c9SHans Petter Selasky #include "opt_rss.h" 36278ce1c9SHans Petter Selasky 37278ce1c9SHans Petter Selasky #ifdef RSS 38278ce1c9SHans Petter Selasky #include <net/rss_config.h> 39278ce1c9SHans Petter Selasky #include <netinet/in_rss.h> 40278ce1c9SHans Petter Selasky #endif 41278ce1c9SHans Petter Selasky 42dc7e38acSHans Petter Selasky enum { 43dc7e38acSHans Petter Selasky MLX5_EQE_SIZE = sizeof(struct mlx5_eqe), 44dc7e38acSHans Petter Selasky MLX5_EQE_OWNER_INIT_VAL = 0x1, 45dc7e38acSHans Petter Selasky }; 46dc7e38acSHans Petter Selasky 47dc7e38acSHans Petter Selasky enum { 48dc7e38acSHans Petter Selasky MLX5_NUM_SPARE_EQE = 0x80, 49dc7e38acSHans Petter Selasky MLX5_NUM_ASYNC_EQE = 0x100, 50dc7e38acSHans Petter Selasky MLX5_NUM_CMD_EQE = 32, 51dc7e38acSHans Petter Selasky }; 52dc7e38acSHans Petter Selasky 53dc7e38acSHans Petter Selasky enum { 54dc7e38acSHans Petter Selasky MLX5_EQ_DOORBEL_OFFSET = 0x40, 55dc7e38acSHans Petter Selasky }; 56dc7e38acSHans Petter Selasky 57dc7e38acSHans Petter Selasky #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \ 58dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_COMM_EST) | \ 59dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \ 60dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \ 61dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \ 62dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \ 63dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 64dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 65dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \ 66dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 67dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \ 68dc7e38acSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT)) 69dc7e38acSHans Petter Selasky 70dc7e38acSHans Petter Selasky struct map_eq_in { 71dc7e38acSHans Petter Selasky u64 mask; 72dc7e38acSHans Petter Selasky u32 reserved; 73dc7e38acSHans Petter Selasky u32 unmap_eqn; 74dc7e38acSHans Petter Selasky }; 75dc7e38acSHans Petter Selasky 76dc7e38acSHans Petter Selasky struct cre_des_eq { 77dc7e38acSHans Petter Selasky u8 reserved[15]; 78dc7e38acSHans Petter Selasky u8 eqn; 79dc7e38acSHans Petter Selasky }; 80dc7e38acSHans Petter Selasky 81dc7e38acSHans Petter Selasky /*Function prototype*/ 82dc7e38acSHans Petter Selasky static void mlx5_port_module_event(struct mlx5_core_dev *dev, 83dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe); 846c7057f7SHans Petter Selasky static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 856c7057f7SHans Petter Selasky struct mlx5_eqe *eqe); 86dc7e38acSHans Petter Selasky 87dc7e38acSHans Petter Selasky static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn) 88dc7e38acSHans Petter Selasky { 89788333d9SHans Petter Selasky u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0}; 90788333d9SHans Petter Selasky u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0}; 91dc7e38acSHans Petter Selasky 92dc7e38acSHans Petter Selasky MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ); 93dc7e38acSHans Petter Selasky MLX5_SET(destroy_eq_in, in, eq_number, eqn); 94dc7e38acSHans Petter Selasky 95788333d9SHans Petter Selasky return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 96dc7e38acSHans Petter Selasky } 97dc7e38acSHans Petter Selasky 98dc7e38acSHans Petter Selasky static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) 99dc7e38acSHans Petter Selasky { 100dc7e38acSHans Petter Selasky return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE); 101dc7e38acSHans Petter Selasky } 102dc7e38acSHans Petter Selasky 103dc7e38acSHans Petter Selasky static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) 104dc7e38acSHans Petter Selasky { 105dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1)); 106dc7e38acSHans Petter Selasky 107dc7e38acSHans Petter Selasky return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe; 108dc7e38acSHans Petter Selasky } 109dc7e38acSHans Petter Selasky 110dc7e38acSHans Petter Selasky static const char *eqe_type_str(u8 type) 111dc7e38acSHans Petter Selasky { 112dc7e38acSHans Petter Selasky switch (type) { 113dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMP: 114dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_COMP"; 115dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG: 116dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PATH_MIG"; 117dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMM_EST: 118dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_COMM_EST"; 119dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SQ_DRAINED: 120dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SQ_DRAINED"; 121dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 122dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_LAST_WQE"; 123dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 124dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT"; 125dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CQ_ERROR: 126dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_CQ_ERROR"; 127dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 128dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR"; 129dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 130dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PATH_MIG_FAILED"; 131dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 132dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR"; 133dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 134dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR"; 135dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 136dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR"; 137dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_INTERNAL_ERROR: 138dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_INTERNAL_ERROR"; 139dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PORT_CHANGE: 140dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PORT_CHANGE"; 141dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_GPIO_EVENT: 142dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_GPIO_EVENT"; 143dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 144dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT"; 145983026eaSHans Petter Selasky case MLX5_EVENT_TYPE_TEMP_WARN_EVENT: 146983026eaSHans Petter Selasky return "MLX5_EVENT_TYPE_TEMP_WARN_EVENT"; 147dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_REMOTE_CONFIG: 148dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_REMOTE_CONFIG"; 149dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_DB_BF_CONGESTION: 150dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_DB_BF_CONGESTION"; 151dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_STALL_EVENT: 152dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_STALL_EVENT"; 153dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CMD: 154dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_CMD"; 155dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PAGE_REQUEST: 156dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_PAGE_REQUEST"; 157dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 158dc7e38acSHans Petter Selasky return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE"; 159e5eae1dcSHans Petter Selasky case MLX5_EVENT_TYPE_FPGA_ERROR: 160e5eae1dcSHans Petter Selasky return "MLX5_EVENT_TYPE_FPGA_ERROR"; 161e5eae1dcSHans Petter Selasky case MLX5_EVENT_TYPE_FPGA_QP_ERROR: 162e5eae1dcSHans Petter Selasky return "MLX5_EVENT_TYPE_FPGA_QP_ERROR"; 163cb4e4a6eSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 164cb4e4a6eSHans Petter Selasky return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT"; 1656c7057f7SHans Petter Selasky case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 1666c7057f7SHans Petter Selasky return "MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT"; 167dc7e38acSHans Petter Selasky default: 168dc7e38acSHans Petter Selasky return "Unrecognized event"; 169dc7e38acSHans Petter Selasky } 170dc7e38acSHans Petter Selasky } 171dc7e38acSHans Petter Selasky 172dc7e38acSHans Petter Selasky static enum mlx5_dev_event port_subtype_event(u8 subtype) 173dc7e38acSHans Petter Selasky { 174dc7e38acSHans Petter Selasky switch (subtype) { 175dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 176dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_DOWN; 177dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 178dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_UP; 179dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 180dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PORT_INITIALIZED; 181dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_LID: 182dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_LID_CHANGE; 183dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 184dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_PKEY_CHANGE; 185dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_GUID: 186dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_GUID_CHANGE; 187dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 188dc7e38acSHans Petter Selasky return MLX5_DEV_EVENT_CLIENT_REREG; 189dc7e38acSHans Petter Selasky } 190dc7e38acSHans Petter Selasky return -1; 191dc7e38acSHans Petter Selasky } 192dc7e38acSHans Petter Selasky 193cb4e4a6eSHans Petter Selasky static enum mlx5_dev_event dcbx_subevent(u8 subtype) 194cb4e4a6eSHans Petter Selasky { 195cb4e4a6eSHans Petter Selasky switch (subtype) { 196cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 197cb4e4a6eSHans Petter Selasky return MLX5_DEV_EVENT_ERROR_STATE_DCBX; 198cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 199cb4e4a6eSHans Petter Selasky return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE; 200cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 201cb4e4a6eSHans Petter Selasky return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE; 202cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 203cb4e4a6eSHans Petter Selasky return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE; 204cb4e4a6eSHans Petter Selasky } 205cb4e4a6eSHans Petter Selasky return -1; 206cb4e4a6eSHans Petter Selasky } 207cb4e4a6eSHans Petter Selasky 208dc7e38acSHans Petter Selasky static void eq_update_ci(struct mlx5_eq *eq, int arm) 209dc7e38acSHans Petter Selasky { 210dc7e38acSHans Petter Selasky __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); 211dc7e38acSHans Petter Selasky u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); 212dc7e38acSHans Petter Selasky __raw_writel((__force u32) cpu_to_be32(val), addr); 213dc7e38acSHans Petter Selasky /* We still want ordering, just not swabbing, so add a barrier */ 214dc7e38acSHans Petter Selasky mb(); 215dc7e38acSHans Petter Selasky } 216dc7e38acSHans Petter Selasky 217983026eaSHans Petter Selasky static void 218983026eaSHans Petter Selasky mlx5_temp_warning_event(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe) 219983026eaSHans Petter Selasky { 220983026eaSHans Petter Selasky 221983026eaSHans Petter Selasky mlx5_core_warn(dev, 222983026eaSHans Petter Selasky "High temperature on sensors with bit set %#jx %#jx", 223983026eaSHans Petter Selasky (uintmax_t)be64_to_cpu(eqe->data.temp_warning.sensor_warning_msb), 224983026eaSHans Petter Selasky (uintmax_t)be64_to_cpu(eqe->data.temp_warning.sensor_warning_lsb)); 225983026eaSHans Petter Selasky } 226983026eaSHans Petter Selasky 227dc7e38acSHans Petter Selasky static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 228dc7e38acSHans Petter Selasky { 229dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe; 230dc7e38acSHans Petter Selasky int eqes_found = 0; 231dc7e38acSHans Petter Selasky int set_ci = 0; 232dc7e38acSHans Petter Selasky u32 cqn; 233dc7e38acSHans Petter Selasky u32 rsn; 234dc7e38acSHans Petter Selasky u8 port; 235dc7e38acSHans Petter Selasky 236dc7e38acSHans Petter Selasky while ((eqe = next_eqe_sw(eq))) { 237dc7e38acSHans Petter Selasky /* 238dc7e38acSHans Petter Selasky * Make sure we read EQ entry contents after we've 239dc7e38acSHans Petter Selasky * checked the ownership bit. 240dc7e38acSHans Petter Selasky */ 241dc7e38acSHans Petter Selasky rmb(); 242dc7e38acSHans Petter Selasky 243dc7e38acSHans Petter Selasky mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", 244dc7e38acSHans Petter Selasky eq->eqn, eqe_type_str(eqe->type)); 245dc7e38acSHans Petter Selasky switch (eqe->type) { 246dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMP: 247dc7e38acSHans Petter Selasky cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; 248dc7e38acSHans Petter Selasky mlx5_cq_completion(dev, cqn); 249dc7e38acSHans Petter Selasky break; 250dc7e38acSHans Petter Selasky 251dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG: 252dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_COMM_EST: 253dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SQ_DRAINED: 254dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 255dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 256dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 257dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 258dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 259dc7e38acSHans Petter Selasky rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 260dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n", 261dc7e38acSHans Petter Selasky eqe_type_str(eqe->type), eqe->type, rsn); 262dc7e38acSHans Petter Selasky mlx5_rsc_event(dev, rsn, eqe->type); 263dc7e38acSHans Petter Selasky break; 264dc7e38acSHans Petter Selasky 265dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 266dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 267dc7e38acSHans Petter Selasky rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 268dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n", 269dc7e38acSHans Petter Selasky eqe_type_str(eqe->type), eqe->type, rsn); 270dc7e38acSHans Petter Selasky mlx5_srq_event(dev, rsn, eqe->type); 271dc7e38acSHans Petter Selasky break; 272dc7e38acSHans Petter Selasky 273dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CMD: 274721a1a6aSSlava Shwartsman if (dev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 275721a1a6aSSlava Shwartsman mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), 276721a1a6aSSlava Shwartsman MLX5_CMD_MODE_EVENTS); 277721a1a6aSSlava Shwartsman } 278dc7e38acSHans Petter Selasky break; 279dc7e38acSHans Petter Selasky 280dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PORT_CHANGE: 281dc7e38acSHans Petter Selasky port = (eqe->data.port.port >> 4) & 0xf; 282dc7e38acSHans Petter Selasky switch (eqe->sub_type) { 283dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 284dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 285dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_LID: 286dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 287dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_GUID: 288dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 289dc7e38acSHans Petter Selasky case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 290dc7e38acSHans Petter Selasky if (dev->event) 291dc7e38acSHans Petter Selasky dev->event(dev, port_subtype_event(eqe->sub_type), 292dc7e38acSHans Petter Selasky (unsigned long)port); 293dc7e38acSHans Petter Selasky break; 294dc7e38acSHans Petter Selasky default: 295dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n", 296dc7e38acSHans Petter Selasky port, eqe->sub_type); 297dc7e38acSHans Petter Selasky } 298dc7e38acSHans Petter Selasky break; 299cb4e4a6eSHans Petter Selasky 300cb4e4a6eSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 301cb4e4a6eSHans Petter Selasky port = (eqe->data.port.port >> 4) & 0xf; 302cb4e4a6eSHans Petter Selasky switch (eqe->sub_type) { 303cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 304cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 305cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 306cb4e4a6eSHans Petter Selasky case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 307cb4e4a6eSHans Petter Selasky if (dev->event) 308cb4e4a6eSHans Petter Selasky dev->event(dev, 309cb4e4a6eSHans Petter Selasky dcbx_subevent(eqe->sub_type), 310cb4e4a6eSHans Petter Selasky 0); 311cb4e4a6eSHans Petter Selasky break; 312cb4e4a6eSHans Petter Selasky default: 313cb4e4a6eSHans Petter Selasky mlx5_core_warn(dev, 314cb4e4a6eSHans Petter Selasky "dcbx event with unrecognized subtype: port %d, sub_type %d\n", 315cb4e4a6eSHans Petter Selasky port, eqe->sub_type); 316cb4e4a6eSHans Petter Selasky } 317cb4e4a6eSHans Petter Selasky break; 318cb4e4a6eSHans Petter Selasky 3196c7057f7SHans Petter Selasky case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 3206c7057f7SHans Petter Selasky mlx5_port_general_notification_event(dev, eqe); 3216c7057f7SHans Petter Selasky break; 3226c7057f7SHans Petter Selasky 323dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CQ_ERROR: 324dc7e38acSHans Petter Selasky cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 325dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n", 326dc7e38acSHans Petter Selasky cqn, eqe->data.cq_err.syndrome); 327dc7e38acSHans Petter Selasky mlx5_cq_event(dev, cqn, eqe->type); 328dc7e38acSHans Petter Selasky break; 329dc7e38acSHans Petter Selasky 330dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_PAGE_REQUEST: 331dc7e38acSHans Petter Selasky { 332dc7e38acSHans Petter Selasky u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id); 333dc7e38acSHans Petter Selasky s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages); 334dc7e38acSHans Petter Selasky 335dc7e38acSHans Petter Selasky mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n", 336dc7e38acSHans Petter Selasky func_id, npages); 337dc7e38acSHans Petter Selasky mlx5_core_req_pages_handler(dev, func_id, npages); 338dc7e38acSHans Petter Selasky } 339dc7e38acSHans Petter Selasky break; 340dc7e38acSHans Petter Selasky 341dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 342dc7e38acSHans Petter Selasky mlx5_port_module_event(dev, eqe); 343dc7e38acSHans Petter Selasky break; 344dc7e38acSHans Petter Selasky 345dc7e38acSHans Petter Selasky case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 346dc7e38acSHans Petter Selasky { 347dc7e38acSHans Petter Selasky struct mlx5_eqe_vport_change *vc_eqe = 348dc7e38acSHans Petter Selasky &eqe->data.vport_change; 349dc7e38acSHans Petter Selasky u16 vport_num = be16_to_cpu(vc_eqe->vport_num); 350dc7e38acSHans Petter Selasky 351dc7e38acSHans Petter Selasky if (dev->event) 352dc7e38acSHans Petter Selasky dev->event(dev, 353dc7e38acSHans Petter Selasky MLX5_DEV_EVENT_VPORT_CHANGE, 354dc7e38acSHans Petter Selasky (unsigned long)vport_num); 355dc7e38acSHans Petter Selasky } 356dc7e38acSHans Petter Selasky break; 357dc7e38acSHans Petter Selasky 358e5eae1dcSHans Petter Selasky case MLX5_EVENT_TYPE_FPGA_ERROR: 359e5eae1dcSHans Petter Selasky case MLX5_EVENT_TYPE_FPGA_QP_ERROR: 360e5eae1dcSHans Petter Selasky mlx5_fpga_event(dev, eqe->type, &eqe->data.raw); 361e5eae1dcSHans Petter Selasky break; 362983026eaSHans Petter Selasky case MLX5_EVENT_TYPE_TEMP_WARN_EVENT: 363983026eaSHans Petter Selasky mlx5_temp_warning_event(dev, eqe); 364983026eaSHans Petter Selasky break; 365e5eae1dcSHans Petter Selasky 366dc7e38acSHans Petter Selasky default: 367dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n", 368dc7e38acSHans Petter Selasky eqe->type, eq->eqn); 369dc7e38acSHans Petter Selasky break; 370dc7e38acSHans Petter Selasky } 371dc7e38acSHans Petter Selasky 372dc7e38acSHans Petter Selasky ++eq->cons_index; 373dc7e38acSHans Petter Selasky eqes_found = 1; 374dc7e38acSHans Petter Selasky ++set_ci; 375dc7e38acSHans Petter Selasky 376dc7e38acSHans Petter Selasky /* The HCA will think the queue has overflowed if we 377dc7e38acSHans Petter Selasky * don't tell it we've been processing events. We 378dc7e38acSHans Petter Selasky * create our EQs with MLX5_NUM_SPARE_EQE extra 379dc7e38acSHans Petter Selasky * entries, so we must update our consumer index at 380dc7e38acSHans Petter Selasky * least that often. 381dc7e38acSHans Petter Selasky */ 382dc7e38acSHans Petter Selasky if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) { 383dc7e38acSHans Petter Selasky eq_update_ci(eq, 0); 384dc7e38acSHans Petter Selasky set_ci = 0; 385dc7e38acSHans Petter Selasky } 386dc7e38acSHans Petter Selasky } 387dc7e38acSHans Petter Selasky 388dc7e38acSHans Petter Selasky eq_update_ci(eq, 1); 389dc7e38acSHans Petter Selasky 390dc7e38acSHans Petter Selasky return eqes_found; 391dc7e38acSHans Petter Selasky } 392dc7e38acSHans Petter Selasky 393dc7e38acSHans Petter Selasky static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr) 394dc7e38acSHans Petter Selasky { 395dc7e38acSHans Petter Selasky struct mlx5_eq *eq = eq_ptr; 396dc7e38acSHans Petter Selasky struct mlx5_core_dev *dev = eq->dev; 397dc7e38acSHans Petter Selasky 398192fc18dSHans Petter Selasky /* check if IRQs are not disabled */ 399192fc18dSHans Petter Selasky if (likely(dev->priv.disable_irqs == 0)) 400dc7e38acSHans Petter Selasky mlx5_eq_int(dev, eq); 401dc7e38acSHans Petter Selasky 402dc7e38acSHans Petter Selasky /* MSI-X vectors always belong to us */ 403dc7e38acSHans Petter Selasky return IRQ_HANDLED; 404dc7e38acSHans Petter Selasky } 405dc7e38acSHans Petter Selasky 406dc7e38acSHans Petter Selasky static void init_eq_buf(struct mlx5_eq *eq) 407dc7e38acSHans Petter Selasky { 408dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe; 409dc7e38acSHans Petter Selasky int i; 410dc7e38acSHans Petter Selasky 411dc7e38acSHans Petter Selasky for (i = 0; i < eq->nent; i++) { 412dc7e38acSHans Petter Selasky eqe = get_eqe(eq, i); 413dc7e38acSHans Petter Selasky eqe->owner = MLX5_EQE_OWNER_INIT_VAL; 414dc7e38acSHans Petter Selasky } 415dc7e38acSHans Petter Selasky } 416dc7e38acSHans Petter Selasky 417dc7e38acSHans Petter Selasky int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 418dc7e38acSHans Petter Selasky int nent, u64 mask, const char *name, struct mlx5_uar *uar) 419dc7e38acSHans Petter Selasky { 420788333d9SHans Petter Selasky u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0}; 421dc7e38acSHans Petter Selasky struct mlx5_priv *priv = &dev->priv; 422788333d9SHans Petter Selasky __be64 *pas; 423788333d9SHans Petter Selasky void *eqc; 424dc7e38acSHans Petter Selasky int inlen; 425788333d9SHans Petter Selasky u32 *in; 426788333d9SHans Petter Selasky int err; 427dc7e38acSHans Petter Selasky 428dc7e38acSHans Petter Selasky eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE); 429a2485fe5SHans Petter Selasky eq->cons_index = 0; 430dc7e38acSHans Petter Selasky err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE, 431dc7e38acSHans Petter Selasky &eq->buf); 432dc7e38acSHans Petter Selasky if (err) 433dc7e38acSHans Petter Selasky return err; 434dc7e38acSHans Petter Selasky 435dc7e38acSHans Petter Selasky init_eq_buf(eq); 436dc7e38acSHans Petter Selasky 437788333d9SHans Petter Selasky inlen = MLX5_ST_SZ_BYTES(create_eq_in) + 438788333d9SHans Petter Selasky MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages; 439dc7e38acSHans Petter Selasky in = mlx5_vzalloc(inlen); 440dc7e38acSHans Petter Selasky if (!in) { 441dc7e38acSHans Petter Selasky err = -ENOMEM; 442dc7e38acSHans Petter Selasky goto err_buf; 443dc7e38acSHans Petter Selasky } 444dc7e38acSHans Petter Selasky 445788333d9SHans Petter Selasky pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas); 446788333d9SHans Petter Selasky mlx5_fill_page_array(&eq->buf, pas); 447dc7e38acSHans Petter Selasky 448788333d9SHans Petter Selasky MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ); 449788333d9SHans Petter Selasky MLX5_SET64(create_eq_in, in, event_bitmask, mask); 450dc7e38acSHans Petter Selasky 451788333d9SHans Petter Selasky eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry); 452788333d9SHans Petter Selasky MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent)); 453788333d9SHans Petter Selasky MLX5_SET(eqc, eqc, uar_page, uar->index); 454788333d9SHans Petter Selasky MLX5_SET(eqc, eqc, intr, vecidx); 455788333d9SHans Petter Selasky MLX5_SET(eqc, eqc, log_page_size, 456788333d9SHans Petter Selasky eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 457788333d9SHans Petter Selasky 458788333d9SHans Petter Selasky err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out)); 459dc7e38acSHans Petter Selasky if (err) 460dc7e38acSHans Petter Selasky goto err_in; 461dc7e38acSHans Petter Selasky 462788333d9SHans Petter Selasky eq->eqn = MLX5_GET(create_eq_out, out, eq_number); 463dc7e38acSHans Petter Selasky eq->irqn = vecidx; 464dc7e38acSHans Petter Selasky eq->dev = dev; 465dc7e38acSHans Petter Selasky eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET; 466dc7e38acSHans Petter Selasky snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s", 467dc7e38acSHans Petter Selasky name, pci_name(dev->pdev)); 468dc7e38acSHans Petter Selasky err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0, 469dc7e38acSHans Petter Selasky priv->irq_info[vecidx].name, eq); 470dc7e38acSHans Petter Selasky if (err) 471dc7e38acSHans Petter Selasky goto err_eq; 472278ce1c9SHans Petter Selasky #ifdef RSS 473278ce1c9SHans Petter Selasky if (vecidx >= MLX5_EQ_VEC_COMP_BASE) { 474278ce1c9SHans Petter Selasky u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE; 475278ce1c9SHans Petter Selasky err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector, 476278ce1c9SHans Petter Selasky rss_getcpu(bucket % rss_getnumbuckets())); 477278ce1c9SHans Petter Selasky if (err) 478278ce1c9SHans Petter Selasky goto err_irq; 479278ce1c9SHans Petter Selasky } 480278ce1c9SHans Petter Selasky #else 481278ce1c9SHans Petter Selasky if (0) 482278ce1c9SHans Petter Selasky goto err_irq; 483278ce1c9SHans Petter Selasky #endif 484dc7e38acSHans Petter Selasky 485dc7e38acSHans Petter Selasky 486dc7e38acSHans Petter Selasky /* EQs are created in ARMED state 487dc7e38acSHans Petter Selasky */ 488dc7e38acSHans Petter Selasky eq_update_ci(eq, 1); 489dc7e38acSHans Petter Selasky 490dc7e38acSHans Petter Selasky kvfree(in); 491dc7e38acSHans Petter Selasky return 0; 492dc7e38acSHans Petter Selasky 493278ce1c9SHans Petter Selasky err_irq: 494278ce1c9SHans Petter Selasky free_irq(priv->msix_arr[vecidx].vector, eq); 495dc7e38acSHans Petter Selasky 496dc7e38acSHans Petter Selasky err_eq: 497dc7e38acSHans Petter Selasky mlx5_cmd_destroy_eq(dev, eq->eqn); 498dc7e38acSHans Petter Selasky 499dc7e38acSHans Petter Selasky err_in: 500dc7e38acSHans Petter Selasky kvfree(in); 501dc7e38acSHans Petter Selasky 502dc7e38acSHans Petter Selasky err_buf: 503dc7e38acSHans Petter Selasky mlx5_buf_free(dev, &eq->buf); 504dc7e38acSHans Petter Selasky return err; 505dc7e38acSHans Petter Selasky } 506dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_create_map_eq); 507dc7e38acSHans Petter Selasky 508dc7e38acSHans Petter Selasky int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 509dc7e38acSHans Petter Selasky { 510dc7e38acSHans Petter Selasky int err; 511dc7e38acSHans Petter Selasky 512dc7e38acSHans Petter Selasky free_irq(dev->priv.msix_arr[eq->irqn].vector, eq); 513dc7e38acSHans Petter Selasky err = mlx5_cmd_destroy_eq(dev, eq->eqn); 514dc7e38acSHans Petter Selasky if (err) 515dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n", 516dc7e38acSHans Petter Selasky eq->eqn); 517dc7e38acSHans Petter Selasky mlx5_buf_free(dev, &eq->buf); 518dc7e38acSHans Petter Selasky 519dc7e38acSHans Petter Selasky return err; 520dc7e38acSHans Petter Selasky } 521dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq); 522dc7e38acSHans Petter Selasky 523dc7e38acSHans Petter Selasky int mlx5_eq_init(struct mlx5_core_dev *dev) 524dc7e38acSHans Petter Selasky { 525dc7e38acSHans Petter Selasky int err; 526dc7e38acSHans Petter Selasky 527dc7e38acSHans Petter Selasky spin_lock_init(&dev->priv.eq_table.lock); 528dc7e38acSHans Petter Selasky 529dc7e38acSHans Petter Selasky err = 0; 530dc7e38acSHans Petter Selasky 531dc7e38acSHans Petter Selasky return err; 532dc7e38acSHans Petter Selasky } 533dc7e38acSHans Petter Selasky 534dc7e38acSHans Petter Selasky 535dc7e38acSHans Petter Selasky void mlx5_eq_cleanup(struct mlx5_core_dev *dev) 536dc7e38acSHans Petter Selasky { 537dc7e38acSHans Petter Selasky } 538dc7e38acSHans Petter Selasky 539dc7e38acSHans Petter Selasky int mlx5_start_eqs(struct mlx5_core_dev *dev) 540dc7e38acSHans Petter Selasky { 541dc7e38acSHans Petter Selasky struct mlx5_eq_table *table = &dev->priv.eq_table; 542a4d6b007SHans Petter Selasky u64 async_event_mask = MLX5_ASYNC_EVENT_MASK; 543dc7e38acSHans Petter Selasky int err; 544dc7e38acSHans Petter Selasky 545dc7e38acSHans Petter Selasky if (MLX5_CAP_GEN(dev, port_module_event)) 546dc7e38acSHans Petter Selasky async_event_mask |= (1ull << 547dc7e38acSHans Petter Selasky MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT); 548dc7e38acSHans Petter Selasky 54998a998d5SHans Petter Selasky if (MLX5_CAP_GEN(dev, nic_vport_change_event)) 55098a998d5SHans Petter Selasky async_event_mask |= (1ull << 55198a998d5SHans Petter Selasky MLX5_EVENT_TYPE_NIC_VPORT_CHANGE); 55298a998d5SHans Petter Selasky 553cb4e4a6eSHans Petter Selasky if (MLX5_CAP_GEN(dev, dcbx)) 554cb4e4a6eSHans Petter Selasky async_event_mask |= (1ull << 555cb4e4a6eSHans Petter Selasky MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT); 556cb4e4a6eSHans Petter Selasky 557e5eae1dcSHans Petter Selasky if (MLX5_CAP_GEN(dev, fpga)) 558e5eae1dcSHans Petter Selasky async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) | 559e5eae1dcSHans Petter Selasky (1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR); 560e5eae1dcSHans Petter Selasky 561983026eaSHans Petter Selasky if (MLX5_CAP_GEN(dev, temp_warn_event)) 562983026eaSHans Petter Selasky async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT); 563983026eaSHans Petter Selasky 564adb6fd50SHans Petter Selasky if (MLX5_CAP_GEN(dev, general_notification_event)) { 565adb6fd50SHans Petter Selasky async_event_mask |= (1ull << 566adb6fd50SHans Petter Selasky MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT); 567adb6fd50SHans Petter Selasky } 568adb6fd50SHans Petter Selasky 569dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, 570dc7e38acSHans Petter Selasky MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, 571dc7e38acSHans Petter Selasky "mlx5_cmd_eq", &dev->priv.uuari.uars[0]); 572dc7e38acSHans Petter Selasky if (err) { 573dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err); 574dc7e38acSHans Petter Selasky return err; 575dc7e38acSHans Petter Selasky } 576dc7e38acSHans Petter Selasky 577dc7e38acSHans Petter Selasky mlx5_cmd_use_events(dev); 578dc7e38acSHans Petter Selasky 579dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC, 580dc7e38acSHans Petter Selasky MLX5_NUM_ASYNC_EQE, async_event_mask, 581dc7e38acSHans Petter Selasky "mlx5_async_eq", &dev->priv.uuari.uars[0]); 582dc7e38acSHans Petter Selasky if (err) { 583dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create async EQ %d\n", err); 584dc7e38acSHans Petter Selasky goto err1; 585dc7e38acSHans Petter Selasky } 586dc7e38acSHans Petter Selasky 587dc7e38acSHans Petter Selasky err = mlx5_create_map_eq(dev, &table->pages_eq, 588dc7e38acSHans Petter Selasky MLX5_EQ_VEC_PAGES, 589dc7e38acSHans Petter Selasky /* TODO: sriov max_vf + */ 1, 590dc7e38acSHans Petter Selasky 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq", 591dc7e38acSHans Petter Selasky &dev->priv.uuari.uars[0]); 592dc7e38acSHans Petter Selasky if (err) { 593dc7e38acSHans Petter Selasky mlx5_core_warn(dev, "failed to create pages EQ %d\n", err); 594dc7e38acSHans Petter Selasky goto err2; 595dc7e38acSHans Petter Selasky } 596dc7e38acSHans Petter Selasky 597dc7e38acSHans Petter Selasky return err; 598dc7e38acSHans Petter Selasky 599dc7e38acSHans Petter Selasky err2: 600dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->async_eq); 601dc7e38acSHans Petter Selasky 602dc7e38acSHans Petter Selasky err1: 603dc7e38acSHans Petter Selasky mlx5_cmd_use_polling(dev); 604dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 605dc7e38acSHans Petter Selasky return err; 606dc7e38acSHans Petter Selasky } 607dc7e38acSHans Petter Selasky 608dc7e38acSHans Petter Selasky int mlx5_stop_eqs(struct mlx5_core_dev *dev) 609dc7e38acSHans Petter Selasky { 610dc7e38acSHans Petter Selasky struct mlx5_eq_table *table = &dev->priv.eq_table; 611dc7e38acSHans Petter Selasky int err; 612dc7e38acSHans Petter Selasky 613dc7e38acSHans Petter Selasky err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); 614dc7e38acSHans Petter Selasky if (err) 615dc7e38acSHans Petter Selasky return err; 616dc7e38acSHans Petter Selasky 617dc7e38acSHans Petter Selasky mlx5_destroy_unmap_eq(dev, &table->async_eq); 618dc7e38acSHans Petter Selasky mlx5_cmd_use_polling(dev); 619dc7e38acSHans Petter Selasky 620dc7e38acSHans Petter Selasky err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 621dc7e38acSHans Petter Selasky if (err) 622dc7e38acSHans Petter Selasky mlx5_cmd_use_events(dev); 623dc7e38acSHans Petter Selasky 624dc7e38acSHans Petter Selasky return err; 625dc7e38acSHans Petter Selasky } 626dc7e38acSHans Petter Selasky 627dc7e38acSHans Petter Selasky int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 628788333d9SHans Petter Selasky u32 *out, int outlen) 629dc7e38acSHans Petter Selasky { 630788333d9SHans Petter Selasky u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0}; 631dc7e38acSHans Petter Selasky 632dc7e38acSHans Petter Selasky memset(out, 0, outlen); 633788333d9SHans Petter Selasky MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ); 634788333d9SHans Petter Selasky MLX5_SET(query_eq_in, in, eq_number, eq->eqn); 635dc7e38acSHans Petter Selasky 636788333d9SHans Petter Selasky return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); 637dc7e38acSHans Petter Selasky } 638dc7e38acSHans Petter Selasky EXPORT_SYMBOL_GPL(mlx5_core_eq_query); 639dc7e38acSHans Petter Selasky 640dc7e38acSHans Petter Selasky static const char *mlx5_port_module_event_error_type_to_string(u8 error_type) 641dc7e38acSHans Petter Selasky { 642dc7e38acSHans Petter Selasky switch (error_type) { 643dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED: 644dc7e38acSHans Petter Selasky return "Power Budget Exceeded"; 645dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE: 646dc7e38acSHans Petter Selasky return "Long Range for non MLNX cable/module"; 647dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_BUS_STUCK: 648dc7e38acSHans Petter Selasky return "Bus stuck(I2C or data shorted)"; 649dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT: 650dc7e38acSHans Petter Selasky return "No EEPROM/retry timeout"; 651dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST: 652dc7e38acSHans Petter Selasky return "Enforce part number list"; 653ecb4fcc4SHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE: 654ecb4fcc4SHans Petter Selasky return "Unsupported Cable"; 655dc7e38acSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE: 656dc7e38acSHans Petter Selasky return "High Temperature"; 657cb4e4a6eSHans Petter Selasky case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED: 658cb4e4a6eSHans Petter Selasky return "Cable is shorted"; 6590c79f82cSSlava Shwartsman case MLX5_MODULE_EVENT_ERROR_PCIE_SYSTEM_POWER_SLOT_EXCEEDED: 6600c79f82cSSlava Shwartsman return "One or more network ports have been powered " 6610c79f82cSSlava Shwartsman "down due to insufficient/unadvertised power on " 6620c79f82cSSlava Shwartsman "the PCIe slot. Please refer to the card's user " 6630c79f82cSSlava Shwartsman "manual for power specifications or contact " 6640c79f82cSSlava Shwartsman "Mellanox support."; 665dc7e38acSHans Petter Selasky 666dc7e38acSHans Petter Selasky default: 667dc7e38acSHans Petter Selasky return "Unknown error type"; 668dc7e38acSHans Petter Selasky } 669dc7e38acSHans Petter Selasky } 670dc7e38acSHans Petter Selasky 67121dd6527SHans Petter Selasky unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num) 67221dd6527SHans Petter Selasky { 67321dd6527SHans Petter Selasky if (module_num < 0 || module_num >= MLX5_MAX_PORTS) 67421dd6527SHans Petter Selasky return 0; /* undefined */ 67521dd6527SHans Petter Selasky return dev->module_status[module_num]; 67621dd6527SHans Petter Selasky } 67721dd6527SHans Petter Selasky 678dc7e38acSHans Petter Selasky static void mlx5_port_module_event(struct mlx5_core_dev *dev, 679dc7e38acSHans Petter Selasky struct mlx5_eqe *eqe) 680dc7e38acSHans Petter Selasky { 681dc7e38acSHans Petter Selasky unsigned int module_num; 682dc7e38acSHans Petter Selasky unsigned int module_status; 683dc7e38acSHans Petter Selasky unsigned int error_type; 684dc7e38acSHans Petter Selasky struct mlx5_eqe_port_module_event *module_event_eqe; 685dc7e38acSHans Petter Selasky struct pci_dev *pdev = dev->pdev; 686dc7e38acSHans Petter Selasky 687dc7e38acSHans Petter Selasky module_event_eqe = &eqe->data.port_module_event; 688dc7e38acSHans Petter Selasky 689dc7e38acSHans Petter Selasky module_num = (unsigned int)module_event_eqe->module; 690dc7e38acSHans Petter Selasky module_status = (unsigned int)module_event_eqe->module_status & 691dc7e38acSHans Petter Selasky PORT_MODULE_EVENT_MODULE_STATUS_MASK; 692dc7e38acSHans Petter Selasky error_type = (unsigned int)module_event_eqe->error_type & 693dc7e38acSHans Petter Selasky PORT_MODULE_EVENT_ERROR_TYPE_MASK; 694dc7e38acSHans Petter Selasky 695dc7e38acSHans Petter Selasky switch (module_status) { 696ecb4fcc4SHans Petter Selasky case MLX5_MODULE_STATUS_PLUGGED_ENABLED: 697ecb4fcc4SHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged and enabled\n", module_num); 698dc7e38acSHans Petter Selasky break; 699dc7e38acSHans Petter Selasky 700dc7e38acSHans Petter Selasky case MLX5_MODULE_STATUS_UNPLUGGED: 701cb4e4a6eSHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged\n", module_num); 702dc7e38acSHans Petter Selasky break; 703dc7e38acSHans Petter Selasky 704dc7e38acSHans Petter Selasky case MLX5_MODULE_STATUS_ERROR: 705cb4e4a6eSHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s\n", module_num, mlx5_port_module_event_error_type_to_string(error_type)); 706dc7e38acSHans Petter Selasky break; 707dc7e38acSHans Petter Selasky 708ecb4fcc4SHans Petter Selasky case MLX5_MODULE_STATUS_PLUGGED_DISABLED: 709ecb4fcc4SHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged but disabled\n", module_num); 710ecb4fcc4SHans Petter Selasky break; 711ecb4fcc4SHans Petter Selasky 712dc7e38acSHans Petter Selasky default: 713cb4e4a6eSHans Petter Selasky device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status\n", module_num); 714dc7e38acSHans Petter Selasky } 71521dd6527SHans Petter Selasky /* store module status */ 71621dd6527SHans Petter Selasky if (module_num < MLX5_MAX_PORTS) 71721dd6527SHans Petter Selasky dev->module_status[module_num] = module_status; 718dc7e38acSHans Petter Selasky } 719dc7e38acSHans Petter Selasky 7206c7057f7SHans Petter Selasky static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 7216c7057f7SHans Petter Selasky struct mlx5_eqe *eqe) 7226c7057f7SHans Petter Selasky { 7236c7057f7SHans Petter Selasky u8 port = (eqe->data.port.port >> 4) & 0xf; 724adb6fd50SHans Petter Selasky u32 rqn; 725adb6fd50SHans Petter Selasky struct mlx5_eqe_general_notification_event *general_event; 7266c7057f7SHans Petter Selasky 7276c7057f7SHans Petter Selasky switch (eqe->sub_type) { 7286c7057f7SHans Petter Selasky case MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT: 7296c7057f7SHans Petter Selasky general_event = &eqe->data.general_notifications; 7306c7057f7SHans Petter Selasky rqn = be32_to_cpu(general_event->rq_user_index_delay_drop) & 7316c7057f7SHans Petter Selasky 0xffffff; 7326c7057f7SHans Petter Selasky break; 733adb6fd50SHans Petter Selasky case MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT: 734adb6fd50SHans Petter Selasky mlx5_trigger_health_watchdog(dev); 735adb6fd50SHans Petter Selasky break; 7366c7057f7SHans Petter Selasky default: 7376c7057f7SHans Petter Selasky mlx5_core_warn(dev, 7386c7057f7SHans Petter Selasky "general event with unrecognized subtype: port %d, sub_type %d\n", 7396c7057f7SHans Petter Selasky port, eqe->sub_type); 7406c7057f7SHans Petter Selasky break; 7416c7057f7SHans Petter Selasky } 7426c7057f7SHans Petter Selasky } 7436c7057f7SHans Petter Selasky 744