1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/interrupt.h> 29 #include <linux/module.h> 30 #include <dev/mlx5/port.h> 31 #include <dev/mlx5/mlx5_ifc.h> 32 #include "mlx5_core.h" 33 34 #include "opt_rss.h" 35 36 #ifdef RSS 37 #include <net/rss_config.h> 38 #include <netinet/in_rss.h> 39 #endif 40 41 enum { 42 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe), 43 MLX5_EQE_OWNER_INIT_VAL = 0x1, 44 }; 45 46 enum { 47 MLX5_NUM_SPARE_EQE = 0x80, 48 MLX5_NUM_ASYNC_EQE = 0x100, 49 MLX5_NUM_CMD_EQE = 32, 50 }; 51 52 enum { 53 MLX5_EQ_DOORBEL_OFFSET = 0x40, 54 }; 55 56 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \ 57 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \ 58 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \ 59 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \ 60 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \ 61 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \ 62 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 63 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 64 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \ 65 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 66 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \ 67 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT)) 68 69 struct map_eq_in { 70 u64 mask; 71 u32 reserved; 72 u32 unmap_eqn; 73 }; 74 75 struct cre_des_eq { 76 u8 reserved[15]; 77 u8 eqn; 78 }; 79 80 /*Function prototype*/ 81 static void mlx5_port_module_event(struct mlx5_core_dev *dev, 82 struct mlx5_eqe *eqe); 83 static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 84 struct mlx5_eqe *eqe); 85 86 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn) 87 { 88 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0}; 89 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0}; 90 91 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ); 92 MLX5_SET(destroy_eq_in, in, eq_number, eqn); 93 94 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 95 } 96 97 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) 98 { 99 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE); 100 } 101 102 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) 103 { 104 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1)); 105 106 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe; 107 } 108 109 static const char *eqe_type_str(u8 type) 110 { 111 switch (type) { 112 case MLX5_EVENT_TYPE_COMP: 113 return "MLX5_EVENT_TYPE_COMP"; 114 case MLX5_EVENT_TYPE_PATH_MIG: 115 return "MLX5_EVENT_TYPE_PATH_MIG"; 116 case MLX5_EVENT_TYPE_COMM_EST: 117 return "MLX5_EVENT_TYPE_COMM_EST"; 118 case MLX5_EVENT_TYPE_SQ_DRAINED: 119 return "MLX5_EVENT_TYPE_SQ_DRAINED"; 120 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 121 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE"; 122 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 123 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT"; 124 case MLX5_EVENT_TYPE_CQ_ERROR: 125 return "MLX5_EVENT_TYPE_CQ_ERROR"; 126 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 127 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR"; 128 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 129 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED"; 130 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 131 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR"; 132 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 133 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR"; 134 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 135 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR"; 136 case MLX5_EVENT_TYPE_INTERNAL_ERROR: 137 return "MLX5_EVENT_TYPE_INTERNAL_ERROR"; 138 case MLX5_EVENT_TYPE_PORT_CHANGE: 139 return "MLX5_EVENT_TYPE_PORT_CHANGE"; 140 case MLX5_EVENT_TYPE_GPIO_EVENT: 141 return "MLX5_EVENT_TYPE_GPIO_EVENT"; 142 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 143 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT"; 144 case MLX5_EVENT_TYPE_REMOTE_CONFIG: 145 return "MLX5_EVENT_TYPE_REMOTE_CONFIG"; 146 case MLX5_EVENT_TYPE_DB_BF_CONGESTION: 147 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION"; 148 case MLX5_EVENT_TYPE_STALL_EVENT: 149 return "MLX5_EVENT_TYPE_STALL_EVENT"; 150 case MLX5_EVENT_TYPE_CMD: 151 return "MLX5_EVENT_TYPE_CMD"; 152 case MLX5_EVENT_TYPE_PAGE_REQUEST: 153 return "MLX5_EVENT_TYPE_PAGE_REQUEST"; 154 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 155 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE"; 156 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 157 return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT"; 158 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 159 return "MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT"; 160 default: 161 return "Unrecognized event"; 162 } 163 } 164 165 static enum mlx5_dev_event port_subtype_event(u8 subtype) 166 { 167 switch (subtype) { 168 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 169 return MLX5_DEV_EVENT_PORT_DOWN; 170 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 171 return MLX5_DEV_EVENT_PORT_UP; 172 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 173 return MLX5_DEV_EVENT_PORT_INITIALIZED; 174 case MLX5_PORT_CHANGE_SUBTYPE_LID: 175 return MLX5_DEV_EVENT_LID_CHANGE; 176 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 177 return MLX5_DEV_EVENT_PKEY_CHANGE; 178 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 179 return MLX5_DEV_EVENT_GUID_CHANGE; 180 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 181 return MLX5_DEV_EVENT_CLIENT_REREG; 182 } 183 return -1; 184 } 185 186 static enum mlx5_dev_event dcbx_subevent(u8 subtype) 187 { 188 switch (subtype) { 189 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 190 return MLX5_DEV_EVENT_ERROR_STATE_DCBX; 191 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 192 return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE; 193 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 194 return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE; 195 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 196 return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE; 197 } 198 return -1; 199 } 200 201 static void eq_update_ci(struct mlx5_eq *eq, int arm) 202 { 203 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); 204 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); 205 __raw_writel((__force u32) cpu_to_be32(val), addr); 206 /* We still want ordering, just not swabbing, so add a barrier */ 207 mb(); 208 } 209 210 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 211 { 212 struct mlx5_eqe *eqe; 213 int eqes_found = 0; 214 int set_ci = 0; 215 u32 cqn; 216 u32 rsn; 217 u8 port; 218 219 while ((eqe = next_eqe_sw(eq))) { 220 /* 221 * Make sure we read EQ entry contents after we've 222 * checked the ownership bit. 223 */ 224 rmb(); 225 226 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", 227 eq->eqn, eqe_type_str(eqe->type)); 228 switch (eqe->type) { 229 case MLX5_EVENT_TYPE_COMP: 230 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; 231 mlx5_cq_completion(dev, cqn); 232 break; 233 234 case MLX5_EVENT_TYPE_PATH_MIG: 235 case MLX5_EVENT_TYPE_COMM_EST: 236 case MLX5_EVENT_TYPE_SQ_DRAINED: 237 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 238 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 239 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 240 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 241 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 242 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 243 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n", 244 eqe_type_str(eqe->type), eqe->type, rsn); 245 mlx5_rsc_event(dev, rsn, eqe->type); 246 break; 247 248 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 249 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 250 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 251 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n", 252 eqe_type_str(eqe->type), eqe->type, rsn); 253 mlx5_srq_event(dev, rsn, eqe->type); 254 break; 255 256 case MLX5_EVENT_TYPE_CMD: 257 if (dev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 258 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), 259 MLX5_CMD_MODE_EVENTS); 260 } 261 break; 262 263 case MLX5_EVENT_TYPE_PORT_CHANGE: 264 port = (eqe->data.port.port >> 4) & 0xf; 265 switch (eqe->sub_type) { 266 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 267 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 268 case MLX5_PORT_CHANGE_SUBTYPE_LID: 269 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 270 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 271 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 272 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 273 if (dev->event) 274 dev->event(dev, port_subtype_event(eqe->sub_type), 275 (unsigned long)port); 276 break; 277 default: 278 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n", 279 port, eqe->sub_type); 280 } 281 break; 282 283 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 284 port = (eqe->data.port.port >> 4) & 0xf; 285 switch (eqe->sub_type) { 286 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 287 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 288 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 289 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 290 if (dev->event) 291 dev->event(dev, 292 dcbx_subevent(eqe->sub_type), 293 0); 294 break; 295 default: 296 mlx5_core_warn(dev, 297 "dcbx event with unrecognized subtype: port %d, sub_type %d\n", 298 port, eqe->sub_type); 299 } 300 break; 301 302 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 303 mlx5_port_general_notification_event(dev, eqe); 304 break; 305 306 case MLX5_EVENT_TYPE_CQ_ERROR: 307 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 308 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n", 309 cqn, eqe->data.cq_err.syndrome); 310 mlx5_cq_event(dev, cqn, eqe->type); 311 break; 312 313 case MLX5_EVENT_TYPE_PAGE_REQUEST: 314 { 315 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id); 316 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages); 317 318 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n", 319 func_id, npages); 320 mlx5_core_req_pages_handler(dev, func_id, npages); 321 } 322 break; 323 324 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 325 mlx5_port_module_event(dev, eqe); 326 break; 327 328 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 329 { 330 struct mlx5_eqe_vport_change *vc_eqe = 331 &eqe->data.vport_change; 332 u16 vport_num = be16_to_cpu(vc_eqe->vport_num); 333 334 if (dev->event) 335 dev->event(dev, 336 MLX5_DEV_EVENT_VPORT_CHANGE, 337 (unsigned long)vport_num); 338 } 339 break; 340 341 default: 342 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n", 343 eqe->type, eq->eqn); 344 break; 345 } 346 347 ++eq->cons_index; 348 eqes_found = 1; 349 ++set_ci; 350 351 /* The HCA will think the queue has overflowed if we 352 * don't tell it we've been processing events. We 353 * create our EQs with MLX5_NUM_SPARE_EQE extra 354 * entries, so we must update our consumer index at 355 * least that often. 356 */ 357 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) { 358 eq_update_ci(eq, 0); 359 set_ci = 0; 360 } 361 } 362 363 eq_update_ci(eq, 1); 364 365 return eqes_found; 366 } 367 368 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr) 369 { 370 struct mlx5_eq *eq = eq_ptr; 371 struct mlx5_core_dev *dev = eq->dev; 372 373 mlx5_eq_int(dev, eq); 374 375 /* MSI-X vectors always belong to us */ 376 return IRQ_HANDLED; 377 } 378 379 static void init_eq_buf(struct mlx5_eq *eq) 380 { 381 struct mlx5_eqe *eqe; 382 int i; 383 384 for (i = 0; i < eq->nent; i++) { 385 eqe = get_eqe(eq, i); 386 eqe->owner = MLX5_EQE_OWNER_INIT_VAL; 387 } 388 } 389 390 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 391 int nent, u64 mask, const char *name, struct mlx5_uar *uar) 392 { 393 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0}; 394 struct mlx5_priv *priv = &dev->priv; 395 __be64 *pas; 396 void *eqc; 397 int inlen; 398 u32 *in; 399 int err; 400 401 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE); 402 eq->cons_index = 0; 403 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE, 404 &eq->buf); 405 if (err) 406 return err; 407 408 init_eq_buf(eq); 409 410 inlen = MLX5_ST_SZ_BYTES(create_eq_in) + 411 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages; 412 in = mlx5_vzalloc(inlen); 413 if (!in) { 414 err = -ENOMEM; 415 goto err_buf; 416 } 417 418 pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas); 419 mlx5_fill_page_array(&eq->buf, pas); 420 421 MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ); 422 MLX5_SET64(create_eq_in, in, event_bitmask, mask); 423 424 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry); 425 MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent)); 426 MLX5_SET(eqc, eqc, uar_page, uar->index); 427 MLX5_SET(eqc, eqc, intr, vecidx); 428 MLX5_SET(eqc, eqc, log_page_size, 429 eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 430 431 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out)); 432 if (err) 433 goto err_in; 434 435 eq->eqn = MLX5_GET(create_eq_out, out, eq_number); 436 eq->irqn = vecidx; 437 eq->dev = dev; 438 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET; 439 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s", 440 name, pci_name(dev->pdev)); 441 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0, 442 priv->irq_info[vecidx].name, eq); 443 if (err) 444 goto err_eq; 445 #ifdef RSS 446 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) { 447 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE; 448 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector, 449 rss_getcpu(bucket % rss_getnumbuckets())); 450 if (err) 451 goto err_irq; 452 } 453 #else 454 if (0) 455 goto err_irq; 456 #endif 457 458 459 /* EQs are created in ARMED state 460 */ 461 eq_update_ci(eq, 1); 462 463 kvfree(in); 464 return 0; 465 466 err_irq: 467 free_irq(priv->msix_arr[vecidx].vector, eq); 468 469 err_eq: 470 mlx5_cmd_destroy_eq(dev, eq->eqn); 471 472 err_in: 473 kvfree(in); 474 475 err_buf: 476 mlx5_buf_free(dev, &eq->buf); 477 return err; 478 } 479 EXPORT_SYMBOL_GPL(mlx5_create_map_eq); 480 481 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 482 { 483 int err; 484 485 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq); 486 err = mlx5_cmd_destroy_eq(dev, eq->eqn); 487 if (err) 488 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n", 489 eq->eqn); 490 mlx5_buf_free(dev, &eq->buf); 491 492 return err; 493 } 494 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq); 495 496 int mlx5_eq_init(struct mlx5_core_dev *dev) 497 { 498 int err; 499 500 spin_lock_init(&dev->priv.eq_table.lock); 501 502 err = 0; 503 504 return err; 505 } 506 507 508 void mlx5_eq_cleanup(struct mlx5_core_dev *dev) 509 { 510 } 511 512 int mlx5_start_eqs(struct mlx5_core_dev *dev) 513 { 514 struct mlx5_eq_table *table = &dev->priv.eq_table; 515 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK; 516 int err; 517 518 if (MLX5_CAP_GEN(dev, port_module_event)) 519 async_event_mask |= (1ull << 520 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT); 521 522 if (MLX5_CAP_GEN(dev, nic_vport_change_event)) 523 async_event_mask |= (1ull << 524 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE); 525 526 if (MLX5_CAP_GEN(dev, dcbx)) 527 async_event_mask |= (1ull << 528 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT); 529 530 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, 531 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, 532 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]); 533 if (err) { 534 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err); 535 return err; 536 } 537 538 mlx5_cmd_use_events(dev); 539 540 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC, 541 MLX5_NUM_ASYNC_EQE, async_event_mask, 542 "mlx5_async_eq", &dev->priv.uuari.uars[0]); 543 if (err) { 544 mlx5_core_warn(dev, "failed to create async EQ %d\n", err); 545 goto err1; 546 } 547 548 err = mlx5_create_map_eq(dev, &table->pages_eq, 549 MLX5_EQ_VEC_PAGES, 550 /* TODO: sriov max_vf + */ 1, 551 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq", 552 &dev->priv.uuari.uars[0]); 553 if (err) { 554 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err); 555 goto err2; 556 } 557 558 return err; 559 560 err2: 561 mlx5_destroy_unmap_eq(dev, &table->async_eq); 562 563 err1: 564 mlx5_cmd_use_polling(dev); 565 mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 566 return err; 567 } 568 569 int mlx5_stop_eqs(struct mlx5_core_dev *dev) 570 { 571 struct mlx5_eq_table *table = &dev->priv.eq_table; 572 int err; 573 574 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); 575 if (err) 576 return err; 577 578 mlx5_destroy_unmap_eq(dev, &table->async_eq); 579 mlx5_cmd_use_polling(dev); 580 581 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 582 if (err) 583 mlx5_cmd_use_events(dev); 584 585 return err; 586 } 587 588 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 589 u32 *out, int outlen) 590 { 591 u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0}; 592 593 memset(out, 0, outlen); 594 MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ); 595 MLX5_SET(query_eq_in, in, eq_number, eq->eqn); 596 597 return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); 598 } 599 EXPORT_SYMBOL_GPL(mlx5_core_eq_query); 600 601 static const char *mlx5_port_module_event_error_type_to_string(u8 error_type) 602 { 603 switch (error_type) { 604 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED: 605 return "Power Budget Exceeded"; 606 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE: 607 return "Long Range for non MLNX cable/module"; 608 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK: 609 return "Bus stuck(I2C or data shorted)"; 610 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT: 611 return "No EEPROM/retry timeout"; 612 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST: 613 return "Enforce part number list"; 614 case MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE: 615 return "Unsupported Cable"; 616 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE: 617 return "High Temperature"; 618 case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED: 619 return "Cable is shorted"; 620 case MLX5_MODULE_EVENT_ERROR_PCIE_SYSTEM_POWER_SLOT_EXCEEDED: 621 return "One or more network ports have been powered " 622 "down due to insufficient/unadvertised power on " 623 "the PCIe slot. Please refer to the card's user " 624 "manual for power specifications or contact " 625 "Mellanox support."; 626 627 default: 628 return "Unknown error type"; 629 } 630 } 631 632 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num) 633 { 634 if (module_num < 0 || module_num >= MLX5_MAX_PORTS) 635 return 0; /* undefined */ 636 return dev->module_status[module_num]; 637 } 638 639 static void mlx5_port_module_event(struct mlx5_core_dev *dev, 640 struct mlx5_eqe *eqe) 641 { 642 unsigned int module_num; 643 unsigned int module_status; 644 unsigned int error_type; 645 struct mlx5_eqe_port_module_event *module_event_eqe; 646 struct pci_dev *pdev = dev->pdev; 647 648 module_event_eqe = &eqe->data.port_module_event; 649 650 module_num = (unsigned int)module_event_eqe->module; 651 module_status = (unsigned int)module_event_eqe->module_status & 652 PORT_MODULE_EVENT_MODULE_STATUS_MASK; 653 error_type = (unsigned int)module_event_eqe->error_type & 654 PORT_MODULE_EVENT_ERROR_TYPE_MASK; 655 656 switch (module_status) { 657 case MLX5_MODULE_STATUS_PLUGGED_ENABLED: 658 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged and enabled\n", module_num); 659 break; 660 661 case MLX5_MODULE_STATUS_UNPLUGGED: 662 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged\n", module_num); 663 break; 664 665 case MLX5_MODULE_STATUS_ERROR: 666 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s\n", module_num, mlx5_port_module_event_error_type_to_string(error_type)); 667 break; 668 669 case MLX5_MODULE_STATUS_PLUGGED_DISABLED: 670 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged but disabled\n", module_num); 671 break; 672 673 default: 674 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status\n", module_num); 675 } 676 /* store module status */ 677 if (module_num < MLX5_MAX_PORTS) 678 dev->module_status[module_num] = module_status; 679 } 680 681 static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 682 struct mlx5_eqe *eqe) 683 { 684 u8 port = (eqe->data.port.port >> 4) & 0xf; 685 u32 rqn = 0; 686 struct mlx5_eqe_general_notification_event *general_event = NULL; 687 688 switch (eqe->sub_type) { 689 case MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT: 690 general_event = &eqe->data.general_notifications; 691 rqn = be32_to_cpu(general_event->rq_user_index_delay_drop) & 692 0xffffff; 693 break; 694 default: 695 mlx5_core_warn(dev, 696 "general event with unrecognized subtype: port %d, sub_type %d\n", 697 port, eqe->sub_type); 698 break; 699 } 700 } 701 702