1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/interrupt.h> 29 #include <linux/module.h> 30 #include <dev/mlx5/port.h> 31 #include <dev/mlx5/mlx5_ifc.h> 32 #include "mlx5_core.h" 33 34 #include "opt_rss.h" 35 36 #ifdef RSS 37 #include <net/rss_config.h> 38 #include <netinet/in_rss.h> 39 #endif 40 41 enum { 42 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe), 43 MLX5_EQE_OWNER_INIT_VAL = 0x1, 44 }; 45 46 enum { 47 MLX5_NUM_SPARE_EQE = 0x80, 48 MLX5_NUM_ASYNC_EQE = 0x100, 49 MLX5_NUM_CMD_EQE = 32, 50 }; 51 52 enum { 53 MLX5_EQ_DOORBEL_OFFSET = 0x40, 54 }; 55 56 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \ 57 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \ 58 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \ 59 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \ 60 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \ 61 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \ 62 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 63 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 64 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \ 65 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 66 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \ 67 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT)) 68 69 struct map_eq_in { 70 u64 mask; 71 u32 reserved; 72 u32 unmap_eqn; 73 }; 74 75 struct cre_des_eq { 76 u8 reserved[15]; 77 u8 eqn; 78 }; 79 80 /*Function prototype*/ 81 static void mlx5_port_module_event(struct mlx5_core_dev *dev, 82 struct mlx5_eqe *eqe); 83 static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 84 struct mlx5_eqe *eqe); 85 86 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn) 87 { 88 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0}; 89 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0}; 90 91 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ); 92 MLX5_SET(destroy_eq_in, in, eq_number, eqn); 93 94 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 95 } 96 97 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) 98 { 99 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE); 100 } 101 102 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) 103 { 104 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1)); 105 106 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe; 107 } 108 109 static const char *eqe_type_str(u8 type) 110 { 111 switch (type) { 112 case MLX5_EVENT_TYPE_COMP: 113 return "MLX5_EVENT_TYPE_COMP"; 114 case MLX5_EVENT_TYPE_PATH_MIG: 115 return "MLX5_EVENT_TYPE_PATH_MIG"; 116 case MLX5_EVENT_TYPE_COMM_EST: 117 return "MLX5_EVENT_TYPE_COMM_EST"; 118 case MLX5_EVENT_TYPE_SQ_DRAINED: 119 return "MLX5_EVENT_TYPE_SQ_DRAINED"; 120 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 121 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE"; 122 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 123 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT"; 124 case MLX5_EVENT_TYPE_CQ_ERROR: 125 return "MLX5_EVENT_TYPE_CQ_ERROR"; 126 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 127 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR"; 128 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 129 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED"; 130 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 131 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR"; 132 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 133 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR"; 134 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 135 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR"; 136 case MLX5_EVENT_TYPE_INTERNAL_ERROR: 137 return "MLX5_EVENT_TYPE_INTERNAL_ERROR"; 138 case MLX5_EVENT_TYPE_PORT_CHANGE: 139 return "MLX5_EVENT_TYPE_PORT_CHANGE"; 140 case MLX5_EVENT_TYPE_GPIO_EVENT: 141 return "MLX5_EVENT_TYPE_GPIO_EVENT"; 142 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 143 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT"; 144 case MLX5_EVENT_TYPE_REMOTE_CONFIG: 145 return "MLX5_EVENT_TYPE_REMOTE_CONFIG"; 146 case MLX5_EVENT_TYPE_DB_BF_CONGESTION: 147 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION"; 148 case MLX5_EVENT_TYPE_STALL_EVENT: 149 return "MLX5_EVENT_TYPE_STALL_EVENT"; 150 case MLX5_EVENT_TYPE_CMD: 151 return "MLX5_EVENT_TYPE_CMD"; 152 case MLX5_EVENT_TYPE_PAGE_REQUEST: 153 return "MLX5_EVENT_TYPE_PAGE_REQUEST"; 154 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 155 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE"; 156 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 157 return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT"; 158 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 159 return "MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT"; 160 default: 161 return "Unrecognized event"; 162 } 163 } 164 165 static enum mlx5_dev_event port_subtype_event(u8 subtype) 166 { 167 switch (subtype) { 168 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 169 return MLX5_DEV_EVENT_PORT_DOWN; 170 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 171 return MLX5_DEV_EVENT_PORT_UP; 172 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 173 return MLX5_DEV_EVENT_PORT_INITIALIZED; 174 case MLX5_PORT_CHANGE_SUBTYPE_LID: 175 return MLX5_DEV_EVENT_LID_CHANGE; 176 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 177 return MLX5_DEV_EVENT_PKEY_CHANGE; 178 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 179 return MLX5_DEV_EVENT_GUID_CHANGE; 180 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 181 return MLX5_DEV_EVENT_CLIENT_REREG; 182 } 183 return -1; 184 } 185 186 static enum mlx5_dev_event dcbx_subevent(u8 subtype) 187 { 188 switch (subtype) { 189 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 190 return MLX5_DEV_EVENT_ERROR_STATE_DCBX; 191 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 192 return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE; 193 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 194 return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE; 195 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 196 return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE; 197 } 198 return -1; 199 } 200 201 static void eq_update_ci(struct mlx5_eq *eq, int arm) 202 { 203 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); 204 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); 205 __raw_writel((__force u32) cpu_to_be32(val), addr); 206 /* We still want ordering, just not swabbing, so add a barrier */ 207 mb(); 208 } 209 210 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 211 { 212 struct mlx5_eqe *eqe; 213 int eqes_found = 0; 214 int set_ci = 0; 215 u32 cqn; 216 u32 rsn; 217 u8 port; 218 219 while ((eqe = next_eqe_sw(eq))) { 220 /* 221 * Make sure we read EQ entry contents after we've 222 * checked the ownership bit. 223 */ 224 rmb(); 225 226 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", 227 eq->eqn, eqe_type_str(eqe->type)); 228 switch (eqe->type) { 229 case MLX5_EVENT_TYPE_COMP: 230 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; 231 mlx5_cq_completion(dev, cqn); 232 break; 233 234 case MLX5_EVENT_TYPE_PATH_MIG: 235 case MLX5_EVENT_TYPE_COMM_EST: 236 case MLX5_EVENT_TYPE_SQ_DRAINED: 237 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 238 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 239 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 240 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 241 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 242 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 243 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n", 244 eqe_type_str(eqe->type), eqe->type, rsn); 245 mlx5_rsc_event(dev, rsn, eqe->type); 246 break; 247 248 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 249 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 250 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 251 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n", 252 eqe_type_str(eqe->type), eqe->type, rsn); 253 mlx5_srq_event(dev, rsn, eqe->type); 254 break; 255 256 case MLX5_EVENT_TYPE_CMD: 257 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector)); 258 break; 259 260 case MLX5_EVENT_TYPE_PORT_CHANGE: 261 port = (eqe->data.port.port >> 4) & 0xf; 262 switch (eqe->sub_type) { 263 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 264 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 265 case MLX5_PORT_CHANGE_SUBTYPE_LID: 266 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 267 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 268 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 269 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 270 if (dev->event) 271 dev->event(dev, port_subtype_event(eqe->sub_type), 272 (unsigned long)port); 273 break; 274 default: 275 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n", 276 port, eqe->sub_type); 277 } 278 break; 279 280 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 281 port = (eqe->data.port.port >> 4) & 0xf; 282 switch (eqe->sub_type) { 283 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 284 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 285 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 286 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 287 if (dev->event) 288 dev->event(dev, 289 dcbx_subevent(eqe->sub_type), 290 0); 291 break; 292 default: 293 mlx5_core_warn(dev, 294 "dcbx event with unrecognized subtype: port %d, sub_type %d\n", 295 port, eqe->sub_type); 296 } 297 break; 298 299 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT: 300 mlx5_port_general_notification_event(dev, eqe); 301 break; 302 303 case MLX5_EVENT_TYPE_CQ_ERROR: 304 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 305 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n", 306 cqn, eqe->data.cq_err.syndrome); 307 mlx5_cq_event(dev, cqn, eqe->type); 308 break; 309 310 case MLX5_EVENT_TYPE_PAGE_REQUEST: 311 { 312 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id); 313 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages); 314 315 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n", 316 func_id, npages); 317 mlx5_core_req_pages_handler(dev, func_id, npages); 318 } 319 break; 320 321 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 322 mlx5_port_module_event(dev, eqe); 323 break; 324 325 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 326 { 327 struct mlx5_eqe_vport_change *vc_eqe = 328 &eqe->data.vport_change; 329 u16 vport_num = be16_to_cpu(vc_eqe->vport_num); 330 331 if (dev->event) 332 dev->event(dev, 333 MLX5_DEV_EVENT_VPORT_CHANGE, 334 (unsigned long)vport_num); 335 } 336 break; 337 338 default: 339 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n", 340 eqe->type, eq->eqn); 341 break; 342 } 343 344 ++eq->cons_index; 345 eqes_found = 1; 346 ++set_ci; 347 348 /* The HCA will think the queue has overflowed if we 349 * don't tell it we've been processing events. We 350 * create our EQs with MLX5_NUM_SPARE_EQE extra 351 * entries, so we must update our consumer index at 352 * least that often. 353 */ 354 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) { 355 eq_update_ci(eq, 0); 356 set_ci = 0; 357 } 358 } 359 360 eq_update_ci(eq, 1); 361 362 return eqes_found; 363 } 364 365 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr) 366 { 367 struct mlx5_eq *eq = eq_ptr; 368 struct mlx5_core_dev *dev = eq->dev; 369 370 mlx5_eq_int(dev, eq); 371 372 /* MSI-X vectors always belong to us */ 373 return IRQ_HANDLED; 374 } 375 376 static void init_eq_buf(struct mlx5_eq *eq) 377 { 378 struct mlx5_eqe *eqe; 379 int i; 380 381 for (i = 0; i < eq->nent; i++) { 382 eqe = get_eqe(eq, i); 383 eqe->owner = MLX5_EQE_OWNER_INIT_VAL; 384 } 385 } 386 387 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 388 int nent, u64 mask, const char *name, struct mlx5_uar *uar) 389 { 390 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0}; 391 struct mlx5_priv *priv = &dev->priv; 392 __be64 *pas; 393 void *eqc; 394 int inlen; 395 u32 *in; 396 int err; 397 398 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE); 399 eq->cons_index = 0; 400 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE, 401 &eq->buf); 402 if (err) 403 return err; 404 405 init_eq_buf(eq); 406 407 inlen = MLX5_ST_SZ_BYTES(create_eq_in) + 408 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages; 409 in = mlx5_vzalloc(inlen); 410 if (!in) { 411 err = -ENOMEM; 412 goto err_buf; 413 } 414 415 pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas); 416 mlx5_fill_page_array(&eq->buf, pas); 417 418 MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ); 419 MLX5_SET64(create_eq_in, in, event_bitmask, mask); 420 421 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry); 422 MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent)); 423 MLX5_SET(eqc, eqc, uar_page, uar->index); 424 MLX5_SET(eqc, eqc, intr, vecidx); 425 MLX5_SET(eqc, eqc, log_page_size, 426 eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 427 428 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out)); 429 if (err) 430 goto err_in; 431 432 eq->eqn = MLX5_GET(create_eq_out, out, eq_number); 433 eq->irqn = vecidx; 434 eq->dev = dev; 435 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET; 436 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s", 437 name, pci_name(dev->pdev)); 438 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0, 439 priv->irq_info[vecidx].name, eq); 440 if (err) 441 goto err_eq; 442 #ifdef RSS 443 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) { 444 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE; 445 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector, 446 rss_getcpu(bucket % rss_getnumbuckets())); 447 if (err) 448 goto err_irq; 449 } 450 #else 451 if (0) 452 goto err_irq; 453 #endif 454 455 456 /* EQs are created in ARMED state 457 */ 458 eq_update_ci(eq, 1); 459 460 kvfree(in); 461 return 0; 462 463 err_irq: 464 free_irq(priv->msix_arr[vecidx].vector, eq); 465 466 err_eq: 467 mlx5_cmd_destroy_eq(dev, eq->eqn); 468 469 err_in: 470 kvfree(in); 471 472 err_buf: 473 mlx5_buf_free(dev, &eq->buf); 474 return err; 475 } 476 EXPORT_SYMBOL_GPL(mlx5_create_map_eq); 477 478 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 479 { 480 int err; 481 482 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq); 483 err = mlx5_cmd_destroy_eq(dev, eq->eqn); 484 if (err) 485 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n", 486 eq->eqn); 487 mlx5_buf_free(dev, &eq->buf); 488 489 return err; 490 } 491 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq); 492 493 int mlx5_eq_init(struct mlx5_core_dev *dev) 494 { 495 int err; 496 497 spin_lock_init(&dev->priv.eq_table.lock); 498 499 err = 0; 500 501 return err; 502 } 503 504 505 void mlx5_eq_cleanup(struct mlx5_core_dev *dev) 506 { 507 } 508 509 int mlx5_start_eqs(struct mlx5_core_dev *dev) 510 { 511 struct mlx5_eq_table *table = &dev->priv.eq_table; 512 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK; 513 int err; 514 515 if (MLX5_CAP_GEN(dev, port_module_event)) 516 async_event_mask |= (1ull << 517 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT); 518 519 if (MLX5_CAP_GEN(dev, nic_vport_change_event)) 520 async_event_mask |= (1ull << 521 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE); 522 523 if (MLX5_CAP_GEN(dev, dcbx)) 524 async_event_mask |= (1ull << 525 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT); 526 527 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, 528 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, 529 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]); 530 if (err) { 531 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err); 532 return err; 533 } 534 535 mlx5_cmd_use_events(dev); 536 537 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC, 538 MLX5_NUM_ASYNC_EQE, async_event_mask, 539 "mlx5_async_eq", &dev->priv.uuari.uars[0]); 540 if (err) { 541 mlx5_core_warn(dev, "failed to create async EQ %d\n", err); 542 goto err1; 543 } 544 545 err = mlx5_create_map_eq(dev, &table->pages_eq, 546 MLX5_EQ_VEC_PAGES, 547 /* TODO: sriov max_vf + */ 1, 548 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq", 549 &dev->priv.uuari.uars[0]); 550 if (err) { 551 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err); 552 goto err2; 553 } 554 555 return err; 556 557 err2: 558 mlx5_destroy_unmap_eq(dev, &table->async_eq); 559 560 err1: 561 mlx5_cmd_use_polling(dev); 562 mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 563 return err; 564 } 565 566 int mlx5_stop_eqs(struct mlx5_core_dev *dev) 567 { 568 struct mlx5_eq_table *table = &dev->priv.eq_table; 569 int err; 570 571 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); 572 if (err) 573 return err; 574 575 mlx5_destroy_unmap_eq(dev, &table->async_eq); 576 mlx5_cmd_use_polling(dev); 577 578 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 579 if (err) 580 mlx5_cmd_use_events(dev); 581 582 return err; 583 } 584 585 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 586 u32 *out, int outlen) 587 { 588 u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0}; 589 590 memset(out, 0, outlen); 591 MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ); 592 MLX5_SET(query_eq_in, in, eq_number, eq->eqn); 593 594 return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); 595 } 596 EXPORT_SYMBOL_GPL(mlx5_core_eq_query); 597 598 static const char *mlx5_port_module_event_error_type_to_string(u8 error_type) 599 { 600 switch (error_type) { 601 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED: 602 return "Power Budget Exceeded"; 603 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE: 604 return "Long Range for non MLNX cable/module"; 605 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK: 606 return "Bus stuck(I2C or data shorted)"; 607 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT: 608 return "No EEPROM/retry timeout"; 609 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST: 610 return "Enforce part number list"; 611 case MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE: 612 return "Unsupported Cable"; 613 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE: 614 return "High Temperature"; 615 case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED: 616 return "Cable is shorted"; 617 618 default: 619 return "Unknown error type"; 620 } 621 } 622 623 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num) 624 { 625 if (module_num < 0 || module_num >= MLX5_MAX_PORTS) 626 return 0; /* undefined */ 627 return dev->module_status[module_num]; 628 } 629 630 static void mlx5_port_module_event(struct mlx5_core_dev *dev, 631 struct mlx5_eqe *eqe) 632 { 633 unsigned int module_num; 634 unsigned int module_status; 635 unsigned int error_type; 636 struct mlx5_eqe_port_module_event *module_event_eqe; 637 struct pci_dev *pdev = dev->pdev; 638 639 module_event_eqe = &eqe->data.port_module_event; 640 641 module_num = (unsigned int)module_event_eqe->module; 642 module_status = (unsigned int)module_event_eqe->module_status & 643 PORT_MODULE_EVENT_MODULE_STATUS_MASK; 644 error_type = (unsigned int)module_event_eqe->error_type & 645 PORT_MODULE_EVENT_ERROR_TYPE_MASK; 646 647 switch (module_status) { 648 case MLX5_MODULE_STATUS_PLUGGED_ENABLED: 649 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged and enabled\n", module_num); 650 break; 651 652 case MLX5_MODULE_STATUS_UNPLUGGED: 653 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged\n", module_num); 654 break; 655 656 case MLX5_MODULE_STATUS_ERROR: 657 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s\n", module_num, mlx5_port_module_event_error_type_to_string(error_type)); 658 break; 659 660 case MLX5_MODULE_STATUS_PLUGGED_DISABLED: 661 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged but disabled\n", module_num); 662 break; 663 664 default: 665 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status\n", module_num); 666 } 667 /* store module status */ 668 if (module_num < MLX5_MAX_PORTS) 669 dev->module_status[module_num] = module_status; 670 } 671 672 static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev, 673 struct mlx5_eqe *eqe) 674 { 675 u8 port = (eqe->data.port.port >> 4) & 0xf; 676 u32 rqn = 0; 677 struct mlx5_eqe_general_notification_event *general_event = NULL; 678 679 switch (eqe->sub_type) { 680 case MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT: 681 general_event = &eqe->data.general_notifications; 682 rqn = be32_to_cpu(general_event->rq_user_index_delay_drop) & 683 0xffffff; 684 break; 685 default: 686 mlx5_core_warn(dev, 687 "general event with unrecognized subtype: port %d, sub_type %d\n", 688 port, eqe->sub_type); 689 break; 690 } 691 } 692 693