1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <dev/mlx5/driver.h> 29 #include <linux/module.h> 30 #include "mlx5_core.h" 31 32 static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out, 33 int outlen) 34 { 35 u32 in[MLX5_ST_SZ_DW(query_adapter_in)]; 36 int err; 37 38 memset(in, 0, sizeof(in)); 39 40 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER); 41 42 err = mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); 43 return err; 44 } 45 46 int mlx5_query_board_id(struct mlx5_core_dev *dev) 47 { 48 u32 *out; 49 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out); 50 int err; 51 52 out = kzalloc(outlen, GFP_KERNEL); 53 54 err = mlx5_cmd_query_adapter(dev, out, outlen); 55 if (err) 56 goto out_out; 57 58 memcpy(dev->board_id, 59 MLX5_ADDR_OF(query_adapter_out, out, 60 query_adapter_struct.vsd_contd_psid), 61 MLX5_FLD_SZ_BYTES(query_adapter_out, 62 query_adapter_struct.vsd_contd_psid)); 63 64 out_out: 65 kfree(out); 66 67 return err; 68 } 69 70 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id) 71 { 72 u32 *out; 73 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out); 74 int err; 75 76 out = kzalloc(outlen, GFP_KERNEL); 77 78 err = mlx5_cmd_query_adapter(mdev, out, outlen); 79 if (err) 80 goto out_out; 81 82 *vendor_id = MLX5_GET(query_adapter_out, out, 83 query_adapter_struct.ieee_vendor_id); 84 85 out_out: 86 kfree(out); 87 88 return err; 89 } 90 EXPORT_SYMBOL(mlx5_core_query_vendor_id); 91 92 static int mlx5_core_query_special_contexts(struct mlx5_core_dev *dev) 93 { 94 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)]; 95 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)]; 96 int err; 97 98 memset(in, 0, sizeof(in)); 99 memset(out, 0, sizeof(out)); 100 101 MLX5_SET(query_special_contexts_in, in, opcode, 102 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS); 103 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 104 if (err) 105 return err; 106 107 dev->special_contexts.resd_lkey = MLX5_GET(query_special_contexts_out, 108 out, resd_lkey); 109 110 return err; 111 } 112 113 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev) 114 { 115 return mlx5_query_qcam_reg(dev, dev->caps.qcam, 116 MLX5_QCAM_FEATURE_ENHANCED_FEATURES, 117 MLX5_QCAM_REGS_FIRST_128); 118 } 119 120 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev) 121 { 122 return mlx5_query_pcam_reg(dev, dev->caps.pcam, 123 MLX5_PCAM_FEATURE_ENHANCED_FEATURES, 124 MLX5_PCAM_REGS_5000_TO_507F); 125 } 126 127 static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev) 128 { 129 return mlx5_query_mcam_reg(dev, dev->caps.mcam, 130 MLX5_MCAM_FEATURE_ENHANCED_FEATURES, 131 MLX5_MCAM_REGS_FIRST_128); 132 } 133 134 int mlx5_query_hca_caps(struct mlx5_core_dev *dev) 135 { 136 int err; 137 138 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 139 if (err) 140 return err; 141 142 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { 143 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS); 144 if (err) 145 return err; 146 } 147 148 if (MLX5_CAP_GEN(dev, pg)) { 149 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 150 if (err) 151 return err; 152 } 153 154 if (MLX5_CAP_GEN(dev, atomic)) { 155 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 156 if (err) 157 return err; 158 } 159 160 if (MLX5_CAP_GEN(dev, roce)) { 161 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 162 if (err) 163 return err; 164 } 165 166 if ((MLX5_CAP_GEN(dev, port_type) == 167 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET && 168 MLX5_CAP_GEN(dev, nic_flow_table)) || 169 (MLX5_CAP_GEN(dev, port_type) == MLX5_CMD_HCA_CAP_PORT_TYPE_IB && 170 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads))) { 171 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE); 172 if (err) 173 return err; 174 } 175 176 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) { 177 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE); 178 if (err) 179 return err; 180 } 181 182 if (MLX5_CAP_GEN(dev, vport_group_manager)) { 183 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH); 184 if (err) 185 return err; 186 } 187 188 if (MLX5_CAP_GEN(dev, snapshot)) { 189 err = mlx5_core_get_caps(dev, MLX5_CAP_SNAPSHOT); 190 if (err) 191 return err; 192 } 193 194 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 195 err = mlx5_core_get_caps(dev, MLX5_CAP_EOIB_OFFLOADS); 196 if (err) 197 return err; 198 } 199 200 if (MLX5_CAP_GEN(dev, debug)) { 201 err = mlx5_core_get_caps(dev, MLX5_CAP_DEBUG); 202 if (err) 203 return err; 204 } 205 206 if (MLX5_CAP_GEN(dev, qos)) { 207 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS); 208 if (err) 209 return err; 210 } 211 212 if (MLX5_CAP_GEN(dev, qcam_reg)) { 213 err = mlx5_get_qcam_reg(dev); 214 if (err) 215 return err; 216 } 217 218 if (MLX5_CAP_GEN(dev, mcam_reg)) { 219 err = mlx5_get_mcam_reg(dev); 220 if (err) 221 return err; 222 } 223 224 if (MLX5_CAP_GEN(dev, pcam_reg)) { 225 err = mlx5_get_pcam_reg(dev); 226 if (err) 227 return err; 228 } 229 230 if (MLX5_CAP_GEN(dev, tls_tx)) { 231 err = mlx5_core_get_caps(dev, MLX5_CAP_TLS); 232 if (err) 233 return err; 234 } 235 236 err = mlx5_core_query_special_contexts(dev); 237 if (err) 238 return err; 239 240 return 0; 241 } 242 243 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev) 244 { 245 u32 in[MLX5_ST_SZ_DW(init_hca_in)]; 246 u32 out[MLX5_ST_SZ_DW(init_hca_out)]; 247 248 memset(in, 0, sizeof(in)); 249 250 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA); 251 252 memset(out, 0, sizeof(out)); 253 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 254 } 255 256 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev) 257 { 258 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; 259 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; 260 261 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 262 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 263 } 264 265 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev) 266 { 267 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; 268 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; 269 int force_state; 270 int ret; 271 272 if (!MLX5_CAP_GEN(dev, force_teardown)) { 273 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n"); 274 return -EOPNOTSUPP; 275 } 276 277 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 278 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE); 279 280 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out)); 281 if (ret) 282 return ret; 283 284 force_state = MLX5_GET(teardown_hca_out, out, state); 285 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) { 286 mlx5_core_err(dev, "teardown with force mode failed\n"); 287 return -EIO; 288 } 289 290 return 0; 291 } 292 293 #define MLX5_FAST_TEARDOWN_WAIT_MS 3000 294 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev) 295 { 296 int end, delay_ms = MLX5_FAST_TEARDOWN_WAIT_MS; 297 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {}; 298 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {}; 299 int state; 300 int ret; 301 302 if (!MLX5_CAP_GEN(dev, fast_teardown)) { 303 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n"); 304 return -EOPNOTSUPP; 305 } 306 307 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 308 MLX5_SET(teardown_hca_in, in, profile, 309 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN); 310 311 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 312 if (ret) 313 return ret; 314 315 state = MLX5_GET(teardown_hca_out, out, state); 316 if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) { 317 mlx5_core_warn(dev, "teardown with fast mode failed\n"); 318 return -EIO; 319 } 320 321 mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED); 322 323 /* Loop until device state turns to disable */ 324 end = jiffies + msecs_to_jiffies(delay_ms); 325 do { 326 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED) 327 break; 328 329 pause("W", 1); 330 } while (!time_after(jiffies, end)); 331 332 if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) { 333 mlx5_core_err(dev, "NIC IFC still %d after %ums.\n", 334 mlx5_get_nic_state(dev), delay_ms); 335 return -EIO; 336 } 337 return 0; 338 } 339 340 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 341 u64 addr) 342 { 343 u32 in[MLX5_ST_SZ_DW(set_dc_cnak_trace_in)] = {0}; 344 u32 out[MLX5_ST_SZ_DW(set_dc_cnak_trace_out)] = {0}; 345 __be64 be_addr; 346 void *pas; 347 348 MLX5_SET(set_dc_cnak_trace_in, in, opcode, MLX5_CMD_OP_SET_DC_CNAK_TRACE); 349 MLX5_SET(set_dc_cnak_trace_in, in, enable, enable); 350 pas = MLX5_ADDR_OF(set_dc_cnak_trace_in, in, pas); 351 be_addr = cpu_to_be64(addr); 352 memcpy(MLX5_ADDR_OF(cmd_pas, pas, pa_h), &be_addr, sizeof(be_addr)); 353 354 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 355 } 356 357 enum mlxsw_reg_mcc_instruction { 358 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 359 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 360 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 361 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 362 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 363 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08, 364 }; 365 366 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev, 367 enum mlxsw_reg_mcc_instruction instr, 368 u16 component_index, u32 update_handle, 369 u32 component_size) 370 { 371 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; 372 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; 373 374 memset(in, 0, sizeof(in)); 375 376 MLX5_SET(mcc_reg, in, instruction, instr); 377 MLX5_SET(mcc_reg, in, component_index, component_index); 378 MLX5_SET(mcc_reg, in, update_handle, update_handle); 379 MLX5_SET(mcc_reg, in, component_size, component_size); 380 381 return mlx5_core_access_reg(dev, in, sizeof(in), out, 382 sizeof(out), MLX5_REG_MCC, 0, 1); 383 } 384 385 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev, 386 u32 *update_handle, u8 *error_code, 387 u8 *control_state) 388 { 389 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; 390 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; 391 int err; 392 393 memset(in, 0, sizeof(in)); 394 memset(out, 0, sizeof(out)); 395 MLX5_SET(mcc_reg, in, update_handle, *update_handle); 396 397 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 398 sizeof(out), MLX5_REG_MCC, 0, 0); 399 if (err) 400 goto out; 401 402 *update_handle = MLX5_GET(mcc_reg, out, update_handle); 403 *error_code = MLX5_GET(mcc_reg, out, error_code); 404 *control_state = MLX5_GET(mcc_reg, out, control_state); 405 406 out: 407 return err; 408 } 409 410 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev, 411 u32 update_handle, 412 u32 offset, u16 size, 413 u8 *data) 414 { 415 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size; 416 u32 out[MLX5_ST_SZ_DW(mcda_reg)]; 417 int i, j, dw_size = size >> 2; 418 __be32 data_element; 419 u32 *in; 420 421 in = kzalloc(in_size, GFP_KERNEL); 422 if (!in) 423 return -ENOMEM; 424 425 MLX5_SET(mcda_reg, in, update_handle, update_handle); 426 MLX5_SET(mcda_reg, in, offset, offset); 427 MLX5_SET(mcda_reg, in, size, size); 428 429 for (i = 0; i < dw_size; i++) { 430 j = i * 4; 431 data_element = htonl(*(u32 *)&data[j]); 432 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4); 433 } 434 435 err = mlx5_core_access_reg(dev, in, in_size, out, 436 sizeof(out), MLX5_REG_MCDA, 0, 1); 437 kfree(in); 438 return err; 439 } 440 441 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev, 442 u16 component_index, 443 u32 *max_component_size, 444 u8 *log_mcda_word_size, 445 u16 *mcda_max_write_size) 446 { 447 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)]; 448 int offset = MLX5_ST_SZ_DW(mcqi_reg); 449 u32 in[MLX5_ST_SZ_DW(mcqi_reg)]; 450 int err; 451 452 memset(in, 0, sizeof(in)); 453 memset(out, 0, sizeof(out)); 454 455 MLX5_SET(mcqi_reg, in, component_index, component_index); 456 MLX5_SET(mcqi_reg, in, data_size, MLX5_ST_SZ_BYTES(mcqi_cap)); 457 458 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 459 sizeof(out), MLX5_REG_MCQI, 0, 0); 460 if (err) 461 goto out; 462 463 *max_component_size = MLX5_GET(mcqi_cap, out + offset, max_component_size); 464 *log_mcda_word_size = MLX5_GET(mcqi_cap, out + offset, log_mcda_word_size); 465 *mcda_max_write_size = MLX5_GET(mcqi_cap, out + offset, mcda_max_write_size); 466 467 out: 468 return err; 469 } 470 471 struct mlx5_mlxfw_dev { 472 struct mlxfw_dev mlxfw_dev; 473 struct mlx5_core_dev *mlx5_core_dev; 474 }; 475 476 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev, 477 u16 component_index, u32 *p_max_size, 478 u8 *p_align_bits, u16 *p_max_write_size) 479 { 480 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 481 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 482 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 483 484 return mlx5_reg_mcqi_query(dev, component_index, p_max_size, 485 p_align_bits, p_max_write_size); 486 } 487 488 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 489 { 490 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 491 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 492 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 493 u8 control_state, error_code; 494 int err; 495 496 *fwhandle = 0; 497 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state); 498 if (err) 499 return err; 500 501 if (control_state != MLXFW_FSM_STATE_IDLE) 502 return -EBUSY; 503 504 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 505 0, *fwhandle, 0); 506 } 507 508 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 509 u16 component_index, u32 component_size) 510 { 511 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 512 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 513 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 514 515 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 516 component_index, fwhandle, component_size); 517 } 518 519 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 520 u8 *data, u16 size, u32 offset) 521 { 522 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 523 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 524 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 525 526 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data); 527 } 528 529 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 530 u16 component_index) 531 { 532 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 533 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 534 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 535 536 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 537 component_index, fwhandle, 0); 538 } 539 540 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 541 { 542 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 543 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 544 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 545 546 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0, 547 fwhandle, 0); 548 } 549 550 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 551 enum mlxfw_fsm_state *fsm_state, 552 enum mlxfw_fsm_state_err *fsm_state_err) 553 { 554 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 555 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 556 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 557 u8 control_state, error_code; 558 int err; 559 560 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state); 561 if (err) 562 return err; 563 564 *fsm_state = control_state; 565 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, 566 MLXFW_FSM_STATE_ERR_MAX); 567 return 0; 568 } 569 570 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 571 { 572 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 573 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 574 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 575 576 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 577 } 578 579 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 580 { 581 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 582 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 583 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 584 585 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, 586 fwhandle, 0); 587 } 588 589 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = { 590 .component_query = mlx5_component_query, 591 .fsm_lock = mlx5_fsm_lock, 592 .fsm_component_update = mlx5_fsm_component_update, 593 .fsm_block_download = mlx5_fsm_block_download, 594 .fsm_component_verify = mlx5_fsm_component_verify, 595 .fsm_activate = mlx5_fsm_activate, 596 .fsm_query_state = mlx5_fsm_query_state, 597 .fsm_cancel = mlx5_fsm_cancel, 598 .fsm_release = mlx5_fsm_release 599 }; 600 601 int mlx5_firmware_flash(struct mlx5_core_dev *dev, 602 const struct firmware *firmware) 603 { 604 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = { 605 .mlxfw_dev = { 606 .ops = &mlx5_mlxfw_dev_ops, 607 .psid = dev->board_id, 608 .psid_size = strlen(dev->board_id), 609 }, 610 .mlx5_core_dev = dev 611 }; 612 613 if (!MLX5_CAP_GEN(dev, mcam_reg) || 614 !MLX5_CAP_MCAM_REG(dev, mcqi) || 615 !MLX5_CAP_MCAM_REG(dev, mcc) || 616 !MLX5_CAP_MCAM_REG(dev, mcda)) { 617 pr_info("%s flashing isn't supported by the running FW\n", __func__); 618 return -EOPNOTSUPP; 619 } 620 621 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, firmware); 622 } 623