1 /*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/random.h> 31 #include <linux/vmalloc.h> 32 #include <linux/hardirq.h> 33 #include <linux/delay.h> 34 #include <dev/mlx5/driver.h> 35 #include <dev/mlx5/mlx5_ifc.h> 36 #include "mlx5_core.h" 37 38 #define MLX5_HEALTH_POLL_INTERVAL (2 * HZ) 39 #define MAX_MISSES 3 40 41 enum { 42 MLX5_NIC_IFC_FULL = 0, 43 MLX5_NIC_IFC_DISABLED = 1, 44 MLX5_NIC_IFC_NO_DRAM_NIC = 2, 45 MLX5_NIC_IFC_SW_RESET = 7, 46 }; 47 48 enum { 49 MLX5_DROP_NEW_HEALTH_WORK, 50 MLX5_DROP_NEW_RECOVERY_WORK, 51 MLX5_SKIP_SW_RESET, 52 MLX5_SW_RESET_SEM_LOCKED, 53 }; 54 55 enum { 56 MLX5_SENSOR_NO_ERR = 0, 57 MLX5_SENSOR_PCI_COMM_ERR = 1, 58 MLX5_SENSOR_PCI_ERR = 2, 59 MLX5_SENSOR_NIC_DISABLED = 3, 60 MLX5_SENSOR_NIC_SW_RESET = 4, 61 MLX5_SENSOR_FW_SYND_RFR = 5, 62 }; 63 64 static int lock_sem_sw_reset(struct mlx5_core_dev *dev, int state) 65 { 66 int ret, err; 67 68 /* Lock GW access */ 69 ret = mlx5_pciconf_cap9_sem(dev, LOCK); 70 if (ret) { 71 mlx5_core_warn(dev, "Timed out locking gateway %d, %d\n", state, ret); 72 return ret; 73 } 74 75 ret = mlx5_pciconf_set_sem_addr_space(dev, MLX5_SEMAPHORE_SW_RESET, state); 76 if (ret && state == LOCK) { 77 if (ret == -EBUSY) 78 mlx5_core_dbg(dev, "SW reset FW semaphore already locked, another function will handle the reset\n"); 79 else 80 mlx5_core_warn(dev, "SW reset semaphore lock return %d\n", ret); 81 } 82 83 /* Unlock GW access */ 84 err = mlx5_pciconf_cap9_sem(dev, UNLOCK); 85 if (err) 86 mlx5_core_warn(dev, "Timed out unlocking gateway: state %d, err %d\n", state, err); 87 88 return ret; 89 } 90 91 static u8 get_nic_mode(struct mlx5_core_dev *dev) 92 { 93 return (ioread32be(&dev->iseg->cmdq_addr_l_sz) >> 8) & 7; 94 } 95 96 static bool sensor_fw_synd_rfr(struct mlx5_core_dev *dev) 97 { 98 struct mlx5_core_health *health = &dev->priv.health; 99 struct mlx5_health_buffer __iomem *h = health->health; 100 u32 rfr = ioread32be(&h->rfr) >> MLX5_RFR_OFFSET; 101 u8 synd = ioread8(&h->synd); 102 103 if (rfr && synd) 104 mlx5_core_dbg(dev, "FW requests reset, synd: %d\n", synd); 105 return rfr && synd; 106 } 107 108 static void mlx5_trigger_cmd_completions(struct mlx5_core_dev *dev) 109 { 110 unsigned long flags; 111 u64 vector; 112 113 /* wait for pending handlers to complete */ 114 synchronize_irq(dev->priv.msix_arr[MLX5_EQ_VEC_CMD].vector); 115 spin_lock_irqsave(&dev->cmd.alloc_lock, flags); 116 vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1); 117 if (!vector) 118 goto no_trig; 119 120 vector |= MLX5_TRIGGERED_CMD_COMP; 121 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags); 122 123 mlx5_core_dbg(dev, "vector 0x%jx\n", (uintmax_t)vector); 124 mlx5_cmd_comp_handler(dev, vector); 125 return; 126 127 no_trig: 128 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags); 129 } 130 131 static bool sensor_pci_no_comm(struct mlx5_core_dev *dev) 132 { 133 struct mlx5_core_health *health = &dev->priv.health; 134 struct mlx5_health_buffer __iomem *h = health->health; 135 bool err = ioread32be(&h->fw_ver) == 0xffffffff; 136 137 return err; 138 } 139 140 static bool sensor_nic_disabled(struct mlx5_core_dev *dev) 141 { 142 return get_nic_mode(dev) == MLX5_NIC_IFC_DISABLED; 143 } 144 145 static bool sensor_nic_sw_reset(struct mlx5_core_dev *dev) 146 { 147 return get_nic_mode(dev) == MLX5_NIC_IFC_SW_RESET; 148 } 149 150 static u32 check_fatal_sensors(struct mlx5_core_dev *dev) 151 { 152 if (sensor_pci_no_comm(dev)) 153 return MLX5_SENSOR_PCI_COMM_ERR; 154 if (pci_channel_offline(dev->pdev)) 155 return MLX5_SENSOR_PCI_ERR; 156 if (sensor_nic_disabled(dev)) 157 return MLX5_SENSOR_NIC_DISABLED; 158 if (sensor_nic_sw_reset(dev)) 159 return MLX5_SENSOR_NIC_SW_RESET; 160 if (sensor_fw_synd_rfr(dev)) 161 return MLX5_SENSOR_FW_SYND_RFR; 162 163 return MLX5_SENSOR_NO_ERR; 164 } 165 166 static void reset_fw_if_needed(struct mlx5_core_dev *dev) 167 { 168 bool supported = (ioread32be(&dev->iseg->initializing) >> 169 MLX5_FW_RESET_SUPPORTED_OFFSET) & 1; 170 struct mlx5_core_health *health = &dev->priv.health; 171 u32 cmdq_addr, fatal_error; 172 173 if (!supported) 174 return; 175 176 /* The reset only needs to be issued by one PF. The health buffer is 177 * shared between all functions, and will be cleared during a reset. 178 * Check again to avoid a redundant 2nd reset. If the fatal erros was 179 * PCI related a reset won't help. 180 */ 181 fatal_error = check_fatal_sensors(dev); 182 if (fatal_error == MLX5_SENSOR_PCI_COMM_ERR || 183 fatal_error == MLX5_SENSOR_NIC_DISABLED || 184 fatal_error == MLX5_SENSOR_NIC_SW_RESET || 185 test_bit(MLX5_SKIP_SW_RESET, &health->flags)) { 186 mlx5_core_warn(dev, "Not issuing FW reset. Either it's already done or won't help.\n"); 187 return; 188 } 189 190 mlx5_core_warn(dev, "Issuing FW Reset\n"); 191 /* Write the NIC interface field to initiate the reset, the command 192 * interface address also resides here, don't overwrite it. 193 */ 194 cmdq_addr = ioread32be(&dev->iseg->cmdq_addr_l_sz); 195 iowrite32be((cmdq_addr & 0xFFFFF000) | 196 MLX5_NIC_IFC_SW_RESET << MLX5_NIC_IFC_OFFSET, 197 &dev->iseg->cmdq_addr_l_sz); 198 } 199 200 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force) 201 { 202 mutex_lock(&dev->intf_state_mutex); 203 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 204 goto unlock; 205 return; 206 } 207 208 if (!force) 209 mlx5_core_err(dev, "internal state error detected\n"); 210 if (check_fatal_sensors(dev) || force) { 211 reset_fw_if_needed(dev); 212 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 213 mlx5_trigger_cmd_completions(dev); 214 } 215 216 mlx5_core_event(dev, MLX5_DEV_EVENT_SYS_ERROR, 0); 217 if (!force) 218 mlx5_core_err(dev, "system error event triggered\n"); 219 220 unlock: 221 mutex_unlock(&dev->intf_state_mutex); 222 } 223 224 static void mlx5_handle_bad_state(struct mlx5_core_dev *dev) 225 { 226 u8 nic_mode = get_nic_mode(dev); 227 228 if (nic_mode == MLX5_NIC_IFC_SW_RESET) { 229 /* The IFC mode field is 3 bits, so it will read 0x7 in two cases: 230 * 1. PCI has been disabled (ie. PCI-AER, PF driver unloaded 231 * and this is a VF), this is not recoverable by SW reset. 232 * Logging of this is handled elsewhere. 233 * 2. FW reset has been issued by another function, driver can 234 * be reloaded to recover after the mode switches to 235 * MLX5_NIC_IFC_DISABLED. 236 */ 237 if (dev->priv.health.fatal_error != MLX5_SENSOR_PCI_COMM_ERR) 238 mlx5_core_warn(dev, "NIC SW reset is already progress\n"); 239 else 240 mlx5_core_warn(dev, "Communication with FW over the PCI link is down\n"); 241 } else { 242 mlx5_core_warn(dev, "NIC mode %d\n", nic_mode); 243 } 244 245 mlx5_disable_device(dev); 246 } 247 248 #define MLX5_FW_RESET_WAIT_MS 1000 249 #define MLX5_NIC_STATE_POLL_MS 5 250 static void health_recover(struct work_struct *work) 251 { 252 unsigned long end = jiffies + msecs_to_jiffies(MLX5_FW_RESET_WAIT_MS); 253 struct mlx5_core_health *health; 254 struct delayed_work *dwork; 255 struct mlx5_core_dev *dev; 256 struct mlx5_priv *priv; 257 bool recover = true; 258 u8 nic_mode; 259 260 dwork = container_of(work, struct delayed_work, work); 261 health = container_of(dwork, struct mlx5_core_health, recover_work); 262 priv = container_of(health, struct mlx5_priv, health); 263 dev = container_of(priv, struct mlx5_core_dev, priv); 264 265 if (sensor_pci_no_comm(dev)) { 266 dev_err(&dev->pdev->dev, "health recovery flow aborted, PCI reads still not working\n"); 267 recover = false; 268 goto clear_sem; 269 } 270 271 nic_mode = get_nic_mode(dev); 272 while (nic_mode != MLX5_NIC_IFC_DISABLED && 273 !time_after(jiffies, end)) { 274 msleep(MLX5_NIC_STATE_POLL_MS); 275 nic_mode = get_nic_mode(dev); 276 } 277 278 if (nic_mode != MLX5_NIC_IFC_DISABLED) { 279 dev_err(&dev->pdev->dev, "health recovery flow aborted, unexpected NIC IFC mode %d.\n", 280 nic_mode); 281 recover = false; 282 } 283 284 clear_sem: 285 if (test_and_clear_bit(MLX5_SW_RESET_SEM_LOCKED, &health->flags)) { 286 mlx5_core_dbg(dev, "Unlocking FW reset semaphore\n"); 287 lock_sem_sw_reset(dev, UNLOCK); 288 } 289 290 test_and_clear_bit(MLX5_SKIP_SW_RESET, &health->flags); 291 292 if (recover) { 293 dev_err(&dev->pdev->dev, "starting health recovery flow\n"); 294 mlx5_recover_device(dev); 295 } 296 } 297 298 /* How much time to wait until health resetting the driver (in msecs) */ 299 #define MLX5_RECOVERY_DELAY_MSECS 60000 300 #define MLX5_RECOVERY_NO_DELAY 0 301 static unsigned long get_recovery_delay(struct mlx5_core_dev *dev) 302 { 303 return dev->priv.health.fatal_error == MLX5_SENSOR_PCI_ERR || 304 dev->priv.health.fatal_error == MLX5_SENSOR_PCI_COMM_ERR ? 305 MLX5_RECOVERY_DELAY_MSECS : MLX5_RECOVERY_NO_DELAY; 306 } 307 308 static void health_care(struct work_struct *work) 309 { 310 struct mlx5_core_health *health; 311 unsigned long recover_delay; 312 struct mlx5_core_dev *dev; 313 struct mlx5_priv *priv; 314 unsigned long flags; 315 int ret; 316 317 health = container_of(work, struct mlx5_core_health, work); 318 priv = container_of(health, struct mlx5_priv, health); 319 dev = container_of(priv, struct mlx5_core_dev, priv); 320 321 if (mlx5_core_is_pf(dev)) { 322 ret = lock_sem_sw_reset(dev, LOCK); 323 if (!ret) { 324 mlx5_core_warn(dev, "Locked FW reset semaphore\n"); 325 set_bit(MLX5_SW_RESET_SEM_LOCKED, &health->flags); 326 } 327 else if (ret == -EBUSY) { 328 /* sw reset will be skipped only in case we detect the 329 * semaphore was already taken. In case of an error 330 * while taking the semaphore we prefer to issue a 331 * reset since longer cr-dump time and multiple resets 332 * are better than a stuck fw. 333 */ 334 set_bit(MLX5_SKIP_SW_RESET, &health->flags); 335 } 336 } 337 338 mlx5_core_warn(dev, "handling bad device here\n"); 339 mlx5_handle_bad_state(dev); 340 recover_delay = msecs_to_jiffies(get_recovery_delay(dev)); 341 342 spin_lock_irqsave(&health->wq_lock, flags); 343 if (!test_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags)) { 344 mlx5_core_warn(dev, "Scheduling recovery work with %lums delay\n", 345 recover_delay); 346 schedule_delayed_work(&health->recover_work, recover_delay); 347 } else { 348 dev_err(&dev->pdev->dev, 349 "new health works are not permitted at this stage\n"); 350 } 351 spin_unlock_irqrestore(&health->wq_lock, flags); 352 } 353 354 static int get_next_poll_jiffies(void) 355 { 356 unsigned long next; 357 358 get_random_bytes(&next, sizeof(next)); 359 next %= HZ; 360 next += jiffies + MLX5_HEALTH_POLL_INTERVAL; 361 362 return next; 363 } 364 365 void mlx5_trigger_health_work(struct mlx5_core_dev *dev) 366 { 367 struct mlx5_core_health *health = &dev->priv.health; 368 unsigned long flags; 369 370 spin_lock_irqsave(&health->wq_lock, flags); 371 if (!test_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags)) 372 queue_work(health->wq, &health->work); 373 else 374 dev_err(&dev->pdev->dev, 375 "new health works are not permitted at this stage\n"); 376 spin_unlock_irqrestore(&health->wq_lock, flags); 377 } 378 379 static const char *hsynd_str(u8 synd) 380 { 381 switch (synd) { 382 case MLX5_HEALTH_SYNDR_FW_ERR: 383 return "firmware internal error"; 384 case MLX5_HEALTH_SYNDR_IRISC_ERR: 385 return "irisc not responding"; 386 case MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR: 387 return "unrecoverable hardware error"; 388 case MLX5_HEALTH_SYNDR_CRC_ERR: 389 return "firmware CRC error"; 390 case MLX5_HEALTH_SYNDR_FETCH_PCI_ERR: 391 return "ICM fetch PCI error"; 392 case MLX5_HEALTH_SYNDR_HW_FTL_ERR: 393 return "HW fatal error\n"; 394 case MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR: 395 return "async EQ buffer overrun"; 396 case MLX5_HEALTH_SYNDR_EQ_ERR: 397 return "EQ error"; 398 case MLX5_HEALTH_SYNDR_EQ_INV: 399 return "Invalid EQ referenced"; 400 case MLX5_HEALTH_SYNDR_FFSER_ERR: 401 return "FFSER error"; 402 case MLX5_HEALTH_SYNDR_HIGH_TEMP: 403 return "High temprature"; 404 default: 405 return "unrecognized error"; 406 } 407 } 408 409 static void print_health_info(struct mlx5_core_dev *dev) 410 { 411 struct mlx5_core_health *health = &dev->priv.health; 412 struct mlx5_health_buffer __iomem *h = health->health; 413 char fw_str[18]; 414 u32 fw; 415 int i; 416 417 /* If the syndrom is 0, the device is OK and no need to print buffer */ 418 if (!ioread8(&h->synd)) 419 return; 420 421 for (i = 0; i < ARRAY_SIZE(h->assert_var); i++) 422 printf("mlx5_core: INFO: ""assert_var[%d] 0x%08x\n", i, ioread32be(h->assert_var + i)); 423 424 printf("mlx5_core: INFO: ""assert_exit_ptr 0x%08x\n", ioread32be(&h->assert_exit_ptr)); 425 printf("mlx5_core: INFO: ""assert_callra 0x%08x\n", ioread32be(&h->assert_callra)); 426 snprintf(fw_str, sizeof(fw_str), "%d.%d.%d", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); 427 printf("mlx5_core: INFO: ""fw_ver %s\n", fw_str); 428 printf("mlx5_core: INFO: ""hw_id 0x%08x\n", ioread32be(&h->hw_id)); 429 printf("mlx5_core: INFO: ""irisc_index %d\n", ioread8(&h->irisc_index)); 430 printf("mlx5_core: INFO: ""synd 0x%x: %s\n", ioread8(&h->synd), hsynd_str(ioread8(&h->synd))); 431 printf("mlx5_core: INFO: ""ext_synd 0x%04x\n", ioread16be(&h->ext_synd)); 432 fw = ioread32be(&h->fw_ver); 433 printf("mlx5_core: INFO: ""raw fw_ver 0x%08x\n", fw); 434 } 435 436 static void poll_health(unsigned long data) 437 { 438 struct mlx5_core_dev *dev = (struct mlx5_core_dev *)data; 439 struct mlx5_core_health *health = &dev->priv.health; 440 u32 fatal_error; 441 u32 count; 442 443 if (dev->state != MLX5_DEVICE_STATE_UP) 444 return; 445 446 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) 447 goto out; 448 449 count = ioread32be(health->health_counter); 450 if (count == health->prev) 451 ++health->miss_counter; 452 else 453 health->miss_counter = 0; 454 455 health->prev = count; 456 if (health->miss_counter == MAX_MISSES) { 457 mlx5_core_err(dev, "device's health compromised - reached miss count\n"); 458 print_health_info(dev); 459 } 460 461 fatal_error = check_fatal_sensors(dev); 462 463 if (fatal_error && !health->fatal_error) { 464 mlx5_core_err(dev, "Fatal error %u detected\n", fatal_error); 465 dev->priv.health.fatal_error = fatal_error; 466 print_health_info(dev); 467 mlx5_trigger_health_work(dev); 468 } 469 470 out: 471 mod_timer(&health->timer, get_next_poll_jiffies()); 472 } 473 474 void mlx5_start_health_poll(struct mlx5_core_dev *dev) 475 { 476 struct mlx5_core_health *health = &dev->priv.health; 477 478 init_timer(&health->timer); 479 health->fatal_error = MLX5_SENSOR_NO_ERR; 480 clear_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags); 481 clear_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags); 482 health->health = &dev->iseg->health; 483 health->health_counter = &dev->iseg->health_counter; 484 485 setup_timer(&health->timer, poll_health, (unsigned long)dev); 486 mod_timer(&health->timer, 487 round_jiffies(jiffies + MLX5_HEALTH_POLL_INTERVAL)); 488 } 489 490 void mlx5_stop_health_poll(struct mlx5_core_dev *dev) 491 { 492 struct mlx5_core_health *health = &dev->priv.health; 493 494 del_timer_sync(&health->timer); 495 } 496 497 void mlx5_drain_health_wq(struct mlx5_core_dev *dev) 498 { 499 struct mlx5_core_health *health = &dev->priv.health; 500 unsigned long flags; 501 502 spin_lock_irqsave(&health->wq_lock, flags); 503 set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags); 504 set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags); 505 spin_unlock_irqrestore(&health->wq_lock, flags); 506 cancel_delayed_work_sync(&health->recover_work); 507 cancel_work_sync(&health->work); 508 } 509 510 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev) 511 { 512 struct mlx5_core_health *health = &dev->priv.health; 513 unsigned long flags; 514 515 spin_lock_irqsave(&health->wq_lock, flags); 516 set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags); 517 spin_unlock_irqrestore(&health->wq_lock, flags); 518 cancel_delayed_work_sync(&dev->priv.health.recover_work); 519 } 520 521 void mlx5_health_cleanup(struct mlx5_core_dev *dev) 522 { 523 struct mlx5_core_health *health = &dev->priv.health; 524 525 destroy_workqueue(health->wq); 526 } 527 528 #define HEALTH_NAME "mlx5_health" 529 int mlx5_health_init(struct mlx5_core_dev *dev) 530 { 531 struct mlx5_core_health *health; 532 char *name; 533 int len; 534 535 health = &dev->priv.health; 536 len = strlen(HEALTH_NAME) + strlen(dev_name(&dev->pdev->dev)); 537 name = kmalloc(len + 1, GFP_KERNEL); 538 if (!name) 539 return -ENOMEM; 540 541 snprintf(name, len, "%s:%s", HEALTH_NAME, dev_name(&dev->pdev->dev)); 542 health->wq = create_singlethread_workqueue(name); 543 kfree(name); 544 if (!health->wq) 545 return -ENOMEM; 546 547 spin_lock_init(&health->wq_lock); 548 INIT_WORK(&health->work, health_care); 549 INIT_DELAYED_WORK(&health->recover_work, health_recover); 550 551 return 0; 552 } 553