1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/random.h> 31 #include <linux/vmalloc.h> 32 #include <linux/hardirq.h> 33 #include <linux/delay.h> 34 #include <dev/mlx5/driver.h> 35 #include <dev/mlx5/mlx5_ifc.h> 36 #include "mlx5_core.h" 37 38 #define MLX5_HEALTH_POLL_INTERVAL (2 * HZ) 39 #define MAX_MISSES 3 40 41 enum { 42 MLX5_DROP_NEW_HEALTH_WORK, 43 MLX5_DROP_NEW_RECOVERY_WORK, 44 MLX5_DROP_NEW_WATCHDOG_WORK, 45 }; 46 47 enum { 48 MLX5_SENSOR_NO_ERR = 0, 49 MLX5_SENSOR_PCI_COMM_ERR = 1, 50 MLX5_SENSOR_PCI_ERR = 2, 51 MLX5_SENSOR_NIC_DISABLED = 3, 52 MLX5_SENSOR_NIC_SW_RESET = 4, 53 MLX5_SENSOR_FW_SYND_RFR = 5, 54 }; 55 56 static int mlx5_fw_reset_enable = 1; 57 SYSCTL_INT(_hw_mlx5, OID_AUTO, fw_reset_enable, CTLFLAG_RWTUN, 58 &mlx5_fw_reset_enable, 0, 59 "Enable firmware reset"); 60 61 static unsigned int sw_reset_to = 1200; 62 SYSCTL_UINT(_hw_mlx5, OID_AUTO, sw_reset_timeout, CTLFLAG_RWTUN, 63 &sw_reset_to, 0, 64 "Minimum timeout in seconds between two firmware resets"); 65 66 67 static int lock_sem_sw_reset(struct mlx5_core_dev *dev) 68 { 69 int ret; 70 71 /* Lock GW access */ 72 ret = -mlx5_vsc_lock(dev); 73 if (ret) { 74 mlx5_core_warn(dev, "Timed out locking gateway %d\n", ret); 75 return ret; 76 } 77 78 ret = -mlx5_vsc_lock_addr_space(dev, MLX5_SEMAPHORE_SW_RESET); 79 if (ret) { 80 if (ret == -EBUSY) 81 mlx5_core_dbg(dev, "SW reset FW semaphore already locked, another function will handle the reset\n"); 82 else 83 mlx5_core_warn(dev, "SW reset semaphore lock return %d\n", ret); 84 } 85 86 /* Unlock GW access */ 87 mlx5_vsc_unlock(dev); 88 89 return ret; 90 } 91 92 static int unlock_sem_sw_reset(struct mlx5_core_dev *dev) 93 { 94 int ret; 95 96 /* Lock GW access */ 97 ret = -mlx5_vsc_lock(dev); 98 if (ret) { 99 mlx5_core_warn(dev, "Timed out locking gateway %d\n", ret); 100 return ret; 101 } 102 103 ret = -mlx5_vsc_unlock_addr_space(dev, MLX5_SEMAPHORE_SW_RESET); 104 105 /* Unlock GW access */ 106 mlx5_vsc_unlock(dev); 107 108 return ret; 109 } 110 111 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev) 112 { 113 return (ioread32be(&dev->iseg->cmdq_addr_l_sz) >> 8) & 7; 114 } 115 116 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state) 117 { 118 u32 cur_cmdq_addr_l_sz; 119 120 cur_cmdq_addr_l_sz = ioread32be(&dev->iseg->cmdq_addr_l_sz); 121 iowrite32be((cur_cmdq_addr_l_sz & 0xFFFFF000) | 122 state << MLX5_NIC_IFC_OFFSET, 123 &dev->iseg->cmdq_addr_l_sz); 124 } 125 126 static bool sensor_fw_synd_rfr(struct mlx5_core_dev *dev) 127 { 128 struct mlx5_core_health *health = &dev->priv.health; 129 struct mlx5_health_buffer __iomem *h = health->health; 130 u32 rfr = ioread32be(&h->rfr) >> MLX5_RFR_OFFSET; 131 u8 synd = ioread8(&h->synd); 132 133 if (rfr && synd) 134 mlx5_core_dbg(dev, "FW requests reset, synd: %d\n", synd); 135 return rfr && synd; 136 } 137 138 static void mlx5_trigger_cmd_completions(struct mlx5_core_dev *dev) 139 { 140 unsigned long flags; 141 u64 vector; 142 143 /* wait for pending handlers to complete */ 144 synchronize_irq(dev->priv.msix_arr[MLX5_EQ_VEC_CMD].vector); 145 spin_lock_irqsave(&dev->cmd.alloc_lock, flags); 146 vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1); 147 if (!vector) 148 goto no_trig; 149 150 vector |= MLX5_TRIGGERED_CMD_COMP; 151 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags); 152 153 mlx5_core_dbg(dev, "vector 0x%jx\n", (uintmax_t)vector); 154 mlx5_cmd_comp_handler(dev, vector, MLX5_CMD_MODE_EVENTS); 155 return; 156 157 no_trig: 158 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags); 159 } 160 161 static bool sensor_pci_no_comm(struct mlx5_core_dev *dev) 162 { 163 struct mlx5_core_health *health = &dev->priv.health; 164 struct mlx5_health_buffer __iomem *h = health->health; 165 bool err = ioread32be(&h->fw_ver) == 0xffffffff; 166 167 return err; 168 } 169 170 static bool sensor_nic_disabled(struct mlx5_core_dev *dev) 171 { 172 return mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED; 173 } 174 175 static bool sensor_nic_sw_reset(struct mlx5_core_dev *dev) 176 { 177 return mlx5_get_nic_state(dev) == MLX5_NIC_IFC_SW_RESET; 178 } 179 180 static u32 check_fatal_sensors(struct mlx5_core_dev *dev) 181 { 182 if (sensor_pci_no_comm(dev)) 183 return MLX5_SENSOR_PCI_COMM_ERR; 184 if (pci_channel_offline(dev->pdev)) 185 return MLX5_SENSOR_PCI_ERR; 186 if (sensor_nic_disabled(dev)) 187 return MLX5_SENSOR_NIC_DISABLED; 188 if (sensor_nic_sw_reset(dev)) 189 return MLX5_SENSOR_NIC_SW_RESET; 190 if (sensor_fw_synd_rfr(dev)) 191 return MLX5_SENSOR_FW_SYND_RFR; 192 193 return MLX5_SENSOR_NO_ERR; 194 } 195 196 static void reset_fw_if_needed(struct mlx5_core_dev *dev) 197 { 198 bool supported; 199 u32 cmdq_addr, fatal_error; 200 201 if (!mlx5_fw_reset_enable) 202 return; 203 supported = (ioread32be(&dev->iseg->initializing) >> 204 MLX5_FW_RESET_SUPPORTED_OFFSET) & 1; 205 if (!supported) 206 return; 207 208 /* The reset only needs to be issued by one PF. The health buffer is 209 * shared between all functions, and will be cleared during a reset. 210 * Check again to avoid a redundant 2nd reset. If the fatal erros was 211 * PCI related a reset won't help. 212 */ 213 fatal_error = check_fatal_sensors(dev); 214 if (fatal_error == MLX5_SENSOR_PCI_COMM_ERR || 215 fatal_error == MLX5_SENSOR_NIC_DISABLED || 216 fatal_error == MLX5_SENSOR_NIC_SW_RESET) { 217 mlx5_core_warn(dev, "Not issuing FW reset. Either it's already done or won't help.\n"); 218 return; 219 } 220 221 mlx5_core_warn(dev, "Issuing FW Reset\n"); 222 /* Write the NIC interface field to initiate the reset, the command 223 * interface address also resides here, don't overwrite it. 224 */ 225 cmdq_addr = ioread32be(&dev->iseg->cmdq_addr_l_sz); 226 iowrite32be((cmdq_addr & 0xFFFFF000) | 227 MLX5_NIC_IFC_SW_RESET << MLX5_NIC_IFC_OFFSET, 228 &dev->iseg->cmdq_addr_l_sz); 229 } 230 231 static bool 232 mlx5_health_allow_reset(struct mlx5_core_dev *dev) 233 { 234 struct mlx5_core_health *health = &dev->priv.health; 235 unsigned int delta; 236 bool ret; 237 238 if (health->last_reset_req != 0) { 239 delta = ticks - health->last_reset_req; 240 delta /= hz; 241 ret = delta >= sw_reset_to; 242 } else { 243 ret = true; 244 } 245 246 /* 247 * In principle, ticks may be 0. Setting it to off by one (-1) 248 * to prevent certain reset in next request. 249 */ 250 health->last_reset_req = ticks ? : -1; 251 if (!ret) 252 mlx5_core_warn(dev, "Firmware reset elided due to " 253 "auto-reset frequency threshold.\n"); 254 return (ret); 255 } 256 257 #define MLX5_CRDUMP_WAIT_MS 60000 258 #define MLX5_FW_RESET_WAIT_MS 1000 259 #define MLX5_NIC_STATE_POLL_MS 5 260 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force) 261 { 262 int end, delay_ms = MLX5_CRDUMP_WAIT_MS; 263 u32 fatal_error; 264 int lock = -EBUSY; 265 266 fatal_error = check_fatal_sensors(dev); 267 268 if (fatal_error || force) { 269 if (xchg(&dev->state, MLX5_DEVICE_STATE_INTERNAL_ERROR) == 270 MLX5_DEVICE_STATE_INTERNAL_ERROR) 271 return; 272 if (!force) 273 mlx5_core_err(dev, "internal state error detected\n"); 274 mlx5_trigger_cmd_completions(dev); 275 } 276 277 mutex_lock(&dev->intf_state_mutex); 278 279 if (force) 280 goto err_state_done; 281 282 if (fatal_error == MLX5_SENSOR_FW_SYND_RFR && 283 mlx5_health_allow_reset(dev)) { 284 /* Get cr-dump and reset FW semaphore */ 285 if (mlx5_core_is_pf(dev)) 286 lock = lock_sem_sw_reset(dev); 287 288 /* Execute cr-dump and SW reset */ 289 if (lock != -EBUSY) { 290 mlx5_fwdump(dev); 291 reset_fw_if_needed(dev); 292 delay_ms = MLX5_FW_RESET_WAIT_MS; 293 } 294 } 295 296 /* Recover from SW reset */ 297 end = jiffies + msecs_to_jiffies(delay_ms); 298 do { 299 if (sensor_nic_disabled(dev)) 300 break; 301 302 msleep(MLX5_NIC_STATE_POLL_MS); 303 } while (!time_after(jiffies, end)); 304 305 if (!sensor_nic_disabled(dev)) { 306 dev_err(&dev->pdev->dev, "NIC IFC still %d after %ums.\n", 307 mlx5_get_nic_state(dev), delay_ms); 308 } 309 310 /* Release FW semaphore if you are the lock owner */ 311 if (!lock) 312 unlock_sem_sw_reset(dev); 313 314 mlx5_core_err(dev, "system error event triggered\n"); 315 316 err_state_done: 317 mlx5_core_event(dev, MLX5_DEV_EVENT_SYS_ERROR, 1); 318 mutex_unlock(&dev->intf_state_mutex); 319 } 320 321 static void mlx5_handle_bad_state(struct mlx5_core_dev *dev) 322 { 323 u8 nic_mode = mlx5_get_nic_state(dev); 324 325 if (nic_mode == MLX5_NIC_IFC_SW_RESET) { 326 /* The IFC mode field is 3 bits, so it will read 0x7 in two cases: 327 * 1. PCI has been disabled (ie. PCI-AER, PF driver unloaded 328 * and this is a VF), this is not recoverable by SW reset. 329 * Logging of this is handled elsewhere. 330 * 2. FW reset has been issued by another function, driver can 331 * be reloaded to recover after the mode switches to 332 * MLX5_NIC_IFC_DISABLED. 333 */ 334 if (dev->priv.health.fatal_error != MLX5_SENSOR_PCI_COMM_ERR) 335 mlx5_core_warn(dev, "NIC SW reset is already progress\n"); 336 else 337 mlx5_core_warn(dev, "Communication with FW over the PCI link is down\n"); 338 } else { 339 mlx5_core_warn(dev, "NIC mode %d\n", nic_mode); 340 } 341 342 mlx5_disable_device(dev); 343 } 344 345 #define MLX5_FW_RESET_WAIT_MS 1000 346 #define MLX5_NIC_STATE_POLL_MS 5 347 static void health_recover(struct work_struct *work) 348 { 349 unsigned long end = jiffies + msecs_to_jiffies(MLX5_FW_RESET_WAIT_MS); 350 struct mlx5_core_health *health; 351 struct delayed_work *dwork; 352 struct mlx5_core_dev *dev; 353 struct mlx5_priv *priv; 354 bool recover = true; 355 u8 nic_mode; 356 357 dwork = container_of(work, struct delayed_work, work); 358 health = container_of(dwork, struct mlx5_core_health, recover_work); 359 priv = container_of(health, struct mlx5_priv, health); 360 dev = container_of(priv, struct mlx5_core_dev, priv); 361 362 mtx_lock(&Giant); /* XXX newbus needs this */ 363 364 if (sensor_pci_no_comm(dev)) { 365 dev_err(&dev->pdev->dev, "health recovery flow aborted, PCI reads still not working\n"); 366 recover = false; 367 } 368 369 nic_mode = mlx5_get_nic_state(dev); 370 while (nic_mode != MLX5_NIC_IFC_DISABLED && 371 !time_after(jiffies, end)) { 372 msleep(MLX5_NIC_STATE_POLL_MS); 373 nic_mode = mlx5_get_nic_state(dev); 374 } 375 376 if (nic_mode != MLX5_NIC_IFC_DISABLED) { 377 dev_err(&dev->pdev->dev, "health recovery flow aborted, unexpected NIC IFC mode %d.\n", 378 nic_mode); 379 recover = false; 380 } 381 382 if (recover) { 383 dev_err(&dev->pdev->dev, "starting health recovery flow\n"); 384 mlx5_recover_device(dev); 385 } 386 387 mtx_unlock(&Giant); 388 } 389 390 /* How much time to wait until health resetting the driver (in msecs) */ 391 #define MLX5_RECOVERY_DELAY_MSECS 60000 392 #define MLX5_RECOVERY_NO_DELAY 0 393 static unsigned long get_recovery_delay(struct mlx5_core_dev *dev) 394 { 395 return dev->priv.health.fatal_error == MLX5_SENSOR_PCI_ERR || 396 dev->priv.health.fatal_error == MLX5_SENSOR_PCI_COMM_ERR ? 397 MLX5_RECOVERY_DELAY_MSECS : MLX5_RECOVERY_NO_DELAY; 398 } 399 400 static void health_care(struct work_struct *work) 401 { 402 struct mlx5_core_health *health; 403 unsigned long recover_delay; 404 struct mlx5_core_dev *dev; 405 struct mlx5_priv *priv; 406 unsigned long flags; 407 408 health = container_of(work, struct mlx5_core_health, work); 409 priv = container_of(health, struct mlx5_priv, health); 410 dev = container_of(priv, struct mlx5_core_dev, priv); 411 412 mlx5_core_warn(dev, "handling bad device here\n"); 413 mlx5_handle_bad_state(dev); 414 recover_delay = msecs_to_jiffies(get_recovery_delay(dev)); 415 416 spin_lock_irqsave(&health->wq_lock, flags); 417 if (!test_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags)) { 418 mlx5_core_warn(dev, "Scheduling recovery work with %lums delay\n", 419 recover_delay); 420 schedule_delayed_work(&health->recover_work, recover_delay); 421 } else { 422 dev_err(&dev->pdev->dev, 423 "new health works are not permitted at this stage\n"); 424 } 425 spin_unlock_irqrestore(&health->wq_lock, flags); 426 } 427 428 static int get_next_poll_jiffies(void) 429 { 430 unsigned long next; 431 432 get_random_bytes(&next, sizeof(next)); 433 next %= HZ; 434 next += jiffies + MLX5_HEALTH_POLL_INTERVAL; 435 436 return next; 437 } 438 439 void mlx5_trigger_health_work(struct mlx5_core_dev *dev) 440 { 441 struct mlx5_core_health *health = &dev->priv.health; 442 unsigned long flags; 443 444 spin_lock_irqsave(&health->wq_lock, flags); 445 if (!test_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags)) 446 queue_work(health->wq, &health->work); 447 else 448 dev_err(&dev->pdev->dev, 449 "new health works are not permitted at this stage\n"); 450 spin_unlock_irqrestore(&health->wq_lock, flags); 451 } 452 453 static const char *hsynd_str(u8 synd) 454 { 455 switch (synd) { 456 case MLX5_HEALTH_SYNDR_FW_ERR: 457 return "firmware internal error"; 458 case MLX5_HEALTH_SYNDR_IRISC_ERR: 459 return "irisc not responding"; 460 case MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR: 461 return "unrecoverable hardware error"; 462 case MLX5_HEALTH_SYNDR_CRC_ERR: 463 return "firmware CRC error"; 464 case MLX5_HEALTH_SYNDR_FETCH_PCI_ERR: 465 return "ICM fetch PCI error"; 466 case MLX5_HEALTH_SYNDR_HW_FTL_ERR: 467 return "HW fatal error\n"; 468 case MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR: 469 return "async EQ buffer overrun"; 470 case MLX5_HEALTH_SYNDR_EQ_ERR: 471 return "EQ error"; 472 case MLX5_HEALTH_SYNDR_EQ_INV: 473 return "Invalid EQ referenced"; 474 case MLX5_HEALTH_SYNDR_FFSER_ERR: 475 return "FFSER error"; 476 case MLX5_HEALTH_SYNDR_HIGH_TEMP: 477 return "High temprature"; 478 default: 479 return "unrecognized error"; 480 } 481 } 482 483 static void print_health_info(struct mlx5_core_dev *dev) 484 { 485 struct mlx5_core_health *health = &dev->priv.health; 486 struct mlx5_health_buffer __iomem *h = health->health; 487 char fw_str[18]; 488 u32 fw; 489 int i; 490 491 /* If the syndrom is 0, the device is OK and no need to print buffer */ 492 if (!ioread8(&h->synd)) 493 return; 494 495 for (i = 0; i < ARRAY_SIZE(h->assert_var); i++) 496 printf("mlx5_core: INFO: ""assert_var[%d] 0x%08x\n", i, ioread32be(h->assert_var + i)); 497 498 printf("mlx5_core: INFO: ""assert_exit_ptr 0x%08x\n", ioread32be(&h->assert_exit_ptr)); 499 printf("mlx5_core: INFO: ""assert_callra 0x%08x\n", ioread32be(&h->assert_callra)); 500 snprintf(fw_str, sizeof(fw_str), "%d.%d.%d", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); 501 printf("mlx5_core: INFO: ""fw_ver %s\n", fw_str); 502 printf("mlx5_core: INFO: ""hw_id 0x%08x\n", ioread32be(&h->hw_id)); 503 printf("mlx5_core: INFO: ""irisc_index %d\n", ioread8(&h->irisc_index)); 504 printf("mlx5_core: INFO: ""synd 0x%x: %s\n", ioread8(&h->synd), hsynd_str(ioread8(&h->synd))); 505 printf("mlx5_core: INFO: ""ext_synd 0x%04x\n", ioread16be(&h->ext_synd)); 506 fw = ioread32be(&h->fw_ver); 507 printf("mlx5_core: INFO: ""raw fw_ver 0x%08x\n", fw); 508 } 509 510 static void health_watchdog(struct work_struct *work) 511 { 512 struct mlx5_core_dev *dev; 513 u16 power; 514 u8 status; 515 int err; 516 517 dev = container_of(work, struct mlx5_core_dev, priv.health.work_watchdog); 518 519 if (!MLX5_CAP_GEN(dev, mcam_reg) || 520 !MLX5_CAP_MCAM_FEATURE(dev, pcie_status_and_power)) 521 return; 522 523 err = mlx5_pci_read_power_status(dev, &power, &status); 524 if (err < 0) { 525 mlx5_core_warn(dev, "Failed reading power status: %d\n", err); 526 return; 527 } 528 529 dev->pwr_value = power; 530 531 if (dev->pwr_status != status) { 532 device_t bsddev = dev->pdev->dev.bsddev; 533 534 switch (status) { 535 case 0: 536 dev->pwr_status = status; 537 device_printf(bsddev, "PCI power is not published by the PCIe slot.\n"); 538 break; 539 case 1: 540 dev->pwr_status = status; 541 device_printf(bsddev, "PCIe slot advertised sufficient power (%uW).\n", power); 542 break; 543 case 2: 544 dev->pwr_status = status; 545 device_printf(bsddev, "WARN: Detected insufficient power on the PCIe slot (%uW).\n", power); 546 break; 547 default: 548 dev->pwr_status = 0; 549 device_printf(bsddev, "WARN: Unknown power state detected(%d).\n", status); 550 break; 551 } 552 } 553 } 554 555 void 556 mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev) 557 { 558 struct mlx5_core_health *health = &dev->priv.health; 559 unsigned long flags; 560 561 spin_lock_irqsave(&health->wq_lock, flags); 562 if (!test_bit(MLX5_DROP_NEW_WATCHDOG_WORK, &health->flags)) 563 queue_work(health->wq_watchdog, &health->work_watchdog); 564 else 565 dev_err(&dev->pdev->dev, 566 "scheduling watchdog is not permitted at this stage\n"); 567 spin_unlock_irqrestore(&health->wq_lock, flags); 568 } 569 570 static void poll_health(unsigned long data) 571 { 572 struct mlx5_core_dev *dev = (struct mlx5_core_dev *)data; 573 struct mlx5_core_health *health = &dev->priv.health; 574 u32 fatal_error; 575 u32 count; 576 577 if (dev->state != MLX5_DEVICE_STATE_UP) 578 return; 579 580 count = ioread32be(health->health_counter); 581 if (count == health->prev) 582 ++health->miss_counter; 583 else 584 health->miss_counter = 0; 585 586 health->prev = count; 587 if (health->miss_counter == MAX_MISSES) { 588 mlx5_core_err(dev, "device's health compromised - reached miss count\n"); 589 print_health_info(dev); 590 } 591 592 fatal_error = check_fatal_sensors(dev); 593 594 if (fatal_error && !health->fatal_error) { 595 mlx5_core_err(dev, "Fatal error %u detected\n", fatal_error); 596 dev->priv.health.fatal_error = fatal_error; 597 print_health_info(dev); 598 mlx5_trigger_health_work(dev); 599 } 600 601 mod_timer(&health->timer, get_next_poll_jiffies()); 602 } 603 604 void mlx5_start_health_poll(struct mlx5_core_dev *dev) 605 { 606 struct mlx5_core_health *health = &dev->priv.health; 607 608 init_timer(&health->timer); 609 health->fatal_error = MLX5_SENSOR_NO_ERR; 610 clear_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags); 611 clear_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags); 612 clear_bit(MLX5_DROP_NEW_WATCHDOG_WORK, &health->flags); 613 health->health = &dev->iseg->health; 614 health->health_counter = &dev->iseg->health_counter; 615 616 setup_timer(&health->timer, poll_health, (unsigned long)dev); 617 mod_timer(&health->timer, 618 round_jiffies(jiffies + MLX5_HEALTH_POLL_INTERVAL)); 619 620 /* do initial PCI power state readout */ 621 mlx5_trigger_health_watchdog(dev); 622 } 623 624 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health) 625 { 626 struct mlx5_core_health *health = &dev->priv.health; 627 unsigned long flags; 628 629 if (disable_health) { 630 spin_lock_irqsave(&health->wq_lock, flags); 631 set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags); 632 set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags); 633 set_bit(MLX5_DROP_NEW_WATCHDOG_WORK, &health->flags); 634 spin_unlock_irqrestore(&health->wq_lock, flags); 635 } 636 637 del_timer_sync(&health->timer); 638 } 639 640 void mlx5_drain_health_wq(struct mlx5_core_dev *dev) 641 { 642 struct mlx5_core_health *health = &dev->priv.health; 643 unsigned long flags; 644 645 spin_lock_irqsave(&health->wq_lock, flags); 646 set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags); 647 set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags); 648 set_bit(MLX5_DROP_NEW_WATCHDOG_WORK, &health->flags); 649 spin_unlock_irqrestore(&health->wq_lock, flags); 650 cancel_delayed_work_sync(&health->recover_work); 651 cancel_work_sync(&health->work); 652 cancel_work_sync(&health->work_watchdog); 653 } 654 655 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev) 656 { 657 struct mlx5_core_health *health = &dev->priv.health; 658 unsigned long flags; 659 660 spin_lock_irqsave(&health->wq_lock, flags); 661 set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags); 662 spin_unlock_irqrestore(&health->wq_lock, flags); 663 cancel_delayed_work_sync(&dev->priv.health.recover_work); 664 } 665 666 void mlx5_health_cleanup(struct mlx5_core_dev *dev) 667 { 668 struct mlx5_core_health *health = &dev->priv.health; 669 670 destroy_workqueue(health->wq); 671 destroy_workqueue(health->wq_watchdog); 672 } 673 674 int mlx5_health_init(struct mlx5_core_dev *dev) 675 { 676 struct mlx5_core_health *health; 677 char name[64]; 678 679 health = &dev->priv.health; 680 681 snprintf(name, sizeof(name), "%s-rec", dev_name(&dev->pdev->dev)); 682 health->wq = create_singlethread_workqueue(name); 683 if (!health->wq) 684 return -ENOMEM; 685 686 snprintf(name, sizeof(name), "%s-wdg", dev_name(&dev->pdev->dev)); 687 health->wq_watchdog = create_singlethread_workqueue(name); 688 if (!health->wq_watchdog) { 689 destroy_workqueue(health->wq); 690 return -ENOMEM; 691 } 692 693 spin_lock_init(&health->wq_lock); 694 INIT_WORK(&health->work, health_care); 695 INIT_WORK(&health->work_watchdog, health_watchdog); 696 INIT_DELAYED_WORK(&health->recover_work, health_recover); 697 698 return 0; 699 } 700