1 /*- 2 * Copyright (c) 2013-2020, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/kmod.h> 29 #include <linux/module.h> 30 #include <linux/errno.h> 31 #include <linux/pci.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/slab.h> 34 #include <linux/io-mapping.h> 35 #include <linux/interrupt.h> 36 #include <linux/hardirq.h> 37 #include <dev/mlx5/driver.h> 38 #include <dev/mlx5/cq.h> 39 #include <dev/mlx5/qp.h> 40 #include <dev/mlx5/srq.h> 41 #include <dev/mlx5/mpfs.h> 42 #include <dev/mlx5/vport.h> 43 #include <linux/delay.h> 44 #include <dev/mlx5/mlx5_ifc.h> 45 #include <dev/mlx5/mlx5_fpga/core.h> 46 #include <dev/mlx5/mlx5_lib/mlx5.h> 47 #include "mlx5_core.h" 48 #include "eswitch.h" 49 #include "fs_core.h" 50 #ifdef PCI_IOV 51 #include <sys/nv.h> 52 #include <dev/pci/pci_iov.h> 53 #include <sys/iov_schema.h> 54 #endif 55 56 static const char mlx5_version[] = "Mellanox Core driver " 57 DRIVER_VERSION " (" DRIVER_RELDATE ")"; 58 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 59 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); 60 MODULE_LICENSE("Dual BSD/GPL"); 61 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1); 62 MODULE_DEPEND(mlx5, mlxfw, 1, 1, 1); 63 MODULE_DEPEND(mlx5, firmware, 1, 1, 1); 64 MODULE_VERSION(mlx5, 1); 65 66 SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 67 "mlx5 hardware controls"); 68 69 int mlx5_core_debug_mask; 70 SYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN, 71 &mlx5_core_debug_mask, 0, 72 "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 73 74 #define MLX5_DEFAULT_PROF 2 75 static int mlx5_prof_sel = MLX5_DEFAULT_PROF; 76 SYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN, 77 &mlx5_prof_sel, 0, 78 "profile selector. Valid range 0 - 2"); 79 80 static int mlx5_fast_unload_enabled = 1; 81 SYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN, 82 &mlx5_fast_unload_enabled, 0, 83 "Set to enable fast unload. Clear to disable."); 84 85 #define NUMA_NO_NODE -1 86 87 static LIST_HEAD(intf_list); 88 static LIST_HEAD(dev_list); 89 static DEFINE_MUTEX(intf_mutex); 90 91 struct mlx5_device_context { 92 struct list_head list; 93 struct mlx5_interface *intf; 94 void *context; 95 }; 96 97 enum { 98 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 99 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 100 }; 101 102 static struct mlx5_profile profiles[] = { 103 [0] = { 104 .mask = 0, 105 }, 106 [1] = { 107 .mask = MLX5_PROF_MASK_QP_SIZE, 108 .log_max_qp = 12, 109 }, 110 [2] = { 111 .mask = MLX5_PROF_MASK_QP_SIZE | 112 MLX5_PROF_MASK_MR_CACHE, 113 .log_max_qp = 17, 114 .mr_cache[0] = { 115 .size = 500, 116 .limit = 250 117 }, 118 .mr_cache[1] = { 119 .size = 500, 120 .limit = 250 121 }, 122 .mr_cache[2] = { 123 .size = 500, 124 .limit = 250 125 }, 126 .mr_cache[3] = { 127 .size = 500, 128 .limit = 250 129 }, 130 .mr_cache[4] = { 131 .size = 500, 132 .limit = 250 133 }, 134 .mr_cache[5] = { 135 .size = 500, 136 .limit = 250 137 }, 138 .mr_cache[6] = { 139 .size = 500, 140 .limit = 250 141 }, 142 .mr_cache[7] = { 143 .size = 500, 144 .limit = 250 145 }, 146 .mr_cache[8] = { 147 .size = 500, 148 .limit = 250 149 }, 150 .mr_cache[9] = { 151 .size = 500, 152 .limit = 250 153 }, 154 .mr_cache[10] = { 155 .size = 500, 156 .limit = 250 157 }, 158 .mr_cache[11] = { 159 .size = 500, 160 .limit = 250 161 }, 162 .mr_cache[12] = { 163 .size = 64, 164 .limit = 32 165 }, 166 .mr_cache[13] = { 167 .size = 32, 168 .limit = 16 169 }, 170 .mr_cache[14] = { 171 .size = 16, 172 .limit = 8 173 }, 174 }, 175 [3] = { 176 .mask = MLX5_PROF_MASK_QP_SIZE, 177 .log_max_qp = 17, 178 }, 179 }; 180 181 #ifdef PCI_IOV 182 static const char iov_mac_addr_name[] = "mac-addr"; 183 static const char iov_node_guid_name[] = "node-guid"; 184 static const char iov_port_guid_name[] = "port-guid"; 185 #endif 186 187 static int set_dma_caps(struct pci_dev *pdev) 188 { 189 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 190 int err; 191 192 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 193 if (err) { 194 mlx5_core_warn(dev, "couldn't set 64-bit PCI DMA mask\n"); 195 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 196 if (err) { 197 mlx5_core_err(dev, "Can't set PCI DMA mask, aborting\n"); 198 return err; 199 } 200 } 201 202 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 203 if (err) { 204 mlx5_core_warn(dev, "couldn't set 64-bit consistent PCI DMA mask\n"); 205 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 206 if (err) { 207 mlx5_core_err(dev, "Can't set consistent PCI DMA mask, aborting\n"); 208 return err; 209 } 210 } 211 212 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 213 return err; 214 } 215 216 int mlx5_pci_read_power_status(struct mlx5_core_dev *dev, 217 u16 *p_power, u8 *p_status) 218 { 219 u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {}; 220 u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {}; 221 int err; 222 223 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), 224 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN, 0, 0); 225 226 *p_status = MLX5_GET(mpein_reg, out, pwr_status); 227 *p_power = MLX5_GET(mpein_reg, out, pci_power); 228 return err; 229 } 230 231 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 232 { 233 struct pci_dev *pdev = dev->pdev; 234 int err = 0; 235 236 mutex_lock(&dev->pci_status_mutex); 237 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 238 err = pci_enable_device(pdev); 239 if (!err) 240 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 241 } 242 mutex_unlock(&dev->pci_status_mutex); 243 244 return err; 245 } 246 247 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 248 { 249 struct pci_dev *pdev = dev->pdev; 250 251 mutex_lock(&dev->pci_status_mutex); 252 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 253 pci_disable_device(pdev); 254 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 255 } 256 mutex_unlock(&dev->pci_status_mutex); 257 } 258 259 static int request_bar(struct pci_dev *pdev) 260 { 261 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 262 int err = 0; 263 264 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 265 mlx5_core_err(dev, "Missing registers BAR, aborting\n"); 266 return -ENODEV; 267 } 268 269 err = pci_request_regions(pdev, DRIVER_NAME); 270 if (err) 271 mlx5_core_err(dev, "Couldn't get PCI resources, aborting\n"); 272 273 return err; 274 } 275 276 static void release_bar(struct pci_dev *pdev) 277 { 278 pci_release_regions(pdev); 279 } 280 281 static int mlx5_enable_msix(struct mlx5_core_dev *dev) 282 { 283 struct mlx5_priv *priv = &dev->priv; 284 struct mlx5_eq_table *table = &priv->eq_table; 285 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); 286 int limit = dev->msix_eqvec; 287 int nvec = MLX5_EQ_VEC_COMP_BASE; 288 int i; 289 290 if (limit > 0) 291 nvec += limit; 292 else 293 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus(); 294 295 if (nvec > num_eqs) 296 nvec = num_eqs; 297 if (nvec > 256) 298 nvec = 256; /* limit of firmware API */ 299 if (nvec <= MLX5_EQ_VEC_COMP_BASE) 300 return -ENOMEM; 301 302 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL); 303 304 for (i = 0; i < nvec; i++) 305 priv->msix_arr[i].entry = i; 306 307 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, 308 MLX5_EQ_VEC_COMP_BASE + 1, nvec); 309 if (nvec < 0) 310 return nvec; 311 312 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; 313 return 0; 314 } 315 316 static void mlx5_disable_msix(struct mlx5_core_dev *dev) 317 { 318 struct mlx5_priv *priv = &dev->priv; 319 320 pci_disable_msix(dev->pdev); 321 kfree(priv->msix_arr); 322 } 323 324 struct mlx5_reg_host_endianess { 325 u8 he; 326 u8 rsvd[15]; 327 }; 328 329 330 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 331 332 enum { 333 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 334 MLX5_DEV_CAP_FLAG_DCT | 335 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR, 336 }; 337 338 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 339 { 340 switch (size) { 341 case 128: 342 return 0; 343 case 256: 344 return 1; 345 case 512: 346 return 2; 347 case 1024: 348 return 3; 349 case 2048: 350 return 4; 351 case 4096: 352 return 5; 353 default: 354 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 355 return 0; 356 } 357 } 358 359 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 360 enum mlx5_cap_type cap_type, 361 enum mlx5_cap_mode cap_mode) 362 { 363 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 364 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 365 void *out, *hca_caps; 366 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 367 int err; 368 369 memset(in, 0, sizeof(in)); 370 out = kzalloc(out_sz, GFP_KERNEL); 371 372 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 373 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 374 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 375 if (err) { 376 mlx5_core_warn(dev, 377 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 378 cap_type, cap_mode, err); 379 goto query_ex; 380 } 381 382 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 383 384 switch (cap_mode) { 385 case HCA_CAP_OPMOD_GET_MAX: 386 memcpy(dev->hca_caps_max[cap_type], hca_caps, 387 MLX5_UN_SZ_BYTES(hca_cap_union)); 388 break; 389 case HCA_CAP_OPMOD_GET_CUR: 390 memcpy(dev->hca_caps_cur[cap_type], hca_caps, 391 MLX5_UN_SZ_BYTES(hca_cap_union)); 392 break; 393 default: 394 mlx5_core_warn(dev, 395 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 396 cap_type, cap_mode); 397 err = -EINVAL; 398 break; 399 } 400 query_ex: 401 kfree(out); 402 return err; 403 } 404 405 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 406 { 407 int ret; 408 409 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 410 if (ret) 411 return ret; 412 413 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 414 } 415 416 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz) 417 { 418 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 419 420 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 421 422 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 423 } 424 425 static int handle_hca_cap(struct mlx5_core_dev *dev) 426 { 427 void *set_ctx = NULL; 428 struct mlx5_profile *prof = dev->profile; 429 int err = -ENOMEM; 430 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 431 void *set_hca_cap; 432 433 set_ctx = kzalloc(set_sz, GFP_KERNEL); 434 435 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 436 if (err) 437 goto query_ex; 438 439 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 440 capability); 441 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], 442 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 443 444 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 445 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 446 128); 447 /* we limit the size of the pkey table to 128 entries for now */ 448 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 449 to_fw_pkey_sz(dev, 128)); 450 451 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 452 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 453 prof->log_max_qp); 454 455 /* disable cmdif checksum */ 456 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 457 458 /* Enable 4K UAR only when HCA supports it and page size is bigger 459 * than 4K. 460 */ 461 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 462 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 463 464 /* enable drain sigerr */ 465 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1); 466 467 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 468 469 err = set_caps(dev, set_ctx, set_sz); 470 471 query_ex: 472 kfree(set_ctx); 473 return err; 474 } 475 476 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 477 { 478 void *set_ctx; 479 void *set_hca_cap; 480 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 481 int req_endianness; 482 int err; 483 484 if (MLX5_CAP_GEN(dev, atomic)) { 485 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 486 if (err) 487 return err; 488 } else { 489 return 0; 490 } 491 492 req_endianness = 493 MLX5_CAP_ATOMIC(dev, 494 supported_atomic_req_8B_endianess_mode_1); 495 496 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 497 return 0; 498 499 set_ctx = kzalloc(set_sz, GFP_KERNEL); 500 if (!set_ctx) 501 return -ENOMEM; 502 503 MLX5_SET(set_hca_cap_in, set_ctx, op_mod, 504 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1); 505 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 506 507 /* Set requestor to host endianness */ 508 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, 509 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 510 511 err = set_caps(dev, set_ctx, set_sz); 512 513 kfree(set_ctx); 514 return err; 515 } 516 517 static int set_hca_ctrl(struct mlx5_core_dev *dev) 518 { 519 struct mlx5_reg_host_endianess he_in; 520 struct mlx5_reg_host_endianess he_out; 521 int err; 522 523 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH && 524 !MLX5_CAP_GEN(dev, roce)) 525 return 0; 526 527 memset(&he_in, 0, sizeof(he_in)); 528 he_in.he = MLX5_SET_HOST_ENDIANNESS; 529 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 530 &he_out, sizeof(he_out), 531 MLX5_REG_HOST_ENDIANNESS, 0, 1); 532 return err; 533 } 534 535 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 536 { 537 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 538 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 539 540 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 541 MLX5_SET(enable_hca_in, in, function_id, func_id); 542 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 543 } 544 545 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev) 546 { 547 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 548 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 549 550 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 551 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 552 } 553 554 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 555 { 556 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 557 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 558 u32 sup_issi; 559 int err; 560 561 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 562 563 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out)); 564 if (err) { 565 u32 syndrome; 566 u8 status; 567 568 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 569 if (status == MLX5_CMD_STAT_BAD_OP_ERR) { 570 mlx5_core_dbg(dev, "Only ISSI 0 is supported\n"); 571 return 0; 572 } 573 574 mlx5_core_err(dev, "failed to query ISSI\n"); 575 return err; 576 } 577 578 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 579 580 if (sup_issi & (1 << 1)) { 581 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 582 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 583 584 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 585 MLX5_SET(set_issi_in, set_in, current_issi, 1); 586 587 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out)); 588 if (err) { 589 mlx5_core_err(dev, "failed to set ISSI=1 err(%d)\n", err); 590 return err; 591 } 592 593 dev->issi = 1; 594 595 return 0; 596 } else if (sup_issi & (1 << 0)) { 597 return 0; 598 } 599 600 return -ENOTSUPP; 601 } 602 603 604 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn) 605 { 606 struct mlx5_eq_table *table = &dev->priv.eq_table; 607 struct mlx5_eq *eq; 608 int err = -ENOENT; 609 610 spin_lock(&table->lock); 611 list_for_each_entry(eq, &table->comp_eqs_list, list) { 612 if (eq->index == vector) { 613 *eqn = eq->eqn; 614 *irqn = eq->irqn; 615 err = 0; 616 break; 617 } 618 } 619 spin_unlock(&table->lock); 620 621 return err; 622 } 623 EXPORT_SYMBOL(mlx5_vector2eqn); 624 625 static void free_comp_eqs(struct mlx5_core_dev *dev) 626 { 627 struct mlx5_eq_table *table = &dev->priv.eq_table; 628 struct mlx5_eq *eq, *n; 629 630 spin_lock(&table->lock); 631 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 632 list_del(&eq->list); 633 spin_unlock(&table->lock); 634 if (mlx5_destroy_unmap_eq(dev, eq)) 635 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", 636 eq->eqn); 637 kfree(eq); 638 spin_lock(&table->lock); 639 } 640 spin_unlock(&table->lock); 641 } 642 643 static int alloc_comp_eqs(struct mlx5_core_dev *dev) 644 { 645 struct mlx5_eq_table *table = &dev->priv.eq_table; 646 struct mlx5_eq *eq; 647 int ncomp_vec; 648 int nent; 649 int err; 650 int i; 651 652 INIT_LIST_HEAD(&table->comp_eqs_list); 653 ncomp_vec = table->num_comp_vectors; 654 nent = MLX5_COMP_EQ_SIZE; 655 for (i = 0; i < ncomp_vec; i++) { 656 eq = kzalloc(sizeof(*eq), GFP_KERNEL); 657 658 err = mlx5_create_map_eq(dev, eq, 659 i + MLX5_EQ_VEC_COMP_BASE, nent, 0); 660 if (err) { 661 kfree(eq); 662 goto clean; 663 } 664 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); 665 eq->index = i; 666 spin_lock(&table->lock); 667 list_add_tail(&eq->list, &table->comp_eqs_list); 668 spin_unlock(&table->lock); 669 } 670 671 return 0; 672 673 clean: 674 free_comp_eqs(dev); 675 return err; 676 } 677 678 static inline int fw_initializing(struct mlx5_core_dev *dev) 679 { 680 return ioread32be(&dev->iseg->initializing) >> 31; 681 } 682 683 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 684 u32 warn_time_mili) 685 { 686 int warn = jiffies + msecs_to_jiffies(warn_time_mili); 687 int end = jiffies + msecs_to_jiffies(max_wait_mili); 688 int err = 0; 689 690 MPASS(max_wait_mili > warn_time_mili); 691 692 while (fw_initializing(dev) == 1) { 693 if (time_after(jiffies, end)) { 694 err = -EBUSY; 695 break; 696 } 697 if (warn_time_mili && time_after(jiffies, warn)) { 698 mlx5_core_warn(dev, 699 "Waiting for FW initialization, timeout abort in %u s\n", 700 (unsigned)(jiffies_to_msecs(end - warn) / 1000)); 701 warn = jiffies + msecs_to_jiffies(warn_time_mili); 702 } 703 msleep(FW_INIT_WAIT_MS); 704 } 705 706 if (err != 0) 707 mlx5_core_dbg(dev, "Full initializing bit dword = 0x%x\n", 708 ioread32be(&dev->iseg->initializing)); 709 710 return err; 711 } 712 713 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 714 { 715 struct mlx5_device_context *dev_ctx; 716 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 717 718 dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL); 719 if (!dev_ctx) 720 return; 721 722 dev_ctx->intf = intf; 723 CURVNET_SET_QUIET(vnet0); 724 dev_ctx->context = intf->add(dev); 725 CURVNET_RESTORE(); 726 727 if (dev_ctx->context) { 728 spin_lock_irq(&priv->ctx_lock); 729 list_add_tail(&dev_ctx->list, &priv->ctx_list); 730 spin_unlock_irq(&priv->ctx_lock); 731 } else { 732 kfree(dev_ctx); 733 } 734 } 735 736 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 737 { 738 struct mlx5_device_context *dev_ctx; 739 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 740 741 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 742 if (dev_ctx->intf == intf) { 743 spin_lock_irq(&priv->ctx_lock); 744 list_del(&dev_ctx->list); 745 spin_unlock_irq(&priv->ctx_lock); 746 747 intf->remove(dev, dev_ctx->context); 748 kfree(dev_ctx); 749 return; 750 } 751 } 752 753 int 754 mlx5_register_device(struct mlx5_core_dev *dev) 755 { 756 struct mlx5_priv *priv = &dev->priv; 757 struct mlx5_interface *intf; 758 759 mutex_lock(&intf_mutex); 760 list_add_tail(&priv->dev_list, &dev_list); 761 list_for_each_entry(intf, &intf_list, list) 762 mlx5_add_device(intf, priv); 763 mutex_unlock(&intf_mutex); 764 765 return 0; 766 } 767 768 void 769 mlx5_unregister_device(struct mlx5_core_dev *dev) 770 { 771 struct mlx5_priv *priv = &dev->priv; 772 struct mlx5_interface *intf; 773 774 mutex_lock(&intf_mutex); 775 list_for_each_entry(intf, &intf_list, list) 776 mlx5_remove_device(intf, priv); 777 list_del(&priv->dev_list); 778 mutex_unlock(&intf_mutex); 779 } 780 781 int mlx5_register_interface(struct mlx5_interface *intf) 782 { 783 struct mlx5_priv *priv; 784 785 if (!intf->add || !intf->remove) 786 return -EINVAL; 787 788 mutex_lock(&intf_mutex); 789 list_add_tail(&intf->list, &intf_list); 790 list_for_each_entry(priv, &dev_list, dev_list) 791 mlx5_add_device(intf, priv); 792 mutex_unlock(&intf_mutex); 793 794 return 0; 795 } 796 EXPORT_SYMBOL(mlx5_register_interface); 797 798 void mlx5_unregister_interface(struct mlx5_interface *intf) 799 { 800 struct mlx5_priv *priv; 801 802 mutex_lock(&intf_mutex); 803 list_for_each_entry(priv, &dev_list, dev_list) 804 mlx5_remove_device(intf, priv); 805 list_del(&intf->list); 806 mutex_unlock(&intf_mutex); 807 } 808 EXPORT_SYMBOL(mlx5_unregister_interface); 809 810 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) 811 { 812 struct mlx5_priv *priv = &mdev->priv; 813 struct mlx5_device_context *dev_ctx; 814 unsigned long flags; 815 void *result = NULL; 816 817 spin_lock_irqsave(&priv->ctx_lock, flags); 818 819 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) 820 if ((dev_ctx->intf->protocol == protocol) && 821 dev_ctx->intf->get_dev) { 822 result = dev_ctx->intf->get_dev(dev_ctx->context); 823 break; 824 } 825 826 spin_unlock_irqrestore(&priv->ctx_lock, flags); 827 828 return result; 829 } 830 EXPORT_SYMBOL(mlx5_get_protocol_dev); 831 832 static int mlx5_auto_fw_update; 833 SYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 834 &mlx5_auto_fw_update, 0, 835 "Allow automatic firmware update on driver start"); 836 static int 837 mlx5_firmware_update(struct mlx5_core_dev *dev) 838 { 839 const struct firmware *fw; 840 int err; 841 842 TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update); 843 if (!mlx5_auto_fw_update) 844 return (0); 845 fw = firmware_get("mlx5fw_mfa"); 846 if (fw) { 847 err = mlx5_firmware_flash(dev, fw); 848 firmware_put(fw, FIRMWARE_UNLOAD); 849 } 850 else 851 return (-ENOENT); 852 853 return err; 854 } 855 856 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 857 { 858 struct pci_dev *pdev = dev->pdev; 859 device_t bsddev; 860 int err; 861 862 pdev = dev->pdev; 863 bsddev = pdev->dev.bsddev; 864 pci_set_drvdata(dev->pdev, dev); 865 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 866 priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 867 868 mutex_init(&priv->pgdir_mutex); 869 INIT_LIST_HEAD(&priv->pgdir_list); 870 spin_lock_init(&priv->mkey_lock); 871 872 priv->numa_node = NUMA_NO_NODE; 873 874 err = mlx5_pci_enable_device(dev); 875 if (err) { 876 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 877 goto err_dbg; 878 } 879 880 err = request_bar(pdev); 881 if (err) { 882 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 883 goto err_disable; 884 } 885 886 pci_set_master(pdev); 887 888 err = set_dma_caps(pdev); 889 if (err) { 890 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 891 goto err_clr_master; 892 } 893 894 dev->iseg_base = pci_resource_start(dev->pdev, 0); 895 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 896 if (!dev->iseg) { 897 err = -ENOMEM; 898 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 899 goto err_clr_master; 900 } 901 902 return 0; 903 904 err_clr_master: 905 release_bar(dev->pdev); 906 err_disable: 907 mlx5_pci_disable_device(dev); 908 err_dbg: 909 return err; 910 } 911 912 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 913 { 914 #ifdef PCI_IOV 915 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) 916 pci_iov_detach(dev->pdev->dev.bsddev); 917 #endif 918 iounmap(dev->iseg); 919 release_bar(dev->pdev); 920 mlx5_pci_disable_device(dev); 921 } 922 923 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 924 { 925 int err; 926 927 err = mlx5_vsc_find_cap(dev); 928 if (err) 929 mlx5_core_warn(dev, "Unable to find vendor specific capabilities\n"); 930 931 err = mlx5_query_hca_caps(dev); 932 if (err) { 933 mlx5_core_err(dev, "query hca failed\n"); 934 goto out; 935 } 936 937 err = mlx5_query_board_id(dev); 938 if (err) { 939 mlx5_core_err(dev, "query board id failed\n"); 940 goto out; 941 } 942 943 err = mlx5_eq_init(dev); 944 if (err) { 945 mlx5_core_err(dev, "failed to initialize eq\n"); 946 goto out; 947 } 948 949 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); 950 951 err = mlx5_init_cq_table(dev); 952 if (err) { 953 mlx5_core_err(dev, "failed to initialize cq table\n"); 954 goto err_eq_cleanup; 955 } 956 957 mlx5_init_qp_table(dev); 958 mlx5_init_srq_table(dev); 959 mlx5_init_mr_table(dev); 960 961 mlx5_init_reserved_gids(dev); 962 mlx5_fpga_init(dev); 963 964 #ifdef RATELIMIT 965 err = mlx5_init_rl_table(dev); 966 if (err) { 967 mlx5_core_err(dev, "Failed to init rate limiting\n"); 968 goto err_tables_cleanup; 969 } 970 #endif 971 return 0; 972 973 #ifdef RATELIMIT 974 err_tables_cleanup: 975 mlx5_cleanup_mr_table(dev); 976 mlx5_cleanup_srq_table(dev); 977 mlx5_cleanup_qp_table(dev); 978 mlx5_cleanup_cq_table(dev); 979 #endif 980 981 err_eq_cleanup: 982 mlx5_eq_cleanup(dev); 983 984 out: 985 return err; 986 } 987 988 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 989 { 990 #ifdef RATELIMIT 991 mlx5_cleanup_rl_table(dev); 992 #endif 993 mlx5_fpga_cleanup(dev); 994 mlx5_cleanup_reserved_gids(dev); 995 mlx5_cleanup_mr_table(dev); 996 mlx5_cleanup_srq_table(dev); 997 mlx5_cleanup_qp_table(dev); 998 mlx5_cleanup_cq_table(dev); 999 mlx5_eq_cleanup(dev); 1000 } 1001 1002 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 1003 bool boot) 1004 { 1005 int err; 1006 1007 mutex_lock(&dev->intf_state_mutex); 1008 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1009 mlx5_core_warn(dev, "interface is up, NOP\n"); 1010 goto out; 1011 } 1012 1013 mlx5_core_dbg(dev, "firmware version: %d.%d.%d\n", 1014 fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); 1015 1016 /* 1017 * On load removing any previous indication of internal error, 1018 * device is up 1019 */ 1020 dev->state = MLX5_DEVICE_STATE_UP; 1021 1022 /* wait for firmware to accept initialization segments configurations 1023 */ 1024 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, 1025 FW_INIT_WARN_MESSAGE_INTERVAL); 1026 if (err) { 1027 dev_err(&dev->pdev->dev, 1028 "Firmware over %d MS in pre-initializing state, aborting\n", 1029 FW_PRE_INIT_TIMEOUT_MILI); 1030 goto out_err; 1031 } 1032 1033 err = mlx5_cmd_init(dev); 1034 if (err) { 1035 mlx5_core_err(dev, 1036 "Failed initializing command interface, aborting\n"); 1037 goto out_err; 1038 } 1039 1040 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 1041 if (err) { 1042 mlx5_core_err(dev, 1043 "Firmware over %d MS in initializing state, aborting\n", 1044 FW_INIT_TIMEOUT_MILI); 1045 goto err_cmd_cleanup; 1046 } 1047 1048 err = mlx5_core_enable_hca(dev, 0); 1049 if (err) { 1050 mlx5_core_err(dev, "enable hca failed\n"); 1051 goto err_cmd_cleanup; 1052 } 1053 1054 err = mlx5_core_set_issi(dev); 1055 if (err) { 1056 mlx5_core_err(dev, "failed to set issi\n"); 1057 goto err_disable_hca; 1058 } 1059 1060 err = mlx5_pagealloc_start(dev); 1061 if (err) { 1062 mlx5_core_err(dev, "mlx5_pagealloc_start failed\n"); 1063 goto err_disable_hca; 1064 } 1065 1066 err = mlx5_satisfy_startup_pages(dev, 1); 1067 if (err) { 1068 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1069 goto err_pagealloc_stop; 1070 } 1071 1072 err = set_hca_ctrl(dev); 1073 if (err) { 1074 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1075 goto reclaim_boot_pages; 1076 } 1077 1078 err = handle_hca_cap(dev); 1079 if (err) { 1080 mlx5_core_err(dev, "handle_hca_cap failed\n"); 1081 goto reclaim_boot_pages; 1082 } 1083 1084 err = handle_hca_cap_atomic(dev); 1085 if (err) { 1086 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 1087 goto reclaim_boot_pages; 1088 } 1089 1090 err = mlx5_satisfy_startup_pages(dev, 0); 1091 if (err) { 1092 mlx5_core_err(dev, "failed to allocate init pages\n"); 1093 goto reclaim_boot_pages; 1094 } 1095 1096 err = mlx5_cmd_init_hca(dev); 1097 if (err) { 1098 mlx5_core_err(dev, "init hca failed\n"); 1099 goto reclaim_boot_pages; 1100 } 1101 1102 mlx5_start_health_poll(dev); 1103 1104 if (boot && mlx5_init_once(dev, priv)) { 1105 mlx5_core_err(dev, "sw objs init failed\n"); 1106 goto err_stop_poll; 1107 } 1108 1109 dev->priv.uar = mlx5_get_uars_page(dev); 1110 if (IS_ERR(dev->priv.uar)) { 1111 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1112 err = PTR_ERR(dev->priv.uar); 1113 goto err_cleanup_once; 1114 } 1115 1116 err = mlx5_enable_msix(dev); 1117 if (err) { 1118 mlx5_core_err(dev, "enable msix failed\n"); 1119 goto err_cleanup_uar; 1120 } 1121 1122 err = mlx5_start_eqs(dev); 1123 if (err) { 1124 mlx5_core_err(dev, "Failed to start pages and async EQs\n"); 1125 goto err_disable_msix; 1126 } 1127 1128 err = alloc_comp_eqs(dev); 1129 if (err) { 1130 mlx5_core_err(dev, "Failed to alloc completion EQs\n"); 1131 goto err_stop_eqs; 1132 } 1133 1134 err = mlx5_init_fs(dev); 1135 if (err) { 1136 mlx5_core_err(dev, "flow steering init %d\n", err); 1137 goto err_free_comp_eqs; 1138 } 1139 1140 err = mlx5_mpfs_init(dev); 1141 if (err) { 1142 mlx5_core_err(dev, "mpfs init failed %d\n", err); 1143 goto err_fs; 1144 } 1145 1146 err = mlx5_fpga_device_start(dev); 1147 if (err) { 1148 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1149 goto err_mpfs; 1150 } 1151 1152 err = mlx5_register_device(dev); 1153 if (err) { 1154 mlx5_core_err(dev, "mlx5_register_device failed %d\n", err); 1155 goto err_fpga; 1156 } 1157 1158 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1159 1160 out: 1161 mutex_unlock(&dev->intf_state_mutex); 1162 return 0; 1163 1164 err_fpga: 1165 mlx5_fpga_device_stop(dev); 1166 1167 err_mpfs: 1168 mlx5_mpfs_destroy(dev); 1169 1170 err_fs: 1171 mlx5_cleanup_fs(dev); 1172 1173 err_free_comp_eqs: 1174 free_comp_eqs(dev); 1175 1176 err_stop_eqs: 1177 mlx5_stop_eqs(dev); 1178 1179 err_disable_msix: 1180 mlx5_disable_msix(dev); 1181 1182 err_cleanup_uar: 1183 mlx5_put_uars_page(dev, dev->priv.uar); 1184 1185 err_cleanup_once: 1186 if (boot) 1187 mlx5_cleanup_once(dev); 1188 1189 err_stop_poll: 1190 mlx5_stop_health_poll(dev, boot); 1191 if (mlx5_cmd_teardown_hca(dev)) { 1192 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1193 goto out_err; 1194 } 1195 1196 reclaim_boot_pages: 1197 mlx5_reclaim_startup_pages(dev); 1198 1199 err_pagealloc_stop: 1200 mlx5_pagealloc_stop(dev); 1201 1202 err_disable_hca: 1203 mlx5_core_disable_hca(dev); 1204 1205 err_cmd_cleanup: 1206 mlx5_cmd_cleanup(dev); 1207 1208 out_err: 1209 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1210 mutex_unlock(&dev->intf_state_mutex); 1211 1212 return err; 1213 } 1214 1215 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 1216 bool cleanup) 1217 { 1218 int err = 0; 1219 1220 if (cleanup) 1221 mlx5_drain_health_recovery(dev); 1222 1223 mutex_lock(&dev->intf_state_mutex); 1224 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1225 mlx5_core_warn(dev, "%s: interface is down, NOP\n", __func__); 1226 if (cleanup) 1227 mlx5_cleanup_once(dev); 1228 goto out; 1229 } 1230 1231 mlx5_unregister_device(dev); 1232 1233 mlx5_eswitch_cleanup(dev->priv.eswitch); 1234 mlx5_fpga_device_stop(dev); 1235 mlx5_mpfs_destroy(dev); 1236 mlx5_cleanup_fs(dev); 1237 mlx5_wait_for_reclaim_vfs_pages(dev); 1238 free_comp_eqs(dev); 1239 mlx5_stop_eqs(dev); 1240 mlx5_disable_msix(dev); 1241 mlx5_put_uars_page(dev, dev->priv.uar); 1242 if (cleanup) 1243 mlx5_cleanup_once(dev); 1244 mlx5_stop_health_poll(dev, cleanup); 1245 err = mlx5_cmd_teardown_hca(dev); 1246 if (err) { 1247 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1248 goto out; 1249 } 1250 mlx5_pagealloc_stop(dev); 1251 mlx5_reclaim_startup_pages(dev); 1252 mlx5_core_disable_hca(dev); 1253 mlx5_cmd_cleanup(dev); 1254 1255 out: 1256 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1257 mutex_unlock(&dev->intf_state_mutex); 1258 return err; 1259 } 1260 1261 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 1262 unsigned long param) 1263 { 1264 struct mlx5_priv *priv = &dev->priv; 1265 struct mlx5_device_context *dev_ctx; 1266 unsigned long flags; 1267 1268 spin_lock_irqsave(&priv->ctx_lock, flags); 1269 1270 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 1271 if (dev_ctx->intf->event) 1272 dev_ctx->intf->event(dev, dev_ctx->context, event, param); 1273 1274 spin_unlock_irqrestore(&priv->ctx_lock, flags); 1275 } 1276 1277 struct mlx5_core_event_handler { 1278 void (*event)(struct mlx5_core_dev *dev, 1279 enum mlx5_dev_event event, 1280 void *data); 1281 }; 1282 1283 #define MLX5_STATS_DESC(a, b, c, d, e, ...) d, e, 1284 1285 #define MLX5_PORT_MODULE_ERROR_STATS(m) \ 1286 m(+1, u64, power_budget_exceeded, "power_budget", "Module Power Budget Exceeded") \ 1287 m(+1, u64, long_range, "long_range", "Module Long Range for non MLNX cable/module") \ 1288 m(+1, u64, bus_stuck, "bus_stuck", "Module Bus stuck(I2C or data shorted)") \ 1289 m(+1, u64, no_eeprom, "no_eeprom", "No EEPROM/retry timeout") \ 1290 m(+1, u64, enforce_part_number, "enforce_part_number", "Module Enforce part number list") \ 1291 m(+1, u64, unknown_id, "unknown_id", "Module Unknown identifier") \ 1292 m(+1, u64, high_temp, "high_temp", "Module High Temperature") \ 1293 m(+1, u64, cable_shorted, "cable_shorted", "Module Cable is shorted") \ 1294 m(+1, u64, pmd_type_not_enabled, "pmd_type_not_enabled", "PMD type is not enabled") \ 1295 m(+1, u64, laster_tec_failure, "laster_tec_failure", "Laster TEC failure") \ 1296 m(+1, u64, high_current, "high_current", "High current") \ 1297 m(+1, u64, high_voltage, "high_voltage", "High voltage") \ 1298 m(+1, u64, pcie_sys_power_slot_exceeded, "pcie_sys_power_slot_exceeded", "PCIe system power slot Exceeded") \ 1299 m(+1, u64, high_power, "high_power", "High power") \ 1300 m(+1, u64, module_state_machine_fault, "module_state_machine_fault", "Module State Machine fault") 1301 1302 static const char *mlx5_pme_err_desc[] = { 1303 MLX5_PORT_MODULE_ERROR_STATS(MLX5_STATS_DESC) 1304 }; 1305 1306 static int init_one(struct pci_dev *pdev, 1307 const struct pci_device_id *id) 1308 { 1309 struct mlx5_core_dev *dev; 1310 struct mlx5_priv *priv; 1311 device_t bsddev = pdev->dev.bsddev; 1312 #ifdef PCI_IOV 1313 nvlist_t *pf_schema, *vf_schema; 1314 int num_vfs, sriov_pos; 1315 #endif 1316 int i,err; 1317 struct sysctl_oid *pme_sysctl_node; 1318 struct sysctl_oid *pme_err_sysctl_node; 1319 struct sysctl_oid *cap_sysctl_node; 1320 struct sysctl_oid *current_cap_sysctl_node; 1321 struct sysctl_oid *max_cap_sysctl_node; 1322 1323 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1324 priv = &dev->priv; 1325 if (id) 1326 priv->pci_dev_data = id->driver_data; 1327 1328 if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) { 1329 device_printf(bsddev, 1330 "WARN: selected profile out of range, selecting default (%d)\n", 1331 MLX5_DEFAULT_PROF); 1332 mlx5_prof_sel = MLX5_DEFAULT_PROF; 1333 } 1334 dev->profile = &profiles[mlx5_prof_sel]; 1335 dev->pdev = pdev; 1336 dev->event = mlx5_core_event; 1337 1338 /* Set desc */ 1339 device_set_desc(bsddev, mlx5_version); 1340 1341 sysctl_ctx_init(&dev->sysctl_ctx); 1342 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1343 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1344 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0, 1345 "Maximum number of MSIX event queue vectors, if set"); 1346 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1347 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1348 OID_AUTO, "power_status", CTLFLAG_RD, &dev->pwr_status, 0, 1349 "0:Invalid 1:Sufficient 2:Insufficient"); 1350 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1351 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1352 OID_AUTO, "power_value", CTLFLAG_RD, &dev->pwr_value, 0, 1353 "Current power value in Watts"); 1354 1355 pme_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1356 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1357 OID_AUTO, "pme_stats", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1358 "Port module event statistics"); 1359 if (pme_sysctl_node == NULL) { 1360 err = -ENOMEM; 1361 goto clean_sysctl_ctx; 1362 } 1363 pme_err_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1364 SYSCTL_CHILDREN(pme_sysctl_node), 1365 OID_AUTO, "errors", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1366 "Port module event error statistics"); 1367 if (pme_err_sysctl_node == NULL) { 1368 err = -ENOMEM; 1369 goto clean_sysctl_ctx; 1370 } 1371 SYSCTL_ADD_U64(&dev->sysctl_ctx, 1372 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO, 1373 "module_plug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1374 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_PLUGGED_ENABLED], 1375 0, "Number of time module plugged"); 1376 SYSCTL_ADD_U64(&dev->sysctl_ctx, 1377 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO, 1378 "module_unplug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1379 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_UNPLUGGED], 1380 0, "Number of time module unplugged"); 1381 for (i = 0 ; i < MLX5_MODULE_EVENT_ERROR_NUM; i++) { 1382 SYSCTL_ADD_U64(&dev->sysctl_ctx, 1383 SYSCTL_CHILDREN(pme_err_sysctl_node), OID_AUTO, 1384 mlx5_pme_err_desc[2 * i], CTLFLAG_RD | CTLFLAG_MPSAFE, 1385 &dev->priv.pme_stats.error_counters[i], 1386 0, mlx5_pme_err_desc[2 * i + 1]); 1387 } 1388 1389 cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1390 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1391 OID_AUTO, "caps", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1392 "hardware capabilities raw bitstrings"); 1393 if (cap_sysctl_node == NULL) { 1394 err = -ENOMEM; 1395 goto clean_sysctl_ctx; 1396 } 1397 current_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1398 SYSCTL_CHILDREN(cap_sysctl_node), 1399 OID_AUTO, "current", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1400 ""); 1401 if (current_cap_sysctl_node == NULL) { 1402 err = -ENOMEM; 1403 goto clean_sysctl_ctx; 1404 } 1405 max_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1406 SYSCTL_CHILDREN(cap_sysctl_node), 1407 OID_AUTO, "max", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1408 ""); 1409 if (max_cap_sysctl_node == NULL) { 1410 err = -ENOMEM; 1411 goto clean_sysctl_ctx; 1412 } 1413 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1414 SYSCTL_CHILDREN(current_cap_sysctl_node), 1415 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE, 1416 &dev->hca_caps_cur[MLX5_CAP_GENERAL], 1417 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1418 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1419 SYSCTL_CHILDREN(max_cap_sysctl_node), 1420 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE, 1421 &dev->hca_caps_max[MLX5_CAP_GENERAL], 1422 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1423 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1424 SYSCTL_CHILDREN(current_cap_sysctl_node), 1425 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE, 1426 &dev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], 1427 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1428 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1429 SYSCTL_CHILDREN(max_cap_sysctl_node), 1430 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE, 1431 &dev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], 1432 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1433 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1434 SYSCTL_CHILDREN(current_cap_sysctl_node), 1435 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE, 1436 &dev->hca_caps_cur[MLX5_CAP_ODP], 1437 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1438 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1439 SYSCTL_CHILDREN(max_cap_sysctl_node), 1440 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE, 1441 &dev->hca_caps_max[MLX5_CAP_ODP], 1442 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1443 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1444 SYSCTL_CHILDREN(current_cap_sysctl_node), 1445 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE, 1446 &dev->hca_caps_cur[MLX5_CAP_ATOMIC], 1447 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1448 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1449 SYSCTL_CHILDREN(max_cap_sysctl_node), 1450 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE, 1451 &dev->hca_caps_max[MLX5_CAP_ATOMIC], 1452 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1453 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1454 SYSCTL_CHILDREN(current_cap_sysctl_node), 1455 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE, 1456 &dev->hca_caps_cur[MLX5_CAP_ROCE], 1457 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1458 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1459 SYSCTL_CHILDREN(max_cap_sysctl_node), 1460 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE, 1461 &dev->hca_caps_max[MLX5_CAP_ROCE], 1462 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1463 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1464 SYSCTL_CHILDREN(current_cap_sysctl_node), 1465 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1466 &dev->hca_caps_cur[MLX5_CAP_IPOIB_OFFLOADS], 1467 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1468 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1469 SYSCTL_CHILDREN(max_cap_sysctl_node), 1470 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1471 &dev->hca_caps_max[MLX5_CAP_IPOIB_OFFLOADS], 1472 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1473 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1474 SYSCTL_CHILDREN(current_cap_sysctl_node), 1475 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1476 &dev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], 1477 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1478 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1479 SYSCTL_CHILDREN(max_cap_sysctl_node), 1480 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1481 &dev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], 1482 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1483 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1484 SYSCTL_CHILDREN(current_cap_sysctl_node), 1485 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1486 &dev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], 1487 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1488 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1489 SYSCTL_CHILDREN(max_cap_sysctl_node), 1490 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1491 &dev->hca_caps_max[MLX5_CAP_FLOW_TABLE], 1492 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1493 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1494 SYSCTL_CHILDREN(current_cap_sysctl_node), 1495 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1496 &dev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], 1497 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1498 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1499 SYSCTL_CHILDREN(max_cap_sysctl_node), 1500 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1501 &dev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], 1502 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1503 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1504 SYSCTL_CHILDREN(current_cap_sysctl_node), 1505 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE, 1506 &dev->hca_caps_cur[MLX5_CAP_ESWITCH], 1507 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1508 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1509 SYSCTL_CHILDREN(max_cap_sysctl_node), 1510 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE, 1511 &dev->hca_caps_max[MLX5_CAP_ESWITCH], 1512 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1513 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1514 SYSCTL_CHILDREN(current_cap_sysctl_node), 1515 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE, 1516 &dev->hca_caps_cur[MLX5_CAP_SNAPSHOT], 1517 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1518 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1519 SYSCTL_CHILDREN(max_cap_sysctl_node), 1520 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE, 1521 &dev->hca_caps_max[MLX5_CAP_SNAPSHOT], 1522 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1523 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1524 SYSCTL_CHILDREN(current_cap_sysctl_node), 1525 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE, 1526 &dev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], 1527 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1528 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1529 SYSCTL_CHILDREN(max_cap_sysctl_node), 1530 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE, 1531 &dev->hca_caps_max[MLX5_CAP_VECTOR_CALC], 1532 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1533 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1534 SYSCTL_CHILDREN(current_cap_sysctl_node), 1535 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE, 1536 &dev->hca_caps_cur[MLX5_CAP_QOS], 1537 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1538 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1539 SYSCTL_CHILDREN(max_cap_sysctl_node), 1540 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE, 1541 &dev->hca_caps_max[MLX5_CAP_QOS], 1542 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1543 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1544 SYSCTL_CHILDREN(current_cap_sysctl_node), 1545 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1546 &dev->hca_caps_cur[MLX5_CAP_DEBUG], 1547 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1548 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1549 SYSCTL_CHILDREN(max_cap_sysctl_node), 1550 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1551 &dev->hca_caps_max[MLX5_CAP_DEBUG], 1552 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1553 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1554 SYSCTL_CHILDREN(cap_sysctl_node), 1555 OID_AUTO, "pcam", CTLFLAG_RD | CTLFLAG_MPSAFE, 1556 &dev->caps.pcam, sizeof(dev->caps.pcam), "IU", ""); 1557 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1558 SYSCTL_CHILDREN(cap_sysctl_node), 1559 OID_AUTO, "mcam", CTLFLAG_RD | CTLFLAG_MPSAFE, 1560 &dev->caps.mcam, sizeof(dev->caps.mcam), "IU", ""); 1561 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1562 SYSCTL_CHILDREN(cap_sysctl_node), 1563 OID_AUTO, "qcam", CTLFLAG_RD | CTLFLAG_MPSAFE, 1564 &dev->caps.qcam, sizeof(dev->caps.qcam), "IU", ""); 1565 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1566 SYSCTL_CHILDREN(cap_sysctl_node), 1567 OID_AUTO, "fpga", CTLFLAG_RD | CTLFLAG_MPSAFE, 1568 &dev->caps.fpga, sizeof(dev->caps.fpga), "IU", ""); 1569 1570 INIT_LIST_HEAD(&priv->ctx_list); 1571 spin_lock_init(&priv->ctx_lock); 1572 mutex_init(&dev->pci_status_mutex); 1573 mutex_init(&dev->intf_state_mutex); 1574 1575 mutex_init(&priv->bfregs.reg_head.lock); 1576 mutex_init(&priv->bfregs.wc_head.lock); 1577 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1578 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1579 1580 mtx_init(&dev->dump_lock, "mlx5dmp", NULL, MTX_DEF | MTX_NEW); 1581 err = mlx5_pci_init(dev, priv); 1582 if (err) { 1583 mlx5_core_err(dev, "mlx5_pci_init failed %d\n", err); 1584 goto clean_dev; 1585 } 1586 1587 err = mlx5_health_init(dev); 1588 if (err) { 1589 mlx5_core_err(dev, "mlx5_health_init failed %d\n", err); 1590 goto close_pci; 1591 } 1592 1593 mlx5_pagealloc_init(dev); 1594 1595 err = mlx5_load_one(dev, priv, true); 1596 if (err) { 1597 mlx5_core_err(dev, "mlx5_load_one failed %d\n", err); 1598 goto clean_health; 1599 } 1600 1601 mlx5_fwdump_prep(dev); 1602 1603 mlx5_firmware_update(dev); 1604 1605 #ifdef PCI_IOV 1606 if (MLX5_CAP_GEN(dev, vport_group_manager)) { 1607 if (pci_find_extcap(bsddev, PCIZ_SRIOV, &sriov_pos) == 0) { 1608 num_vfs = pci_read_config(bsddev, sriov_pos + 1609 PCIR_SRIOV_TOTAL_VFS, 2); 1610 } else { 1611 mlx5_core_info(dev, "cannot find SR-IOV PCIe cap\n"); 1612 num_vfs = 0; 1613 } 1614 err = mlx5_eswitch_init(dev, 1 + num_vfs); 1615 if (err == 0) { 1616 pf_schema = pci_iov_schema_alloc_node(); 1617 vf_schema = pci_iov_schema_alloc_node(); 1618 pci_iov_schema_add_unicast_mac(vf_schema, 1619 iov_mac_addr_name, 0, NULL); 1620 pci_iov_schema_add_uint64(vf_schema, iov_node_guid_name, 1621 0, 0); 1622 pci_iov_schema_add_uint64(vf_schema, iov_port_guid_name, 1623 0, 0); 1624 err = pci_iov_attach(bsddev, pf_schema, vf_schema); 1625 if (err != 0) { 1626 device_printf(bsddev, 1627 "Failed to initialize SR-IOV support, error %d\n", 1628 err); 1629 } 1630 } else { 1631 mlx5_core_err(dev, "eswitch init failed, error %d\n", 1632 err); 1633 } 1634 } 1635 #endif 1636 1637 pci_save_state(bsddev); 1638 return 0; 1639 1640 clean_health: 1641 mlx5_pagealloc_cleanup(dev); 1642 mlx5_health_cleanup(dev); 1643 close_pci: 1644 mlx5_pci_close(dev, priv); 1645 clean_dev: 1646 mtx_destroy(&dev->dump_lock); 1647 clean_sysctl_ctx: 1648 sysctl_ctx_free(&dev->sysctl_ctx); 1649 kfree(dev); 1650 return err; 1651 } 1652 1653 static void remove_one(struct pci_dev *pdev) 1654 { 1655 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1656 struct mlx5_priv *priv = &dev->priv; 1657 1658 #ifdef PCI_IOV 1659 pci_iov_detach(pdev->dev.bsddev); 1660 mlx5_eswitch_disable_sriov(priv->eswitch); 1661 #endif 1662 1663 if (mlx5_unload_one(dev, priv, true)) { 1664 mlx5_core_err(dev, "mlx5_unload_one() failed, leaked %lld bytes\n", 1665 (long long)(dev->priv.fw_pages * MLX5_ADAPTER_PAGE_SIZE)); 1666 } 1667 1668 mlx5_pagealloc_cleanup(dev); 1669 mlx5_health_cleanup(dev); 1670 mlx5_fwdump_clean(dev); 1671 mlx5_pci_close(dev, priv); 1672 mtx_destroy(&dev->dump_lock); 1673 pci_set_drvdata(pdev, NULL); 1674 sysctl_ctx_free(&dev->sysctl_ctx); 1675 kfree(dev); 1676 } 1677 1678 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1679 pci_channel_state_t state) 1680 { 1681 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1682 struct mlx5_priv *priv = &dev->priv; 1683 1684 mlx5_core_info(dev, "%s was called\n", __func__); 1685 mlx5_enter_error_state(dev, false); 1686 mlx5_unload_one(dev, priv, false); 1687 1688 if (state) { 1689 mlx5_drain_health_wq(dev); 1690 mlx5_pci_disable_device(dev); 1691 } 1692 1693 return state == pci_channel_io_perm_failure ? 1694 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1695 } 1696 1697 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1698 { 1699 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1700 int err = 0; 1701 1702 mlx5_core_info(dev,"%s was called\n", __func__); 1703 1704 err = mlx5_pci_enable_device(dev); 1705 if (err) { 1706 mlx5_core_err(dev, "mlx5_pci_enable_device failed with error code: %d\n" 1707 ,err); 1708 return PCI_ERS_RESULT_DISCONNECT; 1709 } 1710 pci_set_master(pdev); 1711 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0); 1712 pci_restore_state(pdev->dev.bsddev); 1713 pci_save_state(pdev->dev.bsddev); 1714 1715 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1716 } 1717 1718 /* wait for the device to show vital signs. For now we check 1719 * that we can read the device ID and that the health buffer 1720 * shows a non zero value which is different than 0xffffffff 1721 */ 1722 static void wait_vital(struct pci_dev *pdev) 1723 { 1724 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1725 struct mlx5_core_health *health = &dev->priv.health; 1726 const int niter = 100; 1727 u32 count; 1728 u16 did; 1729 int i; 1730 1731 /* Wait for firmware to be ready after reset */ 1732 msleep(1000); 1733 for (i = 0; i < niter; i++) { 1734 if (pci_read_config_word(pdev, 2, &did)) { 1735 mlx5_core_warn(dev, "failed reading config word\n"); 1736 break; 1737 } 1738 if (did == pdev->device) { 1739 mlx5_core_info(dev, 1740 "device ID correctly read after %d iterations\n", i); 1741 break; 1742 } 1743 msleep(50); 1744 } 1745 if (i == niter) 1746 mlx5_core_warn(dev, "could not read device ID\n"); 1747 1748 for (i = 0; i < niter; i++) { 1749 count = ioread32be(health->health_counter); 1750 if (count && count != 0xffffffff) { 1751 mlx5_core_info(dev, 1752 "Counter value 0x%x after %d iterations\n", count, i); 1753 break; 1754 } 1755 msleep(50); 1756 } 1757 1758 if (i == niter) 1759 mlx5_core_warn(dev, "could not read device ID\n"); 1760 } 1761 1762 static void mlx5_pci_resume(struct pci_dev *pdev) 1763 { 1764 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1765 struct mlx5_priv *priv = &dev->priv; 1766 int err; 1767 1768 mlx5_core_info(dev,"%s was called\n", __func__); 1769 1770 wait_vital(pdev); 1771 1772 err = mlx5_load_one(dev, priv, false); 1773 if (err) 1774 mlx5_core_err(dev, 1775 "mlx5_load_one failed with error code: %d\n" ,err); 1776 else 1777 mlx5_core_info(dev,"device recovered\n"); 1778 } 1779 1780 static const struct pci_error_handlers mlx5_err_handler = { 1781 .error_detected = mlx5_pci_err_detected, 1782 .slot_reset = mlx5_pci_slot_reset, 1783 .resume = mlx5_pci_resume 1784 }; 1785 1786 #ifdef PCI_IOV 1787 static int 1788 mlx5_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *pf_config) 1789 { 1790 struct pci_dev *pdev; 1791 struct mlx5_core_dev *core_dev; 1792 struct mlx5_priv *priv; 1793 int err; 1794 1795 pdev = device_get_softc(dev); 1796 core_dev = pci_get_drvdata(pdev); 1797 priv = &core_dev->priv; 1798 1799 if (priv->eswitch == NULL) 1800 return (ENXIO); 1801 if (priv->eswitch->total_vports < num_vfs + 1) 1802 num_vfs = priv->eswitch->total_vports - 1; 1803 err = mlx5_eswitch_enable_sriov(priv->eswitch, num_vfs); 1804 return (-err); 1805 } 1806 1807 static void 1808 mlx5_iov_uninit(device_t dev) 1809 { 1810 struct pci_dev *pdev; 1811 struct mlx5_core_dev *core_dev; 1812 struct mlx5_priv *priv; 1813 1814 pdev = device_get_softc(dev); 1815 core_dev = pci_get_drvdata(pdev); 1816 priv = &core_dev->priv; 1817 1818 mlx5_eswitch_disable_sriov(priv->eswitch); 1819 } 1820 1821 static int 1822 mlx5_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *vf_config) 1823 { 1824 struct pci_dev *pdev; 1825 struct mlx5_core_dev *core_dev; 1826 struct mlx5_priv *priv; 1827 const void *mac; 1828 size_t mac_size; 1829 uint64_t node_guid, port_guid; 1830 int error; 1831 1832 pdev = device_get_softc(dev); 1833 core_dev = pci_get_drvdata(pdev); 1834 priv = &core_dev->priv; 1835 1836 if (vfnum + 1 >= priv->eswitch->total_vports) 1837 return (ENXIO); 1838 1839 if (nvlist_exists_binary(vf_config, iov_mac_addr_name)) { 1840 mac = nvlist_get_binary(vf_config, iov_mac_addr_name, 1841 &mac_size); 1842 error = -mlx5_eswitch_set_vport_mac(priv->eswitch, 1843 vfnum + 1, __DECONST(u8 *, mac)); 1844 if (error != 0) { 1845 mlx5_core_err(core_dev, 1846 "setting MAC for VF %d failed, error %d\n", 1847 vfnum + 1, error); 1848 } 1849 } 1850 1851 if (nvlist_exists_number(vf_config, iov_node_guid_name)) { 1852 node_guid = nvlist_get_number(vf_config, iov_node_guid_name); 1853 error = -mlx5_modify_nic_vport_node_guid(core_dev, vfnum + 1, 1854 node_guid); 1855 if (error != 0) { 1856 mlx5_core_err(core_dev, 1857 "modifying node GUID for VF %d failed, error %d\n", 1858 vfnum + 1, error); 1859 } 1860 } 1861 1862 if (nvlist_exists_number(vf_config, iov_port_guid_name)) { 1863 port_guid = nvlist_get_number(vf_config, iov_port_guid_name); 1864 error = -mlx5_modify_nic_vport_port_guid(core_dev, vfnum + 1, 1865 port_guid); 1866 if (error != 0) { 1867 mlx5_core_err(core_dev, 1868 "modifying port GUID for VF %d failed, error %d\n", 1869 vfnum + 1, error); 1870 } 1871 } 1872 1873 error = -mlx5_eswitch_set_vport_state(priv->eswitch, vfnum + 1, 1874 VPORT_STATE_FOLLOW); 1875 if (error != 0) { 1876 mlx5_core_err(core_dev, 1877 "upping vport for VF %d failed, error %d\n", 1878 vfnum + 1, error); 1879 } 1880 error = -mlx5_core_enable_hca(core_dev, vfnum + 1); 1881 if (error != 0) { 1882 mlx5_core_err(core_dev, "enabling VF %d failed, error %d\n", 1883 vfnum + 1, error); 1884 } 1885 return (error); 1886 } 1887 #endif 1888 1889 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1890 { 1891 bool fast_teardown, force_teardown; 1892 int err; 1893 1894 if (!mlx5_fast_unload_enabled) { 1895 mlx5_core_dbg(dev, "fast unload is disabled by user\n"); 1896 return -EOPNOTSUPP; 1897 } 1898 1899 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1900 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1901 1902 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1903 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1904 1905 if (!fast_teardown && !force_teardown) 1906 return -EOPNOTSUPP; 1907 1908 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1909 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1910 return -EAGAIN; 1911 } 1912 1913 /* Panic tear down fw command will stop the PCI bus communication 1914 * with the HCA, so the health polll is no longer needed. 1915 */ 1916 mlx5_drain_health_wq(dev); 1917 mlx5_stop_health_poll(dev, false); 1918 1919 err = mlx5_cmd_fast_teardown_hca(dev); 1920 if (!err) 1921 goto done; 1922 1923 err = mlx5_cmd_force_teardown_hca(dev); 1924 if (!err) 1925 goto done; 1926 1927 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err); 1928 mlx5_start_health_poll(dev); 1929 return err; 1930 done: 1931 mlx5_enter_error_state(dev, true); 1932 return 0; 1933 } 1934 1935 static void mlx5_shutdown_disable_interrupts(struct mlx5_core_dev *mdev) 1936 { 1937 int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE; 1938 int x; 1939 1940 mdev->priv.disable_irqs = 1; 1941 1942 /* wait for all IRQ handlers to finish processing */ 1943 for (x = 0; x != nvec; x++) 1944 synchronize_irq(mdev->priv.msix_arr[x].vector); 1945 } 1946 1947 static void shutdown_one(struct pci_dev *pdev) 1948 { 1949 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1950 struct mlx5_priv *priv = &dev->priv; 1951 int err; 1952 1953 /* enter polling mode */ 1954 mlx5_cmd_use_polling(dev); 1955 1956 set_bit(MLX5_INTERFACE_STATE_TEARDOWN, &dev->intf_state); 1957 1958 /* disable all interrupts */ 1959 mlx5_shutdown_disable_interrupts(dev); 1960 1961 err = mlx5_try_fast_unload(dev); 1962 if (err) 1963 mlx5_unload_one(dev, priv, false); 1964 mlx5_pci_disable_device(dev); 1965 } 1966 1967 static const struct pci_device_id mlx5_core_pci_table[] = { 1968 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */ 1969 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */ 1970 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */ 1971 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */ 1972 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */ 1973 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */ 1974 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5, PCIe 3.0 */ 1975 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */ 1976 { PCI_VDEVICE(MELLANOX, 4121) }, /* ConnectX-5 Ex */ 1977 { PCI_VDEVICE(MELLANOX, 4122) }, /* ConnectX-5 Ex VF */ 1978 { PCI_VDEVICE(MELLANOX, 4123) }, /* ConnectX-6 */ 1979 { PCI_VDEVICE(MELLANOX, 4124) }, /* ConnectX-6 VF */ 1980 { PCI_VDEVICE(MELLANOX, 4125) }, /* ConnectX-6 Dx */ 1981 { PCI_VDEVICE(MELLANOX, 4126) }, /* ConnectX Family mlx5Gen Virtual Function */ 1982 { PCI_VDEVICE(MELLANOX, 4127) }, /* ConnectX-6 LX */ 1983 { PCI_VDEVICE(MELLANOX, 4128) }, 1984 { PCI_VDEVICE(MELLANOX, 4129) }, 1985 { PCI_VDEVICE(MELLANOX, 4130) }, 1986 { PCI_VDEVICE(MELLANOX, 4131) }, 1987 { PCI_VDEVICE(MELLANOX, 4132) }, 1988 { PCI_VDEVICE(MELLANOX, 4133) }, 1989 { PCI_VDEVICE(MELLANOX, 4134) }, 1990 { PCI_VDEVICE(MELLANOX, 4135) }, 1991 { PCI_VDEVICE(MELLANOX, 4136) }, 1992 { PCI_VDEVICE(MELLANOX, 4137) }, 1993 { PCI_VDEVICE(MELLANOX, 4138) }, 1994 { PCI_VDEVICE(MELLANOX, 4139) }, 1995 { PCI_VDEVICE(MELLANOX, 4140) }, 1996 { PCI_VDEVICE(MELLANOX, 4141) }, 1997 { PCI_VDEVICE(MELLANOX, 4142) }, 1998 { PCI_VDEVICE(MELLANOX, 4143) }, 1999 { PCI_VDEVICE(MELLANOX, 4144) }, 2000 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 2001 { PCI_VDEVICE(MELLANOX, 0xa2d3) }, /* BlueField integrated ConnectX-5 network controller VF */ 2002 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2003 { } 2004 }; 2005 2006 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 2007 2008 void mlx5_disable_device(struct mlx5_core_dev *dev) 2009 { 2010 mlx5_pci_err_detected(dev->pdev, 0); 2011 } 2012 2013 void mlx5_recover_device(struct mlx5_core_dev *dev) 2014 { 2015 mlx5_pci_disable_device(dev); 2016 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 2017 mlx5_pci_resume(dev->pdev); 2018 } 2019 2020 struct pci_driver mlx5_core_driver = { 2021 .name = DRIVER_NAME, 2022 .id_table = mlx5_core_pci_table, 2023 .shutdown = shutdown_one, 2024 .probe = init_one, 2025 .remove = remove_one, 2026 .err_handler = &mlx5_err_handler, 2027 #ifdef PCI_IOV 2028 .bsd_iov_init = mlx5_iov_init, 2029 .bsd_iov_uninit = mlx5_iov_uninit, 2030 .bsd_iov_add_vf = mlx5_iov_add_vf, 2031 #endif 2032 }; 2033 2034 static int __init init(void) 2035 { 2036 int err; 2037 2038 err = pci_register_driver(&mlx5_core_driver); 2039 if (err) 2040 goto err_debug; 2041 2042 err = mlx5_ctl_init(); 2043 if (err) 2044 goto err_ctl; 2045 2046 return 0; 2047 2048 err_ctl: 2049 pci_unregister_driver(&mlx5_core_driver); 2050 2051 err_debug: 2052 return err; 2053 } 2054 2055 static void __exit cleanup(void) 2056 { 2057 mlx5_ctl_fini(); 2058 pci_unregister_driver(&mlx5_core_driver); 2059 } 2060 2061 module_init_order(init, SI_ORDER_FIRST); 2062 module_exit_order(cleanup, SI_ORDER_FIRST); 2063