1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/io-mapping.h> 31 #include <dev/mlx5/driver.h> 32 #include "mlx5_core.h" 33 34 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn) 35 { 36 u32 in[MLX5_ST_SZ_DW(alloc_uar_in)] = {0}; 37 u32 out[MLX5_ST_SZ_DW(alloc_uar_out)] = {0}; 38 int err; 39 40 MLX5_SET(alloc_uar_in, in, opcode, MLX5_CMD_OP_ALLOC_UAR); 41 42 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 43 if (err) 44 return err; 45 46 *uarn = MLX5_GET(alloc_uar_out, out, uar); 47 48 return 0; 49 } 50 EXPORT_SYMBOL(mlx5_cmd_alloc_uar); 51 52 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn) 53 { 54 u32 in[MLX5_ST_SZ_DW(dealloc_uar_in)] = {0}; 55 u32 out[MLX5_ST_SZ_DW(dealloc_uar_out)] = {0}; 56 57 MLX5_SET(dealloc_uar_in, in, opcode, MLX5_CMD_OP_DEALLOC_UAR); 58 MLX5_SET(dealloc_uar_in, in, uar, uarn); 59 60 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 61 } 62 EXPORT_SYMBOL(mlx5_cmd_free_uar); 63 64 static int need_uuar_lock(int uuarn) 65 { 66 int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE; 67 68 if (uuarn == 0 || tot_uuars - NUM_LOW_LAT_UUARS) 69 return 0; 70 71 return 1; 72 } 73 74 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari) 75 { 76 int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE; 77 struct mlx5_bf *bf; 78 phys_addr_t addr; 79 int err; 80 int i; 81 82 uuari->num_uars = NUM_DRIVER_UARS; 83 uuari->num_low_latency_uuars = NUM_LOW_LAT_UUARS; 84 85 mutex_init(&uuari->lock); 86 uuari->uars = kcalloc(uuari->num_uars, sizeof(*uuari->uars), GFP_KERNEL); 87 88 uuari->bfs = kcalloc(tot_uuars, sizeof(*uuari->bfs), GFP_KERNEL); 89 90 uuari->bitmap = kcalloc(BITS_TO_LONGS(tot_uuars), sizeof(*uuari->bitmap), 91 GFP_KERNEL); 92 93 uuari->count = kcalloc(tot_uuars, sizeof(*uuari->count), GFP_KERNEL); 94 95 for (i = 0; i < uuari->num_uars; i++) { 96 err = mlx5_cmd_alloc_uar(dev, &uuari->uars[i].index); 97 if (err) 98 goto out_count; 99 100 addr = pci_resource_start(dev->pdev, 0) + 101 ((phys_addr_t)(uuari->uars[i].index) << PAGE_SHIFT); 102 uuari->uars[i].map = ioremap(addr, PAGE_SIZE); 103 if (!uuari->uars[i].map) { 104 mlx5_cmd_free_uar(dev, uuari->uars[i].index); 105 err = -ENOMEM; 106 goto out_count; 107 } 108 mlx5_core_dbg(dev, "allocated uar index 0x%x, mmaped at %p\n", 109 uuari->uars[i].index, uuari->uars[i].map); 110 } 111 112 for (i = 0; i < tot_uuars; i++) { 113 bf = &uuari->bfs[i]; 114 115 bf->buf_size = (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) / 2; 116 bf->uar = &uuari->uars[i / MLX5_BF_REGS_PER_PAGE]; 117 bf->regreg = uuari->uars[i / MLX5_BF_REGS_PER_PAGE].map; 118 bf->reg = NULL; /* Add WC support */ 119 bf->offset = (i % MLX5_BF_REGS_PER_PAGE) * 120 (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) + 121 MLX5_BF_OFFSET; 122 bf->need_lock = need_uuar_lock(i); 123 spin_lock_init(&bf->lock); 124 spin_lock_init(&bf->lock32); 125 bf->uuarn = i; 126 } 127 128 return 0; 129 130 out_count: 131 for (i--; i >= 0; i--) { 132 iounmap(uuari->uars[i].map); 133 mlx5_cmd_free_uar(dev, uuari->uars[i].index); 134 } 135 kfree(uuari->count); 136 137 kfree(uuari->bitmap); 138 139 kfree(uuari->bfs); 140 141 kfree(uuari->uars); 142 return err; 143 } 144 145 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari) 146 { 147 int i = uuari->num_uars; 148 149 for (i--; i >= 0; i--) { 150 iounmap(uuari->uars[i].map); 151 mlx5_cmd_free_uar(dev, uuari->uars[i].index); 152 } 153 154 kfree(uuari->count); 155 kfree(uuari->bitmap); 156 kfree(uuari->bfs); 157 kfree(uuari->uars); 158 159 return 0; 160 } 161 162 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar) 163 { 164 phys_addr_t pfn; 165 phys_addr_t uar_bar_start; 166 int err; 167 168 err = mlx5_cmd_alloc_uar(mdev, &uar->index); 169 if (err) { 170 mlx5_core_warn(mdev, "mlx5_cmd_alloc_uar() failed, %d\n", err); 171 return err; 172 } 173 174 uar_bar_start = pci_resource_start(mdev->pdev, 0); 175 pfn = (uar_bar_start >> PAGE_SHIFT) + uar->index; 176 uar->map = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE); 177 if (!uar->map) { 178 mlx5_core_warn(mdev, "ioremap() failed, %d\n", err); 179 err = -ENOMEM; 180 goto err_free_uar; 181 } 182 183 if (mdev->priv.bf_mapping) 184 uar->bf_map = io_mapping_map_wc(mdev->priv.bf_mapping, 185 uar->index << PAGE_SHIFT, 186 PAGE_SIZE); 187 188 return 0; 189 190 err_free_uar: 191 mlx5_cmd_free_uar(mdev, uar->index); 192 193 return err; 194 } 195 EXPORT_SYMBOL(mlx5_alloc_map_uar); 196 197 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar) 198 { 199 io_mapping_unmap(uar->bf_map); 200 iounmap(uar->map); 201 mlx5_cmd_free_uar(mdev, uar->index); 202 } 203 EXPORT_SYMBOL(mlx5_unmap_free_uar); 204