14b95c665SHans Petter Selasky /*-
24b95c665SHans Petter Selasky * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
34b95c665SHans Petter Selasky *
44b95c665SHans Petter Selasky * Redistribution and use in source and binary forms, with or without
54b95c665SHans Petter Selasky * modification, are permitted provided that the following conditions
64b95c665SHans Petter Selasky * are met:
74b95c665SHans Petter Selasky * 1. Redistributions of source code must retain the above copyright
84b95c665SHans Petter Selasky * notice, this list of conditions and the following disclaimer.
94b95c665SHans Petter Selasky * 2. Redistributions in binary form must reproduce the above copyright
104b95c665SHans Petter Selasky * notice, this list of conditions and the following disclaimer in the
114b95c665SHans Petter Selasky * documentation and/or other materials provided with the distribution.
124b95c665SHans Petter Selasky *
134b95c665SHans Petter Selasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
144b95c665SHans Petter Selasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
154b95c665SHans Petter Selasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
164b95c665SHans Petter Selasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
174b95c665SHans Petter Selasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
184b95c665SHans Petter Selasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
194b95c665SHans Petter Selasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
204b95c665SHans Petter Selasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
214b95c665SHans Petter Selasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
224b95c665SHans Petter Selasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
234b95c665SHans Petter Selasky * SUCH DAMAGE.
244b95c665SHans Petter Selasky */
254b95c665SHans Petter Selasky
26ee9d634bSKonstantin Belousov #include "opt_rss.h"
27ee9d634bSKonstantin Belousov #include "opt_ratelimit.h"
28ee9d634bSKonstantin Belousov
294b95c665SHans Petter Selasky #include <dev/mlx5/driver.h>
304b95c665SHans Petter Selasky #include <dev/mlx5/device.h>
314b95c665SHans Petter Selasky #include <dev/mlx5/mlx5_core/mlx5_core.h>
324b95c665SHans Petter Selasky
mlx5_vsc_lock(struct mlx5_core_dev * mdev)334b95c665SHans Petter Selasky int mlx5_vsc_lock(struct mlx5_core_dev *mdev)
344b95c665SHans Petter Selasky {
354b95c665SHans Petter Selasky device_t dev = mdev->pdev->dev.bsddev;
364b95c665SHans Petter Selasky int vsc_addr = mdev->vsc_addr;
374b95c665SHans Petter Selasky int retries = 0;
384b95c665SHans Petter Selasky u32 lock_val;
394b95c665SHans Petter Selasky u32 counter;
404b95c665SHans Petter Selasky
414b95c665SHans Petter Selasky if (!vsc_addr) {
424b95c665SHans Petter Selasky mlx5_core_warn(mdev, "Unable to acquire vsc lock, vsc_addr not initialized\n");
434b95c665SHans Petter Selasky return EINVAL;
444b95c665SHans Petter Selasky }
454b95c665SHans Petter Selasky
464b95c665SHans Petter Selasky while (true) {
474b95c665SHans Petter Selasky if (retries > MLX5_VSC_MAX_RETRIES)
484b95c665SHans Petter Selasky return EBUSY;
494b95c665SHans Petter Selasky
504b95c665SHans Petter Selasky if (pci_read_config(dev, vsc_addr + MLX5_VSC_SEMA_OFFSET, 4)) {
514b95c665SHans Petter Selasky retries++;
524b95c665SHans Petter Selasky /*
534b95c665SHans Petter Selasky * The PRM suggests random 0 - 10ms to prevent multiple
544b95c665SHans Petter Selasky * waiters on the same interval in order to avoid starvation
554b95c665SHans Petter Selasky */
567bf46a63SHans Petter Selasky DELAY((random() % 9000) + 1000);
574b95c665SHans Petter Selasky continue;
584b95c665SHans Petter Selasky }
594b95c665SHans Petter Selasky
604b95c665SHans Petter Selasky counter = pci_read_config(dev, vsc_addr + MLX5_VSC_COUNTER_OFFSET, 4);
614b95c665SHans Petter Selasky pci_write_config(dev, vsc_addr + MLX5_VSC_SEMA_OFFSET, counter, 4);
624b95c665SHans Petter Selasky lock_val = pci_read_config(dev, vsc_addr + MLX5_VSC_SEMA_OFFSET, 4);
634b95c665SHans Petter Selasky
644b95c665SHans Petter Selasky if (lock_val == counter)
654b95c665SHans Petter Selasky break;
664b95c665SHans Petter Selasky
674b95c665SHans Petter Selasky retries++;
684b95c665SHans Petter Selasky }
694b95c665SHans Petter Selasky
704b95c665SHans Petter Selasky return 0;
714b95c665SHans Petter Selasky }
724b95c665SHans Petter Selasky
mlx5_vsc_unlock(struct mlx5_core_dev * mdev)734b95c665SHans Petter Selasky void mlx5_vsc_unlock(struct mlx5_core_dev *mdev)
744b95c665SHans Petter Selasky {
754b95c665SHans Petter Selasky device_t dev = mdev->pdev->dev.bsddev;
764b95c665SHans Petter Selasky int vsc_addr = mdev->vsc_addr;
774b95c665SHans Petter Selasky
784b95c665SHans Petter Selasky if (!vsc_addr) {
794b95c665SHans Petter Selasky mlx5_core_warn(mdev, "Unable to release vsc lock, vsc_addr not initialized\n");
804b95c665SHans Petter Selasky return;
814b95c665SHans Petter Selasky }
824b95c665SHans Petter Selasky
834b95c665SHans Petter Selasky pci_write_config(dev, vsc_addr + MLX5_VSC_SEMA_OFFSET, 0, 4);
844b95c665SHans Petter Selasky }
854b95c665SHans Petter Selasky
86e456deccSHans Petter Selasky int
mlx5_vsc_wait_on_flag(struct mlx5_core_dev * mdev,u32 expected)87e456deccSHans Petter Selasky mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected)
884b95c665SHans Petter Selasky {
894b95c665SHans Petter Selasky device_t dev = mdev->pdev->dev.bsddev;
904b95c665SHans Petter Selasky int vsc_addr = mdev->vsc_addr;
914b95c665SHans Petter Selasky int retries = 0;
924b95c665SHans Petter Selasky u32 flag;
934b95c665SHans Petter Selasky
944b95c665SHans Petter Selasky while (true) {
954b95c665SHans Petter Selasky if (retries > MLX5_VSC_MAX_RETRIES)
964b95c665SHans Petter Selasky return EBUSY;
974b95c665SHans Petter Selasky
984b95c665SHans Petter Selasky flag = pci_read_config(dev, vsc_addr + MLX5_VSC_ADDR_OFFSET, 4);
994b95c665SHans Petter Selasky if (expected == MLX5_VSC_GET(vsc_addr, &flag, flag))
1004b95c665SHans Petter Selasky break;
1014b95c665SHans Petter Selasky
1024b95c665SHans Petter Selasky retries++;
1037bf46a63SHans Petter Selasky DELAY((random() % 90) + 10);
1044b95c665SHans Petter Selasky }
1054b95c665SHans Petter Selasky
1064b95c665SHans Petter Selasky return 0;
1074b95c665SHans Petter Selasky }
1084b95c665SHans Petter Selasky
mlx5_vsc_set_space(struct mlx5_core_dev * mdev,u16 space)1094b95c665SHans Petter Selasky int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space)
1104b95c665SHans Petter Selasky {
1114b95c665SHans Petter Selasky device_t dev = mdev->pdev->dev.bsddev;
1124b95c665SHans Petter Selasky int vsc_addr = mdev->vsc_addr;
1134b95c665SHans Petter Selasky u32 vsc_space = 0;
1144b95c665SHans Petter Selasky
1154b95c665SHans Petter Selasky if (!vsc_addr) {
1164b95c665SHans Petter Selasky mlx5_core_warn(mdev, "Unable to set vsc space, vsc_addr not initialized\n");
1174b95c665SHans Petter Selasky return EINVAL;
1184b95c665SHans Petter Selasky }
1194b95c665SHans Petter Selasky
1204b95c665SHans Petter Selasky MLX5_VSC_SET(vsc_space, &vsc_space, space, space);
1214b95c665SHans Petter Selasky pci_write_config(dev, vsc_addr + MLX5_VSC_SPACE_OFFSET, vsc_space, 4);
1224b95c665SHans Petter Selasky vsc_space = pci_read_config(dev, vsc_addr + MLX5_VSC_SPACE_OFFSET, 4);
1234b95c665SHans Petter Selasky
1244b95c665SHans Petter Selasky if (MLX5_VSC_GET(vsc_space, &vsc_space, status) != MLX5_VSC_SPACE_SUPPORTED) {
1254b95c665SHans Petter Selasky mlx5_core_warn(mdev, "Space 0x%x is not supported.\n", space);
1264b95c665SHans Petter Selasky return ENOTSUP;
1274b95c665SHans Petter Selasky }
1284b95c665SHans Petter Selasky
1294b95c665SHans Petter Selasky return 0;
1304b95c665SHans Petter Selasky }
1314b95c665SHans Petter Selasky
mlx5_vsc_write(struct mlx5_core_dev * mdev,u32 addr,const u32 * data)132b575d8c8SHans Petter Selasky int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data)
1334b95c665SHans Petter Selasky {
1344b95c665SHans Petter Selasky device_t dev = mdev->pdev->dev.bsddev;
1354b95c665SHans Petter Selasky int vsc_addr = mdev->vsc_addr;
1364b95c665SHans Petter Selasky u32 in = 0;
1374b95c665SHans Petter Selasky int err;
1384b95c665SHans Petter Selasky
1394b95c665SHans Petter Selasky if (!vsc_addr) {
1404b95c665SHans Petter Selasky mlx5_core_warn(mdev, "Unable to call vsc write, vsc_addr not initialized\n");
1414b95c665SHans Petter Selasky return EINVAL;
1424b95c665SHans Petter Selasky }
1434b95c665SHans Petter Selasky
1444b95c665SHans Petter Selasky MLX5_VSC_SET(vsc_addr, &in, address, addr);
1454b95c665SHans Petter Selasky MLX5_VSC_SET(vsc_addr, &in, flag, 1);
1464b95c665SHans Petter Selasky pci_write_config(dev, vsc_addr + MLX5_VSC_DATA_OFFSET, *data, 4);
1474b95c665SHans Petter Selasky pci_write_config(dev, vsc_addr + MLX5_VSC_ADDR_OFFSET, in, 4);
1484b95c665SHans Petter Selasky
1494b95c665SHans Petter Selasky err = mlx5_vsc_wait_on_flag(mdev, 0);
1504b95c665SHans Petter Selasky if (err)
1514b95c665SHans Petter Selasky mlx5_core_warn(mdev, "Failed waiting for write flag!\n");
1524b95c665SHans Petter Selasky
1534b95c665SHans Petter Selasky return err;
1544b95c665SHans Petter Selasky }
1554b95c665SHans Petter Selasky
mlx5_vsc_read(struct mlx5_core_dev * mdev,u32 addr,u32 * data)1564b95c665SHans Petter Selasky int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data)
1574b95c665SHans Petter Selasky {
1584b95c665SHans Petter Selasky device_t dev = mdev->pdev->dev.bsddev;
1594b95c665SHans Petter Selasky int vsc_addr = mdev->vsc_addr;
1604b95c665SHans Petter Selasky int err;
1614b95c665SHans Petter Selasky u32 in;
1624b95c665SHans Petter Selasky
1634b95c665SHans Petter Selasky if (!vsc_addr) {
1644b95c665SHans Petter Selasky mlx5_core_warn(mdev, "Unable to call vsc read, vsc_addr not initialized\n");
1654b95c665SHans Petter Selasky return EINVAL;
1664b95c665SHans Petter Selasky }
1674b95c665SHans Petter Selasky
1684b95c665SHans Petter Selasky MLX5_VSC_SET(vsc_addr, &in, address, addr);
1694b95c665SHans Petter Selasky pci_write_config(dev, vsc_addr + MLX5_VSC_ADDR_OFFSET, in, 4);
1704b95c665SHans Petter Selasky
1714b95c665SHans Petter Selasky err = mlx5_vsc_wait_on_flag(mdev, 1);
1724b95c665SHans Petter Selasky if (err) {
1734b95c665SHans Petter Selasky mlx5_core_warn(mdev, "Failed waiting for read complete flag!\n");
1744b95c665SHans Petter Selasky return err;
1754b95c665SHans Petter Selasky }
1764b95c665SHans Petter Selasky
1774b95c665SHans Petter Selasky *data = pci_read_config(dev, vsc_addr + MLX5_VSC_DATA_OFFSET, 4);
1784b95c665SHans Petter Selasky
1794b95c665SHans Petter Selasky return 0;
1804b95c665SHans Petter Selasky }
1814b95c665SHans Petter Selasky
mlx5_vsc_lock_addr_space(struct mlx5_core_dev * mdev,u32 addr)182b575d8c8SHans Petter Selasky int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr)
183b575d8c8SHans Petter Selasky {
184b575d8c8SHans Petter Selasky device_t dev = mdev->pdev->dev.bsddev;
185b575d8c8SHans Petter Selasky int vsc_addr = mdev->vsc_addr;
186b575d8c8SHans Petter Selasky u32 data;
187b575d8c8SHans Petter Selasky int ret;
188b575d8c8SHans Petter Selasky u32 id;
189b575d8c8SHans Petter Selasky
1904d98df72SHans Petter Selasky ret = mlx5_vsc_set_space(mdev, MLX5_VSC_DOMAIN_SEMAPHORES);
191b575d8c8SHans Petter Selasky if (ret)
192b575d8c8SHans Petter Selasky return ret;
193b575d8c8SHans Petter Selasky
194b575d8c8SHans Petter Selasky /* Get a unique ID based on the counter */
195b575d8c8SHans Petter Selasky id = pci_read_config(dev, vsc_addr + MLX5_VSC_COUNTER_OFFSET, 4);
196b575d8c8SHans Petter Selasky
197b575d8c8SHans Petter Selasky /* Try to modify lock */
198b575d8c8SHans Petter Selasky ret = mlx5_vsc_write(mdev, addr, &id);
199b575d8c8SHans Petter Selasky if (ret)
200b575d8c8SHans Petter Selasky return ret;
201b575d8c8SHans Petter Selasky
202b575d8c8SHans Petter Selasky /* Verify */
203b575d8c8SHans Petter Selasky ret = mlx5_vsc_read(mdev, addr, &data);
204b575d8c8SHans Petter Selasky if (ret)
205b575d8c8SHans Petter Selasky return ret;
206b575d8c8SHans Petter Selasky if (data != id)
207b575d8c8SHans Petter Selasky return EBUSY;
208b575d8c8SHans Petter Selasky
209b575d8c8SHans Petter Selasky return 0;
210b575d8c8SHans Petter Selasky }
211b575d8c8SHans Petter Selasky
mlx5_vsc_unlock_addr_space(struct mlx5_core_dev * mdev,u32 addr)212b575d8c8SHans Petter Selasky int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr)
213b575d8c8SHans Petter Selasky {
214b575d8c8SHans Petter Selasky u32 data = 0;
215b575d8c8SHans Petter Selasky int ret;
216b575d8c8SHans Petter Selasky
2174d98df72SHans Petter Selasky ret = mlx5_vsc_set_space(mdev, MLX5_VSC_DOMAIN_SEMAPHORES);
218b575d8c8SHans Petter Selasky if (ret)
219b575d8c8SHans Petter Selasky return ret;
220b575d8c8SHans Petter Selasky
221b575d8c8SHans Petter Selasky /* Try to modify lock */
222b575d8c8SHans Petter Selasky ret = mlx5_vsc_write(mdev, addr, &data);
223b575d8c8SHans Petter Selasky if (ret)
224b575d8c8SHans Petter Selasky return ret;
225b575d8c8SHans Petter Selasky
226b575d8c8SHans Petter Selasky /* Verify */
227b575d8c8SHans Petter Selasky ret = mlx5_vsc_read(mdev, addr, &data);
228b575d8c8SHans Petter Selasky if (ret)
229b575d8c8SHans Petter Selasky return ret;
230b575d8c8SHans Petter Selasky if (data != 0)
231b575d8c8SHans Petter Selasky return EBUSY;
232b575d8c8SHans Petter Selasky
233b575d8c8SHans Petter Selasky return 0;
234b575d8c8SHans Petter Selasky }
235b575d8c8SHans Petter Selasky
mlx5_vsc_find_cap(struct mlx5_core_dev * mdev)2364b95c665SHans Petter Selasky int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev)
2374b95c665SHans Petter Selasky {
2384b95c665SHans Petter Selasky int *capreg = &mdev->vsc_addr;
2394b95c665SHans Petter Selasky int err;
2404b95c665SHans Petter Selasky
2414b95c665SHans Petter Selasky err = pci_find_cap(mdev->pdev->dev.bsddev, PCIY_VENDOR, capreg);
2424b95c665SHans Petter Selasky
2434b95c665SHans Petter Selasky if (err)
2444b95c665SHans Petter Selasky *capreg = 0;
2454b95c665SHans Petter Selasky
2464b95c665SHans Petter Selasky return err;
2474b95c665SHans Petter Selasky }
2484b95c665SHans Petter Selasky
249