1dc7e38acSHans Petter Selasky /*- 2c8d16d1eSHans Petter Selasky * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved. 3ebdb7006SHans Petter Selasky * Copyright (c) 2022 NVIDIA corporation & affiliates. 4dc7e38acSHans Petter Selasky * 5dc7e38acSHans Petter Selasky * Redistribution and use in source and binary forms, with or without 6dc7e38acSHans Petter Selasky * modification, are permitted provided that the following conditions 7dc7e38acSHans Petter Selasky * are met: 8dc7e38acSHans Petter Selasky * 1. Redistributions of source code must retain the above copyright 9dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer. 10dc7e38acSHans Petter Selasky * 2. Redistributions in binary form must reproduce the above copyright 11dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer in the 12dc7e38acSHans Petter Selasky * documentation and/or other materials provided with the distribution. 13dc7e38acSHans Petter Selasky * 14dc7e38acSHans Petter Selasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 15dc7e38acSHans Petter Selasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16dc7e38acSHans Petter Selasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17dc7e38acSHans Petter Selasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18dc7e38acSHans Petter Selasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19dc7e38acSHans Petter Selasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20dc7e38acSHans Petter Selasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21dc7e38acSHans Petter Selasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22dc7e38acSHans Petter Selasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23dc7e38acSHans Petter Selasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24dc7e38acSHans Petter Selasky * SUCH DAMAGE. 25dc7e38acSHans Petter Selasky * 26dc7e38acSHans Petter Selasky * $FreeBSD$ 27dc7e38acSHans Petter Selasky */ 28dc7e38acSHans Petter Selasky 29dc7e38acSHans Petter Selasky #ifndef _MLX5_EN_H_ 30dc7e38acSHans Petter Selasky #define _MLX5_EN_H_ 31dc7e38acSHans Petter Selasky 32dc7e38acSHans Petter Selasky #include <linux/kmod.h> 33dc7e38acSHans Petter Selasky #include <linux/page.h> 34dc7e38acSHans Petter Selasky #include <linux/slab.h> 35dc7e38acSHans Petter Selasky #include <linux/if_vlan.h> 36dc7e38acSHans Petter Selasky #include <linux/if_ether.h> 37dc7e38acSHans Petter Selasky #include <linux/vmalloc.h> 38dc7e38acSHans Petter Selasky #include <linux/moduleparam.h> 39dc7e38acSHans Petter Selasky #include <linux/delay.h> 40dc7e38acSHans Petter Selasky #include <linux/etherdevice.h> 41423530beSHans Petter Selasky #include <linux/ktime.h> 42423530beSHans Petter Selasky #include <linux/net_dim.h> 43dc7e38acSHans Petter Selasky 44dc7e38acSHans Petter Selasky #include <netinet/in_systm.h> 45dc7e38acSHans Petter Selasky #include <netinet/in.h> 46dc7e38acSHans Petter Selasky #include <netinet/if_ether.h> 47dc7e38acSHans Petter Selasky #include <netinet/ip.h> 48dc7e38acSHans Petter Selasky #include <netinet/ip6.h> 49dc7e38acSHans Petter Selasky #include <netinet/tcp.h> 50dc7e38acSHans Petter Selasky #include <netinet/tcp_lro.h> 51dc7e38acSHans Petter Selasky #include <netinet/udp.h> 52dc7e38acSHans Petter Selasky #include <net/ethernet.h> 53538ff57bSAndrew Gallatin #include <net/pfil.h> 54dc7e38acSHans Petter Selasky #include <sys/buf_ring.h> 5538535d6cSHans Petter Selasky #include <sys/kthread.h> 567272f9cdSHans Petter Selasky #include <sys/counter.h> 57dc7e38acSHans Petter Selasky 58278ce1c9SHans Petter Selasky #ifdef RSS 59278ce1c9SHans Petter Selasky #include <net/rss_config.h> 60278ce1c9SHans Petter Selasky #include <netinet/in_rss.h> 61278ce1c9SHans Petter Selasky #endif 62278ce1c9SHans Petter Selasky 63dc7e38acSHans Petter Selasky #include <machine/bus.h> 64dc7e38acSHans Petter Selasky 65dc7e38acSHans Petter Selasky #include <dev/mlx5/driver.h> 66dc7e38acSHans Petter Selasky #include <dev/mlx5/qp.h> 67dc7e38acSHans Petter Selasky #include <dev/mlx5/cq.h> 68d9142151SHans Petter Selasky #include <dev/mlx5/port.h> 69dc7e38acSHans Petter Selasky #include <dev/mlx5/vport.h> 7066d53750SHans Petter Selasky #include <dev/mlx5/diagnostics.h> 71dc7e38acSHans Petter Selasky 72dc7e38acSHans Petter Selasky #include <dev/mlx5/mlx5_core/wq.h> 73dc7e38acSHans Petter Selasky #include <dev/mlx5/mlx5_core/transobj.h> 74dc7e38acSHans Petter Selasky #include <dev/mlx5/mlx5_core/mlx5_core.h> 75dc7e38acSHans Petter Selasky 762c0ade80SHans Petter Selasky #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) 772c0ade80SHans Petter Selasky 7824385321SHans Petter Selasky #define MLX5E_MAX_PRIORITY 8 7924385321SHans Petter Selasky 8096425f44SHans Petter Selasky #define MLX5E_MAX_FEC_10X_25X 4 8196425f44SHans Petter Selasky #define MLX5E_MAX_FEC_50X 4 8296425f44SHans Petter Selasky 8324385321SHans Petter Selasky /* IEEE 802.1Qaz standard supported values */ 84cfc9c386SHans Petter Selasky #define IEEE_8021QAZ_MAX_TCS 8 85cfc9c386SHans Petter Selasky 86dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 87dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 88351a9c7cSHans Petter Selasky #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 89dc7e38acSHans Petter Selasky 90dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 91dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 92351a9c7cSHans Petter Selasky #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 93dc7e38acSHans Petter Selasky 948b825a18SHans Petter Selasky #define MLX5E_MAX_BUSDMA_RX_SEGS 15 958b825a18SHans Petter Selasky 962f17f76aSHans Petter Selasky #ifndef MLX5E_MAX_RX_BYTES 972f17f76aSHans Petter Selasky #define MLX5E_MAX_RX_BYTES MCLBYTES 982f17f76aSHans Petter Selasky #endif 992f17f76aSHans Petter Selasky 1002f17f76aSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \ 1014d0e6d84SHans Petter Selasky MIN(65535, 7 * MLX5E_MAX_RX_BYTES) 1024d0e6d84SHans Petter Selasky 103423530beSHans Petter Selasky #define MLX5E_DIM_DEFAULT_PROFILE 3 104423530beSHans Petter Selasky #define MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO 16 105dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 106dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 107dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 108dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 109dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 110dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 111dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 112dc7e38acSHans Petter Selasky #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 113dc7e38acSHans Petter Selasky #define MLX5E_HW2SW_MTU(hwmtu) \ 114dc7e38acSHans Petter Selasky ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 115dc7e38acSHans Petter Selasky #define MLX5E_SW2HW_MTU(swmtu) \ 116dc7e38acSHans Petter Selasky ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 117dc7e38acSHans Petter Selasky #define MLX5E_SW2MB_MTU(swmtu) \ 118dc7e38acSHans Petter Selasky (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 119dc7e38acSHans Petter Selasky #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 120bb3853c6SHans Petter Selasky #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 121bb3853c6SHans Petter Selasky * jumbo frames */ 122dc7e38acSHans Petter Selasky 123dc7e38acSHans Petter Selasky #define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 124dc7e38acSHans Petter Selasky #define MLX5E_RX_BUDGET_MAX 256 125dc7e38acSHans Petter Selasky #define MLX5E_SQ_BF_BUDGET 16 126dc7e38acSHans Petter Selasky #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 127dc7e38acSHans Petter Selasky 128dc7e38acSHans Petter Selasky #define MLX5E_MAX_TX_NUM_TC 8 /* units */ 1298b8c71d7SKonstantin Belousov #define MLX5E_MAX_TX_HEADER 192 /* bytes */ 130dc7e38acSHans Petter Selasky #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 131dc7e38acSHans Petter Selasky #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 132dc7e38acSHans Petter Selasky #define MLX5E_MAX_TX_MBUF_FRAGS \ 133dc7e38acSHans Petter Selasky ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 1342d32b0a3SHans Petter Selasky (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \ 1352d32b0a3SHans Petter Selasky 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */ 136dc7e38acSHans Petter Selasky #define MLX5E_MAX_TX_INLINE \ 137dc7e38acSHans Petter Selasky (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 138dc7e38acSHans Petter Selasky sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 139dc7e38acSHans Petter Selasky 140cfc9c386SHans Petter Selasky #define MLX5E_100MB (100000) 141cfc9c386SHans Petter Selasky #define MLX5E_1GB (1000000) 142cfc9c386SHans Petter Selasky 143eeb1ff98SHans Petter Selasky #define MLX5E_ZERO(ptr, field) \ 144eeb1ff98SHans Petter Selasky memset(&(ptr)->field, 0, \ 145eeb1ff98SHans Petter Selasky sizeof(*(ptr)) - __offsetof(__typeof(*(ptr)), field)) 146eeb1ff98SHans Petter Selasky 147dc7e38acSHans Petter Selasky MALLOC_DECLARE(M_MLX5EN); 148dc7e38acSHans Petter Selasky 149dc7e38acSHans Petter Selasky struct mlx5_core_dev; 150dc7e38acSHans Petter Selasky struct mlx5e_cq; 151dc7e38acSHans Petter Selasky 152f34f0a65SHans Petter Selasky typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *, struct mlx5_eqe *); 153dc7e38acSHans Petter Selasky 1546b4040d8SHans Petter Selasky #define mlx5_en_err(_dev, format, ...) \ 1556b4040d8SHans Petter Selasky if_printf(_dev, "ERR: ""%s:%d:(pid %d): " format, \ 1566b4040d8SHans Petter Selasky __func__, __LINE__, curthread->td_proc->p_pid, \ 1576b4040d8SHans Petter Selasky ##__VA_ARGS__) 1586b4040d8SHans Petter Selasky 1596b4040d8SHans Petter Selasky #define mlx5_en_warn(_dev, format, ...) \ 1606b4040d8SHans Petter Selasky if_printf(_dev, "WARN: ""%s:%d:(pid %d): " format, \ 1616b4040d8SHans Petter Selasky __func__, __LINE__, curthread->td_proc->p_pid, \ 1626b4040d8SHans Petter Selasky ##__VA_ARGS__) 1636b4040d8SHans Petter Selasky 1646b4040d8SHans Petter Selasky #define mlx5_en_info(_dev, format, ...) \ 1656b4040d8SHans Petter Selasky if_printf(_dev, "INFO: ""%s:%d:(pid %d): " format, \ 1666b4040d8SHans Petter Selasky __func__, __LINE__, curthread->td_proc->p_pid, \ 1676b4040d8SHans Petter Selasky ##__VA_ARGS__) 1686b4040d8SHans Petter Selasky 16967fd1941SHans Petter Selasky #define MLX5E_STATS_COUNT(a, ...) a 17067fd1941SHans Petter Selasky #define MLX5E_STATS_VAR(a, b, c, ...) b c; 1717272f9cdSHans Petter Selasky #define MLX5E_STATS_COUNTER(a, b, c, ...) counter_##b##_t c; 17267fd1941SHans Petter Selasky #define MLX5E_STATS_DESC(a, b, c, d, e, ...) d, e, 173dc7e38acSHans Petter Selasky 174dc7e38acSHans Petter Selasky #define MLX5E_VPORT_STATS(m) \ 175dc7e38acSHans Petter Selasky /* HW counters */ \ 17667fd1941SHans Petter Selasky m(+1, u64, rx_packets, "rx_packets", "Received packets") \ 17767fd1941SHans Petter Selasky m(+1, u64, rx_bytes, "rx_bytes", "Received bytes") \ 17867fd1941SHans Petter Selasky m(+1, u64, tx_packets, "tx_packets", "Transmitted packets") \ 17967fd1941SHans Petter Selasky m(+1, u64, tx_bytes, "tx_bytes", "Transmitted bytes") \ 18067fd1941SHans Petter Selasky m(+1, u64, rx_error_packets, "rx_error_packets", "Received error packets") \ 18167fd1941SHans Petter Selasky m(+1, u64, rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 18267fd1941SHans Petter Selasky m(+1, u64, tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 18367fd1941SHans Petter Selasky m(+1, u64, tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 18467fd1941SHans Petter Selasky m(+1, u64, rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 18567fd1941SHans Petter Selasky m(+1, u64, rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 18667fd1941SHans Petter Selasky m(+1, u64, tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 18767fd1941SHans Petter Selasky m(+1, u64, tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 18867fd1941SHans Petter Selasky m(+1, u64, rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 18967fd1941SHans Petter Selasky m(+1, u64, rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 19067fd1941SHans Petter Selasky m(+1, u64, tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 19167fd1941SHans Petter Selasky m(+1, u64, tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 19267fd1941SHans Petter Selasky m(+1, u64, rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 19367fd1941SHans Petter Selasky m(+1, u64, rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 19467fd1941SHans Petter Selasky m(+1, u64, tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 19567fd1941SHans Petter Selasky m(+1, u64, tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 19667fd1941SHans Petter Selasky m(+1, u64, rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 197dc7e38acSHans Petter Selasky /* SW counters */ \ 19867fd1941SHans Petter Selasky m(+1, u64, tso_packets, "tso_packets", "Transmitted TSO packets") \ 19967fd1941SHans Petter Selasky m(+1, u64, tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 20067fd1941SHans Petter Selasky m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 20167fd1941SHans Petter Selasky m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 20267fd1941SHans Petter Selasky m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 20367fd1941SHans Petter Selasky m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 20467fd1941SHans Petter Selasky m(+1, u64, rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 20567fd1941SHans Petter Selasky m(+1, u64, rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 20667fd1941SHans Petter Selasky m(+1, u64, tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 20767fd1941SHans Petter Selasky m(+1, u64, tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 20867fd1941SHans Petter Selasky m(+1, u64, tx_defragged, "tx_defragged", "Transmit queue defragged") \ 20967fd1941SHans Petter Selasky m(+1, u64, rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \ 21067fd1941SHans Petter Selasky m(+1, u64, tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") \ 21184d7b8e7SHans Petter Selasky m(+1, u64, rx_steer_missed_packets, "rx_steer_missed_packets", "RX packets dropped by steering rule(s)") \ 21284d7b8e7SHans Petter Selasky m(+1, u64, rx_decrypted_ok_packets, "rx_decrypted_ok_packets", "RX packets successfully decrypted by steering rule(s)") \ 21384d7b8e7SHans Petter Selasky m(+1, u64, rx_decrypted_error_packets, "rx_decrypted_error_packets", "RX packets not decrypted by steering rule(s)") 214dc7e38acSHans Petter Selasky 215dc7e38acSHans Petter Selasky #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 216dc7e38acSHans Petter Selasky 217dc7e38acSHans Petter Selasky struct mlx5e_vport_stats { 218dc7e38acSHans Petter Selasky struct sysctl_ctx_list ctx; 219dc7e38acSHans Petter Selasky u64 arg [0]; 220dc7e38acSHans Petter Selasky MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 221dc7e38acSHans Petter Selasky }; 222dc7e38acSHans Petter Selasky 223dc7e38acSHans Petter Selasky #define MLX5E_PPORT_IEEE802_3_STATS(m) \ 22467fd1941SHans Petter Selasky m(+1, u64, frames_tx, "frames_tx", "Frames transmitted") \ 22567fd1941SHans Petter Selasky m(+1, u64, frames_rx, "frames_rx", "Frames received") \ 22667fd1941SHans Petter Selasky m(+1, u64, check_seq_err, "check_seq_err", "Sequence errors") \ 22767fd1941SHans Petter Selasky m(+1, u64, alignment_err, "alignment_err", "Alignment errors") \ 22867fd1941SHans Petter Selasky m(+1, u64, octets_tx, "octets_tx", "Bytes transmitted") \ 22967fd1941SHans Petter Selasky m(+1, u64, octets_received, "octets_received", "Bytes received") \ 23067fd1941SHans Petter Selasky m(+1, u64, multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 23167fd1941SHans Petter Selasky m(+1, u64, broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 23267fd1941SHans Petter Selasky m(+1, u64, multicast_rx, "multicast_rx", "Multicast received") \ 23367fd1941SHans Petter Selasky m(+1, u64, broadcast_rx, "broadcast_rx", "Broadcast received") \ 23467fd1941SHans Petter Selasky m(+1, u64, in_range_len_errors, "in_range_len_errors", "In range length errors") \ 23567fd1941SHans Petter Selasky m(+1, u64, out_of_range_len, "out_of_range_len", "Out of range length errors") \ 23667fd1941SHans Petter Selasky m(+1, u64, too_long_errors, "too_long_errors", "Too long errors") \ 23767fd1941SHans Petter Selasky m(+1, u64, symbol_err, "symbol_err", "Symbol errors") \ 23867fd1941SHans Petter Selasky m(+1, u64, mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 23967fd1941SHans Petter Selasky m(+1, u64, mac_control_rx, "mac_control_rx", "MAC control received") \ 24067fd1941SHans Petter Selasky m(+1, u64, unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 24167fd1941SHans Petter Selasky m(+1, u64, pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 24267fd1941SHans Petter Selasky m(+1, u64, pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 243dc7e38acSHans Petter Selasky 244dc7e38acSHans Petter Selasky #define MLX5E_PPORT_RFC2819_STATS(m) \ 24567fd1941SHans Petter Selasky m(+1, u64, drop_events, "drop_events", "Dropped events") \ 24667fd1941SHans Petter Selasky m(+1, u64, octets, "octets", "Octets") \ 24767fd1941SHans Petter Selasky m(+1, u64, pkts, "pkts", "Packets") \ 24867fd1941SHans Petter Selasky m(+1, u64, broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 24967fd1941SHans Petter Selasky m(+1, u64, multicast_pkts, "multicast_pkts", "Multicast packets") \ 25067fd1941SHans Petter Selasky m(+1, u64, crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 25167fd1941SHans Petter Selasky m(+1, u64, undersize_pkts, "undersize_pkts", "Undersized packets") \ 25267fd1941SHans Petter Selasky m(+1, u64, oversize_pkts, "oversize_pkts", "Oversized packets") \ 25367fd1941SHans Petter Selasky m(+1, u64, fragments, "fragments", "Fragments") \ 25467fd1941SHans Petter Selasky m(+1, u64, jabbers, "jabbers", "Jabbers") \ 25567fd1941SHans Petter Selasky m(+1, u64, collisions, "collisions", "Collisions") 256dc7e38acSHans Petter Selasky 257dc7e38acSHans Petter Selasky #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 25867fd1941SHans Petter Selasky m(+1, u64, p64octets, "p64octets", "Bytes") \ 25967fd1941SHans Petter Selasky m(+1, u64, p65to127octets, "p65to127octets", "Bytes") \ 26067fd1941SHans Petter Selasky m(+1, u64, p128to255octets, "p128to255octets", "Bytes") \ 26167fd1941SHans Petter Selasky m(+1, u64, p256to511octets, "p256to511octets", "Bytes") \ 26267fd1941SHans Petter Selasky m(+1, u64, p512to1023octets, "p512to1023octets", "Bytes") \ 26367fd1941SHans Petter Selasky m(+1, u64, p1024to1518octets, "p1024to1518octets", "Bytes") \ 26467fd1941SHans Petter Selasky m(+1, u64, p1519to2047octets, "p1519to2047octets", "Bytes") \ 26567fd1941SHans Petter Selasky m(+1, u64, p2048to4095octets, "p2048to4095octets", "Bytes") \ 26667fd1941SHans Petter Selasky m(+1, u64, p4096to8191octets, "p4096to8191octets", "Bytes") \ 26767fd1941SHans Petter Selasky m(+1, u64, p8192to10239octets, "p8192to10239octets", "Bytes") 268dc7e38acSHans Petter Selasky 269dc7e38acSHans Petter Selasky #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 27067fd1941SHans Petter Selasky m(+1, u64, in_octets, "in_octets", "In octets") \ 27167fd1941SHans Petter Selasky m(+1, u64, in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 27267fd1941SHans Petter Selasky m(+1, u64, in_discards, "in_discards", "In discards") \ 27367fd1941SHans Petter Selasky m(+1, u64, in_errors, "in_errors", "In errors") \ 27467fd1941SHans Petter Selasky m(+1, u64, in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 27567fd1941SHans Petter Selasky m(+1, u64, out_octets, "out_octets", "Out octets") \ 27667fd1941SHans Petter Selasky m(+1, u64, out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 27767fd1941SHans Petter Selasky m(+1, u64, out_discards, "out_discards", "Out discards") \ 27867fd1941SHans Petter Selasky m(+1, u64, out_errors, "out_errors", "Out errors") \ 27967fd1941SHans Petter Selasky m(+1, u64, in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 28067fd1941SHans Petter Selasky m(+1, u64, in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 28167fd1941SHans Petter Selasky m(+1, u64, out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 28267fd1941SHans Petter Selasky m(+1, u64, out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 283dc7e38acSHans Petter Selasky 284bcfad025SHans Petter Selasky #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 28555221653SHans Petter Selasky m(+1, u64, port_transmit_wait, "port_transmit_wait", "Port transmit wait") \ 28667fd1941SHans Petter Selasky m(+1, u64, ecn_marked, "ecn_marked", "ECN marked") \ 28767fd1941SHans Petter Selasky m(+1, u64, no_buffer_discard_mc, "no_buffer_discard_mc", "No buffer discard mc") \ 28867fd1941SHans Petter Selasky m(+1, u64, rx_ebp, "rx_ebp", "RX EBP") \ 28967fd1941SHans Petter Selasky m(+1, u64, tx_ebp, "tx_ebp", "TX EBP") \ 29067fd1941SHans Petter Selasky m(+1, u64, rx_buffer_almost_full, "rx_buffer_almost_full", "RX buffer almost full") \ 29167fd1941SHans Petter Selasky m(+1, u64, rx_buffer_full, "rx_buffer_full", "RX buffer full") \ 29267fd1941SHans Petter Selasky m(+1, u64, rx_icrc_encapsulated, "rx_icrc_encapsulated", "RX ICRC encapsulated") \ 29367fd1941SHans Petter Selasky m(+1, u64, ex_reserved_0, "ex_reserved_0", "Reserved") \ 29467fd1941SHans Petter Selasky m(+1, u64, ex_reserved_1, "ex_reserved_1", "Reserved") \ 29567fd1941SHans Petter Selasky m(+1, u64, tx_stat_p64octets, "tx_stat_p64octets", "Bytes") \ 29667fd1941SHans Petter Selasky m(+1, u64, tx_stat_p65to127octets, "tx_stat_p65to127octets", "Bytes") \ 29767fd1941SHans Petter Selasky m(+1, u64, tx_stat_p128to255octets, "tx_stat_p128to255octets", "Bytes") \ 29867fd1941SHans Petter Selasky m(+1, u64, tx_stat_p256to511octets, "tx_stat_p256to511octets", "Bytes") \ 29967fd1941SHans Petter Selasky m(+1, u64, tx_stat_p512to1023octets, "tx_stat_p512to1023octets", "Bytes") \ 30067fd1941SHans Petter Selasky m(+1, u64, tx_stat_p1024to1518octets, "tx_stat_p1024to1518octets", "Bytes") \ 30167fd1941SHans Petter Selasky m(+1, u64, tx_stat_p1519to2047octets, "tx_stat_p1519to2047octets", "Bytes") \ 30267fd1941SHans Petter Selasky m(+1, u64, tx_stat_p2048to4095octets, "tx_stat_p2048to4095octets", "Bytes") \ 30367fd1941SHans Petter Selasky m(+1, u64, tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \ 30467fd1941SHans Petter Selasky m(+1, u64, tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes") 305bcfad025SHans Petter Selasky 306c62f4d8dSHans Petter Selasky #define MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 307c62f4d8dSHans Petter Selasky m(+1, u64, phy_time_since_last_clear, "phy_time_since_last_clear", \ 308c62f4d8dSHans Petter Selasky "Time since last clear in milliseconds") \ 309c62f4d8dSHans Petter Selasky m(+1, u64, phy_received_bits, "phy_received_bits", \ 310c62f4d8dSHans Petter Selasky "Total amount of traffic received in bits before error correction") \ 311c62f4d8dSHans Petter Selasky m(+1, u64, phy_symbol_errors, "phy_symbol_errors", \ 312c62f4d8dSHans Petter Selasky "Total number of symbol errors before error correction") \ 313c62f4d8dSHans Petter Selasky m(+1, u64, phy_corrected_bits, "phy_corrected_bits", \ 314c62f4d8dSHans Petter Selasky "Total number of corrected bits ") \ 315c62f4d8dSHans Petter Selasky m(+1, u64, phy_corrected_bits_lane0, "phy_corrected_bits_lane0", \ 316c62f4d8dSHans Petter Selasky "Total number of corrected bits for lane 0") \ 317c62f4d8dSHans Petter Selasky m(+1, u64, phy_corrected_bits_lane1, "phy_corrected_bits_lane1", \ 318c62f4d8dSHans Petter Selasky "Total number of corrected bits for lane 1") \ 319c62f4d8dSHans Petter Selasky m(+1, u64, phy_corrected_bits_lane2, "phy_corrected_bits_lane2", \ 320c62f4d8dSHans Petter Selasky "Total number of corrected bits for lane 2") \ 321c62f4d8dSHans Petter Selasky m(+1, u64, phy_corrected_bits_lane3, "phy_corrected_bits_lane3", \ 322c62f4d8dSHans Petter Selasky "Total number of corrected bits for lane 3") 323c62f4d8dSHans Petter Selasky 324dc7e38acSHans Petter Selasky #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 32567fd1941SHans Petter Selasky m(+1, u64, time_since_last_clear, "time_since_last_clear", \ 326dc7e38acSHans Petter Selasky "Time since the last counters clear event (msec)") \ 32767fd1941SHans Petter Selasky m(+1, u64, symbol_errors, "symbol_errors", "Symbol errors") \ 32867fd1941SHans Petter Selasky m(+1, u64, sync_headers_errors, "sync_headers_errors", \ 32967fd1941SHans Petter Selasky "Sync header error counter") \ 33067fd1941SHans Petter Selasky m(+1, u64, bip_errors_lane0, "edpl_bip_errors_lane0", \ 331dc7e38acSHans Petter Selasky "Indicates the number of PRBS errors on lane 0") \ 33267fd1941SHans Petter Selasky m(+1, u64, bip_errors_lane1, "edpl_bip_errors_lane1", \ 333dc7e38acSHans Petter Selasky "Indicates the number of PRBS errors on lane 1") \ 33467fd1941SHans Petter Selasky m(+1, u64, bip_errors_lane2, "edpl_bip_errors_lane2", \ 335dc7e38acSHans Petter Selasky "Indicates the number of PRBS errors on lane 2") \ 33667fd1941SHans Petter Selasky m(+1, u64, bip_errors_lane3, "edpl_bip_errors_lane3", \ 337dc7e38acSHans Petter Selasky "Indicates the number of PRBS errors on lane 3") \ 33867fd1941SHans Petter Selasky m(+1, u64, fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 339dc7e38acSHans Petter Selasky "FEC correctable block counter lane 0") \ 34067fd1941SHans Petter Selasky m(+1, u64, fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 341dc7e38acSHans Petter Selasky "FEC correctable block counter lane 1") \ 34267fd1941SHans Petter Selasky m(+1, u64, fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 343dc7e38acSHans Petter Selasky "FEC correctable block counter lane 2") \ 34467fd1941SHans Petter Selasky m(+1, u64, fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 345dc7e38acSHans Petter Selasky "FEC correctable block counter lane 3") \ 34667fd1941SHans Petter Selasky m(+1, u64, rs_corrected_blocks, "rs_corrected_blocks", \ 347dc7e38acSHans Petter Selasky "FEC correcable block counter") \ 34867fd1941SHans Petter Selasky m(+1, u64, rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 349dc7e38acSHans Petter Selasky "FEC uncorrecable block counter") \ 35067fd1941SHans Petter Selasky m(+1, u64, rs_no_errors_blocks, "rs_no_errors_blocks", \ 351dc7e38acSHans Petter Selasky "The number of RS-FEC blocks received that had no errors") \ 35267fd1941SHans Petter Selasky m(+1, u64, rs_single_error_blocks, "rs_single_error_blocks", \ 353dc7e38acSHans Petter Selasky "The number of corrected RS-FEC blocks received that had" \ 354dc7e38acSHans Petter Selasky "exactly 1 error symbol") \ 35567fd1941SHans Petter Selasky m(+1, u64, rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 356dc7e38acSHans Petter Selasky "Port FEC corrected symbol counter") \ 35767fd1941SHans Petter Selasky m(+1, u64, rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 358dc7e38acSHans Petter Selasky "FEC corrected symbol counter lane 0") \ 35967fd1941SHans Petter Selasky m(+1, u64, rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 360dc7e38acSHans Petter Selasky "FEC corrected symbol counter lane 1") \ 36167fd1941SHans Petter Selasky m(+1, u64, rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 362dc7e38acSHans Petter Selasky "FEC corrected symbol counter lane 2") \ 36367fd1941SHans Petter Selasky m(+1, u64, rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 36410b08045SHans Petter Selasky "FEC corrected symbol counter lane 3") 36510b08045SHans Petter Selasky 36610b08045SHans Petter Selasky /* Per priority statistics for PFC */ 36710b08045SHans Petter Selasky #define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 36810b08045SHans Petter Selasky m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 36955221653SHans Petter Selasky m(n, p, +1, u64, rx_uc_frames, "rx_uc_frames", "Received unicast frames") \ 37055221653SHans Petter Selasky m(n, p, +1, u64, rx_mc_frames, "rx_mc_frames", "Received multicast frames") \ 37155221653SHans Petter Selasky m(n, p, +1, u64, rx_bc_frames, "rx_bc_frames", "Received broadcast frames") \ 37210b08045SHans Petter Selasky m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 37310b08045SHans Petter Selasky m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 37455221653SHans Petter Selasky m(n, p, +1, u64, tx_uc_frames, "tx_uc_frames", "Transmitted unicast frames") \ 37555221653SHans Petter Selasky m(n, p, +1, u64, tx_mc_frames, "tx_mc_frames", "Transmitted multicast frames") \ 37655221653SHans Petter Selasky m(n, p, +1, u64, tx_bc_frames, "tx_bc_frames", "Transmitted broadcast frames") \ 37710b08045SHans Petter Selasky m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 37810b08045SHans Petter Selasky m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 37910b08045SHans Petter Selasky m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 38010b08045SHans Petter Selasky "Received pause duration") \ 38110b08045SHans Petter Selasky m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 38210b08045SHans Petter Selasky m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 38310b08045SHans Petter Selasky "Transmitted pause duration") \ 38410b08045SHans Petter Selasky m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 38510b08045SHans Petter Selasky "Received pause transitions") \ 38610b08045SHans Petter Selasky m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 38710b08045SHans Petter Selasky m(n, p, +1, u64, device_stall_minor_watermark, \ 38810b08045SHans Petter Selasky "device_stall_minor_watermark", "Device stall minor watermark") \ 38910b08045SHans Petter Selasky m(n, p, +1, u64, device_stall_critical_watermark, \ 39010b08045SHans Petter Selasky "device_stall_critical_watermark", "Device stall critical watermark") 39110b08045SHans Petter Selasky 39210b08045SHans Petter Selasky #define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 39367fd1941SHans Petter Selasky m(c, t, pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 39410b08045SHans Petter Selasky 39510b08045SHans Petter Selasky #define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 39610b08045SHans Petter Selasky 39710b08045SHans Petter Selasky #define MLX5E_PPORT_PER_PRIO_STATS(m) \ 39810b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 39910b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 40010b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 40110b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 40210b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 40310b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 40410b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 40510b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 406dc7e38acSHans Petter Selasky 4075f9484f3SHans Petter Selasky #define MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 4085f9484f3SHans Petter Selasky m(+1, u64, life_time_counter_high, "life_time_counter", \ 4095f9484f3SHans Petter Selasky "Life time counter.", pcie_perf_counters) \ 4105f9484f3SHans Petter Selasky m(+1, u64, tx_overflow_buffer_pkt, "tx_overflow_buffer_pkt", \ 4115f9484f3SHans Petter Selasky "The number of packets dropped due to lack of PCIe buffers " \ 4125f9484f3SHans Petter Selasky "in receive path from NIC port toward the hosts.", \ 4135f9484f3SHans Petter Selasky pcie_perf_counters) \ 4145f9484f3SHans Petter Selasky m(+1, u64, tx_overflow_buffer_marked_pkt, \ 4155f9484f3SHans Petter Selasky "tx_overflow_buffer_marked_pkt", \ 4165f9484f3SHans Petter Selasky "The number of packets marked due to lack of PCIe buffers " \ 4175f9484f3SHans Petter Selasky "in receive path from NIC port toward the hosts.", \ 4185f9484f3SHans Petter Selasky pcie_perf_counters) 4195f9484f3SHans Petter Selasky 4205f9484f3SHans Petter Selasky #define MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 4215f9484f3SHans Petter Selasky m(+1, u64, rx_errors, "rx_errors", \ 4225f9484f3SHans Petter Selasky "Number of transitions to recovery due to Framing " \ 4235f9484f3SHans Petter Selasky "errors and CRC errors.", pcie_perf_counters) \ 4245f9484f3SHans Petter Selasky m(+1, u64, tx_errors, "tx_errors", "Number of transitions " \ 4255f9484f3SHans Petter Selasky "to recovery due to EIEOS and TS errors.", pcie_perf_counters) \ 4265f9484f3SHans Petter Selasky m(+1, u64, l0_to_recovery_eieos, "l0_to_recovery_eieos", "Number of " \ 4275f9484f3SHans Petter Selasky "transitions to recovery due to getting EIEOS.", pcie_perf_counters)\ 4285f9484f3SHans Petter Selasky m(+1, u64, l0_to_recovery_ts, "l0_to_recovery_ts", "Number of " \ 4295f9484f3SHans Petter Selasky "transitions to recovery due to getting TS.", pcie_perf_counters) \ 4305f9484f3SHans Petter Selasky m(+1, u64, l0_to_recovery_framing, "l0_to_recovery_framing", "Number "\ 4315f9484f3SHans Petter Selasky "of transitions to recovery due to identifying framing " \ 4325f9484f3SHans Petter Selasky "errors at gen3/4.", pcie_perf_counters) \ 4335f9484f3SHans Petter Selasky m(+1, u64, l0_to_recovery_retrain, "l0_to_recovery_retrain", \ 4345f9484f3SHans Petter Selasky "Number of transitions to recovery due to link retrain request " \ 4355f9484f3SHans Petter Selasky "from data link.", pcie_perf_counters) \ 4365f9484f3SHans Petter Selasky m(+1, u64, crc_error_dllp, "crc_error_dllp", "Number of transitions " \ 4375f9484f3SHans Petter Selasky "to recovery due to identifying CRC DLLP errors.", \ 4385f9484f3SHans Petter Selasky pcie_perf_counters) \ 4395f9484f3SHans Petter Selasky m(+1, u64, crc_error_tlp, "crc_error_tlp", "Number of transitions to "\ 4405f9484f3SHans Petter Selasky "recovery due to identifying CRC TLP errors.", pcie_perf_counters) \ 4415f9484f3SHans Petter Selasky m(+1, u64, outbound_stalled_reads, "outbound_stalled_reads", \ 4425f9484f3SHans Petter Selasky "The percentage of time within the last second that the NIC had " \ 4435f9484f3SHans Petter Selasky "outbound non-posted read requests but could not perform the " \ 4445f9484f3SHans Petter Selasky "operation due to insufficient non-posted credits.", \ 4455f9484f3SHans Petter Selasky pcie_perf_counters) \ 4465f9484f3SHans Petter Selasky m(+1, u64, outbound_stalled_writes, "outbound_stalled_writes", \ 4475f9484f3SHans Petter Selasky "The percentage of time within the last second that the NIC had " \ 4485f9484f3SHans Petter Selasky "outbound posted writes requests but could not perform the " \ 4495f9484f3SHans Petter Selasky "operation due to insufficient posted credits.", \ 4505f9484f3SHans Petter Selasky pcie_perf_counters) \ 4515f9484f3SHans Petter Selasky m(+1, u64, outbound_stalled_reads_events, \ 4525f9484f3SHans Petter Selasky "outbound_stalled_reads_events", "The number of events where " \ 4535f9484f3SHans Petter Selasky "outbound_stalled_reads was above a threshold.", \ 4545f9484f3SHans Petter Selasky pcie_perf_counters) \ 4555f9484f3SHans Petter Selasky m(+1, u64, outbound_stalled_writes_events, \ 4565f9484f3SHans Petter Selasky "outbound_stalled_writes_events", \ 4575f9484f3SHans Petter Selasky "The number of events where outbound_stalled_writes was above " \ 4585f9484f3SHans Petter Selasky "a threshold.", pcie_perf_counters) 4595f9484f3SHans Petter Selasky 4605f9484f3SHans Petter Selasky #define MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 4615f9484f3SHans Petter Selasky m(+1, u64, time_to_boot_image_start, "time_to_boot_image_start", \ 4625f9484f3SHans Petter Selasky "Time from start until FW boot image starts running in usec.", \ 4635f9484f3SHans Petter Selasky pcie_timers_states) \ 4645f9484f3SHans Petter Selasky m(+1, u64, time_to_link_image, "time_to_link_image", \ 4655f9484f3SHans Petter Selasky "Time from start until FW pci_link image starts running in usec.", \ 4665f9484f3SHans Petter Selasky pcie_timers_states) \ 4675f9484f3SHans Petter Selasky m(+1, u64, calibration_time, "calibration_time", \ 4685f9484f3SHans Petter Selasky "Time it took FW to do calibration in usec.", \ 4695f9484f3SHans Petter Selasky pcie_timers_states) \ 4705f9484f3SHans Petter Selasky m(+1, u64, time_to_first_perst, "time_to_first_perst", \ 4715f9484f3SHans Petter Selasky "Time form start until FW handle first perst. in usec.", \ 4725f9484f3SHans Petter Selasky pcie_timers_states) \ 4735f9484f3SHans Petter Selasky m(+1, u64, time_to_detect_state, "time_to_detect_state", \ 4745f9484f3SHans Petter Selasky "Time from start until first transition to LTSSM.Detect_Q in usec", \ 4755f9484f3SHans Petter Selasky pcie_timers_states) \ 4765f9484f3SHans Petter Selasky m(+1, u64, time_to_l0, "time_to_l0", \ 4775f9484f3SHans Petter Selasky "Time from start until first transition to LTSSM.L0 in usec", \ 4785f9484f3SHans Petter Selasky pcie_timers_states) \ 4795f9484f3SHans Petter Selasky m(+1, u64, time_to_crs_en, "time_to_crs_en", \ 4805f9484f3SHans Petter Selasky "Time from start until crs is enabled in usec", \ 4815f9484f3SHans Petter Selasky pcie_timers_states) \ 4825f9484f3SHans Petter Selasky m(+1, u64, time_to_plastic_image_start, "time_to_plastic_image_start",\ 4835f9484f3SHans Petter Selasky "Time form start until FW plastic image starts running in usec.", \ 4845f9484f3SHans Petter Selasky pcie_timers_states) \ 4855f9484f3SHans Petter Selasky m(+1, u64, time_to_iron_image_start, "time_to_iron_image_start", \ 4865f9484f3SHans Petter Selasky "Time form start until FW iron image starts running in usec.", \ 4875f9484f3SHans Petter Selasky pcie_timers_states) \ 4885f9484f3SHans Petter Selasky m(+1, u64, perst_handler, "perst_handler", \ 4895f9484f3SHans Petter Selasky "Number of persts arrived.", pcie_timers_states) \ 4905f9484f3SHans Petter Selasky m(+1, u64, times_in_l1, "times_in_l1", \ 4915f9484f3SHans Petter Selasky "Number of times LTSSM entered L1 flow.", pcie_timers_states) \ 4925f9484f3SHans Petter Selasky m(+1, u64, times_in_l23, "times_in_l23", \ 4935f9484f3SHans Petter Selasky "Number of times LTSSM entered L23 flow.", pcie_timers_states) \ 4945f9484f3SHans Petter Selasky m(+1, u64, dl_down, "dl_down", \ 4955f9484f3SHans Petter Selasky "Number of moves for DL_active to DL_down.", pcie_timers_states) \ 4965f9484f3SHans Petter Selasky m(+1, u64, config_cycle1usec, "config_cycle1usec", \ 4975f9484f3SHans Petter Selasky "Number of configuration requests that firmware " \ 4985f9484f3SHans Petter Selasky "handled in less than 1 usec.", pcie_timers_states) \ 4995f9484f3SHans Petter Selasky m(+1, u64, config_cycle2to7usec, "config_cycle2to7usec", \ 5005f9484f3SHans Petter Selasky "Number of configuration requests that firmware " \ 5015f9484f3SHans Petter Selasky "handled within 2 to 7 usec.", pcie_timers_states) \ 5025f9484f3SHans Petter Selasky m(+1, u64, config_cycle8to15usec, "config_cycle8to15usec", \ 5035f9484f3SHans Petter Selasky "Number of configuration requests that firmware " \ 5045f9484f3SHans Petter Selasky "handled within 8 to 15 usec.", pcie_timers_states) \ 5055f9484f3SHans Petter Selasky m(+1, u64, config_cycle16to63usec, "config_cycle16to63usec", \ 5065f9484f3SHans Petter Selasky "Number of configuration requests that firmware " \ 5075f9484f3SHans Petter Selasky "handled within 16 to 63 usec.", pcie_timers_states) \ 5085f9484f3SHans Petter Selasky m(+1, u64, config_cycle64usec, "config_cycle64usec", \ 5095f9484f3SHans Petter Selasky "Number of configuration requests that firmware " \ 5105f9484f3SHans Petter Selasky "handled took more than 64 usec.", pcie_timers_states) \ 5115f9484f3SHans Petter Selasky m(+1, u64, correctable_err_msg_sent, "correctable_err_msg_sent", \ 5125f9484f3SHans Petter Selasky "Number of correctable error messages sent.", pcie_timers_states) \ 5135f9484f3SHans Petter Selasky m(+1, u64, non_fatal_err_msg_sent, "non_fatal_err_msg_sent", \ 5145f9484f3SHans Petter Selasky "Number of non-Fatal error msg sent.", pcie_timers_states) \ 5155f9484f3SHans Petter Selasky m(+1, u64, fatal_err_msg_sent, "fatal_err_msg_sent", \ 5165f9484f3SHans Petter Selasky "Number of fatal error msg sent.", pcie_timers_states) 5175f9484f3SHans Petter Selasky 5185f9484f3SHans Petter Selasky #define MLX5E_PCIE_LANE_COUNTERS_32(m) \ 5195f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane0, "error_counter_lane0", \ 5205f9484f3SHans Petter Selasky "Error counter for PCI lane 0", pcie_lanes_counters) \ 5215f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane1, "error_counter_lane1", \ 5225f9484f3SHans Petter Selasky "Error counter for PCI lane 1", pcie_lanes_counters) \ 5235f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane2, "error_counter_lane2", \ 5245f9484f3SHans Petter Selasky "Error counter for PCI lane 2", pcie_lanes_counters) \ 5255f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane3, "error_counter_lane3", \ 5265f9484f3SHans Petter Selasky "Error counter for PCI lane 3", pcie_lanes_counters) \ 5275f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane4, "error_counter_lane4", \ 5285f9484f3SHans Petter Selasky "Error counter for PCI lane 4", pcie_lanes_counters) \ 5295f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane5, "error_counter_lane5", \ 5305f9484f3SHans Petter Selasky "Error counter for PCI lane 5", pcie_lanes_counters) \ 5315f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane6, "error_counter_lane6", \ 5325f9484f3SHans Petter Selasky "Error counter for PCI lane 6", pcie_lanes_counters) \ 5335f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane7, "error_counter_lane7", \ 5345f9484f3SHans Petter Selasky "Error counter for PCI lane 7", pcie_lanes_counters) \ 5355f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane8, "error_counter_lane8", \ 5365f9484f3SHans Petter Selasky "Error counter for PCI lane 8", pcie_lanes_counters) \ 5375f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane9, "error_counter_lane9", \ 5385f9484f3SHans Petter Selasky "Error counter for PCI lane 9", pcie_lanes_counters) \ 5395f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane10, "error_counter_lane10", \ 5405f9484f3SHans Petter Selasky "Error counter for PCI lane 10", pcie_lanes_counters) \ 5415f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane11, "error_counter_lane11", \ 5425f9484f3SHans Petter Selasky "Error counter for PCI lane 11", pcie_lanes_counters) \ 5435f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane12, "error_counter_lane12", \ 5445f9484f3SHans Petter Selasky "Error counter for PCI lane 12", pcie_lanes_counters) \ 5455f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane13, "error_counter_lane13", \ 5465f9484f3SHans Petter Selasky "Error counter for PCI lane 13", pcie_lanes_counters) \ 5475f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane14, "error_counter_lane14", \ 5485f9484f3SHans Petter Selasky "Error counter for PCI lane 14", pcie_lanes_counters) \ 5495f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane15, "error_counter_lane15", \ 5505f9484f3SHans Petter Selasky "Error counter for PCI lane 15", pcie_lanes_counters) 5515f9484f3SHans Petter Selasky 552dc7e38acSHans Petter Selasky /* 553dc7e38acSHans Petter Selasky * Make sure to update mlx5e_update_pport_counters() 554dc7e38acSHans Petter Selasky * when adding a new MLX5E_PPORT_STATS block 555dc7e38acSHans Petter Selasky */ 556dc7e38acSHans Petter Selasky #define MLX5E_PPORT_STATS(m) \ 55710b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS(m) \ 558dc7e38acSHans Petter Selasky MLX5E_PPORT_IEEE802_3_STATS(m) \ 559ee090799SHans Petter Selasky MLX5E_PPORT_RFC2819_STATS(m) 560dc7e38acSHans Petter Selasky 561dc7e38acSHans Petter Selasky #define MLX5E_PORT_STATS_DEBUG(m) \ 562dc7e38acSHans Petter Selasky MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 563dc7e38acSHans Petter Selasky MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 564bcfad025SHans Petter Selasky MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 5655f9484f3SHans Petter Selasky MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 566c62f4d8dSHans Petter Selasky MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 5675f9484f3SHans Petter Selasky MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 5685f9484f3SHans Petter Selasky MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 5695f9484f3SHans Petter Selasky MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 5705f9484f3SHans Petter Selasky MLX5E_PCIE_LANE_COUNTERS_32(m) 571dc7e38acSHans Petter Selasky 572dc7e38acSHans Petter Selasky #define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 573dc7e38acSHans Petter Selasky (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 574dc7e38acSHans Petter Selasky #define MLX5E_PPORT_RFC2819_STATS_NUM \ 575dc7e38acSHans Petter Selasky (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 576dc7e38acSHans Petter Selasky #define MLX5E_PPORT_STATS_NUM \ 577dc7e38acSHans Petter Selasky (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 578dc7e38acSHans Petter Selasky 57910b08045SHans Petter Selasky #define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 58010b08045SHans Petter Selasky (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 581dc7e38acSHans Petter Selasky #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 582dc7e38acSHans Petter Selasky (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 583dc7e38acSHans Petter Selasky #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 584dc7e38acSHans Petter Selasky (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 585dc7e38acSHans Petter Selasky #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 586dc7e38acSHans Petter Selasky (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 587bcfad025SHans Petter Selasky #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \ 588bcfad025SHans Petter Selasky (0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT)) 589c62f4d8dSHans Petter Selasky #define MLX5E_PPORT_STATISTICAL_DEBUG_NUM \ 590c62f4d8dSHans Petter Selasky (0 MLX5E_PPORT_STATISTICAL_DEBUG(MLX5E_STATS_COUNT)) 591dc7e38acSHans Petter Selasky #define MLX5E_PORT_STATS_DEBUG_NUM \ 592dc7e38acSHans Petter Selasky (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 593dc7e38acSHans Petter Selasky 594dc7e38acSHans Petter Selasky struct mlx5e_pport_stats { 595dc7e38acSHans Petter Selasky struct sysctl_ctx_list ctx; 596dc7e38acSHans Petter Selasky u64 arg [0]; 597dc7e38acSHans Petter Selasky MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 598dc7e38acSHans Petter Selasky }; 599dc7e38acSHans Petter Selasky 600dc7e38acSHans Petter Selasky struct mlx5e_port_stats_debug { 601dc7e38acSHans Petter Selasky struct sysctl_ctx_list ctx; 602dc7e38acSHans Petter Selasky u64 arg [0]; 603dc7e38acSHans Petter Selasky MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 604dc7e38acSHans Petter Selasky }; 605dc7e38acSHans Petter Selasky 606dc7e38acSHans Petter Selasky #define MLX5E_RQ_STATS(m) \ 60767fd1941SHans Petter Selasky m(+1, u64, packets, "packets", "Received packets") \ 60867fd1941SHans Petter Selasky m(+1, u64, bytes, "bytes", "Received bytes") \ 60967fd1941SHans Petter Selasky m(+1, u64, csum_none, "csum_none", "Received packets") \ 61067fd1941SHans Petter Selasky m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 61167fd1941SHans Petter Selasky m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 61267fd1941SHans Petter Selasky m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 61367fd1941SHans Petter Selasky m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 61484d7b8e7SHans Petter Selasky m(+1, u64, wqe_err, "wqe_err", "Received packets") \ 61584d7b8e7SHans Petter Selasky m(+1, u64, decrypted_ok_packets, "decrypted_ok_packets", "Received packets successfully decrypted by steering rule(s)") \ 61684d7b8e7SHans Petter Selasky m(+1, u64, decrypted_error_packets, "decrypted_error_packets", "Received packets not decrypted by steering rule(s)") 617dc7e38acSHans Petter Selasky 618dc7e38acSHans Petter Selasky #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 619dc7e38acSHans Petter Selasky 620dc7e38acSHans Petter Selasky struct mlx5e_rq_stats { 621dc7e38acSHans Petter Selasky struct sysctl_ctx_list ctx; 622dc7e38acSHans Petter Selasky u64 arg [0]; 623dc7e38acSHans Petter Selasky MLX5E_RQ_STATS(MLX5E_STATS_VAR) 624dc7e38acSHans Petter Selasky }; 625dc7e38acSHans Petter Selasky 626dc7e38acSHans Petter Selasky #define MLX5E_SQ_STATS(m) \ 62767fd1941SHans Petter Selasky m(+1, u64, packets, "packets", "Transmitted packets") \ 62867fd1941SHans Petter Selasky m(+1, u64, bytes, "bytes", "Transmitted bytes") \ 62967fd1941SHans Petter Selasky m(+1, u64, tso_packets, "tso_packets", "Transmitted packets") \ 63067fd1941SHans Petter Selasky m(+1, u64, tso_bytes, "tso_bytes", "Transmitted bytes") \ 63167fd1941SHans Petter Selasky m(+1, u64, csum_offload_none, "csum_offload_none", "Transmitted packets") \ 63267fd1941SHans Petter Selasky m(+1, u64, defragged, "defragged", "Transmitted packets") \ 63367fd1941SHans Petter Selasky m(+1, u64, dropped, "dropped", "Transmitted packets") \ 634f5049490SHans Petter Selasky m(+1, u64, enobuf, "enobuf", "Transmitted packets") \ 6354f4739a7SHans Petter Selasky m(+1, u64, cqe_err, "cqe_err", "Transmit CQE errors") \ 63667fd1941SHans Petter Selasky m(+1, u64, nop, "nop", "Transmitted packets") 637dc7e38acSHans Petter Selasky 638dc7e38acSHans Petter Selasky #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 639dc7e38acSHans Petter Selasky 640dc7e38acSHans Petter Selasky struct mlx5e_sq_stats { 641dc7e38acSHans Petter Selasky struct sysctl_ctx_list ctx; 642dc7e38acSHans Petter Selasky u64 arg [0]; 643dc7e38acSHans Petter Selasky MLX5E_SQ_STATS(MLX5E_STATS_VAR) 644dc7e38acSHans Petter Selasky }; 645dc7e38acSHans Petter Selasky 646dc7e38acSHans Petter Selasky struct mlx5e_stats { 647dc7e38acSHans Petter Selasky struct mlx5e_vport_stats vport; 648dc7e38acSHans Petter Selasky struct mlx5e_pport_stats pport; 649dc7e38acSHans Petter Selasky struct mlx5e_port_stats_debug port_stats_debug; 650dc7e38acSHans Petter Selasky }; 651dc7e38acSHans Petter Selasky 65228f22cceSHans Petter Selasky struct mlx5e_rq_param { 65328f22cceSHans Petter Selasky u32 rqc [MLX5_ST_SZ_DW(rqc)]; 65428f22cceSHans Petter Selasky struct mlx5_wq_param wq; 65528f22cceSHans Petter Selasky }; 65628f22cceSHans Petter Selasky 65728f22cceSHans Petter Selasky struct mlx5e_sq_param { 65828f22cceSHans Petter Selasky u32 sqc [MLX5_ST_SZ_DW(sqc)]; 65928f22cceSHans Petter Selasky struct mlx5_wq_param wq; 66028f22cceSHans Petter Selasky }; 66128f22cceSHans Petter Selasky 66228f22cceSHans Petter Selasky struct mlx5e_cq_param { 66328f22cceSHans Petter Selasky u32 cqc [MLX5_ST_SZ_DW(cqc)]; 66428f22cceSHans Petter Selasky struct mlx5_wq_param wq; 66528f22cceSHans Petter Selasky }; 66628f22cceSHans Petter Selasky 667dc7e38acSHans Petter Selasky struct mlx5e_params { 668dc7e38acSHans Petter Selasky u8 log_sq_size; 669dc7e38acSHans Petter Selasky u8 log_rq_size; 670dc7e38acSHans Petter Selasky u16 num_channels; 671dc7e38acSHans Petter Selasky u8 default_vlan_prio; 672dc7e38acSHans Petter Selasky u8 num_tc; 673dc7e38acSHans Petter Selasky u8 rx_cq_moderation_mode; 67474540a31SHans Petter Selasky u8 tx_cq_moderation_mode; 675dc7e38acSHans Petter Selasky u16 rx_cq_moderation_usec; 676dc7e38acSHans Petter Selasky u16 rx_cq_moderation_pkts; 677dc7e38acSHans Petter Selasky u16 tx_cq_moderation_usec; 678dc7e38acSHans Petter Selasky u16 tx_cq_moderation_pkts; 679dc7e38acSHans Petter Selasky u16 min_rx_wqes; 680dc7e38acSHans Petter Selasky bool hw_lro_en; 68190cc1c77SHans Petter Selasky bool cqe_zipping_en; 682dc7e38acSHans Petter Selasky u32 lro_wqe_sz; 683dc7e38acSHans Petter Selasky u16 rx_hash_log_tbl_sz; 68410b08045SHans Petter Selasky u32 tx_pauseframe_control __aligned(4); 68510b08045SHans Petter Selasky u32 rx_pauseframe_control __aligned(4); 68605399002SHans Petter Selasky u16 tx_max_inline; 68705399002SHans Petter Selasky u8 tx_min_inline_mode; 68824385321SHans Petter Selasky u8 tx_priority_flow_control; 68924385321SHans Petter Selasky u8 rx_priority_flow_control; 69016ae32f9SHans Petter Selasky u8 channels_rsss; 691dc7e38acSHans Petter Selasky }; 692dc7e38acSHans Petter Selasky 693dc7e38acSHans Petter Selasky #define MLX5E_PARAMS(m) \ 69467fd1941SHans Petter Selasky m(+1, u64, tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 69567fd1941SHans Petter Selasky m(+1, u64, rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 69667fd1941SHans Petter Selasky m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \ 69767fd1941SHans Petter Selasky m(+1, u64, rx_queue_size, "rx_queue_size", "Default receive queue size") \ 69867fd1941SHans Petter Selasky m(+1, u64, channels, "channels", "Default number of channels") \ 69967fd1941SHans Petter Selasky m(+1, u64, channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \ 70067fd1941SHans Petter Selasky m(+1, u64, coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 70167fd1941SHans Petter Selasky m(+1, u64, coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 70267fd1941SHans Petter Selasky m(+1, u64, rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 70367fd1941SHans Petter Selasky m(+1, u64, rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 70467fd1941SHans Petter Selasky m(+1, u64, rx_coalesce_mode, "rx_coalesce_mode", "0: EQE fixed mode 1: CQE fixed mode 2: EQE auto mode 3: CQE auto mode") \ 70567fd1941SHans Petter Selasky m(+1, u64, tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 70667fd1941SHans Petter Selasky m(+1, u64, tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 70767fd1941SHans Petter Selasky m(+1, u64, tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 70867fd1941SHans Petter Selasky m(+1, u64, tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 70967fd1941SHans Petter Selasky m(+1, u64, tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 71067fd1941SHans Petter Selasky m(+1, u64, hw_lro, "hw_lro", "set to enable hw_lro") \ 71167fd1941SHans Petter Selasky m(+1, u64, cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 71267fd1941SHans Petter Selasky m(+1, u64, modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 71367fd1941SHans Petter Selasky m(+1, u64, modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 71467fd1941SHans Petter Selasky m(+1, u64, diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 71567fd1941SHans Petter Selasky m(+1, u64, diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 71667fd1941SHans Petter Selasky m(+1, u64, hw_mtu, "hw_mtu", "Current hardware MTU value") \ 71767fd1941SHans Petter Selasky m(+1, u64, mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 718c8d16d1eSHans Petter Selasky m(+1, u64, uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") \ 719c8d16d1eSHans Petter Selasky m(+1, s64, irq_cpu_base, "irq_cpu_base", "-1: Don't bind IRQ 0..NCPU-1: select this base CPU when binding IRQs") \ 720c8d16d1eSHans Petter Selasky m(+1, s64, irq_cpu_stride, "irq_cpu_stride", "0..NCPU-1: Distance between IRQ vectors when binding them") 721cfc9c386SHans Petter Selasky 722dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 723dc7e38acSHans Petter Selasky 724dc7e38acSHans Petter Selasky struct mlx5e_params_ethtool { 725dc7e38acSHans Petter Selasky u64 arg [0]; 726dc7e38acSHans Petter Selasky MLX5E_PARAMS(MLX5E_STATS_VAR) 727cfc9c386SHans Petter Selasky u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 728e870c0abSSlava Shwartsman u8 max_bw_share[IEEE_8021QAZ_MAX_TCS]; 72924385321SHans Petter Selasky u8 prio_tc[MLX5E_MAX_PRIORITY]; 730ed0cee0bSHans Petter Selasky u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP]; 731ed0cee0bSHans Petter Selasky u8 trust_state; 73296425f44SHans Petter Selasky u8 fec_mask_10x_25x[MLX5E_MAX_FEC_10X_25X]; 73396425f44SHans Petter Selasky u16 fec_mask_50x[MLX5E_MAX_FEC_50X]; 73496425f44SHans Petter Selasky u8 fec_avail_10x_25x[MLX5E_MAX_FEC_10X_25X]; 73596425f44SHans Petter Selasky u16 fec_avail_50x[MLX5E_MAX_FEC_50X]; 73696425f44SHans Petter Selasky u32 fec_mode_active; 7377272f9cdSHans Petter Selasky u32 hw_mtu_msb; 738decb087cSHans Petter Selasky s32 hw_val_temp[MLX5_MAX_TEMPERATURE]; 739decb087cSHans Petter Selasky u32 hw_num_temp; 740dc7e38acSHans Petter Selasky }; 741dc7e38acSHans Petter Selasky 742dc7e38acSHans Petter Selasky struct mlx5e_cq { 743dc7e38acSHans Petter Selasky /* data path - accessed per cqe */ 744dc7e38acSHans Petter Selasky struct mlx5_cqwq wq; 745dc7e38acSHans Petter Selasky 746dc7e38acSHans Petter Selasky /* data path - accessed per HW polling */ 747dc7e38acSHans Petter Selasky struct mlx5_core_cq mcq; 748dc7e38acSHans Petter Selasky 749dc7e38acSHans Petter Selasky /* control */ 75098626886SHans Petter Selasky struct mlx5e_priv *priv; 751dc7e38acSHans Petter Selasky struct mlx5_wq_ctrl wq_ctrl; 752dc7e38acSHans Petter Selasky } __aligned(MLX5E_CACHELINE_SIZE); 753dc7e38acSHans Petter Selasky 754dc7e38acSHans Petter Selasky struct mlx5e_rq_mbuf { 755dc7e38acSHans Petter Selasky bus_dmamap_t dma_map; 756dc7e38acSHans Petter Selasky caddr_t data; 757dc7e38acSHans Petter Selasky struct mbuf *mbuf; 758dc7e38acSHans Petter Selasky }; 759dc7e38acSHans Petter Selasky 760dc7e38acSHans Petter Selasky struct mlx5e_rq { 7614a87beecSGordon Bergling /* persistent fields */ 762dc7e38acSHans Petter Selasky struct mtx mtx; 763eeb1ff98SHans Petter Selasky struct mlx5e_rq_stats stats; 76408650d17SHans Petter Selasky struct callout watchdog; 765eeb1ff98SHans Petter Selasky 766eeb1ff98SHans Petter Selasky /* data path */ 767eeb1ff98SHans Petter Selasky #define mlx5e_rq_zero_start wq 768eeb1ff98SHans Petter Selasky struct mlx5_wq_ll wq; 769dc7e38acSHans Petter Selasky bus_dma_tag_t dma_tag; 770dc7e38acSHans Petter Selasky u32 wqe_sz; 7712f17f76aSHans Petter Selasky u32 nsegs; 772dc7e38acSHans Petter Selasky struct mlx5e_rq_mbuf *mbuf; 773dc7e38acSHans Petter Selasky struct ifnet *ifp; 774dc7e38acSHans Petter Selasky struct mlx5e_cq cq; 775dc7e38acSHans Petter Selasky struct lro_ctrl lro; 776dc7e38acSHans Petter Selasky volatile int enabled; 777dc7e38acSHans Petter Selasky int ix; 778dc7e38acSHans Petter Selasky 779423530beSHans Petter Selasky /* Dynamic Interrupt Moderation */ 780423530beSHans Petter Selasky struct net_dim dim; 781423530beSHans Petter Selasky 782dc7e38acSHans Petter Selasky /* control */ 783dc7e38acSHans Petter Selasky struct mlx5_wq_ctrl wq_ctrl; 784dc7e38acSHans Petter Selasky u32 rqn; 785dc7e38acSHans Petter Selasky struct mlx5e_channel *channel; 786dc7e38acSHans Petter Selasky } __aligned(MLX5E_CACHELINE_SIZE); 787dc7e38acSHans Petter Selasky 78869426357SHans Petter Selasky typedef void (mlx5e_iq_callback_t)(void *arg); 78969426357SHans Petter Selasky 79069426357SHans Petter Selasky struct mlx5e_iq_data { 79169426357SHans Petter Selasky bus_dmamap_t dma_map; 79269426357SHans Petter Selasky mlx5e_iq_callback_t *callback; 79369426357SHans Petter Selasky void *arg; 79469426357SHans Petter Selasky volatile s32 *p_refcount; /* in use refcount, if any */ 79569426357SHans Petter Selasky u32 num_wqebbs; 79669426357SHans Petter Selasky u32 dma_sync; 79769426357SHans Petter Selasky }; 79869426357SHans Petter Selasky 79969426357SHans Petter Selasky struct mlx5e_iq { 80069426357SHans Petter Selasky /* persistant fields */ 80169426357SHans Petter Selasky struct mtx lock; 80269426357SHans Petter Selasky struct mtx comp_lock; 80369426357SHans Petter Selasky int db_inhibit; 80469426357SHans Petter Selasky 80569426357SHans Petter Selasky /* data path */ 80669426357SHans Petter Selasky #define mlx5e_iq_zero_start dma_tag 80769426357SHans Petter Selasky bus_dma_tag_t dma_tag; 80869426357SHans Petter Selasky 80969426357SHans Petter Selasky u16 cc; /* consumer counter */ 81069426357SHans Petter Selasky u16 pc __aligned(MLX5E_CACHELINE_SIZE); 81169426357SHans Petter Selasky u16 running; 81269426357SHans Petter Selasky 81369426357SHans Petter Selasky union { 81469426357SHans Petter Selasky u32 d32[2]; 81569426357SHans Petter Selasky u64 d64; 81669426357SHans Petter Selasky } doorbell; 81769426357SHans Petter Selasky 81869426357SHans Petter Selasky struct mlx5e_cq cq; 81969426357SHans Petter Selasky 82069426357SHans Petter Selasky /* pointers to per request info: write@xmit, read@completion */ 82169426357SHans Petter Selasky struct mlx5e_iq_data *data; 82269426357SHans Petter Selasky 82369426357SHans Petter Selasky /* read only */ 82469426357SHans Petter Selasky struct mlx5_wq_cyc wq; 82569426357SHans Petter Selasky void __iomem *uar_map; 82669426357SHans Petter Selasky u32 sqn; 82769426357SHans Petter Selasky u32 mkey_be; 82869426357SHans Petter Selasky 82969426357SHans Petter Selasky /* control path */ 83069426357SHans Petter Selasky struct mlx5_wq_ctrl wq_ctrl; 83169426357SHans Petter Selasky struct mlx5e_priv *priv; 83269426357SHans Petter Selasky }; 83369426357SHans Petter Selasky 834dc7e38acSHans Petter Selasky struct mlx5e_sq_mbuf { 835dc7e38acSHans Petter Selasky bus_dmamap_t dma_map; 836dc7e38acSHans Petter Selasky struct mbuf *mbuf; 837ebdb7006SHans Petter Selasky struct m_snd_tag *mst; /* if set, unref this send tag on completion */ 838dc7e38acSHans Petter Selasky u32 num_bytes; 839dc7e38acSHans Petter Selasky u32 num_wqebbs; 840dc7e38acSHans Petter Selasky }; 841dc7e38acSHans Petter Selasky 842dc7e38acSHans Petter Selasky enum { 843dc7e38acSHans Petter Selasky MLX5E_SQ_READY, 844dc7e38acSHans Petter Selasky MLX5E_SQ_FULL 845dc7e38acSHans Petter Selasky }; 846dc7e38acSHans Petter Selasky 847dc7e38acSHans Petter Selasky struct mlx5e_sq { 8484a87beecSGordon Bergling /* persistent fields */ 849dc7e38acSHans Petter Selasky struct mtx lock; 850dc7e38acSHans Petter Selasky struct mtx comp_lock; 851eeb1ff98SHans Petter Selasky struct mlx5e_sq_stats stats; 85208650d17SHans Petter Selasky struct callout cev_callout; 8532d5e5a0dSHans Petter Selasky int db_inhibit; 854eeb1ff98SHans Petter Selasky 855eeb1ff98SHans Petter Selasky /* data path */ 856eeb1ff98SHans Petter Selasky #define mlx5e_sq_zero_start dma_tag 857eeb1ff98SHans Petter Selasky bus_dma_tag_t dma_tag; 858dc7e38acSHans Petter Selasky 859dc7e38acSHans Petter Selasky /* dirtied @completion */ 860dc7e38acSHans Petter Selasky u16 cc; 861dc7e38acSHans Petter Selasky 862dc7e38acSHans Petter Selasky /* dirtied @xmit */ 863dc7e38acSHans Petter Selasky u16 pc __aligned(MLX5E_CACHELINE_SIZE); 864376bcf63SHans Petter Selasky u16 cev_counter; /* completion event counter */ 865376bcf63SHans Petter Selasky u16 cev_factor; /* completion event factor */ 8663dfa7645SHans Petter Selasky u16 cev_next_state; /* next completion event state */ 867376bcf63SHans Petter Selasky #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 868376bcf63SHans Petter Selasky #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 869376bcf63SHans Petter Selasky #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 8703230c29dSSlava Shwartsman u16 running; /* set if SQ is running */ 871af89c4afSHans Petter Selasky union { 872af89c4afSHans Petter Selasky u32 d32[2]; 873af89c4afSHans Petter Selasky u64 d64; 874af89c4afSHans Petter Selasky } doorbell; 875dc7e38acSHans Petter Selasky 876dc7e38acSHans Petter Selasky struct mlx5e_cq cq; 877dc7e38acSHans Petter Selasky 878dc7e38acSHans Petter Selasky /* pointers to per packet info: write@xmit, read@completion */ 879dc7e38acSHans Petter Selasky struct mlx5e_sq_mbuf *mbuf; 880dc7e38acSHans Petter Selasky 881dc7e38acSHans Petter Selasky /* read only */ 882dc7e38acSHans Petter Selasky struct mlx5_wq_cyc wq; 883f8f5b459SHans Petter Selasky void __iomem *uar_map; 88498626886SHans Petter Selasky struct ifnet *ifp; 885dc7e38acSHans Petter Selasky u32 sqn; 886dc7e38acSHans Petter Selasky u32 mkey_be; 88705399002SHans Petter Selasky u16 max_inline; 88805399002SHans Petter Selasky u8 min_inline_mode; 8893e581cabSSlava Shwartsman u8 min_insert_caps; 890266c81aaSHans Petter Selasky u32 queue_handle; /* SQ remap support */ 8913e581cabSSlava Shwartsman #define MLX5E_INSERT_VLAN 1 8923e581cabSSlava Shwartsman #define MLX5E_INSERT_NON_VLAN 2 893dc7e38acSHans Petter Selasky 894dc7e38acSHans Petter Selasky /* control path */ 895dc7e38acSHans Petter Selasky struct mlx5_wq_ctrl wq_ctrl; 89698626886SHans Petter Selasky struct mlx5e_priv *priv; 897dc7e38acSHans Petter Selasky int tc; 898dc7e38acSHans Petter Selasky } __aligned(MLX5E_CACHELINE_SIZE); 899dc7e38acSHans Petter Selasky 900dc7e38acSHans Petter Selasky static inline bool 901dc7e38acSHans Petter Selasky mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 902dc7e38acSHans Petter Selasky { 9035e6a76beSHans Petter Selasky u16 cc = sq->cc; 9045e6a76beSHans Petter Selasky u16 pc = sq->pc; 9055e6a76beSHans Petter Selasky 9065e6a76beSHans Petter Selasky return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 907dc7e38acSHans Petter Selasky } 908dc7e38acSHans Petter Selasky 909cc971b22SSlava Shwartsman static inline u32 910cc971b22SSlava Shwartsman mlx5e_sq_queue_level(struct mlx5e_sq *sq) 911cc971b22SSlava Shwartsman { 912cc971b22SSlava Shwartsman u16 cc; 913cc971b22SSlava Shwartsman u16 pc; 914cc971b22SSlava Shwartsman 915cc971b22SSlava Shwartsman if (sq == NULL) 916cc971b22SSlava Shwartsman return (0); 917cc971b22SSlava Shwartsman 918cc971b22SSlava Shwartsman cc = sq->cc; 919cc971b22SSlava Shwartsman pc = sq->pc; 920cc971b22SSlava Shwartsman 921cc971b22SSlava Shwartsman return (((sq->wq.sz_m1 & (pc - cc)) * 922cc971b22SSlava Shwartsman IF_SND_QUEUE_LEVEL_MAX) / sq->wq.sz_m1); 923cc971b22SSlava Shwartsman } 924cc971b22SSlava Shwartsman 925dc7e38acSHans Petter Selasky struct mlx5e_channel { 926dc7e38acSHans Petter Selasky struct mlx5e_rq rq; 92756fb710fSJohn Baldwin struct m_snd_tag tag; 9289dfa2148SHans Petter Selasky struct mlx5_sq_bfreg bfreg; 929dc7e38acSHans Petter Selasky struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 93069426357SHans Petter Selasky struct mlx5e_iq iq; 931dc7e38acSHans Petter Selasky struct mlx5e_priv *priv; 932c84e0068SHans Petter Selasky struct completion completion; 933dc7e38acSHans Petter Selasky int ix; 9348e332232SHans Petter Selasky u32 rqtn; 935dc7e38acSHans Petter Selasky } __aligned(MLX5E_CACHELINE_SIZE); 936dc7e38acSHans Petter Selasky 937dc7e38acSHans Petter Selasky enum mlx5e_traffic_types { 938dc7e38acSHans Petter Selasky MLX5E_TT_IPV4_TCP, 939dc7e38acSHans Petter Selasky MLX5E_TT_IPV6_TCP, 940dc7e38acSHans Petter Selasky MLX5E_TT_IPV4_UDP, 941dc7e38acSHans Petter Selasky MLX5E_TT_IPV6_UDP, 942dc7e38acSHans Petter Selasky MLX5E_TT_IPV4_IPSEC_AH, 943dc7e38acSHans Petter Selasky MLX5E_TT_IPV6_IPSEC_AH, 944dc7e38acSHans Petter Selasky MLX5E_TT_IPV4_IPSEC_ESP, 945dc7e38acSHans Petter Selasky MLX5E_TT_IPV6_IPSEC_ESP, 946dc7e38acSHans Petter Selasky MLX5E_TT_IPV4, 947dc7e38acSHans Petter Selasky MLX5E_TT_IPV6, 948dc7e38acSHans Petter Selasky MLX5E_TT_ANY, 949dc7e38acSHans Petter Selasky MLX5E_NUM_TT, 950dc7e38acSHans Petter Selasky }; 951dc7e38acSHans Petter Selasky 952dc7e38acSHans Petter Selasky enum { 953dc7e38acSHans Petter Selasky MLX5E_RQT_SPREADING = 0, 954dc7e38acSHans Petter Selasky MLX5E_RQT_DEFAULT_RQ = 1, 955dc7e38acSHans Petter Selasky MLX5E_NUM_RQT = 2, 956dc7e38acSHans Petter Selasky }; 957dc7e38acSHans Petter Selasky 9585a93b4cdSHans Petter Selasky struct mlx5_flow_rule; 9595a93b4cdSHans Petter Selasky 960dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_info { 961dc7e38acSHans Petter Selasky u8 addr [ETH_ALEN + 2]; 962dc7e38acSHans Petter Selasky u32 tt_vec; 9635a93b4cdSHans Petter Selasky /* flow table rule per traffic type */ 9645a93b4cdSHans Petter Selasky struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 965dc7e38acSHans Petter Selasky }; 966dc7e38acSHans Petter Selasky 967dc7e38acSHans Petter Selasky #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 968dc7e38acSHans Petter Selasky 969dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_hash_node; 970dc7e38acSHans Petter Selasky 971dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_hash_head { 972dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_hash_node *lh_first; 973dc7e38acSHans Petter Selasky }; 974dc7e38acSHans Petter Selasky 975dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_db { 976dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 977dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 978dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_info broadcast; 979dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_info allmulti; 980dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_info promisc; 981dc7e38acSHans Petter Selasky bool broadcast_enabled; 982dc7e38acSHans Petter Selasky bool allmulti_enabled; 983dc7e38acSHans Petter Selasky bool promisc_enabled; 984dc7e38acSHans Petter Selasky }; 985dc7e38acSHans Petter Selasky 986dc7e38acSHans Petter Selasky enum { 987dc7e38acSHans Petter Selasky MLX5E_STATE_ASYNC_EVENTS_ENABLE, 988dc7e38acSHans Petter Selasky MLX5E_STATE_OPENED, 989e059c120SHans Petter Selasky MLX5E_STATE_FLOW_RULES_READY, 990dc7e38acSHans Petter Selasky }; 991dc7e38acSHans Petter Selasky 992cfc9c386SHans Petter Selasky enum { 993cfc9c386SHans Petter Selasky MLX5_BW_NO_LIMIT = 0, 994cfc9c386SHans Petter Selasky MLX5_100_MBPS_UNIT = 3, 995cfc9c386SHans Petter Selasky MLX5_GBPS_UNIT = 4, 996cfc9c386SHans Petter Selasky }; 997cfc9c386SHans Petter Selasky 998dc7e38acSHans Petter Selasky struct mlx5e_vlan_db { 999dc7e38acSHans Petter Selasky unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 10005a93b4cdSHans Petter Selasky struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 10015a93b4cdSHans Petter Selasky struct mlx5_flow_rule *untagged_ft_rule; 10025a93b4cdSHans Petter Selasky struct mlx5_flow_rule *any_cvlan_ft_rule; 10035a93b4cdSHans Petter Selasky struct mlx5_flow_rule *any_svlan_ft_rule; 1004dc7e38acSHans Petter Selasky bool filter_disabled; 1005dc7e38acSHans Petter Selasky }; 1006dc7e38acSHans Petter Selasky 1007861a612dSKonstantin Belousov struct mlx5e_vxlan_db_el { 1008861a612dSKonstantin Belousov u_int refcount; 1009861a612dSKonstantin Belousov u_int proto; 1010861a612dSKonstantin Belousov u_int port; 10110e4cb0d5SKonstantin Belousov bool installed; 1012861a612dSKonstantin Belousov struct mlx5_flow_rule *vxlan_ft_rule; 1013861a612dSKonstantin Belousov TAILQ_ENTRY(mlx5e_vxlan_db_el) link; 1014861a612dSKonstantin Belousov }; 1015861a612dSKonstantin Belousov 1016861a612dSKonstantin Belousov struct mlx5e_vxlan_db { 1017861a612dSKonstantin Belousov TAILQ_HEAD(, mlx5e_vxlan_db_el) head; 1018861a612dSKonstantin Belousov }; 1019861a612dSKonstantin Belousov 1020dc7e38acSHans Petter Selasky struct mlx5e_flow_table { 10215a93b4cdSHans Petter Selasky int num_groups; 10225a93b4cdSHans Petter Selasky struct mlx5_flow_table *t; 10235a93b4cdSHans Petter Selasky struct mlx5_flow_group **g; 10245a93b4cdSHans Petter Selasky }; 10255a93b4cdSHans Petter Selasky 10262c0ade80SHans Petter Selasky enum accel_fs_tcp_type { 10272c0ade80SHans Petter Selasky MLX5E_ACCEL_FS_IPV4_TCP, 10282c0ade80SHans Petter Selasky MLX5E_ACCEL_FS_IPV6_TCP, 10292c0ade80SHans Petter Selasky MLX5E_ACCEL_FS_TCP_NUM_TYPES, 10302c0ade80SHans Petter Selasky }; 10312c0ade80SHans Petter Selasky 10322c0ade80SHans Petter Selasky struct mlx5e_accel_fs_tcp { 10332c0ade80SHans Petter Selasky struct mlx5_flow_namespace *ns; 10342c0ade80SHans Petter Selasky struct mlx5e_flow_table tables[MLX5E_ACCEL_FS_TCP_NUM_TYPES]; 10352c0ade80SHans Petter Selasky struct mlx5_flow_rule *default_rules[MLX5E_ACCEL_FS_TCP_NUM_TYPES]; 10362c0ade80SHans Petter Selasky }; 10372c0ade80SHans Petter Selasky 10385a93b4cdSHans Petter Selasky struct mlx5e_flow_tables { 10395a93b4cdSHans Petter Selasky struct mlx5_flow_namespace *ns; 10405a93b4cdSHans Petter Selasky struct mlx5e_flow_table vlan; 1041861a612dSKonstantin Belousov struct mlx5e_flow_table vxlan; 1042861a612dSKonstantin Belousov struct mlx5_flow_rule *vxlan_catchall_ft_rule; 10435a93b4cdSHans Petter Selasky struct mlx5e_flow_table main; 1044861a612dSKonstantin Belousov struct mlx5e_flow_table main_vxlan; 1045861a612dSKonstantin Belousov struct mlx5_flow_rule *main_vxlan_rule[MLX5E_NUM_TT]; 10465a93b4cdSHans Petter Selasky struct mlx5e_flow_table inner_rss; 10472c0ade80SHans Petter Selasky struct mlx5e_accel_fs_tcp accel_tcp; 1048dc7e38acSHans Petter Selasky }; 1049dc7e38acSHans Petter Selasky 10507272f9cdSHans Petter Selasky struct mlx5e_xmit_args { 1051ebdb7006SHans Petter Selasky struct m_snd_tag *mst; 10527272f9cdSHans Petter Selasky u32 tisn; 10537272f9cdSHans Petter Selasky u16 ihs; 10547272f9cdSHans Petter Selasky }; 10557272f9cdSHans Petter Selasky 105689918a23SKonstantin Belousov #include <dev/mlx5/mlx5_en/en_rl.h> 105789918a23SKonstantin Belousov #include <dev/mlx5/mlx5_en/en_hw_tls.h> 105884d7b8e7SHans Petter Selasky #include <dev/mlx5/mlx5_en/en_hw_tls_rx.h> 105938535d6cSHans Petter Selasky 1060ef23f141SKonstantin Belousov #define MLX5E_TSTMP_PREC 10 1061ef23f141SKonstantin Belousov 1062ef23f141SKonstantin Belousov struct mlx5e_clbr_point { 1063ef23f141SKonstantin Belousov uint64_t base_curr; 1064ef23f141SKonstantin Belousov uint64_t base_prev; 1065ef23f141SKonstantin Belousov uint64_t clbr_hw_prev; 1066ef23f141SKonstantin Belousov uint64_t clbr_hw_curr; 1067ef23f141SKonstantin Belousov u_int clbr_gen; 1068ef23f141SKonstantin Belousov }; 1069ef23f141SKonstantin Belousov 1070c28ef249SHans Petter Selasky struct mlx5e_dcbx { 1071c28ef249SHans Petter Selasky u32 cable_len; 1072c28ef249SHans Petter Selasky u32 xoff; 1073c28ef249SHans Petter Selasky }; 1074c28ef249SHans Petter Selasky 1075dc7e38acSHans Petter Selasky struct mlx5e_priv { 10761cbc85fdSHans Petter Selasky struct mlx5_core_dev *mdev; /* must be first */ 10771cbc85fdSHans Petter Selasky 1078dc7e38acSHans Petter Selasky /* priv data path fields - start */ 1079dc7e38acSHans Petter Selasky int order_base_2_num_channels; 1080dc7e38acSHans Petter Selasky int queue_mapping_channel_mask; 1081dc7e38acSHans Petter Selasky int num_tc; 1082dc7e38acSHans Petter Selasky int default_vlan_prio; 1083dc7e38acSHans Petter Selasky /* priv data path fields - end */ 1084dc7e38acSHans Petter Selasky 1085dc7e38acSHans Petter Selasky unsigned long state; 1086dc7e38acSHans Petter Selasky int gone; 1087dc7e38acSHans Petter Selasky #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 1088dc7e38acSHans Petter Selasky #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 1089dc7e38acSHans Petter Selasky #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 10902db3dd50SHans Petter Selasky #define PRIV_ASSERT_LOCKED(priv) sx_assert(&(priv)->state_lock, SA_XLOCKED) 1091dc7e38acSHans Petter Selasky struct sx state_lock; /* Protects Interface state */ 109227b778aeSHans Petter Selasky struct mlx5e_rq drop_rq; 1093dc7e38acSHans Petter Selasky u32 pdn; 1094dc7e38acSHans Petter Selasky u32 tdn; 1095b633e08cSHans Petter Selasky struct mlx5_core_mkey mr; 1096dc7e38acSHans Petter Selasky 1097dc7e38acSHans Petter Selasky u32 tisn[MLX5E_MAX_TX_NUM_TC]; 1098dc7e38acSHans Petter Selasky u32 rqtn; 1099dc7e38acSHans Petter Selasky u32 tirn[MLX5E_NUM_TT]; 1100861a612dSKonstantin Belousov u32 tirn_inner_vxlan[MLX5E_NUM_TT]; 1101dc7e38acSHans Petter Selasky 11025a93b4cdSHans Petter Selasky struct mlx5e_flow_tables fts; 1103dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_db eth_addr; 1104dc7e38acSHans Petter Selasky struct mlx5e_vlan_db vlan; 1105861a612dSKonstantin Belousov struct mlx5e_vxlan_db vxlan; 1106dc7e38acSHans Petter Selasky 1107dc7e38acSHans Petter Selasky struct mlx5e_params params; 1108dc7e38acSHans Petter Selasky struct mlx5e_params_ethtool params_ethtool; 110966d53750SHans Petter Selasky union mlx5_core_pci_diagnostics params_pci; 111066d53750SHans Petter Selasky union mlx5_core_general_diagnostics params_general; 1111dc7e38acSHans Petter Selasky struct mtx async_events_mtx; /* sync hw events */ 1112dc7e38acSHans Petter Selasky struct work_struct update_stats_work; 1113dc7e38acSHans Petter Selasky struct work_struct update_carrier_work; 1114dc7e38acSHans Petter Selasky struct work_struct set_rx_mode_work; 111581b3cdc1SHans Petter Selasky MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 1116dc7e38acSHans Petter Selasky 1117dc7e38acSHans Petter Selasky struct ifnet *ifp; 1118dc7e38acSHans Petter Selasky struct sysctl_ctx_list sysctl_ctx; 1119dc7e38acSHans Petter Selasky struct sysctl_oid *sysctl_ifnet; 1120dc7e38acSHans Petter Selasky struct sysctl_oid *sysctl_hw; 1121dc7e38acSHans Petter Selasky int sysctl_debug; 1122dc7e38acSHans Petter Selasky struct mlx5e_stats stats; 1123dc7e38acSHans Petter Selasky int counter_set_id; 1124dc7e38acSHans Petter Selasky 112517778156SHans Petter Selasky struct workqueue_struct *wq; 112617778156SHans Petter Selasky 1127dc7e38acSHans Petter Selasky eventhandler_tag vlan_detach; 1128dc7e38acSHans Petter Selasky eventhandler_tag vlan_attach; 1129dc7e38acSHans Petter Selasky struct ifmedia media; 1130dc7e38acSHans Petter Selasky int media_status_last; 1131dc7e38acSHans Petter Selasky int media_active_last; 1132861a612dSKonstantin Belousov eventhandler_tag vxlan_start; 1133861a612dSKonstantin Belousov eventhandler_tag vxlan_stop; 1134dc7e38acSHans Petter Selasky 1135dc7e38acSHans Petter Selasky struct callout watchdog; 11367272f9cdSHans Petter Selasky 113738535d6cSHans Petter Selasky struct mlx5e_rl_priv_data rl; 11387272f9cdSHans Petter Selasky 11397272f9cdSHans Petter Selasky struct mlx5e_tls tls; 114084d7b8e7SHans Petter Selasky struct mlx5e_tls_rx tls_rx; 1141ef23f141SKonstantin Belousov 1142ef23f141SKonstantin Belousov struct callout tstmp_clbr; 1143ef23f141SKonstantin Belousov int clbr_done; 1144ef23f141SKonstantin Belousov int clbr_curr; 1145ef23f141SKonstantin Belousov struct mlx5e_clbr_point clbr_points[2]; 1146ef23f141SKonstantin Belousov u_int clbr_gen; 11477cc3ea9cSRandall Stewart uint64_t cclk; 11483230c29dSSlava Shwartsman 1149c28ef249SHans Petter Selasky struct mlx5e_dcbx dcbx; 1150e525a7f0SHans Petter Selasky bool sw_is_port_buf_owner; 1151c28ef249SHans Petter Selasky 1152538ff57bSAndrew Gallatin struct pfil_head *pfil; 11533230c29dSSlava Shwartsman struct mlx5e_channel channel[]; 1154dc7e38acSHans Petter Selasky }; 1155dc7e38acSHans Petter Selasky 1156dc7e38acSHans Petter Selasky #define MLX5E_NET_IP_ALIGN 2 1157dc7e38acSHans Petter Selasky 1158dc7e38acSHans Petter Selasky struct mlx5e_tx_wqe { 1159dc7e38acSHans Petter Selasky struct mlx5_wqe_ctrl_seg ctrl; 1160dc7e38acSHans Petter Selasky struct mlx5_wqe_eth_seg eth; 1161dc7e38acSHans Petter Selasky }; 1162dc7e38acSHans Petter Selasky 116304f1690bSHans Petter Selasky struct mlx5e_tx_umr_wqe { 116404f1690bSHans Petter Selasky struct mlx5_wqe_ctrl_seg ctrl; 116504f1690bSHans Petter Selasky struct mlx5_wqe_umr_ctrl_seg umr; 116604f1690bSHans Petter Selasky uint8_t mkc[64]; 116704f1690bSHans Petter Selasky }; 116804f1690bSHans Petter Selasky 116904f1690bSHans Petter Selasky struct mlx5e_tx_psv_wqe { 117004f1690bSHans Petter Selasky struct mlx5_wqe_ctrl_seg ctrl; 117104f1690bSHans Petter Selasky struct mlx5_seg_set_psv psv; 117204f1690bSHans Petter Selasky }; 117304f1690bSHans Petter Selasky 1174266c81aaSHans Petter Selasky struct mlx5e_tx_qos_remap_wqe { 1175266c81aaSHans Petter Selasky struct mlx5_wqe_ctrl_seg ctrl; 1176266c81aaSHans Petter Selasky struct mlx5_wqe_qos_remap_seg qos_remap; 1177266c81aaSHans Petter Selasky }; 1178266c81aaSHans Petter Selasky 1179dc7e38acSHans Petter Selasky struct mlx5e_rx_wqe { 1180dc7e38acSHans Petter Selasky struct mlx5_wqe_srq_next_seg next; 11812f17f76aSHans Petter Selasky struct mlx5_wqe_data_seg data[]; 1182dc7e38acSHans Petter Selasky }; 1183dc7e38acSHans Petter Selasky 11842f17f76aSHans Petter Selasky /* the size of the structure above must be power of two */ 11852f17f76aSHans Petter Selasky CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe))); 11862f17f76aSHans Petter Selasky 1187dc7e38acSHans Petter Selasky struct mlx5e_eeprom { 1188dc7e38acSHans Petter Selasky int lock_bit; 1189dc7e38acSHans Petter Selasky int i2c_addr; 1190dc7e38acSHans Petter Selasky int page_num; 1191dc7e38acSHans Petter Selasky int device_addr; 1192dc7e38acSHans Petter Selasky int module_num; 1193dc7e38acSHans Petter Selasky int len; 1194dc7e38acSHans Petter Selasky int type; 1195dc7e38acSHans Petter Selasky int page_valid; 1196dc7e38acSHans Petter Selasky u32 *data; 1197dc7e38acSHans Petter Selasky }; 1198dc7e38acSHans Petter Selasky 1199dc7e38acSHans Petter Selasky #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 1200dc7e38acSHans Petter Selasky 12017272f9cdSHans Petter Selasky bool mlx5e_do_send_cqe(struct mlx5e_sq *); 12029eb1e4aaSHans Petter Selasky int mlx5e_get_full_header_size(const struct mbuf *, const struct tcphdr **); 1203dc7e38acSHans Petter Selasky int mlx5e_xmit(struct ifnet *, struct mbuf *); 1204dc7e38acSHans Petter Selasky 1205dc7e38acSHans Petter Selasky int mlx5e_open_locked(struct ifnet *); 1206dc7e38acSHans Petter Selasky int mlx5e_close_locked(struct ifnet *); 1207dc7e38acSHans Petter Selasky 1208dc7e38acSHans Petter Selasky void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 1209bc531a1fSHans Petter Selasky void mlx5e_dump_err_cqe(struct mlx5e_cq *, u32, const struct mlx5_err_cqe *); 1210bc531a1fSHans Petter Selasky 1211f34f0a65SHans Petter Selasky mlx5e_cq_comp_t mlx5e_rx_cq_comp; 1212f34f0a65SHans Petter Selasky mlx5e_cq_comp_t mlx5e_tx_cq_comp; 1213dc7e38acSHans Petter Selasky struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 1214dc7e38acSHans Petter Selasky 1215423530beSHans Petter Selasky void mlx5e_dim_work(struct work_struct *); 1216423530beSHans Petter Selasky void mlx5e_dim_build_cq_param(struct mlx5e_priv *, struct mlx5e_cq_param *); 1217423530beSHans Petter Selasky 1218e059c120SHans Petter Selasky int mlx5e_open_flow_tables(struct mlx5e_priv *priv); 1219e059c120SHans Petter Selasky void mlx5e_close_flow_tables(struct mlx5e_priv *priv); 1220e059c120SHans Petter Selasky int mlx5e_open_flow_rules(struct mlx5e_priv *priv); 1221e059c120SHans Petter Selasky void mlx5e_close_flow_rules(struct mlx5e_priv *priv); 1222dc7e38acSHans Petter Selasky void mlx5e_set_rx_mode_work(struct work_struct *work); 1223dc7e38acSHans Petter Selasky 1224dc7e38acSHans Petter Selasky void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 1225dc7e38acSHans Petter Selasky void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 1226dc7e38acSHans Petter Selasky void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 1227dc7e38acSHans Petter Selasky void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 1228dc7e38acSHans Petter Selasky 1229861a612dSKonstantin Belousov void mlx5e_vxlan_start(void *arg, struct ifnet *ifp, sa_family_t family, 1230861a612dSKonstantin Belousov u_int port); 1231861a612dSKonstantin Belousov void mlx5e_vxlan_stop(void *arg, struct ifnet *ifp, sa_family_t family, 1232861a612dSKonstantin Belousov u_int port); 12330e4cb0d5SKonstantin Belousov int mlx5e_add_all_vxlan_rules(struct mlx5e_priv *priv); 12340e4cb0d5SKonstantin Belousov void mlx5e_del_all_vxlan_rules(struct mlx5e_priv *priv); 12350e4cb0d5SKonstantin Belousov 1236dc7e38acSHans Petter Selasky static inline void 12372d5e5a0dSHans Petter Selasky mlx5e_tx_notify_hw(struct mlx5e_sq *sq, bool force) 1238dc7e38acSHans Petter Selasky { 12392d5e5a0dSHans Petter Selasky if (unlikely((force == false && sq->db_inhibit != 0) || sq->doorbell.d64 == 0)) { 12402d5e5a0dSHans Petter Selasky /* skip writing the doorbell record */ 12412d5e5a0dSHans Petter Selasky return; 12422d5e5a0dSHans Petter Selasky } 12432d5e5a0dSHans Petter Selasky 1244dc7e38acSHans Petter Selasky /* ensure wqe is visible to device before updating doorbell record */ 1245dc7e38acSHans Petter Selasky wmb(); 1246dc7e38acSHans Petter Selasky 1247dc7e38acSHans Petter Selasky *sq->wq.db = cpu_to_be32(sq->pc); 1248dc7e38acSHans Petter Selasky 1249dc7e38acSHans Petter Selasky /* 1250dc7e38acSHans Petter Selasky * Ensure the doorbell record is visible to device before ringing 1251dc7e38acSHans Petter Selasky * the doorbell: 1252dc7e38acSHans Petter Selasky */ 1253dc7e38acSHans Petter Selasky wmb(); 1254dc7e38acSHans Petter Selasky 12552d5e5a0dSHans Petter Selasky mlx5_write64(sq->doorbell.d32, sq->uar_map, 125681b3cdc1SHans Petter Selasky MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 12572d5e5a0dSHans Petter Selasky 12582d5e5a0dSHans Petter Selasky sq->doorbell.d64 = 0; 1259dc7e38acSHans Petter Selasky } 1260dc7e38acSHans Petter Selasky 1261dc7e38acSHans Petter Selasky static inline void 1262e5d6b589SHans Petter Selasky mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 1263dc7e38acSHans Petter Selasky { 1264dc7e38acSHans Petter Selasky struct mlx5_core_cq *mcq; 1265dc7e38acSHans Petter Selasky 1266dc7e38acSHans Petter Selasky mcq = &cq->mcq; 1267e5d6b589SHans Petter Selasky mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 1268dc7e38acSHans Petter Selasky } 1269dc7e38acSHans Petter Selasky 1270d585ff62SHans Petter Selasky #define mlx5e_dbg(_IGN, _priv, ...) mlx5_core_dbg((_priv)->mdev, __VA_ARGS__) 1271d585ff62SHans Petter Selasky 1272dc7e38acSHans Petter Selasky extern const struct ethtool_ops mlx5e_ethtool_ops; 1273dc7e38acSHans Petter Selasky void mlx5e_create_ethtool(struct mlx5e_priv *); 1274dc7e38acSHans Petter Selasky void mlx5e_create_stats(struct sysctl_ctx_list *, 1275dc7e38acSHans Petter Selasky struct sysctl_oid_list *, const char *, 1276dc7e38acSHans Petter Selasky const char **, unsigned, u64 *); 12777272f9cdSHans Petter Selasky void mlx5e_create_counter_stats(struct sysctl_ctx_list *, 12787272f9cdSHans Petter Selasky struct sysctl_oid_list *, const char *, 12797272f9cdSHans Petter Selasky const char **, unsigned, counter_u64_t *); 1280af89c4afSHans Petter Selasky void mlx5e_send_nop(struct mlx5e_sq *, u32); 12817272f9cdSHans Petter Selasky int mlx5e_sq_dump_xmit(struct mlx5e_sq *, struct mlx5e_xmit_args *, struct mbuf **); 12827272f9cdSHans Petter Selasky int mlx5e_sq_xmit(struct mlx5e_sq *, struct mbuf **); 1283376bcf63SHans Petter Selasky void mlx5e_sq_cev_timeout(void *); 1284f03f517bSHans Petter Selasky int mlx5e_refresh_channel_params(struct mlx5e_priv *); 128528f22cceSHans Petter Selasky int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 128628f22cceSHans Petter Selasky struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 128728f22cceSHans Petter Selasky void mlx5e_close_cq(struct mlx5e_cq *); 12887b4e6e4aSHans Petter Selasky void mlx5e_free_sq_db(struct mlx5e_sq *); 12897b4e6e4aSHans Petter Selasky int mlx5e_alloc_sq_db(struct mlx5e_sq *); 12909dfa2148SHans Petter Selasky int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, 12919dfa2148SHans Petter Selasky const struct mlx5_sq_bfreg *, int tis_num); 12927b4e6e4aSHans Petter Selasky int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 12937b4e6e4aSHans Petter Selasky void mlx5e_disable_sq(struct mlx5e_sq *); 12947b4e6e4aSHans Petter Selasky void mlx5e_drain_sq(struct mlx5e_sq *); 1295bb3616abSHans Petter Selasky void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 1296bb3616abSHans Petter Selasky void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 1297bb3616abSHans Petter Selasky void mlx5e_resume_sq(struct mlx5e_sq *sq); 12983e581cabSSlava Shwartsman void mlx5e_update_sq_inline(struct mlx5e_sq *sq); 12993e581cabSSlava Shwartsman void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv); 13006deb0b1eSHans Petter Selasky int mlx5e_update_buf_lossy(struct mlx5e_priv *priv); 130196425f44SHans Petter Selasky int mlx5e_fec_update(struct mlx5e_priv *priv); 1302decb087cSHans Petter Selasky int mlx5e_hw_temperature_update(struct mlx5e_priv *priv); 1303dc7e38acSHans Petter Selasky 130469426357SHans Petter Selasky /* Internal Queue, IQ, API functions */ 130569426357SHans Petter Selasky void mlx5e_iq_send_nop(struct mlx5e_iq *, u32); 130669426357SHans Petter Selasky int mlx5e_iq_open(struct mlx5e_channel *, struct mlx5e_sq_param *, struct mlx5e_cq_param *, struct mlx5e_iq *); 130769426357SHans Petter Selasky void mlx5e_iq_close(struct mlx5e_iq *); 130869426357SHans Petter Selasky void mlx5e_iq_static_init(struct mlx5e_iq *); 130969426357SHans Petter Selasky void mlx5e_iq_static_destroy(struct mlx5e_iq *); 131069426357SHans Petter Selasky void mlx5e_iq_notify_hw(struct mlx5e_iq *); 131169426357SHans Petter Selasky int mlx5e_iq_get_producer_index(struct mlx5e_iq *); 131269426357SHans Petter Selasky void mlx5e_iq_load_memory_single(struct mlx5e_iq *, u16, void *, size_t, u64 *, u32); 131369426357SHans Petter Selasky 1314dc7e38acSHans Petter Selasky #endif /* _MLX5_EN_H_ */ 1315