1dc7e38acSHans Petter Selasky /*- 267fd1941SHans Petter Selasky * Copyright (c) 2015-2019 Mellanox Technologies. All rights reserved. 3dc7e38acSHans Petter Selasky * 4dc7e38acSHans Petter Selasky * Redistribution and use in source and binary forms, with or without 5dc7e38acSHans Petter Selasky * modification, are permitted provided that the following conditions 6dc7e38acSHans Petter Selasky * are met: 7dc7e38acSHans Petter Selasky * 1. Redistributions of source code must retain the above copyright 8dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer. 9dc7e38acSHans Petter Selasky * 2. Redistributions in binary form must reproduce the above copyright 10dc7e38acSHans Petter Selasky * notice, this list of conditions and the following disclaimer in the 11dc7e38acSHans Petter Selasky * documentation and/or other materials provided with the distribution. 12dc7e38acSHans Petter Selasky * 13dc7e38acSHans Petter Selasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14dc7e38acSHans Petter Selasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15dc7e38acSHans Petter Selasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16dc7e38acSHans Petter Selasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17dc7e38acSHans Petter Selasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18dc7e38acSHans Petter Selasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19dc7e38acSHans Petter Selasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20dc7e38acSHans Petter Selasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21dc7e38acSHans Petter Selasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22dc7e38acSHans Petter Selasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23dc7e38acSHans Petter Selasky * SUCH DAMAGE. 24dc7e38acSHans Petter Selasky * 25dc7e38acSHans Petter Selasky * $FreeBSD$ 26dc7e38acSHans Petter Selasky */ 27dc7e38acSHans Petter Selasky 28dc7e38acSHans Petter Selasky #ifndef _MLX5_EN_H_ 29dc7e38acSHans Petter Selasky #define _MLX5_EN_H_ 30dc7e38acSHans Petter Selasky 31dc7e38acSHans Petter Selasky #include <linux/kmod.h> 32dc7e38acSHans Petter Selasky #include <linux/page.h> 33dc7e38acSHans Petter Selasky #include <linux/slab.h> 34dc7e38acSHans Petter Selasky #include <linux/if_vlan.h> 35dc7e38acSHans Petter Selasky #include <linux/if_ether.h> 36dc7e38acSHans Petter Selasky #include <linux/vmalloc.h> 37dc7e38acSHans Petter Selasky #include <linux/moduleparam.h> 38dc7e38acSHans Petter Selasky #include <linux/delay.h> 39dc7e38acSHans Petter Selasky #include <linux/netdevice.h> 40dc7e38acSHans Petter Selasky #include <linux/etherdevice.h> 41423530beSHans Petter Selasky #include <linux/ktime.h> 42423530beSHans Petter Selasky #include <linux/net_dim.h> 43dc7e38acSHans Petter Selasky 44dc7e38acSHans Petter Selasky #include <netinet/in_systm.h> 45dc7e38acSHans Petter Selasky #include <netinet/in.h> 46dc7e38acSHans Petter Selasky #include <netinet/if_ether.h> 47dc7e38acSHans Petter Selasky #include <netinet/ip.h> 48dc7e38acSHans Petter Selasky #include <netinet/ip6.h> 49dc7e38acSHans Petter Selasky #include <netinet/tcp.h> 50dc7e38acSHans Petter Selasky #include <netinet/tcp_lro.h> 51dc7e38acSHans Petter Selasky #include <netinet/udp.h> 52dc7e38acSHans Petter Selasky #include <net/ethernet.h> 53538ff57bSAndrew Gallatin #include <net/pfil.h> 54dc7e38acSHans Petter Selasky #include <sys/buf_ring.h> 5538535d6cSHans Petter Selasky #include <sys/kthread.h> 56dc7e38acSHans Petter Selasky 57278ce1c9SHans Petter Selasky #include "opt_rss.h" 58278ce1c9SHans Petter Selasky 59278ce1c9SHans Petter Selasky #ifdef RSS 60278ce1c9SHans Petter Selasky #include <net/rss_config.h> 61278ce1c9SHans Petter Selasky #include <netinet/in_rss.h> 62278ce1c9SHans Petter Selasky #endif 63278ce1c9SHans Petter Selasky 64dc7e38acSHans Petter Selasky #include <machine/bus.h> 65dc7e38acSHans Petter Selasky 66dc7e38acSHans Petter Selasky #include <dev/mlx5/driver.h> 67dc7e38acSHans Petter Selasky #include <dev/mlx5/qp.h> 68dc7e38acSHans Petter Selasky #include <dev/mlx5/cq.h> 69d9142151SHans Petter Selasky #include <dev/mlx5/port.h> 70dc7e38acSHans Petter Selasky #include <dev/mlx5/vport.h> 7166d53750SHans Petter Selasky #include <dev/mlx5/diagnostics.h> 72dc7e38acSHans Petter Selasky 73dc7e38acSHans Petter Selasky #include <dev/mlx5/mlx5_core/wq.h> 74dc7e38acSHans Petter Selasky #include <dev/mlx5/mlx5_core/transobj.h> 75dc7e38acSHans Petter Selasky #include <dev/mlx5/mlx5_core/mlx5_core.h> 76dc7e38acSHans Petter Selasky 7724385321SHans Petter Selasky #define MLX5E_MAX_PRIORITY 8 7824385321SHans Petter Selasky 7924385321SHans Petter Selasky /* IEEE 802.1Qaz standard supported values */ 80cfc9c386SHans Petter Selasky #define IEEE_8021QAZ_MAX_TCS 8 81cfc9c386SHans Petter Selasky 82dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 83dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 84351a9c7cSHans Petter Selasky #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 85dc7e38acSHans Petter Selasky 86dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 87dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 88351a9c7cSHans Petter Selasky #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 89dc7e38acSHans Petter Selasky 902f17f76aSHans Petter Selasky #define MLX5E_MAX_RX_SEGS 7 912f17f76aSHans Petter Selasky 922f17f76aSHans Petter Selasky #ifndef MLX5E_MAX_RX_BYTES 932f17f76aSHans Petter Selasky #define MLX5E_MAX_RX_BYTES MCLBYTES 942f17f76aSHans Petter Selasky #endif 952f17f76aSHans Petter Selasky 962f17f76aSHans Petter Selasky #if (MLX5E_MAX_RX_SEGS == 1) 972f17f76aSHans Petter Selasky /* FreeBSD HW LRO is limited by 16KB - the size of max mbuf */ 98dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES 992f17f76aSHans Petter Selasky #else 1002f17f76aSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \ 1012f17f76aSHans Petter Selasky MIN(65535, MLX5E_MAX_RX_SEGS * MLX5E_MAX_RX_BYTES) 1022f17f76aSHans Petter Selasky #endif 103423530beSHans Petter Selasky #define MLX5E_DIM_DEFAULT_PROFILE 3 104423530beSHans Petter Selasky #define MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO 16 105dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 106dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 107dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 108dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 109dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 110dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 111dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 112dc7e38acSHans Petter Selasky #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 113dc7e38acSHans Petter Selasky #define MLX5E_HW2SW_MTU(hwmtu) \ 114dc7e38acSHans Petter Selasky ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 115dc7e38acSHans Petter Selasky #define MLX5E_SW2HW_MTU(swmtu) \ 116dc7e38acSHans Petter Selasky ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 117dc7e38acSHans Petter Selasky #define MLX5E_SW2MB_MTU(swmtu) \ 118dc7e38acSHans Petter Selasky (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 119dc7e38acSHans Petter Selasky #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 120bb3853c6SHans Petter Selasky #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 121bb3853c6SHans Petter Selasky * jumbo frames */ 122dc7e38acSHans Petter Selasky 123dc7e38acSHans Petter Selasky #define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 124dc7e38acSHans Petter Selasky #define MLX5E_RX_BUDGET_MAX 256 125dc7e38acSHans Petter Selasky #define MLX5E_SQ_BF_BUDGET 16 126dc7e38acSHans Petter Selasky #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 127dc7e38acSHans Petter Selasky 128dc7e38acSHans Petter Selasky #define MLX5E_MAX_TX_NUM_TC 8 /* units */ 129dc7e38acSHans Petter Selasky #define MLX5E_MAX_TX_HEADER 128 /* bytes */ 130dc7e38acSHans Petter Selasky #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 131dc7e38acSHans Petter Selasky #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 132dc7e38acSHans Petter Selasky #define MLX5E_MAX_TX_MBUF_FRAGS \ 133dc7e38acSHans Petter Selasky ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 1342d32b0a3SHans Petter Selasky (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \ 1352d32b0a3SHans Petter Selasky 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */ 136dc7e38acSHans Petter Selasky #define MLX5E_MAX_TX_INLINE \ 137dc7e38acSHans Petter Selasky (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 138dc7e38acSHans Petter Selasky sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 139dc7e38acSHans Petter Selasky 140cfc9c386SHans Petter Selasky #define MLX5E_100MB (100000) 141cfc9c386SHans Petter Selasky #define MLX5E_1GB (1000000) 142cfc9c386SHans Petter Selasky 143dc7e38acSHans Petter Selasky MALLOC_DECLARE(M_MLX5EN); 144dc7e38acSHans Petter Selasky 145dc7e38acSHans Petter Selasky struct mlx5_core_dev; 146dc7e38acSHans Petter Selasky struct mlx5e_cq; 147dc7e38acSHans Petter Selasky 148dc7e38acSHans Petter Selasky typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 149dc7e38acSHans Petter Selasky 15067fd1941SHans Petter Selasky #define MLX5E_STATS_COUNT(a, ...) a 15167fd1941SHans Petter Selasky #define MLX5E_STATS_VAR(a, b, c, ...) b c; 15267fd1941SHans Petter Selasky #define MLX5E_STATS_DESC(a, b, c, d, e, ...) d, e, 153dc7e38acSHans Petter Selasky 154dc7e38acSHans Petter Selasky #define MLX5E_VPORT_STATS(m) \ 155dc7e38acSHans Petter Selasky /* HW counters */ \ 15667fd1941SHans Petter Selasky m(+1, u64, rx_packets, "rx_packets", "Received packets") \ 15767fd1941SHans Petter Selasky m(+1, u64, rx_bytes, "rx_bytes", "Received bytes") \ 15867fd1941SHans Petter Selasky m(+1, u64, tx_packets, "tx_packets", "Transmitted packets") \ 15967fd1941SHans Petter Selasky m(+1, u64, tx_bytes, "tx_bytes", "Transmitted bytes") \ 16067fd1941SHans Petter Selasky m(+1, u64, rx_error_packets, "rx_error_packets", "Received error packets") \ 16167fd1941SHans Petter Selasky m(+1, u64, rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 16267fd1941SHans Petter Selasky m(+1, u64, tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 16367fd1941SHans Petter Selasky m(+1, u64, tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 16467fd1941SHans Petter Selasky m(+1, u64, rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 16567fd1941SHans Petter Selasky m(+1, u64, rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 16667fd1941SHans Petter Selasky m(+1, u64, tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 16767fd1941SHans Petter Selasky m(+1, u64, tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 16867fd1941SHans Petter Selasky m(+1, u64, rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 16967fd1941SHans Petter Selasky m(+1, u64, rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 17067fd1941SHans Petter Selasky m(+1, u64, tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 17167fd1941SHans Petter Selasky m(+1, u64, tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 17267fd1941SHans Petter Selasky m(+1, u64, rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 17367fd1941SHans Petter Selasky m(+1, u64, rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 17467fd1941SHans Petter Selasky m(+1, u64, tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 17567fd1941SHans Petter Selasky m(+1, u64, tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 17667fd1941SHans Petter Selasky m(+1, u64, rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 177dc7e38acSHans Petter Selasky /* SW counters */ \ 17867fd1941SHans Petter Selasky m(+1, u64, tso_packets, "tso_packets", "Transmitted TSO packets") \ 17967fd1941SHans Petter Selasky m(+1, u64, tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 18067fd1941SHans Petter Selasky m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 18167fd1941SHans Petter Selasky m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 18267fd1941SHans Petter Selasky m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 18367fd1941SHans Petter Selasky m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 18467fd1941SHans Petter Selasky m(+1, u64, rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 18567fd1941SHans Petter Selasky m(+1, u64, rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 18667fd1941SHans Petter Selasky m(+1, u64, tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 18767fd1941SHans Petter Selasky m(+1, u64, tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 18867fd1941SHans Petter Selasky m(+1, u64, tx_defragged, "tx_defragged", "Transmit queue defragged") \ 18967fd1941SHans Petter Selasky m(+1, u64, rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \ 19067fd1941SHans Petter Selasky m(+1, u64, tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") \ 19167fd1941SHans Petter Selasky m(+1, u64, rx_steer_missed_packets, "rx_steer_missed_packets", "RX packets dropped by steering rule(s)") 192dc7e38acSHans Petter Selasky 193dc7e38acSHans Petter Selasky #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 194dc7e38acSHans Petter Selasky 195dc7e38acSHans Petter Selasky struct mlx5e_vport_stats { 196dc7e38acSHans Petter Selasky struct sysctl_ctx_list ctx; 197dc7e38acSHans Petter Selasky u64 arg [0]; 198dc7e38acSHans Petter Selasky MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 199dc7e38acSHans Petter Selasky }; 200dc7e38acSHans Petter Selasky 201dc7e38acSHans Petter Selasky #define MLX5E_PPORT_IEEE802_3_STATS(m) \ 20267fd1941SHans Petter Selasky m(+1, u64, frames_tx, "frames_tx", "Frames transmitted") \ 20367fd1941SHans Petter Selasky m(+1, u64, frames_rx, "frames_rx", "Frames received") \ 20467fd1941SHans Petter Selasky m(+1, u64, check_seq_err, "check_seq_err", "Sequence errors") \ 20567fd1941SHans Petter Selasky m(+1, u64, alignment_err, "alignment_err", "Alignment errors") \ 20667fd1941SHans Petter Selasky m(+1, u64, octets_tx, "octets_tx", "Bytes transmitted") \ 20767fd1941SHans Petter Selasky m(+1, u64, octets_received, "octets_received", "Bytes received") \ 20867fd1941SHans Petter Selasky m(+1, u64, multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 20967fd1941SHans Petter Selasky m(+1, u64, broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 21067fd1941SHans Petter Selasky m(+1, u64, multicast_rx, "multicast_rx", "Multicast received") \ 21167fd1941SHans Petter Selasky m(+1, u64, broadcast_rx, "broadcast_rx", "Broadcast received") \ 21267fd1941SHans Petter Selasky m(+1, u64, in_range_len_errors, "in_range_len_errors", "In range length errors") \ 21367fd1941SHans Petter Selasky m(+1, u64, out_of_range_len, "out_of_range_len", "Out of range length errors") \ 21467fd1941SHans Petter Selasky m(+1, u64, too_long_errors, "too_long_errors", "Too long errors") \ 21567fd1941SHans Petter Selasky m(+1, u64, symbol_err, "symbol_err", "Symbol errors") \ 21667fd1941SHans Petter Selasky m(+1, u64, mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 21767fd1941SHans Petter Selasky m(+1, u64, mac_control_rx, "mac_control_rx", "MAC control received") \ 21867fd1941SHans Petter Selasky m(+1, u64, unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 21967fd1941SHans Petter Selasky m(+1, u64, pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 22067fd1941SHans Petter Selasky m(+1, u64, pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 221dc7e38acSHans Petter Selasky 222dc7e38acSHans Petter Selasky #define MLX5E_PPORT_RFC2819_STATS(m) \ 22367fd1941SHans Petter Selasky m(+1, u64, drop_events, "drop_events", "Dropped events") \ 22467fd1941SHans Petter Selasky m(+1, u64, octets, "octets", "Octets") \ 22567fd1941SHans Petter Selasky m(+1, u64, pkts, "pkts", "Packets") \ 22667fd1941SHans Petter Selasky m(+1, u64, broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 22767fd1941SHans Petter Selasky m(+1, u64, multicast_pkts, "multicast_pkts", "Multicast packets") \ 22867fd1941SHans Petter Selasky m(+1, u64, crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 22967fd1941SHans Petter Selasky m(+1, u64, undersize_pkts, "undersize_pkts", "Undersized packets") \ 23067fd1941SHans Petter Selasky m(+1, u64, oversize_pkts, "oversize_pkts", "Oversized packets") \ 23167fd1941SHans Petter Selasky m(+1, u64, fragments, "fragments", "Fragments") \ 23267fd1941SHans Petter Selasky m(+1, u64, jabbers, "jabbers", "Jabbers") \ 23367fd1941SHans Petter Selasky m(+1, u64, collisions, "collisions", "Collisions") 234dc7e38acSHans Petter Selasky 235dc7e38acSHans Petter Selasky #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 23667fd1941SHans Petter Selasky m(+1, u64, p64octets, "p64octets", "Bytes") \ 23767fd1941SHans Petter Selasky m(+1, u64, p65to127octets, "p65to127octets", "Bytes") \ 23867fd1941SHans Petter Selasky m(+1, u64, p128to255octets, "p128to255octets", "Bytes") \ 23967fd1941SHans Petter Selasky m(+1, u64, p256to511octets, "p256to511octets", "Bytes") \ 24067fd1941SHans Petter Selasky m(+1, u64, p512to1023octets, "p512to1023octets", "Bytes") \ 24167fd1941SHans Petter Selasky m(+1, u64, p1024to1518octets, "p1024to1518octets", "Bytes") \ 24267fd1941SHans Petter Selasky m(+1, u64, p1519to2047octets, "p1519to2047octets", "Bytes") \ 24367fd1941SHans Petter Selasky m(+1, u64, p2048to4095octets, "p2048to4095octets", "Bytes") \ 24467fd1941SHans Petter Selasky m(+1, u64, p4096to8191octets, "p4096to8191octets", "Bytes") \ 24567fd1941SHans Petter Selasky m(+1, u64, p8192to10239octets, "p8192to10239octets", "Bytes") 246dc7e38acSHans Petter Selasky 247dc7e38acSHans Petter Selasky #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 24867fd1941SHans Petter Selasky m(+1, u64, in_octets, "in_octets", "In octets") \ 24967fd1941SHans Petter Selasky m(+1, u64, in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 25067fd1941SHans Petter Selasky m(+1, u64, in_discards, "in_discards", "In discards") \ 25167fd1941SHans Petter Selasky m(+1, u64, in_errors, "in_errors", "In errors") \ 25267fd1941SHans Petter Selasky m(+1, u64, in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 25367fd1941SHans Petter Selasky m(+1, u64, out_octets, "out_octets", "Out octets") \ 25467fd1941SHans Petter Selasky m(+1, u64, out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 25567fd1941SHans Petter Selasky m(+1, u64, out_discards, "out_discards", "Out discards") \ 25667fd1941SHans Petter Selasky m(+1, u64, out_errors, "out_errors", "Out errors") \ 25767fd1941SHans Petter Selasky m(+1, u64, in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 25867fd1941SHans Petter Selasky m(+1, u64, in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 25967fd1941SHans Petter Selasky m(+1, u64, out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 26067fd1941SHans Petter Selasky m(+1, u64, out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 261dc7e38acSHans Petter Selasky 262bcfad025SHans Petter Selasky #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 26367fd1941SHans Petter Selasky m(+1, u64, port_transmit_wait_high, "port_transmit_wait_high", "Port transmit wait high") \ 26467fd1941SHans Petter Selasky m(+1, u64, ecn_marked, "ecn_marked", "ECN marked") \ 26567fd1941SHans Petter Selasky m(+1, u64, no_buffer_discard_mc, "no_buffer_discard_mc", "No buffer discard mc") \ 26667fd1941SHans Petter Selasky m(+1, u64, rx_ebp, "rx_ebp", "RX EBP") \ 26767fd1941SHans Petter Selasky m(+1, u64, tx_ebp, "tx_ebp", "TX EBP") \ 26867fd1941SHans Petter Selasky m(+1, u64, rx_buffer_almost_full, "rx_buffer_almost_full", "RX buffer almost full") \ 26967fd1941SHans Petter Selasky m(+1, u64, rx_buffer_full, "rx_buffer_full", "RX buffer full") \ 27067fd1941SHans Petter Selasky m(+1, u64, rx_icrc_encapsulated, "rx_icrc_encapsulated", "RX ICRC encapsulated") \ 27167fd1941SHans Petter Selasky m(+1, u64, ex_reserved_0, "ex_reserved_0", "Reserved") \ 27267fd1941SHans Petter Selasky m(+1, u64, ex_reserved_1, "ex_reserved_1", "Reserved") \ 27367fd1941SHans Petter Selasky m(+1, u64, tx_stat_p64octets, "tx_stat_p64octets", "Bytes") \ 27467fd1941SHans Petter Selasky m(+1, u64, tx_stat_p65to127octets, "tx_stat_p65to127octets", "Bytes") \ 27567fd1941SHans Petter Selasky m(+1, u64, tx_stat_p128to255octets, "tx_stat_p128to255octets", "Bytes") \ 27667fd1941SHans Petter Selasky m(+1, u64, tx_stat_p256to511octets, "tx_stat_p256to511octets", "Bytes") \ 27767fd1941SHans Petter Selasky m(+1, u64, tx_stat_p512to1023octets, "tx_stat_p512to1023octets", "Bytes") \ 27867fd1941SHans Petter Selasky m(+1, u64, tx_stat_p1024to1518octets, "tx_stat_p1024to1518octets", "Bytes") \ 27967fd1941SHans Petter Selasky m(+1, u64, tx_stat_p1519to2047octets, "tx_stat_p1519to2047octets", "Bytes") \ 28067fd1941SHans Petter Selasky m(+1, u64, tx_stat_p2048to4095octets, "tx_stat_p2048to4095octets", "Bytes") \ 28167fd1941SHans Petter Selasky m(+1, u64, tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \ 28267fd1941SHans Petter Selasky m(+1, u64, tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes") 283bcfad025SHans Petter Selasky 284c62f4d8dSHans Petter Selasky #define MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 285c62f4d8dSHans Petter Selasky m(+1, u64, phy_time_since_last_clear, "phy_time_since_last_clear", \ 286c62f4d8dSHans Petter Selasky "Time since last clear in milliseconds") \ 287c62f4d8dSHans Petter Selasky m(+1, u64, phy_received_bits, "phy_received_bits", \ 288c62f4d8dSHans Petter Selasky "Total amount of traffic received in bits before error correction") \ 289c62f4d8dSHans Petter Selasky m(+1, u64, phy_symbol_errors, "phy_symbol_errors", \ 290c62f4d8dSHans Petter Selasky "Total number of symbol errors before error correction") \ 291c62f4d8dSHans Petter Selasky m(+1, u64, phy_corrected_bits, "phy_corrected_bits", \ 292c62f4d8dSHans Petter Selasky "Total number of corrected bits ") \ 293c62f4d8dSHans Petter Selasky m(+1, u64, phy_corrected_bits_lane0, "phy_corrected_bits_lane0", \ 294c62f4d8dSHans Petter Selasky "Total number of corrected bits for lane 0") \ 295c62f4d8dSHans Petter Selasky m(+1, u64, phy_corrected_bits_lane1, "phy_corrected_bits_lane1", \ 296c62f4d8dSHans Petter Selasky "Total number of corrected bits for lane 1") \ 297c62f4d8dSHans Petter Selasky m(+1, u64, phy_corrected_bits_lane2, "phy_corrected_bits_lane2", \ 298c62f4d8dSHans Petter Selasky "Total number of corrected bits for lane 2") \ 299c62f4d8dSHans Petter Selasky m(+1, u64, phy_corrected_bits_lane3, "phy_corrected_bits_lane3", \ 300c62f4d8dSHans Petter Selasky "Total number of corrected bits for lane 3") 301c62f4d8dSHans Petter Selasky 302dc7e38acSHans Petter Selasky #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 30367fd1941SHans Petter Selasky m(+1, u64, time_since_last_clear, "time_since_last_clear", \ 304dc7e38acSHans Petter Selasky "Time since the last counters clear event (msec)") \ 30567fd1941SHans Petter Selasky m(+1, u64, symbol_errors, "symbol_errors", "Symbol errors") \ 30667fd1941SHans Petter Selasky m(+1, u64, sync_headers_errors, "sync_headers_errors", \ 30767fd1941SHans Petter Selasky "Sync header error counter") \ 30867fd1941SHans Petter Selasky m(+1, u64, bip_errors_lane0, "edpl_bip_errors_lane0", \ 309dc7e38acSHans Petter Selasky "Indicates the number of PRBS errors on lane 0") \ 31067fd1941SHans Petter Selasky m(+1, u64, bip_errors_lane1, "edpl_bip_errors_lane1", \ 311dc7e38acSHans Petter Selasky "Indicates the number of PRBS errors on lane 1") \ 31267fd1941SHans Petter Selasky m(+1, u64, bip_errors_lane2, "edpl_bip_errors_lane2", \ 313dc7e38acSHans Petter Selasky "Indicates the number of PRBS errors on lane 2") \ 31467fd1941SHans Petter Selasky m(+1, u64, bip_errors_lane3, "edpl_bip_errors_lane3", \ 315dc7e38acSHans Petter Selasky "Indicates the number of PRBS errors on lane 3") \ 31667fd1941SHans Petter Selasky m(+1, u64, fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 317dc7e38acSHans Petter Selasky "FEC correctable block counter lane 0") \ 31867fd1941SHans Petter Selasky m(+1, u64, fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 319dc7e38acSHans Petter Selasky "FEC correctable block counter lane 1") \ 32067fd1941SHans Petter Selasky m(+1, u64, fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 321dc7e38acSHans Petter Selasky "FEC correctable block counter lane 2") \ 32267fd1941SHans Petter Selasky m(+1, u64, fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 323dc7e38acSHans Petter Selasky "FEC correctable block counter lane 3") \ 32467fd1941SHans Petter Selasky m(+1, u64, rs_corrected_blocks, "rs_corrected_blocks", \ 325dc7e38acSHans Petter Selasky "FEC correcable block counter") \ 32667fd1941SHans Petter Selasky m(+1, u64, rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 327dc7e38acSHans Petter Selasky "FEC uncorrecable block counter") \ 32867fd1941SHans Petter Selasky m(+1, u64, rs_no_errors_blocks, "rs_no_errors_blocks", \ 329dc7e38acSHans Petter Selasky "The number of RS-FEC blocks received that had no errors") \ 33067fd1941SHans Petter Selasky m(+1, u64, rs_single_error_blocks, "rs_single_error_blocks", \ 331dc7e38acSHans Petter Selasky "The number of corrected RS-FEC blocks received that had" \ 332dc7e38acSHans Petter Selasky "exactly 1 error symbol") \ 33367fd1941SHans Petter Selasky m(+1, u64, rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 334dc7e38acSHans Petter Selasky "Port FEC corrected symbol counter") \ 33567fd1941SHans Petter Selasky m(+1, u64, rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 336dc7e38acSHans Petter Selasky "FEC corrected symbol counter lane 0") \ 33767fd1941SHans Petter Selasky m(+1, u64, rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 338dc7e38acSHans Petter Selasky "FEC corrected symbol counter lane 1") \ 33967fd1941SHans Petter Selasky m(+1, u64, rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 340dc7e38acSHans Petter Selasky "FEC corrected symbol counter lane 2") \ 34167fd1941SHans Petter Selasky m(+1, u64, rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 34210b08045SHans Petter Selasky "FEC corrected symbol counter lane 3") 34310b08045SHans Petter Selasky 34410b08045SHans Petter Selasky /* Per priority statistics for PFC */ 34510b08045SHans Petter Selasky #define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 34610b08045SHans Petter Selasky m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 34710b08045SHans Petter Selasky m(n, p, +1, u64, reserved_0, "reserved_0", "Reserved") \ 34810b08045SHans Petter Selasky m(n, p, +1, u64, reserved_1, "reserved_1", "Reserved") \ 34910b08045SHans Petter Selasky m(n, p, +1, u64, reserved_2, "reserved_2", "Reserved") \ 35010b08045SHans Petter Selasky m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 35110b08045SHans Petter Selasky m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 35210b08045SHans Petter Selasky m(n, p, +1, u64, reserved_3, "reserved_3", "Reserved") \ 35310b08045SHans Petter Selasky m(n, p, +1, u64, reserved_4, "reserved_4", "Reserved") \ 35410b08045SHans Petter Selasky m(n, p, +1, u64, reserved_5, "reserved_5", "Reserved") \ 35510b08045SHans Petter Selasky m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 35610b08045SHans Petter Selasky m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 35710b08045SHans Petter Selasky m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 35810b08045SHans Petter Selasky "Received pause duration") \ 35910b08045SHans Petter Selasky m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 36010b08045SHans Petter Selasky m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 36110b08045SHans Petter Selasky "Transmitted pause duration") \ 36210b08045SHans Petter Selasky m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 36310b08045SHans Petter Selasky "Received pause transitions") \ 36410b08045SHans Petter Selasky m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 36510b08045SHans Petter Selasky m(n, p, +1, u64, device_stall_minor_watermark, \ 36610b08045SHans Petter Selasky "device_stall_minor_watermark", "Device stall minor watermark") \ 36710b08045SHans Petter Selasky m(n, p, +1, u64, device_stall_critical_watermark, \ 36810b08045SHans Petter Selasky "device_stall_critical_watermark", "Device stall critical watermark") 36910b08045SHans Petter Selasky 37010b08045SHans Petter Selasky #define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 37167fd1941SHans Petter Selasky m(c, t, pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 37210b08045SHans Petter Selasky 37310b08045SHans Petter Selasky #define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 37410b08045SHans Petter Selasky 37510b08045SHans Petter Selasky #define MLX5E_PPORT_PER_PRIO_STATS(m) \ 37610b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 37710b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 37810b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 37910b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 38010b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 38110b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 38210b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 38310b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 384dc7e38acSHans Petter Selasky 3855f9484f3SHans Petter Selasky #define MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 3865f9484f3SHans Petter Selasky m(+1, u64, life_time_counter_high, "life_time_counter", \ 3875f9484f3SHans Petter Selasky "Life time counter.", pcie_perf_counters) \ 3885f9484f3SHans Petter Selasky m(+1, u64, tx_overflow_buffer_pkt, "tx_overflow_buffer_pkt", \ 3895f9484f3SHans Petter Selasky "The number of packets dropped due to lack of PCIe buffers " \ 3905f9484f3SHans Petter Selasky "in receive path from NIC port toward the hosts.", \ 3915f9484f3SHans Petter Selasky pcie_perf_counters) \ 3925f9484f3SHans Petter Selasky m(+1, u64, tx_overflow_buffer_marked_pkt, \ 3935f9484f3SHans Petter Selasky "tx_overflow_buffer_marked_pkt", \ 3945f9484f3SHans Petter Selasky "The number of packets marked due to lack of PCIe buffers " \ 3955f9484f3SHans Petter Selasky "in receive path from NIC port toward the hosts.", \ 3965f9484f3SHans Petter Selasky pcie_perf_counters) 3975f9484f3SHans Petter Selasky 3985f9484f3SHans Petter Selasky #define MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 3995f9484f3SHans Petter Selasky m(+1, u64, rx_errors, "rx_errors", \ 4005f9484f3SHans Petter Selasky "Number of transitions to recovery due to Framing " \ 4015f9484f3SHans Petter Selasky "errors and CRC errors.", pcie_perf_counters) \ 4025f9484f3SHans Petter Selasky m(+1, u64, tx_errors, "tx_errors", "Number of transitions " \ 4035f9484f3SHans Petter Selasky "to recovery due to EIEOS and TS errors.", pcie_perf_counters) \ 4045f9484f3SHans Petter Selasky m(+1, u64, l0_to_recovery_eieos, "l0_to_recovery_eieos", "Number of " \ 4055f9484f3SHans Petter Selasky "transitions to recovery due to getting EIEOS.", pcie_perf_counters)\ 4065f9484f3SHans Petter Selasky m(+1, u64, l0_to_recovery_ts, "l0_to_recovery_ts", "Number of " \ 4075f9484f3SHans Petter Selasky "transitions to recovery due to getting TS.", pcie_perf_counters) \ 4085f9484f3SHans Petter Selasky m(+1, u64, l0_to_recovery_framing, "l0_to_recovery_framing", "Number "\ 4095f9484f3SHans Petter Selasky "of transitions to recovery due to identifying framing " \ 4105f9484f3SHans Petter Selasky "errors at gen3/4.", pcie_perf_counters) \ 4115f9484f3SHans Petter Selasky m(+1, u64, l0_to_recovery_retrain, "l0_to_recovery_retrain", \ 4125f9484f3SHans Petter Selasky "Number of transitions to recovery due to link retrain request " \ 4135f9484f3SHans Petter Selasky "from data link.", pcie_perf_counters) \ 4145f9484f3SHans Petter Selasky m(+1, u64, crc_error_dllp, "crc_error_dllp", "Number of transitions " \ 4155f9484f3SHans Petter Selasky "to recovery due to identifying CRC DLLP errors.", \ 4165f9484f3SHans Petter Selasky pcie_perf_counters) \ 4175f9484f3SHans Petter Selasky m(+1, u64, crc_error_tlp, "crc_error_tlp", "Number of transitions to "\ 4185f9484f3SHans Petter Selasky "recovery due to identifying CRC TLP errors.", pcie_perf_counters) \ 4195f9484f3SHans Petter Selasky m(+1, u64, outbound_stalled_reads, "outbound_stalled_reads", \ 4205f9484f3SHans Petter Selasky "The percentage of time within the last second that the NIC had " \ 4215f9484f3SHans Petter Selasky "outbound non-posted read requests but could not perform the " \ 4225f9484f3SHans Petter Selasky "operation due to insufficient non-posted credits.", \ 4235f9484f3SHans Petter Selasky pcie_perf_counters) \ 4245f9484f3SHans Petter Selasky m(+1, u64, outbound_stalled_writes, "outbound_stalled_writes", \ 4255f9484f3SHans Petter Selasky "The percentage of time within the last second that the NIC had " \ 4265f9484f3SHans Petter Selasky "outbound posted writes requests but could not perform the " \ 4275f9484f3SHans Petter Selasky "operation due to insufficient posted credits.", \ 4285f9484f3SHans Petter Selasky pcie_perf_counters) \ 4295f9484f3SHans Petter Selasky m(+1, u64, outbound_stalled_reads_events, \ 4305f9484f3SHans Petter Selasky "outbound_stalled_reads_events", "The number of events where " \ 4315f9484f3SHans Petter Selasky "outbound_stalled_reads was above a threshold.", \ 4325f9484f3SHans Petter Selasky pcie_perf_counters) \ 4335f9484f3SHans Petter Selasky m(+1, u64, outbound_stalled_writes_events, \ 4345f9484f3SHans Petter Selasky "outbound_stalled_writes_events", \ 4355f9484f3SHans Petter Selasky "The number of events where outbound_stalled_writes was above " \ 4365f9484f3SHans Petter Selasky "a threshold.", pcie_perf_counters) 4375f9484f3SHans Petter Selasky 4385f9484f3SHans Petter Selasky #define MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 4395f9484f3SHans Petter Selasky m(+1, u64, time_to_boot_image_start, "time_to_boot_image_start", \ 4405f9484f3SHans Petter Selasky "Time from start until FW boot image starts running in usec.", \ 4415f9484f3SHans Petter Selasky pcie_timers_states) \ 4425f9484f3SHans Petter Selasky m(+1, u64, time_to_link_image, "time_to_link_image", \ 4435f9484f3SHans Petter Selasky "Time from start until FW pci_link image starts running in usec.", \ 4445f9484f3SHans Petter Selasky pcie_timers_states) \ 4455f9484f3SHans Petter Selasky m(+1, u64, calibration_time, "calibration_time", \ 4465f9484f3SHans Petter Selasky "Time it took FW to do calibration in usec.", \ 4475f9484f3SHans Petter Selasky pcie_timers_states) \ 4485f9484f3SHans Petter Selasky m(+1, u64, time_to_first_perst, "time_to_first_perst", \ 4495f9484f3SHans Petter Selasky "Time form start until FW handle first perst. in usec.", \ 4505f9484f3SHans Petter Selasky pcie_timers_states) \ 4515f9484f3SHans Petter Selasky m(+1, u64, time_to_detect_state, "time_to_detect_state", \ 4525f9484f3SHans Petter Selasky "Time from start until first transition to LTSSM.Detect_Q in usec", \ 4535f9484f3SHans Petter Selasky pcie_timers_states) \ 4545f9484f3SHans Petter Selasky m(+1, u64, time_to_l0, "time_to_l0", \ 4555f9484f3SHans Petter Selasky "Time from start until first transition to LTSSM.L0 in usec", \ 4565f9484f3SHans Petter Selasky pcie_timers_states) \ 4575f9484f3SHans Petter Selasky m(+1, u64, time_to_crs_en, "time_to_crs_en", \ 4585f9484f3SHans Petter Selasky "Time from start until crs is enabled in usec", \ 4595f9484f3SHans Petter Selasky pcie_timers_states) \ 4605f9484f3SHans Petter Selasky m(+1, u64, time_to_plastic_image_start, "time_to_plastic_image_start",\ 4615f9484f3SHans Petter Selasky "Time form start until FW plastic image starts running in usec.", \ 4625f9484f3SHans Petter Selasky pcie_timers_states) \ 4635f9484f3SHans Petter Selasky m(+1, u64, time_to_iron_image_start, "time_to_iron_image_start", \ 4645f9484f3SHans Petter Selasky "Time form start until FW iron image starts running in usec.", \ 4655f9484f3SHans Petter Selasky pcie_timers_states) \ 4665f9484f3SHans Petter Selasky m(+1, u64, perst_handler, "perst_handler", \ 4675f9484f3SHans Petter Selasky "Number of persts arrived.", pcie_timers_states) \ 4685f9484f3SHans Petter Selasky m(+1, u64, times_in_l1, "times_in_l1", \ 4695f9484f3SHans Petter Selasky "Number of times LTSSM entered L1 flow.", pcie_timers_states) \ 4705f9484f3SHans Petter Selasky m(+1, u64, times_in_l23, "times_in_l23", \ 4715f9484f3SHans Petter Selasky "Number of times LTSSM entered L23 flow.", pcie_timers_states) \ 4725f9484f3SHans Petter Selasky m(+1, u64, dl_down, "dl_down", \ 4735f9484f3SHans Petter Selasky "Number of moves for DL_active to DL_down.", pcie_timers_states) \ 4745f9484f3SHans Petter Selasky m(+1, u64, config_cycle1usec, "config_cycle1usec", \ 4755f9484f3SHans Petter Selasky "Number of configuration requests that firmware " \ 4765f9484f3SHans Petter Selasky "handled in less than 1 usec.", pcie_timers_states) \ 4775f9484f3SHans Petter Selasky m(+1, u64, config_cycle2to7usec, "config_cycle2to7usec", \ 4785f9484f3SHans Petter Selasky "Number of configuration requests that firmware " \ 4795f9484f3SHans Petter Selasky "handled within 2 to 7 usec.", pcie_timers_states) \ 4805f9484f3SHans Petter Selasky m(+1, u64, config_cycle8to15usec, "config_cycle8to15usec", \ 4815f9484f3SHans Petter Selasky "Number of configuration requests that firmware " \ 4825f9484f3SHans Petter Selasky "handled within 8 to 15 usec.", pcie_timers_states) \ 4835f9484f3SHans Petter Selasky m(+1, u64, config_cycle16to63usec, "config_cycle16to63usec", \ 4845f9484f3SHans Petter Selasky "Number of configuration requests that firmware " \ 4855f9484f3SHans Petter Selasky "handled within 16 to 63 usec.", pcie_timers_states) \ 4865f9484f3SHans Petter Selasky m(+1, u64, config_cycle64usec, "config_cycle64usec", \ 4875f9484f3SHans Petter Selasky "Number of configuration requests that firmware " \ 4885f9484f3SHans Petter Selasky "handled took more than 64 usec.", pcie_timers_states) \ 4895f9484f3SHans Petter Selasky m(+1, u64, correctable_err_msg_sent, "correctable_err_msg_sent", \ 4905f9484f3SHans Petter Selasky "Number of correctable error messages sent.", pcie_timers_states) \ 4915f9484f3SHans Petter Selasky m(+1, u64, non_fatal_err_msg_sent, "non_fatal_err_msg_sent", \ 4925f9484f3SHans Petter Selasky "Number of non-Fatal error msg sent.", pcie_timers_states) \ 4935f9484f3SHans Petter Selasky m(+1, u64, fatal_err_msg_sent, "fatal_err_msg_sent", \ 4945f9484f3SHans Petter Selasky "Number of fatal error msg sent.", pcie_timers_states) 4955f9484f3SHans Petter Selasky 4965f9484f3SHans Petter Selasky #define MLX5E_PCIE_LANE_COUNTERS_32(m) \ 4975f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane0, "error_counter_lane0", \ 4985f9484f3SHans Petter Selasky "Error counter for PCI lane 0", pcie_lanes_counters) \ 4995f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane1, "error_counter_lane1", \ 5005f9484f3SHans Petter Selasky "Error counter for PCI lane 1", pcie_lanes_counters) \ 5015f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane2, "error_counter_lane2", \ 5025f9484f3SHans Petter Selasky "Error counter for PCI lane 2", pcie_lanes_counters) \ 5035f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane3, "error_counter_lane3", \ 5045f9484f3SHans Petter Selasky "Error counter for PCI lane 3", pcie_lanes_counters) \ 5055f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane4, "error_counter_lane4", \ 5065f9484f3SHans Petter Selasky "Error counter for PCI lane 4", pcie_lanes_counters) \ 5075f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane5, "error_counter_lane5", \ 5085f9484f3SHans Petter Selasky "Error counter for PCI lane 5", pcie_lanes_counters) \ 5095f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane6, "error_counter_lane6", \ 5105f9484f3SHans Petter Selasky "Error counter for PCI lane 6", pcie_lanes_counters) \ 5115f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane7, "error_counter_lane7", \ 5125f9484f3SHans Petter Selasky "Error counter for PCI lane 7", pcie_lanes_counters) \ 5135f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane8, "error_counter_lane8", \ 5145f9484f3SHans Petter Selasky "Error counter for PCI lane 8", pcie_lanes_counters) \ 5155f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane9, "error_counter_lane9", \ 5165f9484f3SHans Petter Selasky "Error counter for PCI lane 9", pcie_lanes_counters) \ 5175f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane10, "error_counter_lane10", \ 5185f9484f3SHans Petter Selasky "Error counter for PCI lane 10", pcie_lanes_counters) \ 5195f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane11, "error_counter_lane11", \ 5205f9484f3SHans Petter Selasky "Error counter for PCI lane 11", pcie_lanes_counters) \ 5215f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane12, "error_counter_lane12", \ 5225f9484f3SHans Petter Selasky "Error counter for PCI lane 12", pcie_lanes_counters) \ 5235f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane13, "error_counter_lane13", \ 5245f9484f3SHans Petter Selasky "Error counter for PCI lane 13", pcie_lanes_counters) \ 5255f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane14, "error_counter_lane14", \ 5265f9484f3SHans Petter Selasky "Error counter for PCI lane 14", pcie_lanes_counters) \ 5275f9484f3SHans Petter Selasky m(+1, u64, error_counter_lane15, "error_counter_lane15", \ 5285f9484f3SHans Petter Selasky "Error counter for PCI lane 15", pcie_lanes_counters) 5295f9484f3SHans Petter Selasky 530dc7e38acSHans Petter Selasky /* 531dc7e38acSHans Petter Selasky * Make sure to update mlx5e_update_pport_counters() 532dc7e38acSHans Petter Selasky * when adding a new MLX5E_PPORT_STATS block 533dc7e38acSHans Petter Selasky */ 534dc7e38acSHans Petter Selasky #define MLX5E_PPORT_STATS(m) \ 53510b08045SHans Petter Selasky MLX5E_PPORT_PER_PRIO_STATS(m) \ 536dc7e38acSHans Petter Selasky MLX5E_PPORT_IEEE802_3_STATS(m) \ 537ee090799SHans Petter Selasky MLX5E_PPORT_RFC2819_STATS(m) 538dc7e38acSHans Petter Selasky 539dc7e38acSHans Petter Selasky #define MLX5E_PORT_STATS_DEBUG(m) \ 540dc7e38acSHans Petter Selasky MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 541dc7e38acSHans Petter Selasky MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 542bcfad025SHans Petter Selasky MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 5435f9484f3SHans Petter Selasky MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 544c62f4d8dSHans Petter Selasky MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 5455f9484f3SHans Petter Selasky MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 5465f9484f3SHans Petter Selasky MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 5475f9484f3SHans Petter Selasky MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 5485f9484f3SHans Petter Selasky MLX5E_PCIE_LANE_COUNTERS_32(m) 549dc7e38acSHans Petter Selasky 550dc7e38acSHans Petter Selasky #define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 551dc7e38acSHans Petter Selasky (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 552dc7e38acSHans Petter Selasky #define MLX5E_PPORT_RFC2819_STATS_NUM \ 553dc7e38acSHans Petter Selasky (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 554dc7e38acSHans Petter Selasky #define MLX5E_PPORT_STATS_NUM \ 555dc7e38acSHans Petter Selasky (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 556dc7e38acSHans Petter Selasky 55710b08045SHans Petter Selasky #define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 55810b08045SHans Petter Selasky (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 559dc7e38acSHans Petter Selasky #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 560dc7e38acSHans Petter Selasky (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 561dc7e38acSHans Petter Selasky #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 562dc7e38acSHans Petter Selasky (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 563dc7e38acSHans Petter Selasky #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 564dc7e38acSHans Petter Selasky (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 565bcfad025SHans Petter Selasky #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \ 566bcfad025SHans Petter Selasky (0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT)) 567c62f4d8dSHans Petter Selasky #define MLX5E_PPORT_STATISTICAL_DEBUG_NUM \ 568c62f4d8dSHans Petter Selasky (0 MLX5E_PPORT_STATISTICAL_DEBUG(MLX5E_STATS_COUNT)) 569dc7e38acSHans Petter Selasky #define MLX5E_PORT_STATS_DEBUG_NUM \ 570dc7e38acSHans Petter Selasky (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 571dc7e38acSHans Petter Selasky 572dc7e38acSHans Petter Selasky struct mlx5e_pport_stats { 573dc7e38acSHans Petter Selasky struct sysctl_ctx_list ctx; 574dc7e38acSHans Petter Selasky u64 arg [0]; 575dc7e38acSHans Petter Selasky MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 576dc7e38acSHans Petter Selasky }; 577dc7e38acSHans Petter Selasky 578dc7e38acSHans Petter Selasky struct mlx5e_port_stats_debug { 579dc7e38acSHans Petter Selasky struct sysctl_ctx_list ctx; 580dc7e38acSHans Petter Selasky u64 arg [0]; 581dc7e38acSHans Petter Selasky MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 582dc7e38acSHans Petter Selasky }; 583dc7e38acSHans Petter Selasky 584dc7e38acSHans Petter Selasky #define MLX5E_RQ_STATS(m) \ 58567fd1941SHans Petter Selasky m(+1, u64, packets, "packets", "Received packets") \ 58667fd1941SHans Petter Selasky m(+1, u64, bytes, "bytes", "Received bytes") \ 58767fd1941SHans Petter Selasky m(+1, u64, csum_none, "csum_none", "Received packets") \ 58867fd1941SHans Petter Selasky m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 58967fd1941SHans Petter Selasky m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 59067fd1941SHans Petter Selasky m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 59167fd1941SHans Petter Selasky m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 59267fd1941SHans Petter Selasky m(+1, u64, wqe_err, "wqe_err", "Received packets") 593dc7e38acSHans Petter Selasky 594dc7e38acSHans Petter Selasky #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 595dc7e38acSHans Petter Selasky 596dc7e38acSHans Petter Selasky struct mlx5e_rq_stats { 597dc7e38acSHans Petter Selasky struct sysctl_ctx_list ctx; 598dc7e38acSHans Petter Selasky u64 arg [0]; 599dc7e38acSHans Petter Selasky MLX5E_RQ_STATS(MLX5E_STATS_VAR) 600dc7e38acSHans Petter Selasky }; 601dc7e38acSHans Petter Selasky 602dc7e38acSHans Petter Selasky #define MLX5E_SQ_STATS(m) \ 60367fd1941SHans Petter Selasky m(+1, u64, packets, "packets", "Transmitted packets") \ 60467fd1941SHans Petter Selasky m(+1, u64, bytes, "bytes", "Transmitted bytes") \ 60567fd1941SHans Petter Selasky m(+1, u64, tso_packets, "tso_packets", "Transmitted packets") \ 60667fd1941SHans Petter Selasky m(+1, u64, tso_bytes, "tso_bytes", "Transmitted bytes") \ 60767fd1941SHans Petter Selasky m(+1, u64, csum_offload_none, "csum_offload_none", "Transmitted packets") \ 60867fd1941SHans Petter Selasky m(+1, u64, defragged, "defragged", "Transmitted packets") \ 60967fd1941SHans Petter Selasky m(+1, u64, dropped, "dropped", "Transmitted packets") \ 61067fd1941SHans Petter Selasky m(+1, u64, nop, "nop", "Transmitted packets") 611dc7e38acSHans Petter Selasky 612dc7e38acSHans Petter Selasky #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 613dc7e38acSHans Petter Selasky 614dc7e38acSHans Petter Selasky struct mlx5e_sq_stats { 615dc7e38acSHans Petter Selasky struct sysctl_ctx_list ctx; 616dc7e38acSHans Petter Selasky u64 arg [0]; 617dc7e38acSHans Petter Selasky MLX5E_SQ_STATS(MLX5E_STATS_VAR) 618dc7e38acSHans Petter Selasky }; 619dc7e38acSHans Petter Selasky 620dc7e38acSHans Petter Selasky struct mlx5e_stats { 621dc7e38acSHans Petter Selasky struct mlx5e_vport_stats vport; 622dc7e38acSHans Petter Selasky struct mlx5e_pport_stats pport; 623dc7e38acSHans Petter Selasky struct mlx5e_port_stats_debug port_stats_debug; 624dc7e38acSHans Petter Selasky }; 625dc7e38acSHans Petter Selasky 62628f22cceSHans Petter Selasky struct mlx5e_rq_param { 62728f22cceSHans Petter Selasky u32 rqc [MLX5_ST_SZ_DW(rqc)]; 62828f22cceSHans Petter Selasky struct mlx5_wq_param wq; 62928f22cceSHans Petter Selasky }; 63028f22cceSHans Petter Selasky 63128f22cceSHans Petter Selasky struct mlx5e_sq_param { 63228f22cceSHans Petter Selasky u32 sqc [MLX5_ST_SZ_DW(sqc)]; 63328f22cceSHans Petter Selasky struct mlx5_wq_param wq; 63428f22cceSHans Petter Selasky }; 63528f22cceSHans Petter Selasky 63628f22cceSHans Petter Selasky struct mlx5e_cq_param { 63728f22cceSHans Petter Selasky u32 cqc [MLX5_ST_SZ_DW(cqc)]; 63828f22cceSHans Petter Selasky struct mlx5_wq_param wq; 63928f22cceSHans Petter Selasky }; 64028f22cceSHans Petter Selasky 641dc7e38acSHans Petter Selasky struct mlx5e_params { 642dc7e38acSHans Petter Selasky u8 log_sq_size; 643dc7e38acSHans Petter Selasky u8 log_rq_size; 644dc7e38acSHans Petter Selasky u16 num_channels; 645dc7e38acSHans Petter Selasky u8 default_vlan_prio; 646dc7e38acSHans Petter Selasky u8 num_tc; 647dc7e38acSHans Petter Selasky u8 rx_cq_moderation_mode; 64874540a31SHans Petter Selasky u8 tx_cq_moderation_mode; 649dc7e38acSHans Petter Selasky u16 rx_cq_moderation_usec; 650dc7e38acSHans Petter Selasky u16 rx_cq_moderation_pkts; 651dc7e38acSHans Petter Selasky u16 tx_cq_moderation_usec; 652dc7e38acSHans Petter Selasky u16 tx_cq_moderation_pkts; 653dc7e38acSHans Petter Selasky u16 min_rx_wqes; 654dc7e38acSHans Petter Selasky bool hw_lro_en; 65590cc1c77SHans Petter Selasky bool cqe_zipping_en; 656dc7e38acSHans Petter Selasky u32 lro_wqe_sz; 657dc7e38acSHans Petter Selasky u16 rx_hash_log_tbl_sz; 65810b08045SHans Petter Selasky u32 tx_pauseframe_control __aligned(4); 65910b08045SHans Petter Selasky u32 rx_pauseframe_control __aligned(4); 66005399002SHans Petter Selasky u16 tx_max_inline; 66105399002SHans Petter Selasky u8 tx_min_inline_mode; 66224385321SHans Petter Selasky u8 tx_priority_flow_control; 66324385321SHans Petter Selasky u8 rx_priority_flow_control; 66416ae32f9SHans Petter Selasky u8 channels_rsss; 665dc7e38acSHans Petter Selasky }; 666dc7e38acSHans Petter Selasky 667dc7e38acSHans Petter Selasky #define MLX5E_PARAMS(m) \ 66867fd1941SHans Petter Selasky m(+1, u64, tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 66967fd1941SHans Petter Selasky m(+1, u64, rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 67067fd1941SHans Petter Selasky m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \ 67167fd1941SHans Petter Selasky m(+1, u64, rx_queue_size, "rx_queue_size", "Default receive queue size") \ 67267fd1941SHans Petter Selasky m(+1, u64, channels, "channels", "Default number of channels") \ 67367fd1941SHans Petter Selasky m(+1, u64, channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \ 67467fd1941SHans Petter Selasky m(+1, u64, coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 67567fd1941SHans Petter Selasky m(+1, u64, coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 67667fd1941SHans Petter Selasky m(+1, u64, rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 67767fd1941SHans Petter Selasky m(+1, u64, rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 67867fd1941SHans Petter Selasky m(+1, u64, rx_coalesce_mode, "rx_coalesce_mode", "0: EQE fixed mode 1: CQE fixed mode 2: EQE auto mode 3: CQE auto mode") \ 67967fd1941SHans Petter Selasky m(+1, u64, tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 68067fd1941SHans Petter Selasky m(+1, u64, tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 68167fd1941SHans Petter Selasky m(+1, u64, tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 68267fd1941SHans Petter Selasky m(+1, u64, tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 68367fd1941SHans Petter Selasky m(+1, u64, tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 68467fd1941SHans Petter Selasky m(+1, u64, hw_lro, "hw_lro", "set to enable hw_lro") \ 68567fd1941SHans Petter Selasky m(+1, u64, cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 68667fd1941SHans Petter Selasky m(+1, u64, modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 68767fd1941SHans Petter Selasky m(+1, u64, modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 68867fd1941SHans Petter Selasky m(+1, u64, diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 68967fd1941SHans Petter Selasky m(+1, u64, diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 69067fd1941SHans Petter Selasky m(+1, u64, hw_mtu, "hw_mtu", "Current hardware MTU value") \ 69167fd1941SHans Petter Selasky m(+1, u64, mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 69267fd1941SHans Petter Selasky m(+1, u64, uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") 693cfc9c386SHans Petter Selasky 694dc7e38acSHans Petter Selasky #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 695dc7e38acSHans Petter Selasky 696dc7e38acSHans Petter Selasky struct mlx5e_params_ethtool { 697dc7e38acSHans Petter Selasky u64 arg [0]; 698dc7e38acSHans Petter Selasky MLX5E_PARAMS(MLX5E_STATS_VAR) 699cfc9c386SHans Petter Selasky u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 700e870c0abSSlava Shwartsman u8 max_bw_share[IEEE_8021QAZ_MAX_TCS]; 70124385321SHans Petter Selasky u8 prio_tc[MLX5E_MAX_PRIORITY]; 702ed0cee0bSHans Petter Selasky u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP]; 703ed0cee0bSHans Petter Selasky u8 trust_state; 704dc7e38acSHans Petter Selasky }; 705dc7e38acSHans Petter Selasky 706dc7e38acSHans Petter Selasky /* EEPROM Standards for plug in modules */ 707dc7e38acSHans Petter Selasky #ifndef MLX5E_ETH_MODULE_SFF_8472 708dc7e38acSHans Petter Selasky #define MLX5E_ETH_MODULE_SFF_8472 0x1 709dc7e38acSHans Petter Selasky #define MLX5E_ETH_MODULE_SFF_8472_LEN 128 710dc7e38acSHans Petter Selasky #endif 711dc7e38acSHans Petter Selasky 712dc7e38acSHans Petter Selasky #ifndef MLX5E_ETH_MODULE_SFF_8636 713dc7e38acSHans Petter Selasky #define MLX5E_ETH_MODULE_SFF_8636 0x2 714dc7e38acSHans Petter Selasky #define MLX5E_ETH_MODULE_SFF_8636_LEN 256 715dc7e38acSHans Petter Selasky #endif 716dc7e38acSHans Petter Selasky 717dc7e38acSHans Petter Selasky #ifndef MLX5E_ETH_MODULE_SFF_8436 718dc7e38acSHans Petter Selasky #define MLX5E_ETH_MODULE_SFF_8436 0x3 719dc7e38acSHans Petter Selasky #define MLX5E_ETH_MODULE_SFF_8436_LEN 256 720dc7e38acSHans Petter Selasky #endif 721dc7e38acSHans Petter Selasky 722dc7e38acSHans Petter Selasky /* EEPROM I2C Addresses */ 723dc7e38acSHans Petter Selasky #define MLX5E_I2C_ADDR_LOW 0x50 724dc7e38acSHans Petter Selasky #define MLX5E_I2C_ADDR_HIGH 0x51 725dc7e38acSHans Petter Selasky 726dc7e38acSHans Petter Selasky #define MLX5E_EEPROM_LOW_PAGE 0x0 727dc7e38acSHans Petter Selasky #define MLX5E_EEPROM_HIGH_PAGE 0x3 728dc7e38acSHans Petter Selasky 729dc7e38acSHans Petter Selasky #define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128 730dc7e38acSHans Petter Selasky #define MLX5E_EEPROM_PAGE_LENGTH 256 731dc7e38acSHans Petter Selasky 732dc7e38acSHans Petter Selasky #define MLX5E_EEPROM_INFO_BYTES 0x3 733dc7e38acSHans Petter Selasky 734dc7e38acSHans Petter Selasky struct mlx5e_cq { 735dc7e38acSHans Petter Selasky /* data path - accessed per cqe */ 736dc7e38acSHans Petter Selasky struct mlx5_cqwq wq; 737dc7e38acSHans Petter Selasky 738dc7e38acSHans Petter Selasky /* data path - accessed per HW polling */ 739dc7e38acSHans Petter Selasky struct mlx5_core_cq mcq; 740dc7e38acSHans Petter Selasky 741dc7e38acSHans Petter Selasky /* control */ 74298626886SHans Petter Selasky struct mlx5e_priv *priv; 743dc7e38acSHans Petter Selasky struct mlx5_wq_ctrl wq_ctrl; 744dc7e38acSHans Petter Selasky } __aligned(MLX5E_CACHELINE_SIZE); 745dc7e38acSHans Petter Selasky 746dc7e38acSHans Petter Selasky struct mlx5e_rq_mbuf { 747dc7e38acSHans Petter Selasky bus_dmamap_t dma_map; 748dc7e38acSHans Petter Selasky caddr_t data; 749dc7e38acSHans Petter Selasky struct mbuf *mbuf; 750dc7e38acSHans Petter Selasky }; 751dc7e38acSHans Petter Selasky 752dc7e38acSHans Petter Selasky struct mlx5e_rq { 753dc7e38acSHans Petter Selasky /* data path */ 754dc7e38acSHans Petter Selasky struct mlx5_wq_ll wq; 755dc7e38acSHans Petter Selasky struct mtx mtx; 756dc7e38acSHans Petter Selasky bus_dma_tag_t dma_tag; 757dc7e38acSHans Petter Selasky u32 wqe_sz; 7582f17f76aSHans Petter Selasky u32 nsegs; 759dc7e38acSHans Petter Selasky struct mlx5e_rq_mbuf *mbuf; 760dc7e38acSHans Petter Selasky struct ifnet *ifp; 761dc7e38acSHans Petter Selasky struct mlx5e_rq_stats stats; 762dc7e38acSHans Petter Selasky struct mlx5e_cq cq; 763dc7e38acSHans Petter Selasky struct lro_ctrl lro; 764dc7e38acSHans Petter Selasky volatile int enabled; 765dc7e38acSHans Petter Selasky int ix; 766dc7e38acSHans Petter Selasky 767423530beSHans Petter Selasky /* Dynamic Interrupt Moderation */ 768423530beSHans Petter Selasky struct net_dim dim; 769423530beSHans Petter Selasky 770dc7e38acSHans Petter Selasky /* control */ 771dc7e38acSHans Petter Selasky struct mlx5_wq_ctrl wq_ctrl; 772dc7e38acSHans Petter Selasky u32 rqn; 773dc7e38acSHans Petter Selasky struct mlx5e_channel *channel; 7746f4cab6cSHans Petter Selasky struct callout watchdog; 775dc7e38acSHans Petter Selasky } __aligned(MLX5E_CACHELINE_SIZE); 776dc7e38acSHans Petter Selasky 777dc7e38acSHans Petter Selasky struct mlx5e_sq_mbuf { 778dc7e38acSHans Petter Selasky bus_dmamap_t dma_map; 779dc7e38acSHans Petter Selasky struct mbuf *mbuf; 780dc7e38acSHans Petter Selasky u32 num_bytes; 781dc7e38acSHans Petter Selasky u32 num_wqebbs; 782dc7e38acSHans Petter Selasky }; 783dc7e38acSHans Petter Selasky 784dc7e38acSHans Petter Selasky enum { 785dc7e38acSHans Petter Selasky MLX5E_SQ_READY, 786dc7e38acSHans Petter Selasky MLX5E_SQ_FULL 787dc7e38acSHans Petter Selasky }; 788dc7e38acSHans Petter Selasky 789cc971b22SSlava Shwartsman struct mlx5e_snd_tag { 790cc971b22SSlava Shwartsman struct m_snd_tag m_snd_tag; /* send tag */ 791cc971b22SSlava Shwartsman u32 type; /* tag type */ 792cc971b22SSlava Shwartsman }; 793cc971b22SSlava Shwartsman 794dc7e38acSHans Petter Selasky struct mlx5e_sq { 795dc7e38acSHans Petter Selasky /* data path */ 796dc7e38acSHans Petter Selasky struct mtx lock; 797dc7e38acSHans Petter Selasky bus_dma_tag_t dma_tag; 798dc7e38acSHans Petter Selasky struct mtx comp_lock; 799dc7e38acSHans Petter Selasky 800dc7e38acSHans Petter Selasky /* dirtied @completion */ 801dc7e38acSHans Petter Selasky u16 cc; 802dc7e38acSHans Petter Selasky 803dc7e38acSHans Petter Selasky /* dirtied @xmit */ 804dc7e38acSHans Petter Selasky u16 pc __aligned(MLX5E_CACHELINE_SIZE); 805dc7e38acSHans Petter Selasky u16 bf_offset; 806376bcf63SHans Petter Selasky u16 cev_counter; /* completion event counter */ 807376bcf63SHans Petter Selasky u16 cev_factor; /* completion event factor */ 8083dfa7645SHans Petter Selasky u16 cev_next_state; /* next completion event state */ 809376bcf63SHans Petter Selasky #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 810376bcf63SHans Petter Selasky #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 811376bcf63SHans Petter Selasky #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 8123230c29dSSlava Shwartsman u16 running; /* set if SQ is running */ 813376bcf63SHans Petter Selasky struct callout cev_callout; 814af89c4afSHans Petter Selasky union { 815af89c4afSHans Petter Selasky u32 d32[2]; 816af89c4afSHans Petter Selasky u64 d64; 817af89c4afSHans Petter Selasky } doorbell; 818dc7e38acSHans Petter Selasky struct mlx5e_sq_stats stats; 819dc7e38acSHans Petter Selasky 820dc7e38acSHans Petter Selasky struct mlx5e_cq cq; 821dc7e38acSHans Petter Selasky 822dc7e38acSHans Petter Selasky /* pointers to per packet info: write@xmit, read@completion */ 823dc7e38acSHans Petter Selasky struct mlx5e_sq_mbuf *mbuf; 824dc7e38acSHans Petter Selasky struct buf_ring *br; 825dc7e38acSHans Petter Selasky 826dc7e38acSHans Petter Selasky /* read only */ 827dc7e38acSHans Petter Selasky struct mlx5_wq_cyc wq; 8285eadc44cSHans Petter Selasky struct mlx5_uar uar; 82998626886SHans Petter Selasky struct ifnet *ifp; 830dc7e38acSHans Petter Selasky u32 sqn; 831dc7e38acSHans Petter Selasky u32 bf_buf_size; 832dc7e38acSHans Petter Selasky u32 mkey_be; 83305399002SHans Petter Selasky u16 max_inline; 83405399002SHans Petter Selasky u8 min_inline_mode; 8353e581cabSSlava Shwartsman u8 min_insert_caps; 8363e581cabSSlava Shwartsman #define MLX5E_INSERT_VLAN 1 8373e581cabSSlava Shwartsman #define MLX5E_INSERT_NON_VLAN 2 838dc7e38acSHans Petter Selasky 839dc7e38acSHans Petter Selasky /* control path */ 840dc7e38acSHans Petter Selasky struct mlx5_wq_ctrl wq_ctrl; 84198626886SHans Petter Selasky struct mlx5e_priv *priv; 842dc7e38acSHans Petter Selasky int tc; 843dc7e38acSHans Petter Selasky } __aligned(MLX5E_CACHELINE_SIZE); 844dc7e38acSHans Petter Selasky 845dc7e38acSHans Petter Selasky static inline bool 846dc7e38acSHans Petter Selasky mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 847dc7e38acSHans Petter Selasky { 8485e6a76beSHans Petter Selasky u16 cc = sq->cc; 8495e6a76beSHans Petter Selasky u16 pc = sq->pc; 8505e6a76beSHans Petter Selasky 8515e6a76beSHans Petter Selasky return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 852dc7e38acSHans Petter Selasky } 853dc7e38acSHans Petter Selasky 854cc971b22SSlava Shwartsman static inline u32 855cc971b22SSlava Shwartsman mlx5e_sq_queue_level(struct mlx5e_sq *sq) 856cc971b22SSlava Shwartsman { 857cc971b22SSlava Shwartsman u16 cc; 858cc971b22SSlava Shwartsman u16 pc; 859cc971b22SSlava Shwartsman 860cc971b22SSlava Shwartsman if (sq == NULL) 861cc971b22SSlava Shwartsman return (0); 862cc971b22SSlava Shwartsman 863cc971b22SSlava Shwartsman cc = sq->cc; 864cc971b22SSlava Shwartsman pc = sq->pc; 865cc971b22SSlava Shwartsman 866cc971b22SSlava Shwartsman return (((sq->wq.sz_m1 & (pc - cc)) * 867cc971b22SSlava Shwartsman IF_SND_QUEUE_LEVEL_MAX) / sq->wq.sz_m1); 868cc971b22SSlava Shwartsman } 869cc971b22SSlava Shwartsman 870dc7e38acSHans Petter Selasky struct mlx5e_channel { 871dc7e38acSHans Petter Selasky /* data path */ 872dc7e38acSHans Petter Selasky struct mlx5e_rq rq; 873cc971b22SSlava Shwartsman struct mlx5e_snd_tag tag; 874dc7e38acSHans Petter Selasky struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 875dc7e38acSHans Petter Selasky u32 mkey_be; 876dc7e38acSHans Petter Selasky u8 num_tc; 877dc7e38acSHans Petter Selasky 878dc7e38acSHans Petter Selasky /* control */ 879dc7e38acSHans Petter Selasky struct mlx5e_priv *priv; 880dc7e38acSHans Petter Selasky int ix; 881dc7e38acSHans Petter Selasky int cpu; 882dc7e38acSHans Petter Selasky } __aligned(MLX5E_CACHELINE_SIZE); 883dc7e38acSHans Petter Selasky 884dc7e38acSHans Petter Selasky enum mlx5e_traffic_types { 885dc7e38acSHans Petter Selasky MLX5E_TT_IPV4_TCP, 886dc7e38acSHans Petter Selasky MLX5E_TT_IPV6_TCP, 887dc7e38acSHans Petter Selasky MLX5E_TT_IPV4_UDP, 888dc7e38acSHans Petter Selasky MLX5E_TT_IPV6_UDP, 889dc7e38acSHans Petter Selasky MLX5E_TT_IPV4_IPSEC_AH, 890dc7e38acSHans Petter Selasky MLX5E_TT_IPV6_IPSEC_AH, 891dc7e38acSHans Petter Selasky MLX5E_TT_IPV4_IPSEC_ESP, 892dc7e38acSHans Petter Selasky MLX5E_TT_IPV6_IPSEC_ESP, 893dc7e38acSHans Petter Selasky MLX5E_TT_IPV4, 894dc7e38acSHans Petter Selasky MLX5E_TT_IPV6, 895dc7e38acSHans Petter Selasky MLX5E_TT_ANY, 896dc7e38acSHans Petter Selasky MLX5E_NUM_TT, 897dc7e38acSHans Petter Selasky }; 898dc7e38acSHans Petter Selasky 899dc7e38acSHans Petter Selasky enum { 900dc7e38acSHans Petter Selasky MLX5E_RQT_SPREADING = 0, 901dc7e38acSHans Petter Selasky MLX5E_RQT_DEFAULT_RQ = 1, 902dc7e38acSHans Petter Selasky MLX5E_NUM_RQT = 2, 903dc7e38acSHans Petter Selasky }; 904dc7e38acSHans Petter Selasky 9055a93b4cdSHans Petter Selasky struct mlx5_flow_rule; 9065a93b4cdSHans Petter Selasky 907dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_info { 908dc7e38acSHans Petter Selasky u8 addr [ETH_ALEN + 2]; 909dc7e38acSHans Petter Selasky u32 tt_vec; 9105a93b4cdSHans Petter Selasky /* flow table rule per traffic type */ 9115a93b4cdSHans Petter Selasky struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 912dc7e38acSHans Petter Selasky }; 913dc7e38acSHans Petter Selasky 914dc7e38acSHans Petter Selasky #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 915dc7e38acSHans Petter Selasky 916dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_hash_node; 917dc7e38acSHans Petter Selasky 918dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_hash_head { 919dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_hash_node *lh_first; 920dc7e38acSHans Petter Selasky }; 921dc7e38acSHans Petter Selasky 922dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_db { 923dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 924dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 925dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_info broadcast; 926dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_info allmulti; 927dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_info promisc; 928dc7e38acSHans Petter Selasky bool broadcast_enabled; 929dc7e38acSHans Petter Selasky bool allmulti_enabled; 930dc7e38acSHans Petter Selasky bool promisc_enabled; 931dc7e38acSHans Petter Selasky }; 932dc7e38acSHans Petter Selasky 933dc7e38acSHans Petter Selasky enum { 934dc7e38acSHans Petter Selasky MLX5E_STATE_ASYNC_EVENTS_ENABLE, 935dc7e38acSHans Petter Selasky MLX5E_STATE_OPENED, 936dc7e38acSHans Petter Selasky }; 937dc7e38acSHans Petter Selasky 938cfc9c386SHans Petter Selasky enum { 939cfc9c386SHans Petter Selasky MLX5_BW_NO_LIMIT = 0, 940cfc9c386SHans Petter Selasky MLX5_100_MBPS_UNIT = 3, 941cfc9c386SHans Petter Selasky MLX5_GBPS_UNIT = 4, 942cfc9c386SHans Petter Selasky }; 943cfc9c386SHans Petter Selasky 944dc7e38acSHans Petter Selasky struct mlx5e_vlan_db { 945dc7e38acSHans Petter Selasky unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 9465a93b4cdSHans Petter Selasky struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 9475a93b4cdSHans Petter Selasky struct mlx5_flow_rule *untagged_ft_rule; 9485a93b4cdSHans Petter Selasky struct mlx5_flow_rule *any_cvlan_ft_rule; 9495a93b4cdSHans Petter Selasky struct mlx5_flow_rule *any_svlan_ft_rule; 950dc7e38acSHans Petter Selasky bool filter_disabled; 951dc7e38acSHans Petter Selasky }; 952dc7e38acSHans Petter Selasky 953dc7e38acSHans Petter Selasky struct mlx5e_flow_table { 9545a93b4cdSHans Petter Selasky int num_groups; 9555a93b4cdSHans Petter Selasky struct mlx5_flow_table *t; 9565a93b4cdSHans Petter Selasky struct mlx5_flow_group **g; 9575a93b4cdSHans Petter Selasky }; 9585a93b4cdSHans Petter Selasky 9595a93b4cdSHans Petter Selasky struct mlx5e_flow_tables { 9605a93b4cdSHans Petter Selasky struct mlx5_flow_namespace *ns; 9615a93b4cdSHans Petter Selasky struct mlx5e_flow_table vlan; 9625a93b4cdSHans Petter Selasky struct mlx5e_flow_table main; 9635a93b4cdSHans Petter Selasky struct mlx5e_flow_table inner_rss; 964dc7e38acSHans Petter Selasky }; 965dc7e38acSHans Petter Selasky 96638535d6cSHans Petter Selasky #ifdef RATELIMIT 96738535d6cSHans Petter Selasky #include "en_rl.h" 96838535d6cSHans Petter Selasky #endif 96938535d6cSHans Petter Selasky 970ef23f141SKonstantin Belousov #define MLX5E_TSTMP_PREC 10 971ef23f141SKonstantin Belousov 972ef23f141SKonstantin Belousov struct mlx5e_clbr_point { 973ef23f141SKonstantin Belousov uint64_t base_curr; 974ef23f141SKonstantin Belousov uint64_t base_prev; 975ef23f141SKonstantin Belousov uint64_t clbr_hw_prev; 976ef23f141SKonstantin Belousov uint64_t clbr_hw_curr; 977ef23f141SKonstantin Belousov u_int clbr_gen; 978ef23f141SKonstantin Belousov }; 979ef23f141SKonstantin Belousov 980dc7e38acSHans Petter Selasky struct mlx5e_priv { 9811cbc85fdSHans Petter Selasky struct mlx5_core_dev *mdev; /* must be first */ 9821cbc85fdSHans Petter Selasky 983dc7e38acSHans Petter Selasky /* priv data path fields - start */ 984dc7e38acSHans Petter Selasky int order_base_2_num_channels; 985dc7e38acSHans Petter Selasky int queue_mapping_channel_mask; 986dc7e38acSHans Petter Selasky int num_tc; 987dc7e38acSHans Petter Selasky int default_vlan_prio; 988dc7e38acSHans Petter Selasky /* priv data path fields - end */ 989dc7e38acSHans Petter Selasky 990dc7e38acSHans Petter Selasky unsigned long state; 991dc7e38acSHans Petter Selasky int gone; 992dc7e38acSHans Petter Selasky #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 993dc7e38acSHans Petter Selasky #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 994dc7e38acSHans Petter Selasky #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 995dc7e38acSHans Petter Selasky struct sx state_lock; /* Protects Interface state */ 996dc7e38acSHans Petter Selasky struct mlx5_uar cq_uar; 997dc7e38acSHans Petter Selasky u32 pdn; 998dc7e38acSHans Petter Selasky u32 tdn; 999dc7e38acSHans Petter Selasky struct mlx5_core_mr mr; 1000cc971b22SSlava Shwartsman volatile unsigned int channel_refs; 1001dc7e38acSHans Petter Selasky 1002dc7e38acSHans Petter Selasky u32 tisn[MLX5E_MAX_TX_NUM_TC]; 1003dc7e38acSHans Petter Selasky u32 rqtn; 1004dc7e38acSHans Petter Selasky u32 tirn[MLX5E_NUM_TT]; 1005dc7e38acSHans Petter Selasky 10065a93b4cdSHans Petter Selasky struct mlx5e_flow_tables fts; 1007dc7e38acSHans Petter Selasky struct mlx5e_eth_addr_db eth_addr; 1008dc7e38acSHans Petter Selasky struct mlx5e_vlan_db vlan; 1009dc7e38acSHans Petter Selasky 1010dc7e38acSHans Petter Selasky struct mlx5e_params params; 1011dc7e38acSHans Petter Selasky struct mlx5e_params_ethtool params_ethtool; 101266d53750SHans Petter Selasky union mlx5_core_pci_diagnostics params_pci; 101366d53750SHans Petter Selasky union mlx5_core_general_diagnostics params_general; 1014dc7e38acSHans Petter Selasky struct mtx async_events_mtx; /* sync hw events */ 1015dc7e38acSHans Petter Selasky struct work_struct update_stats_work; 1016dc7e38acSHans Petter Selasky struct work_struct update_carrier_work; 1017dc7e38acSHans Petter Selasky struct work_struct set_rx_mode_work; 101881b3cdc1SHans Petter Selasky MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 1019dc7e38acSHans Petter Selasky 1020dc7e38acSHans Petter Selasky struct ifnet *ifp; 1021dc7e38acSHans Petter Selasky struct sysctl_ctx_list sysctl_ctx; 1022dc7e38acSHans Petter Selasky struct sysctl_oid *sysctl_ifnet; 1023dc7e38acSHans Petter Selasky struct sysctl_oid *sysctl_hw; 1024dc7e38acSHans Petter Selasky int sysctl_debug; 1025dc7e38acSHans Petter Selasky struct mlx5e_stats stats; 1026dc7e38acSHans Petter Selasky int counter_set_id; 1027dc7e38acSHans Petter Selasky 102817778156SHans Petter Selasky struct workqueue_struct *wq; 102917778156SHans Petter Selasky 1030dc7e38acSHans Petter Selasky eventhandler_tag vlan_detach; 1031dc7e38acSHans Petter Selasky eventhandler_tag vlan_attach; 1032dc7e38acSHans Petter Selasky struct ifmedia media; 1033dc7e38acSHans Petter Selasky int media_status_last; 1034dc7e38acSHans Petter Selasky int media_active_last; 1035dc7e38acSHans Petter Selasky 1036dc7e38acSHans Petter Selasky struct callout watchdog; 103738535d6cSHans Petter Selasky #ifdef RATELIMIT 103838535d6cSHans Petter Selasky struct mlx5e_rl_priv_data rl; 103938535d6cSHans Petter Selasky #endif 1040ef23f141SKonstantin Belousov 1041ef23f141SKonstantin Belousov struct callout tstmp_clbr; 1042ef23f141SKonstantin Belousov int clbr_done; 1043ef23f141SKonstantin Belousov int clbr_curr; 1044ef23f141SKonstantin Belousov struct mlx5e_clbr_point clbr_points[2]; 1045ef23f141SKonstantin Belousov u_int clbr_gen; 10463230c29dSSlava Shwartsman 1047538ff57bSAndrew Gallatin struct pfil_head *pfil; 10483230c29dSSlava Shwartsman struct mlx5e_channel channel[]; 1049dc7e38acSHans Petter Selasky }; 1050dc7e38acSHans Petter Selasky 1051dc7e38acSHans Petter Selasky #define MLX5E_NET_IP_ALIGN 2 1052dc7e38acSHans Petter Selasky 1053dc7e38acSHans Petter Selasky struct mlx5e_tx_wqe { 1054dc7e38acSHans Petter Selasky struct mlx5_wqe_ctrl_seg ctrl; 1055dc7e38acSHans Petter Selasky struct mlx5_wqe_eth_seg eth; 1056dc7e38acSHans Petter Selasky }; 1057dc7e38acSHans Petter Selasky 1058dc7e38acSHans Petter Selasky struct mlx5e_rx_wqe { 1059dc7e38acSHans Petter Selasky struct mlx5_wqe_srq_next_seg next; 10602f17f76aSHans Petter Selasky struct mlx5_wqe_data_seg data[]; 1061dc7e38acSHans Petter Selasky }; 1062dc7e38acSHans Petter Selasky 10632f17f76aSHans Petter Selasky /* the size of the structure above must be power of two */ 10642f17f76aSHans Petter Selasky CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe))); 10652f17f76aSHans Petter Selasky 1066dc7e38acSHans Petter Selasky struct mlx5e_eeprom { 1067dc7e38acSHans Petter Selasky int lock_bit; 1068dc7e38acSHans Petter Selasky int i2c_addr; 1069dc7e38acSHans Petter Selasky int page_num; 1070dc7e38acSHans Petter Selasky int device_addr; 1071dc7e38acSHans Petter Selasky int module_num; 1072dc7e38acSHans Petter Selasky int len; 1073dc7e38acSHans Petter Selasky int type; 1074dc7e38acSHans Petter Selasky int page_valid; 1075dc7e38acSHans Petter Selasky u32 *data; 1076dc7e38acSHans Petter Selasky }; 1077dc7e38acSHans Petter Selasky 1078dc7e38acSHans Petter Selasky #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 1079dc7e38acSHans Petter Selasky 1080dc7e38acSHans Petter Selasky int mlx5e_xmit(struct ifnet *, struct mbuf *); 1081dc7e38acSHans Petter Selasky 1082dc7e38acSHans Petter Selasky int mlx5e_open_locked(struct ifnet *); 1083dc7e38acSHans Petter Selasky int mlx5e_close_locked(struct ifnet *); 1084dc7e38acSHans Petter Selasky 1085dc7e38acSHans Petter Selasky void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 1086dc7e38acSHans Petter Selasky void mlx5e_rx_cq_comp(struct mlx5_core_cq *); 1087dc7e38acSHans Petter Selasky void mlx5e_tx_cq_comp(struct mlx5_core_cq *); 1088dc7e38acSHans Petter Selasky struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 1089dc7e38acSHans Petter Selasky 1090423530beSHans Petter Selasky void mlx5e_dim_work(struct work_struct *); 1091423530beSHans Petter Selasky void mlx5e_dim_build_cq_param(struct mlx5e_priv *, struct mlx5e_cq_param *); 1092423530beSHans Petter Selasky 1093dc7e38acSHans Petter Selasky int mlx5e_open_flow_table(struct mlx5e_priv *priv); 1094dc7e38acSHans Petter Selasky void mlx5e_close_flow_table(struct mlx5e_priv *priv); 1095dc7e38acSHans Petter Selasky void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 1096dc7e38acSHans Petter Selasky void mlx5e_set_rx_mode_work(struct work_struct *work); 1097dc7e38acSHans Petter Selasky 1098dc7e38acSHans Petter Selasky void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 1099dc7e38acSHans Petter Selasky void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 1100dc7e38acSHans Petter Selasky void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 1101dc7e38acSHans Petter Selasky void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 1102dc7e38acSHans Petter Selasky int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 1103dc7e38acSHans Petter Selasky void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 1104dc7e38acSHans Petter Selasky 1105dc7e38acSHans Petter Selasky static inline void 1106af89c4afSHans Petter Selasky mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 1107dc7e38acSHans Petter Selasky { 1108dc7e38acSHans Petter Selasky u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 1109dc7e38acSHans Petter Selasky 1110dc7e38acSHans Petter Selasky /* ensure wqe is visible to device before updating doorbell record */ 1111dc7e38acSHans Petter Selasky wmb(); 1112dc7e38acSHans Petter Selasky 1113dc7e38acSHans Petter Selasky *sq->wq.db = cpu_to_be32(sq->pc); 1114dc7e38acSHans Petter Selasky 1115dc7e38acSHans Petter Selasky /* 1116dc7e38acSHans Petter Selasky * Ensure the doorbell record is visible to device before ringing 1117dc7e38acSHans Petter Selasky * the doorbell: 1118dc7e38acSHans Petter Selasky */ 1119dc7e38acSHans Petter Selasky wmb(); 1120dc7e38acSHans Petter Selasky 1121dc7e38acSHans Petter Selasky if (bf_sz) { 11225eadc44cSHans Petter Selasky __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 1123dc7e38acSHans Petter Selasky 1124dc7e38acSHans Petter Selasky /* flush the write-combining mapped buffer */ 1125dc7e38acSHans Petter Selasky wmb(); 1126dc7e38acSHans Petter Selasky 1127dc7e38acSHans Petter Selasky } else { 112881b3cdc1SHans Petter Selasky mlx5_write64(wqe, sq->uar.map + ofst, 112981b3cdc1SHans Petter Selasky MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 1130dc7e38acSHans Petter Selasky } 1131dc7e38acSHans Petter Selasky 1132dc7e38acSHans Petter Selasky sq->bf_offset ^= sq->bf_buf_size; 1133dc7e38acSHans Petter Selasky } 1134dc7e38acSHans Petter Selasky 1135dc7e38acSHans Petter Selasky static inline void 1136e5d6b589SHans Petter Selasky mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 1137dc7e38acSHans Petter Selasky { 1138dc7e38acSHans Petter Selasky struct mlx5_core_cq *mcq; 1139dc7e38acSHans Petter Selasky 1140dc7e38acSHans Petter Selasky mcq = &cq->mcq; 1141e5d6b589SHans Petter Selasky mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 1142dc7e38acSHans Petter Selasky } 1143dc7e38acSHans Petter Selasky 1144cc971b22SSlava Shwartsman static inline void 1145cc971b22SSlava Shwartsman mlx5e_ref_channel(struct mlx5e_priv *priv) 1146cc971b22SSlava Shwartsman { 1147cc971b22SSlava Shwartsman 1148cc971b22SSlava Shwartsman KASSERT(priv->channel_refs < INT_MAX, 1149cc971b22SSlava Shwartsman ("Channel refs will overflow")); 1150cc971b22SSlava Shwartsman atomic_fetchadd_int(&priv->channel_refs, 1); 1151cc971b22SSlava Shwartsman } 1152cc971b22SSlava Shwartsman 1153cc971b22SSlava Shwartsman static inline void 1154cc971b22SSlava Shwartsman mlx5e_unref_channel(struct mlx5e_priv *priv) 1155cc971b22SSlava Shwartsman { 1156cc971b22SSlava Shwartsman 1157cc971b22SSlava Shwartsman KASSERT(priv->channel_refs > 0, 1158cc971b22SSlava Shwartsman ("Channel refs is not greater than zero")); 1159cc971b22SSlava Shwartsman atomic_fetchadd_int(&priv->channel_refs, -1); 1160cc971b22SSlava Shwartsman } 1161cc971b22SSlava Shwartsman 1162dc7e38acSHans Petter Selasky extern const struct ethtool_ops mlx5e_ethtool_ops; 1163dc7e38acSHans Petter Selasky void mlx5e_create_ethtool(struct mlx5e_priv *); 1164dc7e38acSHans Petter Selasky void mlx5e_create_stats(struct sysctl_ctx_list *, 1165dc7e38acSHans Petter Selasky struct sysctl_oid_list *, const char *, 1166dc7e38acSHans Petter Selasky const char **, unsigned, u64 *); 1167af89c4afSHans Petter Selasky void mlx5e_send_nop(struct mlx5e_sq *, u32); 1168376bcf63SHans Petter Selasky void mlx5e_sq_cev_timeout(void *); 1169f03f517bSHans Petter Selasky int mlx5e_refresh_channel_params(struct mlx5e_priv *); 117028f22cceSHans Petter Selasky int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 117128f22cceSHans Petter Selasky struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 117228f22cceSHans Petter Selasky void mlx5e_close_cq(struct mlx5e_cq *); 11737b4e6e4aSHans Petter Selasky void mlx5e_free_sq_db(struct mlx5e_sq *); 11747b4e6e4aSHans Petter Selasky int mlx5e_alloc_sq_db(struct mlx5e_sq *); 11757b4e6e4aSHans Petter Selasky int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 11767b4e6e4aSHans Petter Selasky int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 11777b4e6e4aSHans Petter Selasky void mlx5e_disable_sq(struct mlx5e_sq *); 11787b4e6e4aSHans Petter Selasky void mlx5e_drain_sq(struct mlx5e_sq *); 1179bb3616abSHans Petter Selasky void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 1180bb3616abSHans Petter Selasky void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 1181bb3616abSHans Petter Selasky void mlx5e_resume_sq(struct mlx5e_sq *sq); 11823e581cabSSlava Shwartsman void mlx5e_update_sq_inline(struct mlx5e_sq *sq); 11833e581cabSSlava Shwartsman void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv); 1184dc7e38acSHans Petter Selasky 1185dc7e38acSHans Petter Selasky #endif /* _MLX5_EN_H_ */ 1186