1 /*- 2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _MLX5_EN_H_ 29 #define _MLX5_EN_H_ 30 31 #include <linux/kmod.h> 32 #include <linux/page.h> 33 #include <linux/slab.h> 34 #include <linux/if_vlan.h> 35 #include <linux/if_ether.h> 36 #include <linux/vmalloc.h> 37 #include <linux/moduleparam.h> 38 #include <linux/delay.h> 39 #include <linux/netdevice.h> 40 #include <linux/etherdevice.h> 41 42 #include <netinet/in_systm.h> 43 #include <netinet/in.h> 44 #include <netinet/if_ether.h> 45 #include <netinet/ip.h> 46 #include <netinet/ip6.h> 47 #include <netinet/tcp.h> 48 #include <netinet/tcp_lro.h> 49 #include <netinet/udp.h> 50 #include <net/ethernet.h> 51 #include <sys/buf_ring.h> 52 #include <sys/kthread.h> 53 54 #include "opt_rss.h" 55 56 #ifdef RSS 57 #include <net/rss_config.h> 58 #include <netinet/in_rss.h> 59 #endif 60 61 #include <machine/bus.h> 62 63 #include <dev/mlx5/driver.h> 64 #include <dev/mlx5/qp.h> 65 #include <dev/mlx5/cq.h> 66 #include <dev/mlx5/port.h> 67 #include <dev/mlx5/vport.h> 68 #include <dev/mlx5/diagnostics.h> 69 70 #include <dev/mlx5/mlx5_core/wq.h> 71 #include <dev/mlx5/mlx5_core/transobj.h> 72 #include <dev/mlx5/mlx5_core/mlx5_core.h> 73 74 #define IEEE_8021QAZ_MAX_TCS 8 75 76 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 77 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 78 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 79 80 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 81 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 82 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 83 84 /* freeBSD HW LRO is limited by 16KB - the size of max mbuf */ 85 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES 86 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 87 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 88 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 89 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 90 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 91 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 92 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 93 #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 94 #define MLX5E_HW2SW_MTU(hwmtu) \ 95 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 96 #define MLX5E_SW2HW_MTU(swmtu) \ 97 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 98 #define MLX5E_SW2MB_MTU(swmtu) \ 99 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 100 #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 101 #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 102 * jumbo frames */ 103 104 #define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 105 #define MLX5E_RX_BUDGET_MAX 256 106 #define MLX5E_SQ_BF_BUDGET 16 107 #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 108 109 #define MLX5E_MAX_TX_NUM_TC 8 /* units */ 110 #define MLX5E_MAX_TX_HEADER 128 /* bytes */ 111 #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 112 #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 113 #define MLX5E_MAX_TX_MBUF_FRAGS \ 114 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 115 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS)) /* units */ 116 #define MLX5E_MAX_TX_INLINE \ 117 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 118 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 119 120 #define MLX5E_100MB (100000) 121 #define MLX5E_1GB (1000000) 122 123 MALLOC_DECLARE(M_MLX5EN); 124 125 struct mlx5_core_dev; 126 struct mlx5e_cq; 127 128 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 129 130 #define MLX5E_STATS_COUNT(a,b,c,d) a 131 #define MLX5E_STATS_VAR(a,b,c,d) b; 132 #define MLX5E_STATS_DESC(a,b,c,d) c, d, 133 134 #define MLX5E_VPORT_STATS(m) \ 135 /* HW counters */ \ 136 m(+1, u64 rx_packets, "rx_packets", "Received packets") \ 137 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \ 138 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \ 139 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \ 140 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \ 141 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 142 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 143 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 144 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 145 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 146 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 147 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 148 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 149 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 150 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 151 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 152 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 153 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 154 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 155 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 156 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 157 /* SW counters */ \ 158 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \ 159 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 160 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \ 161 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \ 162 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 163 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 164 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 165 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 166 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 167 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 168 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \ 169 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors") 170 171 #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 172 173 struct mlx5e_vport_stats { 174 struct sysctl_ctx_list ctx; 175 u64 arg [0]; 176 MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 177 u32 rx_out_of_buffer_prev; 178 }; 179 180 #define MLX5E_PPORT_IEEE802_3_STATS(m) \ 181 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \ 182 m(+1, u64 frames_rx, "frames_rx", "Frames received") \ 183 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \ 184 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \ 185 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \ 186 m(+1, u64 octets_received, "octets_received", "Bytes received") \ 187 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 188 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 189 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \ 190 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \ 191 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \ 192 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \ 193 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \ 194 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \ 195 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 196 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \ 197 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 198 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 199 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 200 201 #define MLX5E_PPORT_RFC2819_STATS(m) \ 202 m(+1, u64 drop_events, "drop_events", "Dropped events") \ 203 m(+1, u64 octets, "octets", "Octets") \ 204 m(+1, u64 pkts, "pkts", "Packets") \ 205 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 206 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \ 207 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 208 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \ 209 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \ 210 m(+1, u64 fragments, "fragments", "Fragments") \ 211 m(+1, u64 jabbers, "jabbers", "Jabbers") \ 212 m(+1, u64 collisions, "collisions", "Collisions") 213 214 #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 215 m(+1, u64 p64octets, "p64octets", "Bytes") \ 216 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \ 217 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \ 218 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \ 219 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \ 220 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \ 221 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \ 222 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \ 223 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \ 224 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes") 225 226 #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 227 m(+1, u64 in_octets, "in_octets", "In octets") \ 228 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 229 m(+1, u64 in_discards, "in_discards", "In discards") \ 230 m(+1, u64 in_errors, "in_errors", "In errors") \ 231 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 232 m(+1, u64 out_octets, "out_octets", "Out octets") \ 233 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 234 m(+1, u64 out_discards, "out_discards", "Out discards") \ 235 m(+1, u64 out_errors, "out_errors", "Out errors") \ 236 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 237 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 238 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 239 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 240 241 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 242 m(+1, u64 time_since_last_clear, "time_since_last_clear", \ 243 "Time since the last counters clear event (msec)") \ 244 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \ 245 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \ 246 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \ 247 "Indicates the number of PRBS errors on lane 0") \ 248 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \ 249 "Indicates the number of PRBS errors on lane 1") \ 250 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \ 251 "Indicates the number of PRBS errors on lane 2") \ 252 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \ 253 "Indicates the number of PRBS errors on lane 3") \ 254 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 255 "FEC correctable block counter lane 0") \ 256 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 257 "FEC correctable block counter lane 1") \ 258 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 259 "FEC correctable block counter lane 2") \ 260 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 261 "FEC correctable block counter lane 3") \ 262 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \ 263 "FEC correcable block counter") \ 264 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 265 "FEC uncorrecable block counter") \ 266 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \ 267 "The number of RS-FEC blocks received that had no errors") \ 268 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \ 269 "The number of corrected RS-FEC blocks received that had" \ 270 "exactly 1 error symbol") \ 271 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 272 "Port FEC corrected symbol counter") \ 273 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 274 "FEC corrected symbol counter lane 0") \ 275 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 276 "FEC corrected symbol counter lane 1") \ 277 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 278 "FEC corrected symbol counter lane 2") \ 279 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 280 "FEC corrected symbol counter lane 3") 281 282 /* Per priority statistics for PFC */ 283 #define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 284 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 285 m(n, p, +1, u64, reserved_0, "reserved_0", "Reserved") \ 286 m(n, p, +1, u64, reserved_1, "reserved_1", "Reserved") \ 287 m(n, p, +1, u64, reserved_2, "reserved_2", "Reserved") \ 288 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 289 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 290 m(n, p, +1, u64, reserved_3, "reserved_3", "Reserved") \ 291 m(n, p, +1, u64, reserved_4, "reserved_4", "Reserved") \ 292 m(n, p, +1, u64, reserved_5, "reserved_5", "Reserved") \ 293 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 294 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 295 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 296 "Received pause duration") \ 297 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 298 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 299 "Transmitted pause duration") \ 300 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 301 "Received pause transitions") \ 302 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 303 m(n, p, +1, u64, device_stall_minor_watermark, \ 304 "device_stall_minor_watermark", "Device stall minor watermark") \ 305 m(n, p, +1, u64, device_stall_critical_watermark, \ 306 "device_stall_critical_watermark", "Device stall critical watermark") 307 308 #define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 309 m(c, t pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 310 311 #define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 312 313 #define MLX5E_PPORT_PER_PRIO_STATS(m) \ 314 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 315 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 316 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 317 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 318 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 319 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 320 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 321 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 322 323 /* 324 * Make sure to update mlx5e_update_pport_counters() 325 * when adding a new MLX5E_PPORT_STATS block 326 */ 327 #define MLX5E_PPORT_STATS(m) \ 328 MLX5E_PPORT_PER_PRIO_STATS(m) \ 329 MLX5E_PPORT_IEEE802_3_STATS(m) \ 330 MLX5E_PPORT_RFC2819_STATS(m) 331 332 #define MLX5E_PORT_STATS_DEBUG(m) \ 333 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 334 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 335 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) 336 337 #define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 338 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 339 #define MLX5E_PPORT_RFC2819_STATS_NUM \ 340 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 341 #define MLX5E_PPORT_STATS_NUM \ 342 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 343 344 #define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 345 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 346 #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 347 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 348 #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 349 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 350 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 351 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 352 #define MLX5E_PORT_STATS_DEBUG_NUM \ 353 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 354 355 struct mlx5e_pport_stats { 356 struct sysctl_ctx_list ctx; 357 u64 arg [0]; 358 MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 359 }; 360 361 struct mlx5e_port_stats_debug { 362 struct sysctl_ctx_list ctx; 363 u64 arg [0]; 364 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 365 }; 366 367 #define MLX5E_RQ_STATS(m) \ 368 m(+1, u64 packets, "packets", "Received packets") \ 369 m(+1, u64 csum_none, "csum_none", "Received packets") \ 370 m(+1, u64 lro_packets, "lro_packets", "Received packets") \ 371 m(+1, u64 lro_bytes, "lro_bytes", "Received packets") \ 372 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 373 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 374 m(+1, u64 wqe_err, "wqe_err", "Received packets") 375 376 #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 377 378 struct mlx5e_rq_stats { 379 struct sysctl_ctx_list ctx; 380 u64 arg [0]; 381 MLX5E_RQ_STATS(MLX5E_STATS_VAR) 382 }; 383 384 #define MLX5E_SQ_STATS(m) \ 385 m(+1, u64 packets, "packets", "Transmitted packets") \ 386 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \ 387 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \ 388 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \ 389 m(+1, u64 defragged, "defragged", "Transmitted packets") \ 390 m(+1, u64 dropped, "dropped", "Transmitted packets") \ 391 m(+1, u64 nop, "nop", "Transmitted packets") 392 393 #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 394 395 struct mlx5e_sq_stats { 396 struct sysctl_ctx_list ctx; 397 u64 arg [0]; 398 MLX5E_SQ_STATS(MLX5E_STATS_VAR) 399 }; 400 401 struct mlx5e_stats { 402 struct mlx5e_vport_stats vport; 403 struct mlx5e_pport_stats pport; 404 struct mlx5e_port_stats_debug port_stats_debug; 405 }; 406 407 struct mlx5e_rq_param { 408 u32 rqc [MLX5_ST_SZ_DW(rqc)]; 409 struct mlx5_wq_param wq; 410 }; 411 412 struct mlx5e_sq_param { 413 u32 sqc [MLX5_ST_SZ_DW(sqc)]; 414 struct mlx5_wq_param wq; 415 }; 416 417 struct mlx5e_cq_param { 418 u32 cqc [MLX5_ST_SZ_DW(cqc)]; 419 struct mlx5_wq_param wq; 420 }; 421 422 struct mlx5e_params { 423 u8 log_sq_size; 424 u8 log_rq_size; 425 u16 num_channels; 426 u8 default_vlan_prio; 427 u8 num_tc; 428 u8 rx_cq_moderation_mode; 429 u8 tx_cq_moderation_mode; 430 u16 rx_cq_moderation_usec; 431 u16 rx_cq_moderation_pkts; 432 u16 tx_cq_moderation_usec; 433 u16 tx_cq_moderation_pkts; 434 u16 min_rx_wqes; 435 bool hw_lro_en; 436 bool cqe_zipping_en; 437 u32 lro_wqe_sz; 438 u16 rx_hash_log_tbl_sz; 439 u32 tx_pauseframe_control __aligned(4); 440 u32 rx_pauseframe_control __aligned(4); 441 u32 tx_priority_flow_control __aligned(4); 442 u32 rx_priority_flow_control __aligned(4); 443 }; 444 445 #define MLX5E_PARAMS(m) \ 446 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 447 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 448 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \ 449 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \ 450 m(+1, u64 channels, "channels", "Default number of channels") \ 451 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 452 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 453 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 454 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 455 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 456 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 457 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 458 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 459 m(+1, u64 tx_bufring_disable, "tx_bufring_disable", "0: Enable bufring 1: Disable bufring") \ 460 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 461 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 462 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \ 463 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 464 m(+1, u64 modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 465 m(+1, u64 modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 466 m(+1, u64 diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 467 m(+1, u64 diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 468 m(+1, u64 hw_mtu, "hw_mtu", "Current hardware MTU value") \ 469 m(+1, u64 mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 470 m(+1, u64 uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") 471 472 473 #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 474 475 struct mlx5e_params_ethtool { 476 u64 arg [0]; 477 MLX5E_PARAMS(MLX5E_STATS_VAR) 478 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 479 u8 prio_tc[IEEE_8021QAZ_MAX_TCS]; 480 }; 481 482 /* EEPROM Standards for plug in modules */ 483 #ifndef MLX5E_ETH_MODULE_SFF_8472 484 #define MLX5E_ETH_MODULE_SFF_8472 0x1 485 #define MLX5E_ETH_MODULE_SFF_8472_LEN 128 486 #endif 487 488 #ifndef MLX5E_ETH_MODULE_SFF_8636 489 #define MLX5E_ETH_MODULE_SFF_8636 0x2 490 #define MLX5E_ETH_MODULE_SFF_8636_LEN 256 491 #endif 492 493 #ifndef MLX5E_ETH_MODULE_SFF_8436 494 #define MLX5E_ETH_MODULE_SFF_8436 0x3 495 #define MLX5E_ETH_MODULE_SFF_8436_LEN 256 496 #endif 497 498 /* EEPROM I2C Addresses */ 499 #define MLX5E_I2C_ADDR_LOW 0x50 500 #define MLX5E_I2C_ADDR_HIGH 0x51 501 502 #define MLX5E_EEPROM_LOW_PAGE 0x0 503 #define MLX5E_EEPROM_HIGH_PAGE 0x3 504 505 #define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128 506 #define MLX5E_EEPROM_PAGE_LENGTH 256 507 508 #define MLX5E_EEPROM_INFO_BYTES 0x3 509 510 struct mlx5e_cq { 511 /* data path - accessed per cqe */ 512 struct mlx5_cqwq wq; 513 514 /* data path - accessed per HW polling */ 515 struct mlx5_core_cq mcq; 516 517 /* control */ 518 struct mlx5e_priv *priv; 519 struct mlx5_wq_ctrl wq_ctrl; 520 } __aligned(MLX5E_CACHELINE_SIZE); 521 522 struct mlx5e_rq_mbuf { 523 bus_dmamap_t dma_map; 524 caddr_t data; 525 struct mbuf *mbuf; 526 }; 527 528 struct mlx5e_rq { 529 /* data path */ 530 struct mlx5_wq_ll wq; 531 struct mtx mtx; 532 bus_dma_tag_t dma_tag; 533 u32 wqe_sz; 534 struct mlx5e_rq_mbuf *mbuf; 535 struct ifnet *ifp; 536 struct mlx5e_rq_stats stats; 537 struct mlx5e_cq cq; 538 struct lro_ctrl lro; 539 volatile int enabled; 540 int ix; 541 542 /* control */ 543 struct mlx5_wq_ctrl wq_ctrl; 544 u32 rqn; 545 struct mlx5e_channel *channel; 546 struct callout watchdog; 547 } __aligned(MLX5E_CACHELINE_SIZE); 548 549 struct mlx5e_sq_mbuf { 550 bus_dmamap_t dma_map; 551 struct mbuf *mbuf; 552 u32 num_bytes; 553 u32 num_wqebbs; 554 }; 555 556 enum { 557 MLX5E_SQ_READY, 558 MLX5E_SQ_FULL 559 }; 560 561 struct mlx5e_sq { 562 /* data path */ 563 struct mtx lock; 564 bus_dma_tag_t dma_tag; 565 struct mtx comp_lock; 566 567 /* dirtied @completion */ 568 u16 cc; 569 570 /* dirtied @xmit */ 571 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 572 u16 bf_offset; 573 u16 cev_counter; /* completion event counter */ 574 u16 cev_factor; /* completion event factor */ 575 u16 cev_next_state; /* next completion event state */ 576 #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 577 #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 578 #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 579 u16 stopped; /* set if SQ is stopped */ 580 struct callout cev_callout; 581 union { 582 u32 d32[2]; 583 u64 d64; 584 } doorbell; 585 struct mlx5e_sq_stats stats; 586 587 struct mlx5e_cq cq; 588 struct task sq_task; 589 struct taskqueue *sq_tq; 590 591 /* pointers to per packet info: write@xmit, read@completion */ 592 struct mlx5e_sq_mbuf *mbuf; 593 struct buf_ring *br; 594 595 /* read only */ 596 struct mlx5_wq_cyc wq; 597 struct mlx5_uar uar; 598 struct ifnet *ifp; 599 u32 sqn; 600 u32 bf_buf_size; 601 u32 mkey_be; 602 603 /* control path */ 604 struct mlx5_wq_ctrl wq_ctrl; 605 struct mlx5e_priv *priv; 606 int tc; 607 unsigned int queue_state; 608 } __aligned(MLX5E_CACHELINE_SIZE); 609 610 static inline bool 611 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 612 { 613 u16 cc = sq->cc; 614 u16 pc = sq->pc; 615 616 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 617 } 618 619 struct mlx5e_channel { 620 /* data path */ 621 struct mlx5e_rq rq; 622 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 623 struct ifnet *ifp; 624 u32 mkey_be; 625 u8 num_tc; 626 627 /* control */ 628 struct mlx5e_priv *priv; 629 int ix; 630 int cpu; 631 } __aligned(MLX5E_CACHELINE_SIZE); 632 633 enum mlx5e_traffic_types { 634 MLX5E_TT_IPV4_TCP, 635 MLX5E_TT_IPV6_TCP, 636 MLX5E_TT_IPV4_UDP, 637 MLX5E_TT_IPV6_UDP, 638 MLX5E_TT_IPV4_IPSEC_AH, 639 MLX5E_TT_IPV6_IPSEC_AH, 640 MLX5E_TT_IPV4_IPSEC_ESP, 641 MLX5E_TT_IPV6_IPSEC_ESP, 642 MLX5E_TT_IPV4, 643 MLX5E_TT_IPV6, 644 MLX5E_TT_ANY, 645 MLX5E_NUM_TT, 646 }; 647 648 enum { 649 MLX5E_RQT_SPREADING = 0, 650 MLX5E_RQT_DEFAULT_RQ = 1, 651 MLX5E_NUM_RQT = 2, 652 }; 653 654 struct mlx5_flow_rule; 655 656 struct mlx5e_eth_addr_info { 657 u8 addr [ETH_ALEN + 2]; 658 u32 tt_vec; 659 /* flow table rule per traffic type */ 660 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 661 }; 662 663 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 664 665 struct mlx5e_eth_addr_hash_node; 666 667 struct mlx5e_eth_addr_hash_head { 668 struct mlx5e_eth_addr_hash_node *lh_first; 669 }; 670 671 struct mlx5e_eth_addr_db { 672 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 673 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 674 struct mlx5e_eth_addr_info broadcast; 675 struct mlx5e_eth_addr_info allmulti; 676 struct mlx5e_eth_addr_info promisc; 677 bool broadcast_enabled; 678 bool allmulti_enabled; 679 bool promisc_enabled; 680 }; 681 682 enum { 683 MLX5E_STATE_ASYNC_EVENTS_ENABLE, 684 MLX5E_STATE_OPENED, 685 }; 686 687 enum { 688 MLX5_BW_NO_LIMIT = 0, 689 MLX5_100_MBPS_UNIT = 3, 690 MLX5_GBPS_UNIT = 4, 691 }; 692 693 struct mlx5e_vlan_db { 694 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 695 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 696 struct mlx5_flow_rule *untagged_ft_rule; 697 struct mlx5_flow_rule *any_cvlan_ft_rule; 698 struct mlx5_flow_rule *any_svlan_ft_rule; 699 bool filter_disabled; 700 }; 701 702 struct mlx5e_flow_table { 703 int num_groups; 704 struct mlx5_flow_table *t; 705 struct mlx5_flow_group **g; 706 }; 707 708 struct mlx5e_flow_tables { 709 struct mlx5_flow_namespace *ns; 710 struct mlx5e_flow_table vlan; 711 struct mlx5e_flow_table main; 712 struct mlx5e_flow_table inner_rss; 713 }; 714 715 #ifdef RATELIMIT 716 #include "en_rl.h" 717 #endif 718 719 #define MLX5E_TSTMP_PREC 10 720 721 struct mlx5e_clbr_point { 722 uint64_t base_curr; 723 uint64_t base_prev; 724 uint64_t clbr_hw_prev; 725 uint64_t clbr_hw_curr; 726 u_int clbr_gen; 727 }; 728 729 struct mlx5e_priv { 730 struct mlx5_core_dev *mdev; /* must be first */ 731 732 /* priv data path fields - start */ 733 int order_base_2_num_channels; 734 int queue_mapping_channel_mask; 735 int num_tc; 736 int default_vlan_prio; 737 /* priv data path fields - end */ 738 739 unsigned long state; 740 int gone; 741 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 742 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 743 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 744 struct sx state_lock; /* Protects Interface state */ 745 struct mlx5_uar cq_uar; 746 u32 pdn; 747 u32 tdn; 748 struct mlx5_core_mr mr; 749 750 struct mlx5e_channel *volatile *channel; 751 u32 tisn[MLX5E_MAX_TX_NUM_TC]; 752 u32 rqtn; 753 u32 tirn[MLX5E_NUM_TT]; 754 755 struct mlx5e_flow_tables fts; 756 struct mlx5e_eth_addr_db eth_addr; 757 struct mlx5e_vlan_db vlan; 758 759 struct mlx5e_params params; 760 struct mlx5e_params_ethtool params_ethtool; 761 union mlx5_core_pci_diagnostics params_pci; 762 union mlx5_core_general_diagnostics params_general; 763 struct mtx async_events_mtx; /* sync hw events */ 764 struct work_struct update_stats_work; 765 struct work_struct update_carrier_work; 766 struct work_struct set_rx_mode_work; 767 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 768 769 struct ifnet *ifp; 770 struct sysctl_ctx_list sysctl_ctx; 771 struct sysctl_oid *sysctl_ifnet; 772 struct sysctl_oid *sysctl_hw; 773 int sysctl_debug; 774 struct mlx5e_stats stats; 775 int counter_set_id; 776 777 struct workqueue_struct *wq; 778 779 eventhandler_tag vlan_detach; 780 eventhandler_tag vlan_attach; 781 struct ifmedia media; 782 int media_status_last; 783 int media_active_last; 784 785 struct callout watchdog; 786 #ifdef RATELIMIT 787 struct mlx5e_rl_priv_data rl; 788 #endif 789 790 struct callout tstmp_clbr; 791 int clbr_done; 792 int clbr_curr; 793 struct mlx5e_clbr_point clbr_points[2]; 794 u_int clbr_gen; 795 }; 796 797 #define MLX5E_NET_IP_ALIGN 2 798 799 struct mlx5e_tx_wqe { 800 struct mlx5_wqe_ctrl_seg ctrl; 801 struct mlx5_wqe_eth_seg eth; 802 }; 803 804 struct mlx5e_rx_wqe { 805 struct mlx5_wqe_srq_next_seg next; 806 struct mlx5_wqe_data_seg data; 807 }; 808 809 struct mlx5e_eeprom { 810 int lock_bit; 811 int i2c_addr; 812 int page_num; 813 int device_addr; 814 int module_num; 815 int len; 816 int type; 817 int page_valid; 818 u32 *data; 819 }; 820 821 /* 822 * This structure contains rate limit extension to the IEEE 802.1Qaz ETS 823 * managed object. 824 * Values are 64 bits long and specified in Kbps to enable usage over both 825 * slow and very fast networks. 826 * 827 * @tc_maxrate: maximal tc tx bandwidth indexed by traffic class 828 */ 829 struct ieee_maxrate { 830 __u64 tc_maxrate[IEEE_8021QAZ_MAX_TCS]; 831 }; 832 833 834 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 835 836 int mlx5e_xmit(struct ifnet *, struct mbuf *); 837 838 int mlx5e_open_locked(struct ifnet *); 839 int mlx5e_close_locked(struct ifnet *); 840 841 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 842 void mlx5e_rx_cq_comp(struct mlx5_core_cq *); 843 void mlx5e_tx_cq_comp(struct mlx5_core_cq *); 844 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 845 void mlx5e_tx_que(void *context, int pending); 846 847 int mlx5e_open_flow_table(struct mlx5e_priv *priv); 848 void mlx5e_close_flow_table(struct mlx5e_priv *priv); 849 void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 850 void mlx5e_set_rx_mode_work(struct work_struct *work); 851 852 void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 853 void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 854 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 855 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 856 int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 857 void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 858 859 static inline void 860 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 861 { 862 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 863 864 /* ensure wqe is visible to device before updating doorbell record */ 865 wmb(); 866 867 *sq->wq.db = cpu_to_be32(sq->pc); 868 869 /* 870 * Ensure the doorbell record is visible to device before ringing 871 * the doorbell: 872 */ 873 wmb(); 874 875 if (bf_sz) { 876 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 877 878 /* flush the write-combining mapped buffer */ 879 wmb(); 880 881 } else { 882 mlx5_write64(wqe, sq->uar.map + ofst, 883 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 884 } 885 886 sq->bf_offset ^= sq->bf_buf_size; 887 } 888 889 static inline void 890 mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 891 { 892 struct mlx5_core_cq *mcq; 893 894 mcq = &cq->mcq; 895 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 896 } 897 898 extern const struct ethtool_ops mlx5e_ethtool_ops; 899 void mlx5e_create_ethtool(struct mlx5e_priv *); 900 void mlx5e_create_stats(struct sysctl_ctx_list *, 901 struct sysctl_oid_list *, const char *, 902 const char **, unsigned, u64 *); 903 void mlx5e_send_nop(struct mlx5e_sq *, u32); 904 void mlx5e_sq_cev_timeout(void *); 905 int mlx5e_refresh_channel_params(struct mlx5e_priv *); 906 int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 907 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 908 void mlx5e_close_cq(struct mlx5e_cq *); 909 void mlx5e_free_sq_db(struct mlx5e_sq *); 910 int mlx5e_alloc_sq_db(struct mlx5e_sq *); 911 int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 912 int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 913 void mlx5e_disable_sq(struct mlx5e_sq *); 914 void mlx5e_drain_sq(struct mlx5e_sq *); 915 void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 916 void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 917 void mlx5e_resume_sq(struct mlx5e_sq *sq); 918 919 #endif /* _MLX5_EN_H_ */ 920