1 /*- 2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2022 NVIDIA corporation & affiliates. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include "opt_kern_tls.h" 30 #include "opt_rss.h" 31 #include "opt_ratelimit.h" 32 33 #include <dev/mlx5/mlx5_en/en.h> 34 35 #include <sys/eventhandler.h> 36 #include <sys/sockio.h> 37 #include <machine/atomic.h> 38 39 #include <net/debugnet.h> 40 41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs); 42 static if_snd_tag_query_t mlx5e_ul_snd_tag_query; 43 static if_snd_tag_free_t mlx5e_ul_snd_tag_free; 44 45 struct mlx5e_channel_param { 46 struct mlx5e_rq_param rq; 47 struct mlx5e_sq_param sq; 48 struct mlx5e_cq_param rx_cq; 49 struct mlx5e_cq_param tx_cq; 50 }; 51 52 struct media { 53 u32 subtype; 54 u64 baudrate; 55 }; 56 57 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER] = 58 { 59 [MLX5E_1000BASE_CX_SGMII] = { 60 .subtype = IFM_1000_CX_SGMII, 61 .baudrate = IF_Mbps(1000ULL), 62 }, 63 [MLX5E_1000BASE_KX] = { 64 .subtype = IFM_1000_KX, 65 .baudrate = IF_Mbps(1000ULL), 66 }, 67 [MLX5E_10GBASE_CX4] = { 68 .subtype = IFM_10G_CX4, 69 .baudrate = IF_Gbps(10ULL), 70 }, 71 [MLX5E_10GBASE_KX4] = { 72 .subtype = IFM_10G_KX4, 73 .baudrate = IF_Gbps(10ULL), 74 }, 75 [MLX5E_10GBASE_KR] = { 76 .subtype = IFM_10G_KR, 77 .baudrate = IF_Gbps(10ULL), 78 }, 79 [MLX5E_20GBASE_KR2] = { 80 .subtype = IFM_20G_KR2, 81 .baudrate = IF_Gbps(20ULL), 82 }, 83 [MLX5E_40GBASE_CR4] = { 84 .subtype = IFM_40G_CR4, 85 .baudrate = IF_Gbps(40ULL), 86 }, 87 [MLX5E_40GBASE_KR4] = { 88 .subtype = IFM_40G_KR4, 89 .baudrate = IF_Gbps(40ULL), 90 }, 91 [MLX5E_56GBASE_R4] = { 92 .subtype = IFM_56G_R4, 93 .baudrate = IF_Gbps(56ULL), 94 }, 95 [MLX5E_10GBASE_CR] = { 96 .subtype = IFM_10G_CR1, 97 .baudrate = IF_Gbps(10ULL), 98 }, 99 [MLX5E_10GBASE_SR] = { 100 .subtype = IFM_10G_SR, 101 .baudrate = IF_Gbps(10ULL), 102 }, 103 [MLX5E_10GBASE_ER_LR] = { 104 .subtype = IFM_10G_ER, 105 .baudrate = IF_Gbps(10ULL), 106 }, 107 [MLX5E_40GBASE_SR4] = { 108 .subtype = IFM_40G_SR4, 109 .baudrate = IF_Gbps(40ULL), 110 }, 111 [MLX5E_40GBASE_LR4_ER4] = { 112 .subtype = IFM_40G_LR4, 113 .baudrate = IF_Gbps(40ULL), 114 }, 115 [MLX5E_100GBASE_CR4] = { 116 .subtype = IFM_100G_CR4, 117 .baudrate = IF_Gbps(100ULL), 118 }, 119 [MLX5E_100GBASE_SR4] = { 120 .subtype = IFM_100G_SR4, 121 .baudrate = IF_Gbps(100ULL), 122 }, 123 [MLX5E_100GBASE_KR4] = { 124 .subtype = IFM_100G_KR4, 125 .baudrate = IF_Gbps(100ULL), 126 }, 127 [MLX5E_100GBASE_LR4] = { 128 .subtype = IFM_100G_LR4, 129 .baudrate = IF_Gbps(100ULL), 130 }, 131 [MLX5E_100BASE_TX] = { 132 .subtype = IFM_100_TX, 133 .baudrate = IF_Mbps(100ULL), 134 }, 135 [MLX5E_1000BASE_T] = { 136 .subtype = IFM_1000_T, 137 .baudrate = IF_Mbps(1000ULL), 138 }, 139 [MLX5E_10GBASE_T] = { 140 .subtype = IFM_10G_T, 141 .baudrate = IF_Gbps(10ULL), 142 }, 143 [MLX5E_25GBASE_CR] = { 144 .subtype = IFM_25G_CR, 145 .baudrate = IF_Gbps(25ULL), 146 }, 147 [MLX5E_25GBASE_KR] = { 148 .subtype = IFM_25G_KR, 149 .baudrate = IF_Gbps(25ULL), 150 }, 151 [MLX5E_25GBASE_SR] = { 152 .subtype = IFM_25G_SR, 153 .baudrate = IF_Gbps(25ULL), 154 }, 155 [MLX5E_50GBASE_CR2] = { 156 .subtype = IFM_50G_CR2, 157 .baudrate = IF_Gbps(50ULL), 158 }, 159 [MLX5E_50GBASE_KR2] = { 160 .subtype = IFM_50G_KR2, 161 .baudrate = IF_Gbps(50ULL), 162 }, 163 [MLX5E_50GBASE_KR4] = { 164 .subtype = IFM_50G_KR4, 165 .baudrate = IF_Gbps(50ULL), 166 }, 167 }; 168 169 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_CABLE_TYPE_NUMBER] = 170 { 171 /**/ 172 [MLX5E_SGMII_100M][MLX5E_CABLE_TYPE_UNKNOWN] = { 173 .subtype = IFM_100_SGMII, 174 .baudrate = IF_Mbps(100), 175 }, 176 177 /**/ 178 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_UNKNOWN] = { 179 .subtype = IFM_1000_CX, 180 .baudrate = IF_Mbps(1000), 181 }, 182 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 183 .subtype = IFM_1000_SX, 184 .baudrate = IF_Mbps(1000), 185 }, 186 187 /**/ 188 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_UNKNOWN] = { 189 .subtype = IFM_5000_KR, 190 .baudrate = IF_Mbps(5000), 191 }, 192 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_TWISTED_PAIR] = { 193 .subtype = IFM_5000_T, 194 .baudrate = IF_Mbps(5000), 195 }, 196 197 /**/ 198 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_UNKNOWN] = { 199 .subtype = IFM_10G_KR, 200 .baudrate = IF_Gbps(10ULL), 201 }, 202 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 203 .subtype = IFM_10G_CR1, 204 .baudrate = IF_Gbps(10ULL), 205 }, 206 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 207 .subtype = IFM_10G_SR, 208 .baudrate = IF_Gbps(10ULL), 209 }, 210 211 /**/ 212 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_UNKNOWN] = { 213 .subtype = IFM_40G_KR4, 214 .baudrate = IF_Gbps(40ULL), 215 }, 216 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 217 .subtype = IFM_40G_CR4, 218 .baudrate = IF_Gbps(40ULL), 219 }, 220 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 221 .subtype = IFM_40G_SR4, 222 .baudrate = IF_Gbps(40ULL), 223 }, 224 225 /**/ 226 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 227 .subtype = IFM_25G_KR, 228 .baudrate = IF_Gbps(25ULL), 229 }, 230 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 231 .subtype = IFM_25G_CR, 232 .baudrate = IF_Gbps(25ULL), 233 }, 234 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 235 .subtype = IFM_25G_SR, 236 .baudrate = IF_Gbps(25ULL), 237 }, 238 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_TWISTED_PAIR] = { 239 .subtype = IFM_25G_T, 240 .baudrate = IF_Gbps(25ULL), 241 }, 242 243 /**/ 244 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 245 .subtype = IFM_50G_KR2, 246 .baudrate = IF_Gbps(50ULL), 247 }, 248 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 249 .subtype = IFM_50G_CR2, 250 .baudrate = IF_Gbps(50ULL), 251 }, 252 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 253 .subtype = IFM_50G_SR2, 254 .baudrate = IF_Gbps(50ULL), 255 }, 256 257 /**/ 258 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 259 .subtype = IFM_50G_KR_PAM4, 260 .baudrate = IF_Gbps(50ULL), 261 }, 262 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 263 .subtype = IFM_50G_CP, 264 .baudrate = IF_Gbps(50ULL), 265 }, 266 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 267 .subtype = IFM_50G_SR, 268 .baudrate = IF_Gbps(50ULL), 269 }, 270 271 /**/ 272 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 273 .subtype = IFM_100G_KR4, 274 .baudrate = IF_Gbps(100ULL), 275 }, 276 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 277 .subtype = IFM_100G_CR4, 278 .baudrate = IF_Gbps(100ULL), 279 }, 280 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 281 .subtype = IFM_100G_SR4, 282 .baudrate = IF_Gbps(100ULL), 283 }, 284 285 /**/ 286 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 287 .subtype = IFM_100G_KR_PAM4, 288 .baudrate = IF_Gbps(100ULL), 289 }, 290 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 291 .subtype = IFM_100G_CR_PAM4, 292 .baudrate = IF_Gbps(100ULL), 293 }, 294 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 295 .subtype = IFM_100G_SR2, /* XXX */ 296 .baudrate = IF_Gbps(100ULL), 297 }, 298 299 /**/ 300 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 301 .subtype = IFM_100G_KR4, 302 .baudrate = IF_Gbps(100ULL), 303 }, 304 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 305 .subtype = IFM_100G_CP2, 306 .baudrate = IF_Gbps(100ULL), 307 }, 308 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 309 .subtype = IFM_100G_SR2, 310 .baudrate = IF_Gbps(100ULL), 311 }, 312 313 /**/ 314 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 315 .subtype = IFM_200G_KR4_PAM4, /* XXX */ 316 .baudrate = IF_Gbps(200ULL), 317 }, 318 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 319 .subtype = IFM_200G_CR4_PAM4, /* XXX */ 320 .baudrate = IF_Gbps(200ULL), 321 }, 322 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 323 .subtype = IFM_200G_SR4, /* XXX */ 324 .baudrate = IF_Gbps(200ULL), 325 }, 326 327 /**/ 328 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 329 .subtype = IFM_200G_KR4_PAM4, 330 .baudrate = IF_Gbps(200ULL), 331 }, 332 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 333 .subtype = IFM_200G_CR4_PAM4, 334 .baudrate = IF_Gbps(200ULL), 335 }, 336 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 337 .subtype = IFM_200G_SR4, 338 .baudrate = IF_Gbps(200ULL), 339 }, 340 341 /**/ 342 [MLX5E_400GAUI_8][MLX5E_CABLE_TYPE_UNKNOWN] = { 343 .subtype = IFM_400G_LR8, /* XXX */ 344 .baudrate = IF_Gbps(400ULL), 345 }, 346 347 /**/ 348 [MLX5E_400GAUI_4_400GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 349 .subtype = IFM_400G_LR8, /* XXX */ 350 .baudrate = IF_Gbps(400ULL), 351 }, 352 }; 353 354 static const struct if_snd_tag_sw mlx5e_ul_snd_tag_sw = { 355 .snd_tag_query = mlx5e_ul_snd_tag_query, 356 .snd_tag_free = mlx5e_ul_snd_tag_free, 357 .type = IF_SND_TAG_TYPE_UNLIMITED 358 }; 359 360 DEBUGNET_DEFINE(mlx5_en); 361 362 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 363 364 static void 365 mlx5e_update_carrier(struct mlx5e_priv *priv) 366 { 367 struct mlx5_core_dev *mdev = priv->mdev; 368 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 369 u32 eth_proto_oper; 370 int error; 371 u8 i; 372 u8 cable_type; 373 u8 port_state; 374 u8 is_er_type; 375 bool ext; 376 struct media media_entry = {}; 377 378 port_state = mlx5_query_vport_state(mdev, 379 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 380 381 if (port_state == VPORT_STATE_UP) { 382 priv->media_status_last |= IFM_ACTIVE; 383 } else { 384 priv->media_status_last &= ~IFM_ACTIVE; 385 priv->media_active_last = IFM_ETHER; 386 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 387 return; 388 } 389 390 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 391 MLX5_PTYS_EN, 1); 392 if (error) { 393 priv->media_active_last = IFM_ETHER; 394 if_setbaudrate(priv->ifp, 1); 395 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n", 396 error); 397 return; 398 } 399 400 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 401 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 402 eth_proto_oper); 403 404 i = ilog2(eth_proto_oper); 405 406 if (ext) { 407 error = mlx5_query_pddr_cable_type(mdev, 1, &cable_type); 408 if (error != 0) { 409 /* use fallback entry */ 410 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN]; 411 412 mlx5_en_err(priv->ifp, 413 "query port pddr failed: %d\n", error); 414 } else { 415 media_entry = mlx5e_ext_mode_table[i][cable_type]; 416 417 /* check if we should use fallback entry */ 418 if (media_entry.subtype == 0) 419 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN]; 420 } 421 } else { 422 media_entry = mlx5e_mode_table[i]; 423 } 424 425 if (media_entry.subtype == 0) { 426 mlx5_en_err(priv->ifp, 427 "Could not find operational media subtype\n"); 428 return; 429 } 430 431 switch (media_entry.subtype) { 432 case IFM_10G_ER: 433 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 434 if (error != 0) { 435 mlx5_en_err(priv->ifp, 436 "query port pddr failed: %d\n", error); 437 } 438 if (error != 0 || is_er_type == 0) 439 media_entry.subtype = IFM_10G_LR; 440 break; 441 case IFM_40G_LR4: 442 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 443 if (error != 0) { 444 mlx5_en_err(priv->ifp, 445 "query port pddr failed: %d\n", error); 446 } 447 if (error == 0 && is_er_type != 0) 448 media_entry.subtype = IFM_40G_ER4; 449 break; 450 } 451 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX; 452 if_setbaudrate(priv->ifp, media_entry.baudrate); 453 454 if_link_state_change(priv->ifp, LINK_STATE_UP); 455 } 456 457 static void 458 mlx5e_media_status(if_t dev, struct ifmediareq *ifmr) 459 { 460 struct mlx5e_priv *priv = if_getsoftc(dev); 461 462 ifmr->ifm_status = priv->media_status_last; 463 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last | 464 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 465 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 466 467 } 468 469 static u32 470 mlx5e_find_link_mode(u32 subtype, bool ext) 471 { 472 u32 link_mode = 0; 473 474 switch (subtype) { 475 case 0: 476 goto done; 477 case IFM_10G_LR: 478 subtype = IFM_10G_ER; 479 break; 480 case IFM_40G_ER4: 481 subtype = IFM_40G_LR4; 482 break; 483 default: 484 break; 485 } 486 487 if (ext) { 488 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) { 489 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) { 490 if (mlx5e_ext_mode_table[i][j].subtype == subtype) 491 link_mode |= MLX5E_PROT_MASK(i); 492 } 493 } 494 } else { 495 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) { 496 if (mlx5e_mode_table[i].subtype == subtype) 497 link_mode |= MLX5E_PROT_MASK(i); 498 } 499 } 500 done: 501 return (link_mode); 502 } 503 504 static int 505 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv) 506 { 507 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1, 508 priv->params.rx_pauseframe_control, 509 priv->params.tx_pauseframe_control, 510 priv->params.rx_priority_flow_control, 511 priv->params.tx_priority_flow_control)); 512 } 513 514 static int 515 mlx5e_set_port_pfc(struct mlx5e_priv *priv) 516 { 517 int error; 518 519 if (priv->gone != 0) { 520 error = -ENXIO; 521 } else if (priv->params.rx_pauseframe_control || 522 priv->params.tx_pauseframe_control) { 523 mlx5_en_err(priv->ifp, 524 "Global pauseframes must be disabled before enabling PFC.\n"); 525 error = -EINVAL; 526 } else { 527 error = mlx5e_set_port_pause_and_pfc(priv); 528 } 529 return (error); 530 } 531 532 static int 533 mlx5e_media_change(if_t dev) 534 { 535 struct mlx5e_priv *priv = if_getsoftc(dev); 536 struct mlx5_core_dev *mdev = priv->mdev; 537 u32 eth_proto_cap; 538 u32 link_mode; 539 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 540 int was_opened; 541 int locked; 542 int error; 543 bool ext; 544 545 locked = PRIV_LOCKED(priv); 546 if (!locked) 547 PRIV_LOCK(priv); 548 549 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 550 error = EINVAL; 551 goto done; 552 } 553 554 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 555 MLX5_PTYS_EN, 1); 556 if (error != 0) { 557 mlx5_en_err(dev, "Query port media capability failed\n"); 558 goto done; 559 } 560 561 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 562 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext); 563 564 /* query supported capabilities */ 565 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 566 eth_proto_capability); 567 568 /* check for autoselect */ 569 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 570 link_mode = eth_proto_cap; 571 if (link_mode == 0) { 572 mlx5_en_err(dev, "Port media capability is zero\n"); 573 error = EINVAL; 574 goto done; 575 } 576 } else { 577 link_mode = link_mode & eth_proto_cap; 578 if (link_mode == 0) { 579 mlx5_en_err(dev, "Not supported link mode requested\n"); 580 error = EINVAL; 581 goto done; 582 } 583 } 584 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 585 /* check if PFC is enabled */ 586 if (priv->params.rx_priority_flow_control || 587 priv->params.tx_priority_flow_control) { 588 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n"); 589 error = EINVAL; 590 goto done; 591 } 592 } 593 /* update pauseframe control bits */ 594 priv->params.rx_pauseframe_control = 595 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 596 priv->params.tx_pauseframe_control = 597 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 598 599 /* check if device is opened */ 600 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 601 602 /* reconfigure the hardware */ 603 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 604 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext); 605 error = -mlx5e_set_port_pause_and_pfc(priv); 606 if (was_opened) 607 mlx5_set_port_status(mdev, MLX5_PORT_UP); 608 609 done: 610 if (!locked) 611 PRIV_UNLOCK(priv); 612 return (error); 613 } 614 615 static void 616 mlx5e_update_carrier_work(struct work_struct *work) 617 { 618 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 619 update_carrier_work); 620 621 PRIV_LOCK(priv); 622 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 623 mlx5e_update_carrier(priv); 624 PRIV_UNLOCK(priv); 625 } 626 627 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \ 628 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c); 629 630 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \ 631 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c); 632 633 static void 634 mlx5e_update_pcie_counters(struct mlx5e_priv *priv) 635 { 636 struct mlx5_core_dev *mdev = priv->mdev; 637 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 638 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 639 void *out; 640 void *in; 641 int err; 642 643 /* allocate firmware request structures */ 644 in = mlx5_vzalloc(sz); 645 out = mlx5_vzalloc(sz); 646 if (in == NULL || out == NULL) 647 goto free_out; 648 649 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 650 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 651 if (err != 0) 652 goto free_out; 653 654 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64) 655 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 656 657 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP); 658 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 659 if (err != 0) 660 goto free_out; 661 662 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 663 664 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP); 665 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 666 if (err != 0) 667 goto free_out; 668 669 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 670 671 free_out: 672 /* free firmware request structures */ 673 kvfree(in); 674 kvfree(out); 675 } 676 677 /* 678 * This function reads the physical port counters from the firmware 679 * using a pre-defined layout defined by various MLX5E_PPORT_XXX() 680 * macros. The output is converted from big-endian 64-bit values into 681 * host endian ones and stored in the "priv->stats.pport" structure. 682 */ 683 static void 684 mlx5e_update_pport_counters(struct mlx5e_priv *priv) 685 { 686 struct mlx5_core_dev *mdev = priv->mdev; 687 struct mlx5e_pport_stats *s = &priv->stats.pport; 688 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 689 u32 *in; 690 u32 *out; 691 const u64 *ptr; 692 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 693 unsigned x; 694 unsigned y; 695 unsigned z; 696 697 /* allocate firmware request structures */ 698 in = mlx5_vzalloc(sz); 699 out = mlx5_vzalloc(sz); 700 if (in == NULL || out == NULL) 701 goto free_out; 702 703 /* 704 * Get pointer to the 64-bit counter set which is located at a 705 * fixed offset in the output firmware request structure: 706 */ 707 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 708 709 MLX5_SET(ppcnt_reg, in, local_port, 1); 710 711 /* read IEEE802_3 counter group using predefined counter layout */ 712 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 713 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 714 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM; 715 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 716 s->arg[y] = be64toh(ptr[x]); 717 718 /* read RFC2819 counter group using predefined counter layout */ 719 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 720 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 721 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 722 s->arg[y] = be64toh(ptr[x]); 723 724 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 725 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 726 s_debug->arg[y] = be64toh(ptr[x]); 727 728 /* read RFC2863 counter group using predefined counter layout */ 729 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 730 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 731 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 732 s_debug->arg[y] = be64toh(ptr[x]); 733 734 /* read physical layer stats counter group using predefined counter layout */ 735 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 736 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 737 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 738 s_debug->arg[y] = be64toh(ptr[x]); 739 740 /* read Extended Ethernet counter group using predefined counter layout */ 741 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 742 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 743 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++) 744 s_debug->arg[y] = be64toh(ptr[x]); 745 746 /* read Extended Statistical Group */ 747 if (MLX5_CAP_GEN(mdev, pcam_reg) && 748 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) && 749 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) { 750 /* read Extended Statistical counter group using predefined counter layout */ 751 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 752 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 753 754 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++) 755 s_debug->arg[y] = be64toh(ptr[x]); 756 } 757 758 /* read PCIE counters */ 759 mlx5e_update_pcie_counters(priv); 760 761 /* read per-priority counters */ 762 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 763 764 /* iterate all the priorities */ 765 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) { 766 MLX5_SET(ppcnt_reg, in, prio_tc, z); 767 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 768 769 /* read per priority stats counter group using predefined counter layout */ 770 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM / 771 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++) 772 s->arg[y] = be64toh(ptr[x]); 773 } 774 775 free_out: 776 /* free firmware request structures */ 777 kvfree(in); 778 kvfree(out); 779 } 780 781 static void 782 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 783 { 784 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {}; 785 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; 786 787 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 788 return; 789 790 MLX5_SET(query_vnic_env_in, in, opcode, 791 MLX5_CMD_OP_QUERY_VNIC_ENV); 792 MLX5_SET(query_vnic_env_in, in, op_mod, 0); 793 MLX5_SET(query_vnic_env_in, in, other_vport, 0); 794 795 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0) 796 return; 797 798 priv->stats.vport.rx_steer_missed_packets = 799 MLX5_GET64(query_vnic_env_out, out, 800 vport_env.nic_receive_steering_discard); 801 } 802 803 /* 804 * This function is called regularly to collect all statistics 805 * counters from the firmware. The values can be viewed through the 806 * sysctl interface. Execution is serialized using the priv's global 807 * configuration lock. 808 */ 809 static void 810 mlx5e_update_stats_locked(struct mlx5e_priv *priv) 811 { 812 struct mlx5_core_dev *mdev = priv->mdev; 813 struct mlx5e_vport_stats *s = &priv->stats.vport; 814 struct mlx5e_sq_stats *sq_stats; 815 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 816 u32 *out; 817 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 818 u64 tso_packets = 0; 819 u64 tso_bytes = 0; 820 u64 tx_queue_dropped = 0; 821 u64 tx_defragged = 0; 822 u64 tx_offload_none = 0; 823 u64 lro_packets = 0; 824 u64 lro_bytes = 0; 825 u64 sw_lro_queued = 0; 826 u64 sw_lro_flushed = 0; 827 u64 rx_csum_none = 0; 828 u64 rx_wqe_err = 0; 829 u64 rx_packets = 0; 830 u64 rx_bytes = 0; 831 u64 rx_decrypted_error = 0; 832 u64 rx_decrypted_ok = 0; 833 u32 rx_out_of_buffer = 0; 834 int error; 835 int i; 836 int j; 837 838 out = mlx5_vzalloc(outlen); 839 if (out == NULL) 840 goto free_out; 841 842 /* Collect firts the SW counters and then HW for consistency */ 843 for (i = 0; i < priv->params.num_channels; i++) { 844 struct mlx5e_channel *pch = priv->channel + i; 845 struct mlx5e_rq *rq = &pch->rq; 846 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats; 847 848 /* collect stats from LRO */ 849 rq_stats->sw_lro_queued = rq->lro.lro_queued; 850 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 851 sw_lro_queued += rq_stats->sw_lro_queued; 852 sw_lro_flushed += rq_stats->sw_lro_flushed; 853 lro_packets += rq_stats->lro_packets; 854 lro_bytes += rq_stats->lro_bytes; 855 rx_csum_none += rq_stats->csum_none; 856 rx_wqe_err += rq_stats->wqe_err; 857 rx_packets += rq_stats->packets; 858 rx_bytes += rq_stats->bytes; 859 rx_decrypted_error += rq_stats->decrypted_error_packets; 860 rx_decrypted_ok += rq_stats->decrypted_ok_packets; 861 862 for (j = 0; j < priv->num_tc; j++) { 863 sq_stats = &pch->sq[j].stats; 864 865 tso_packets += sq_stats->tso_packets; 866 tso_bytes += sq_stats->tso_bytes; 867 tx_queue_dropped += sq_stats->dropped; 868 tx_queue_dropped += sq_stats->enobuf; 869 tx_defragged += sq_stats->defragged; 870 tx_offload_none += sq_stats->csum_offload_none; 871 } 872 } 873 874 #ifdef RATELIMIT 875 /* Collect statistics from all rate-limit queues */ 876 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) { 877 struct mlx5e_rl_worker *rlw = priv->rl.workers + j; 878 879 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) { 880 struct mlx5e_rl_channel *channel = rlw->channels + i; 881 struct mlx5e_sq *sq = channel->sq; 882 883 if (sq == NULL) 884 continue; 885 886 sq_stats = &sq->stats; 887 888 tso_packets += sq_stats->tso_packets; 889 tso_bytes += sq_stats->tso_bytes; 890 tx_queue_dropped += sq_stats->dropped; 891 tx_queue_dropped += sq_stats->enobuf; 892 tx_defragged += sq_stats->defragged; 893 tx_offload_none += sq_stats->csum_offload_none; 894 } 895 } 896 #endif 897 898 /* update counters */ 899 s->tso_packets = tso_packets; 900 s->tso_bytes = tso_bytes; 901 s->tx_queue_dropped = tx_queue_dropped; 902 s->tx_defragged = tx_defragged; 903 s->lro_packets = lro_packets; 904 s->lro_bytes = lro_bytes; 905 s->sw_lro_queued = sw_lro_queued; 906 s->sw_lro_flushed = sw_lro_flushed; 907 s->rx_csum_none = rx_csum_none; 908 s->rx_wqe_err = rx_wqe_err; 909 s->rx_packets = rx_packets; 910 s->rx_bytes = rx_bytes; 911 s->rx_decrypted_error_packets = rx_decrypted_error; 912 s->rx_decrypted_ok_packets = rx_decrypted_ok; 913 914 mlx5e_grp_vnic_env_update_stats(priv); 915 916 /* HW counters */ 917 memset(in, 0, sizeof(in)); 918 919 MLX5_SET(query_vport_counter_in, in, opcode, 920 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 921 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 922 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 923 924 memset(out, 0, outlen); 925 926 /* get number of out-of-buffer drops first */ 927 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 928 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 929 &rx_out_of_buffer) == 0) { 930 s->rx_out_of_buffer = rx_out_of_buffer; 931 } 932 933 /* get port statistics */ 934 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) { 935 #define MLX5_GET_CTR(out, x) \ 936 MLX5_GET64(query_vport_counter_out, out, x) 937 938 s->rx_error_packets = 939 MLX5_GET_CTR(out, received_errors.packets); 940 s->rx_error_bytes = 941 MLX5_GET_CTR(out, received_errors.octets); 942 s->tx_error_packets = 943 MLX5_GET_CTR(out, transmit_errors.packets); 944 s->tx_error_bytes = 945 MLX5_GET_CTR(out, transmit_errors.octets); 946 947 s->rx_unicast_packets = 948 MLX5_GET_CTR(out, received_eth_unicast.packets); 949 s->rx_unicast_bytes = 950 MLX5_GET_CTR(out, received_eth_unicast.octets); 951 s->tx_unicast_packets = 952 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 953 s->tx_unicast_bytes = 954 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 955 956 s->rx_multicast_packets = 957 MLX5_GET_CTR(out, received_eth_multicast.packets); 958 s->rx_multicast_bytes = 959 MLX5_GET_CTR(out, received_eth_multicast.octets); 960 s->tx_multicast_packets = 961 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 962 s->tx_multicast_bytes = 963 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 964 965 s->rx_broadcast_packets = 966 MLX5_GET_CTR(out, received_eth_broadcast.packets); 967 s->rx_broadcast_bytes = 968 MLX5_GET_CTR(out, received_eth_broadcast.octets); 969 s->tx_broadcast_packets = 970 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 971 s->tx_broadcast_bytes = 972 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 973 974 s->tx_packets = s->tx_unicast_packets + 975 s->tx_multicast_packets + s->tx_broadcast_packets; 976 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes + 977 s->tx_broadcast_bytes; 978 979 /* Update calculated offload counters */ 980 s->tx_csum_offload = s->tx_packets - tx_offload_none; 981 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 982 } 983 984 /* Get physical port counters */ 985 mlx5e_update_pport_counters(priv); 986 987 s->tx_jumbo_packets = 988 priv->stats.port_stats_debug.tx_stat_p1519to2047octets + 989 priv->stats.port_stats_debug.tx_stat_p2048to4095octets + 990 priv->stats.port_stats_debug.tx_stat_p4096to8191octets + 991 priv->stats.port_stats_debug.tx_stat_p8192to10239octets; 992 993 free_out: 994 kvfree(out); 995 996 /* Update diagnostics, if any */ 997 if (priv->params_ethtool.diag_pci_enable || 998 priv->params_ethtool.diag_general_enable) { 999 error = mlx5_core_get_diagnostics_full(mdev, 1000 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL, 1001 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL); 1002 if (error != 0) 1003 mlx5_en_err(priv->ifp, 1004 "Failed reading diagnostics: %d\n", error); 1005 } 1006 1007 /* Update FEC, if any */ 1008 error = mlx5e_fec_update(priv); 1009 if (error != 0 && error != EOPNOTSUPP) { 1010 mlx5_en_err(priv->ifp, 1011 "Updating FEC failed: %d\n", error); 1012 } 1013 1014 /* Update temperature, if any */ 1015 if (priv->params_ethtool.hw_num_temp != 0) { 1016 error = mlx5e_hw_temperature_update(priv); 1017 if (error != 0 && error != EOPNOTSUPP) { 1018 mlx5_en_err(priv->ifp, 1019 "Updating temperature failed: %d\n", error); 1020 } 1021 } 1022 } 1023 1024 static void 1025 mlx5e_update_stats_work(struct work_struct *work) 1026 { 1027 struct mlx5e_priv *priv; 1028 1029 priv = container_of(work, struct mlx5e_priv, update_stats_work); 1030 PRIV_LOCK(priv); 1031 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 1032 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state)) 1033 mlx5e_update_stats_locked(priv); 1034 PRIV_UNLOCK(priv); 1035 } 1036 1037 static void 1038 mlx5e_update_stats(void *arg) 1039 { 1040 struct mlx5e_priv *priv = arg; 1041 1042 queue_work(priv->wq, &priv->update_stats_work); 1043 1044 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv); 1045 } 1046 1047 static void 1048 mlx5e_async_event_sub(struct mlx5e_priv *priv, 1049 enum mlx5_dev_event event) 1050 { 1051 switch (event) { 1052 case MLX5_DEV_EVENT_PORT_UP: 1053 case MLX5_DEV_EVENT_PORT_DOWN: 1054 queue_work(priv->wq, &priv->update_carrier_work); 1055 break; 1056 1057 default: 1058 break; 1059 } 1060 } 1061 1062 static void 1063 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 1064 enum mlx5_dev_event event, unsigned long param) 1065 { 1066 struct mlx5e_priv *priv = vpriv; 1067 1068 mtx_lock(&priv->async_events_mtx); 1069 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 1070 mlx5e_async_event_sub(priv, event); 1071 mtx_unlock(&priv->async_events_mtx); 1072 } 1073 1074 static void 1075 mlx5e_enable_async_events(struct mlx5e_priv *priv) 1076 { 1077 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1078 } 1079 1080 static void 1081 mlx5e_disable_async_events(struct mlx5e_priv *priv) 1082 { 1083 mtx_lock(&priv->async_events_mtx); 1084 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1085 mtx_unlock(&priv->async_events_mtx); 1086 } 1087 1088 static void mlx5e_calibration_callout(void *arg); 1089 static int mlx5e_calibration_duration = 20; 1090 static int mlx5e_fast_calibration = 1; 1091 static int mlx5e_normal_calibration = 30; 1092 1093 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1094 "MLX5 timestamp calibration parameters"); 1095 1096 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN, 1097 &mlx5e_calibration_duration, 0, 1098 "Duration of initial calibration"); 1099 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN, 1100 &mlx5e_fast_calibration, 0, 1101 "Recalibration interval during initial calibration"); 1102 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN, 1103 &mlx5e_normal_calibration, 0, 1104 "Recalibration interval during normal operations"); 1105 1106 /* 1107 * Ignites the calibration process. 1108 */ 1109 static void 1110 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv) 1111 { 1112 1113 if (priv->clbr_done == 0) 1114 mlx5e_calibration_callout(priv); 1115 else 1116 callout_reset_sbt_curcpu(&priv->tstmp_clbr, (priv->clbr_done < 1117 mlx5e_calibration_duration ? mlx5e_fast_calibration : 1118 mlx5e_normal_calibration) * SBT_1S, 0, 1119 mlx5e_calibration_callout, priv, C_DIRECT_EXEC); 1120 } 1121 1122 static uint64_t 1123 mlx5e_timespec2usec(const struct timespec *ts) 1124 { 1125 1126 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec); 1127 } 1128 1129 static uint64_t 1130 mlx5e_hw_clock(struct mlx5e_priv *priv) 1131 { 1132 struct mlx5_init_seg *iseg; 1133 uint32_t hw_h, hw_h1, hw_l; 1134 1135 iseg = priv->mdev->iseg; 1136 do { 1137 hw_h = ioread32be(&iseg->internal_timer_h); 1138 hw_l = ioread32be(&iseg->internal_timer_l); 1139 hw_h1 = ioread32be(&iseg->internal_timer_h); 1140 } while (hw_h1 != hw_h); 1141 return (((uint64_t)hw_h << 32) | hw_l); 1142 } 1143 1144 /* 1145 * The calibration callout, it runs either in the context of the 1146 * thread which enables calibration, or in callout. It takes the 1147 * snapshot of system and adapter clocks, then advances the pointers to 1148 * the calibration point to allow rx path to read the consistent data 1149 * lockless. 1150 */ 1151 static void 1152 mlx5e_calibration_callout(void *arg) 1153 { 1154 struct mlx5e_priv *priv; 1155 struct mlx5e_clbr_point *next, *curr; 1156 struct timespec ts; 1157 int clbr_curr_next; 1158 1159 priv = arg; 1160 curr = &priv->clbr_points[priv->clbr_curr]; 1161 clbr_curr_next = priv->clbr_curr + 1; 1162 if (clbr_curr_next >= nitems(priv->clbr_points)) 1163 clbr_curr_next = 0; 1164 next = &priv->clbr_points[clbr_curr_next]; 1165 1166 next->base_prev = curr->base_curr; 1167 next->clbr_hw_prev = curr->clbr_hw_curr; 1168 1169 next->clbr_hw_curr = mlx5e_hw_clock(priv); 1170 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) == 1171 0) { 1172 if (priv->clbr_done != 0) { 1173 mlx5_en_err(priv->ifp, 1174 "HW failed tstmp frozen %#jx %#jx, disabling\n", 1175 next->clbr_hw_curr, curr->clbr_hw_prev); 1176 priv->clbr_done = 0; 1177 } 1178 atomic_store_rel_int(&curr->clbr_gen, 0); 1179 return; 1180 } 1181 1182 nanouptime(&ts); 1183 next->base_curr = mlx5e_timespec2usec(&ts); 1184 1185 curr->clbr_gen = 0; 1186 atomic_thread_fence_rel(); 1187 priv->clbr_curr = clbr_curr_next; 1188 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen)); 1189 1190 if (priv->clbr_done < mlx5e_calibration_duration) 1191 priv->clbr_done++; 1192 mlx5e_reset_calibration_callout(priv); 1193 } 1194 1195 static const char *mlx5e_rq_stats_desc[] = { 1196 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 1197 }; 1198 1199 static int 1200 mlx5e_create_rq(struct mlx5e_channel *c, 1201 struct mlx5e_rq_param *param, 1202 struct mlx5e_rq *rq) 1203 { 1204 struct mlx5e_priv *priv = c->priv; 1205 struct mlx5_core_dev *mdev = priv->mdev; 1206 char buffer[16]; 1207 void *rqc = param->rqc; 1208 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 1209 int wq_sz; 1210 int err; 1211 int i; 1212 u32 nsegs, wqe_sz; 1213 1214 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 1215 if (err != 0) 1216 goto done; 1217 1218 /* Create DMA descriptor TAG */ 1219 if ((err = -bus_dma_tag_create( 1220 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1221 1, /* any alignment */ 1222 0, /* no boundary */ 1223 BUS_SPACE_MAXADDR, /* lowaddr */ 1224 BUS_SPACE_MAXADDR, /* highaddr */ 1225 NULL, NULL, /* filter, filterarg */ 1226 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */ 1227 nsegs, /* nsegments */ 1228 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */ 1229 0, /* flags */ 1230 NULL, NULL, /* lockfunc, lockfuncarg */ 1231 &rq->dma_tag))) 1232 goto done; 1233 1234 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 1235 &rq->wq_ctrl); 1236 if (err) 1237 goto err_free_dma_tag; 1238 1239 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 1240 1241 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs); 1242 if (err != 0) 1243 goto err_rq_wq_destroy; 1244 1245 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1246 1247 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz); 1248 if (err) 1249 goto err_rq_wq_destroy; 1250 1251 rq->mbuf = malloc_domainset(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, 1252 mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO); 1253 for (i = 0; i != wq_sz; i++) { 1254 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 1255 int j; 1256 1257 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 1258 if (err != 0) { 1259 while (i--) 1260 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1261 goto err_rq_mbuf_free; 1262 } 1263 1264 /* set value for constant fields */ 1265 for (j = 0; j < rq->nsegs; j++) 1266 wqe->data[j].lkey = cpu_to_be32(priv->mr.key); 1267 } 1268 1269 INIT_WORK(&rq->dim.work, mlx5e_dim_work); 1270 if (priv->params.rx_cq_moderation_mode < 2) { 1271 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1272 } else { 1273 void *cqc = container_of(param, 1274 struct mlx5e_channel_param, rq)->rx_cq.cqc; 1275 1276 switch (MLX5_GET(cqc, cqc, cq_period_mode)) { 1277 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 1278 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 1279 break; 1280 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 1281 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1282 break; 1283 default: 1284 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1285 break; 1286 } 1287 } 1288 1289 rq->ifp = priv->ifp; 1290 rq->channel = c; 1291 rq->ix = c->ix; 1292 1293 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 1294 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1295 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 1296 rq->stats.arg); 1297 return (0); 1298 1299 err_rq_mbuf_free: 1300 free(rq->mbuf, M_MLX5EN); 1301 tcp_lro_free(&rq->lro); 1302 err_rq_wq_destroy: 1303 mlx5_wq_destroy(&rq->wq_ctrl); 1304 err_free_dma_tag: 1305 bus_dma_tag_destroy(rq->dma_tag); 1306 done: 1307 return (err); 1308 } 1309 1310 static void 1311 mlx5e_destroy_rq(struct mlx5e_rq *rq) 1312 { 1313 int wq_sz; 1314 int i; 1315 1316 /* destroy all sysctl nodes */ 1317 sysctl_ctx_free(&rq->stats.ctx); 1318 1319 /* free leftover LRO packets, if any */ 1320 tcp_lro_free(&rq->lro); 1321 1322 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1323 for (i = 0; i != wq_sz; i++) { 1324 if (rq->mbuf[i].mbuf != NULL) { 1325 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map); 1326 m_freem(rq->mbuf[i].mbuf); 1327 } 1328 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1329 } 1330 free(rq->mbuf, M_MLX5EN); 1331 mlx5_wq_destroy(&rq->wq_ctrl); 1332 bus_dma_tag_destroy(rq->dma_tag); 1333 } 1334 1335 static int 1336 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 1337 { 1338 struct mlx5e_channel *c = rq->channel; 1339 struct mlx5e_priv *priv = c->priv; 1340 struct mlx5_core_dev *mdev = priv->mdev; 1341 void *in; 1342 void *rqc; 1343 void *wq; 1344 int inlen; 1345 int err; 1346 u8 ts_format; 1347 1348 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1349 sizeof(u64) * rq->wq_ctrl.buf.npages; 1350 in = mlx5_vzalloc(inlen); 1351 if (in == NULL) 1352 return (-ENOMEM); 1353 1354 ts_format = mlx5_get_rq_default_ts(mdev); 1355 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1356 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1357 1358 memcpy(rqc, param->rqc, sizeof(param->rqc)); 1359 1360 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1361 MLX5_SET(rqc, rqc, ts_format, ts_format); 1362 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1363 if (priv->counter_set_id >= 0) 1364 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 1365 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 1366 MLX5_ADAPTER_PAGE_SHIFT); 1367 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 1368 1369 mlx5_fill_page_array(&rq->wq_ctrl.buf, 1370 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1371 1372 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 1373 1374 kvfree(in); 1375 1376 return (err); 1377 } 1378 1379 static int 1380 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 1381 { 1382 struct mlx5e_channel *c = rq->channel; 1383 struct mlx5e_priv *priv = c->priv; 1384 struct mlx5_core_dev *mdev = priv->mdev; 1385 1386 void *in; 1387 void *rqc; 1388 int inlen; 1389 int err; 1390 1391 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1392 in = mlx5_vzalloc(inlen); 1393 if (in == NULL) 1394 return (-ENOMEM); 1395 1396 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1397 1398 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 1399 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 1400 MLX5_SET(rqc, rqc, state, next_state); 1401 1402 err = mlx5_core_modify_rq(mdev, in, inlen); 1403 1404 kvfree(in); 1405 1406 return (err); 1407 } 1408 1409 static void 1410 mlx5e_disable_rq(struct mlx5e_rq *rq) 1411 { 1412 struct mlx5e_channel *c = rq->channel; 1413 struct mlx5e_priv *priv = c->priv; 1414 struct mlx5_core_dev *mdev = priv->mdev; 1415 1416 mlx5_core_destroy_rq(mdev, rq->rqn); 1417 } 1418 1419 static int 1420 mlx5e_open_rq(struct mlx5e_channel *c, 1421 struct mlx5e_rq_param *param, 1422 struct mlx5e_rq *rq) 1423 { 1424 int err; 1425 1426 err = mlx5e_create_rq(c, param, rq); 1427 if (err) 1428 return (err); 1429 1430 /* set CQN in RQ parameters */ 1431 MLX5_SET(rqc, param->rqc, cqn, c->rq.cq.mcq.cqn); 1432 1433 err = mlx5e_enable_rq(rq, param); 1434 if (err) 1435 goto err_destroy_rq; 1436 1437 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1438 if (err) 1439 goto err_disable_rq; 1440 1441 c->rq.enabled = 1; 1442 1443 return (0); 1444 1445 err_disable_rq: 1446 mlx5e_disable_rq(rq); 1447 err_destroy_rq: 1448 mlx5e_destroy_rq(rq); 1449 1450 return (err); 1451 } 1452 1453 static void 1454 mlx5e_close_rq(struct mlx5e_rq *rq) 1455 { 1456 mtx_lock(&rq->mtx); 1457 rq->enabled = 0; 1458 callout_stop(&rq->watchdog); 1459 mtx_unlock(&rq->mtx); 1460 1461 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1462 } 1463 1464 static void 1465 mlx5e_close_rq_wait(struct mlx5e_rq *rq) 1466 { 1467 1468 mlx5e_disable_rq(rq); 1469 mlx5e_close_cq(&rq->cq); 1470 cancel_work_sync(&rq->dim.work); 1471 mlx5e_destroy_rq(rq); 1472 } 1473 1474 /* 1475 * What is a drop RQ and why is it needed? 1476 * 1477 * The RSS indirection table, also called the RQT, selects the 1478 * destination RQ based on the receive queue number, RQN. The RQT is 1479 * frequently referred to by flow steering rules to distribute traffic 1480 * among multiple RQs. The problem is that the RQs cannot be destroyed 1481 * before the RQT referring them is destroyed too. Further, TLS RX 1482 * rules may still be referring to the RQT even if the link went 1483 * down. Because there is no magic RQN for dropping packets, we create 1484 * a dummy RQ, also called drop RQ, which sole purpose is to drop all 1485 * received packets. When the link goes down this RQN is filled in all 1486 * RQT entries, of the main RQT, so the real RQs which are about to be 1487 * destroyed can be released and the TLS RX rules can be sustained. 1488 */ 1489 static void 1490 mlx5e_open_drop_rq_comp(struct mlx5_core_cq *mcq __unused, struct mlx5_eqe *eqe __unused) 1491 { 1492 } 1493 1494 static int 1495 mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1496 struct mlx5e_rq *drop_rq) 1497 { 1498 struct mlx5e_cq_param param_cq = {}; 1499 struct mlx5e_rq_param param_rq = {}; 1500 void *rqc_wq = MLX5_ADDR_OF(rqc, param_rq.rqc, wq); 1501 int err; 1502 1503 /* set channel pointer */ 1504 drop_rq->channel = priv->channel; 1505 1506 /* set basic CQ parameters needed */ 1507 MLX5_SET(cqc, param_cq.cqc, log_cq_size, 0); 1508 MLX5_SET(cqc, param_cq.cqc, uar_page, priv->mdev->priv.uar->index); 1509 1510 /* open receive completion queue */ 1511 err = mlx5e_open_cq(priv, ¶m_cq, &drop_rq->cq, 1512 &mlx5e_open_drop_rq_comp, 0); 1513 if (err) 1514 goto err_done; 1515 1516 /* set basic WQ parameters needed */ 1517 MLX5_SET(wq, rqc_wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 1518 MLX5_SET(wq, rqc_wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1519 MLX5_SET(wq, rqc_wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + sizeof(struct mlx5_wqe_data_seg))); 1520 MLX5_SET(wq, rqc_wq, log_wq_sz, 0); 1521 MLX5_SET(wq, rqc_wq, pd, priv->pdn); 1522 1523 param_rq.wq.linear = 1; 1524 1525 err = mlx5_wq_ll_create(priv->mdev, ¶m_rq.wq, rqc_wq, &drop_rq->wq, 1526 &drop_rq->wq_ctrl); 1527 if (err) 1528 goto err_close_cq; 1529 1530 /* set CQN in RQ parameters */ 1531 MLX5_SET(rqc, param_rq.rqc, cqn, drop_rq->cq.mcq.cqn); 1532 1533 err = mlx5e_enable_rq(drop_rq, ¶m_rq); 1534 if (err) 1535 goto err_wq_destroy; 1536 1537 err = mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1538 if (err) 1539 goto err_disable_rq; 1540 1541 return (err); 1542 1543 err_disable_rq: 1544 mlx5e_disable_rq(drop_rq); 1545 err_wq_destroy: 1546 mlx5_wq_destroy(&drop_rq->wq_ctrl); 1547 err_close_cq: 1548 mlx5e_close_cq(&drop_rq->cq); 1549 err_done: 1550 return (err); 1551 } 1552 1553 static void 1554 mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) 1555 { 1556 mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1557 mlx5e_disable_rq(drop_rq); 1558 mlx5_wq_destroy(&drop_rq->wq_ctrl); 1559 mlx5e_close_cq(&drop_rq->cq); 1560 } 1561 1562 void 1563 mlx5e_free_sq_db(struct mlx5e_sq *sq) 1564 { 1565 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1566 int x; 1567 1568 for (x = 0; x != wq_sz; x++) { 1569 if (sq->mbuf[x].mbuf != NULL) { 1570 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map); 1571 m_freem(sq->mbuf[x].mbuf); 1572 } 1573 if (sq->mbuf[x].mst != NULL) { 1574 m_snd_tag_rele(sq->mbuf[x].mst); 1575 sq->mbuf[x].mst = NULL; 1576 } 1577 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1578 } 1579 free(sq->mbuf, M_MLX5EN); 1580 } 1581 1582 int 1583 mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 1584 { 1585 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1586 int err; 1587 int x; 1588 1589 sq->mbuf = malloc_domainset(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, 1590 mlx5_dev_domainset(sq->priv->mdev), M_WAITOK | M_ZERO); 1591 1592 /* Create DMA descriptor MAPs */ 1593 for (x = 0; x != wq_sz; x++) { 1594 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 1595 if (err != 0) { 1596 while (x--) 1597 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1598 free(sq->mbuf, M_MLX5EN); 1599 return (err); 1600 } 1601 } 1602 return (0); 1603 } 1604 1605 static const char *mlx5e_sq_stats_desc[] = { 1606 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 1607 }; 1608 1609 void 1610 mlx5e_update_sq_inline(struct mlx5e_sq *sq) 1611 { 1612 sq->max_inline = sq->priv->params.tx_max_inline; 1613 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode; 1614 1615 /* 1616 * Check if trust state is DSCP or if inline mode is NONE which 1617 * indicates CX-5 or newer hardware. 1618 */ 1619 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP || 1620 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) { 1621 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert)) 1622 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN; 1623 else 1624 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN; 1625 } else { 1626 sq->min_insert_caps = 0; 1627 } 1628 } 1629 1630 static void 1631 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1632 { 1633 int i; 1634 1635 for (i = 0; i != priv->num_tc; i++) { 1636 mtx_lock(&c->sq[i].lock); 1637 mlx5e_update_sq_inline(&c->sq[i]); 1638 mtx_unlock(&c->sq[i].lock); 1639 } 1640 } 1641 1642 void 1643 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv) 1644 { 1645 int i; 1646 1647 /* check if channels are closed */ 1648 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 1649 return; 1650 1651 for (i = 0; i < priv->params.num_channels; i++) 1652 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]); 1653 } 1654 1655 static int 1656 mlx5e_create_sq(struct mlx5e_channel *c, 1657 int tc, 1658 struct mlx5e_sq_param *param, 1659 struct mlx5e_sq *sq) 1660 { 1661 struct mlx5e_priv *priv = c->priv; 1662 struct mlx5_core_dev *mdev = priv->mdev; 1663 char buffer[16]; 1664 void *sqc = param->sqc; 1665 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 1666 int err; 1667 1668 /* Create DMA descriptor TAG */ 1669 if ((err = -bus_dma_tag_create( 1670 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1671 1, /* any alignment */ 1672 0, /* no boundary */ 1673 BUS_SPACE_MAXADDR, /* lowaddr */ 1674 BUS_SPACE_MAXADDR, /* highaddr */ 1675 NULL, NULL, /* filter, filterarg */ 1676 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 1677 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 1678 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 1679 0, /* flags */ 1680 NULL, NULL, /* lockfunc, lockfuncarg */ 1681 &sq->dma_tag))) 1682 goto done; 1683 1684 sq->mkey_be = cpu_to_be32(priv->mr.key); 1685 sq->ifp = priv->ifp; 1686 sq->priv = priv; 1687 sq->tc = tc; 1688 1689 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 1690 &sq->wq_ctrl); 1691 if (err) 1692 goto err_free_dma_tag; 1693 1694 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 1695 1696 err = mlx5e_alloc_sq_db(sq); 1697 if (err) 1698 goto err_sq_wq_destroy; 1699 1700 mlx5e_update_sq_inline(sq); 1701 1702 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1703 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1704 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1705 sq->stats.arg); 1706 1707 return (0); 1708 1709 err_sq_wq_destroy: 1710 mlx5_wq_destroy(&sq->wq_ctrl); 1711 1712 err_free_dma_tag: 1713 bus_dma_tag_destroy(sq->dma_tag); 1714 done: 1715 return (err); 1716 } 1717 1718 static void 1719 mlx5e_destroy_sq(struct mlx5e_sq *sq) 1720 { 1721 /* destroy all sysctl nodes */ 1722 sysctl_ctx_free(&sq->stats.ctx); 1723 1724 mlx5e_free_sq_db(sq); 1725 mlx5_wq_destroy(&sq->wq_ctrl); 1726 bus_dma_tag_destroy(sq->dma_tag); 1727 } 1728 1729 int 1730 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1731 const struct mlx5_sq_bfreg *bfreg, int tis_num) 1732 { 1733 void *in; 1734 void *sqc; 1735 void *wq; 1736 int inlen; 1737 int err; 1738 u8 ts_format; 1739 1740 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1741 sizeof(u64) * sq->wq_ctrl.buf.npages; 1742 in = mlx5_vzalloc(inlen); 1743 if (in == NULL) 1744 return (-ENOMEM); 1745 1746 sq->uar_map = bfreg->map; 1747 1748 ts_format = mlx5_get_sq_default_ts(sq->priv->mdev); 1749 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1750 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1751 1752 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1753 1754 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1755 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1756 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1757 MLX5_SET(sqc, sqc, ts_format, ts_format); 1758 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1759 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1760 MLX5_SET(sqc, sqc, allow_swp, 1); 1761 1762 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1763 MLX5_SET(wq, wq, uar_page, bfreg->index); 1764 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1765 MLX5_ADAPTER_PAGE_SHIFT); 1766 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1767 1768 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1769 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1770 1771 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1772 1773 kvfree(in); 1774 1775 return (err); 1776 } 1777 1778 int 1779 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1780 { 1781 void *in; 1782 void *sqc; 1783 int inlen; 1784 int err; 1785 1786 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1787 in = mlx5_vzalloc(inlen); 1788 if (in == NULL) 1789 return (-ENOMEM); 1790 1791 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1792 1793 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1794 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1795 MLX5_SET(sqc, sqc, state, next_state); 1796 1797 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1798 1799 kvfree(in); 1800 1801 return (err); 1802 } 1803 1804 void 1805 mlx5e_disable_sq(struct mlx5e_sq *sq) 1806 { 1807 1808 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1809 } 1810 1811 static int 1812 mlx5e_open_sq(struct mlx5e_channel *c, 1813 int tc, 1814 struct mlx5e_sq_param *param, 1815 struct mlx5e_sq *sq) 1816 { 1817 int err; 1818 1819 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1820 1821 /* ensure the TX completion event factor is not zero */ 1822 if (sq->cev_factor == 0) 1823 sq->cev_factor = 1; 1824 1825 err = mlx5e_create_sq(c, tc, param, sq); 1826 if (err) 1827 return (err); 1828 1829 err = mlx5e_enable_sq(sq, param, &c->bfreg, c->priv->tisn[tc]); 1830 if (err) 1831 goto err_destroy_sq; 1832 1833 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1834 if (err) 1835 goto err_disable_sq; 1836 1837 WRITE_ONCE(sq->running, 1); 1838 1839 return (0); 1840 1841 err_disable_sq: 1842 mlx5e_disable_sq(sq); 1843 err_destroy_sq: 1844 mlx5e_destroy_sq(sq); 1845 1846 return (err); 1847 } 1848 1849 static void 1850 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1851 { 1852 /* fill up remainder with NOPs */ 1853 while (sq->cev_counter != 0) { 1854 while (!mlx5e_sq_has_room_for(sq, 1)) { 1855 if (can_sleep != 0) { 1856 mtx_unlock(&sq->lock); 1857 msleep(4); 1858 mtx_lock(&sq->lock); 1859 } else { 1860 goto done; 1861 } 1862 } 1863 /* send a single NOP */ 1864 mlx5e_send_nop(sq, 1); 1865 atomic_thread_fence_rel(); 1866 } 1867 done: 1868 mlx5e_tx_notify_hw(sq, false); 1869 } 1870 1871 void 1872 mlx5e_sq_cev_timeout(void *arg) 1873 { 1874 struct mlx5e_sq *sq = arg; 1875 1876 mtx_assert(&sq->lock, MA_OWNED); 1877 1878 /* check next state */ 1879 switch (sq->cev_next_state) { 1880 case MLX5E_CEV_STATE_SEND_NOPS: 1881 /* fill TX ring with NOPs, if any */ 1882 mlx5e_sq_send_nops_locked(sq, 0); 1883 1884 /* check if completed */ 1885 if (sq->cev_counter == 0) { 1886 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1887 return; 1888 } 1889 break; 1890 default: 1891 /* send NOPs on next timeout */ 1892 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1893 break; 1894 } 1895 1896 /* restart timer */ 1897 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1898 } 1899 1900 void 1901 mlx5e_drain_sq(struct mlx5e_sq *sq) 1902 { 1903 int error; 1904 struct mlx5_core_dev *mdev= sq->priv->mdev; 1905 1906 /* 1907 * Check if already stopped. 1908 * 1909 * NOTE: Serialization of this function is managed by the 1910 * caller ensuring the priv's state lock is locked or in case 1911 * of rate limit support, a single thread manages drain and 1912 * resume of SQs. The "running" variable can therefore safely 1913 * be read without any locks. 1914 */ 1915 if (READ_ONCE(sq->running) == 0) 1916 return; 1917 1918 /* don't put more packets into the SQ */ 1919 WRITE_ONCE(sq->running, 0); 1920 1921 /* serialize access to DMA rings */ 1922 mtx_lock(&sq->lock); 1923 1924 /* teardown event factor timer, if any */ 1925 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1926 callout_stop(&sq->cev_callout); 1927 1928 /* send dummy NOPs in order to flush the transmit ring */ 1929 mlx5e_sq_send_nops_locked(sq, 1); 1930 mtx_unlock(&sq->lock); 1931 1932 /* wait till SQ is empty or link is down */ 1933 mtx_lock(&sq->lock); 1934 while (sq->cc != sq->pc && 1935 (sq->priv->media_status_last & IFM_ACTIVE) != 0 && 1936 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR && 1937 pci_channel_offline(mdev->pdev) == 0) { 1938 mtx_unlock(&sq->lock); 1939 msleep(1); 1940 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1941 mtx_lock(&sq->lock); 1942 } 1943 mtx_unlock(&sq->lock); 1944 1945 /* error out remaining requests */ 1946 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1947 if (error != 0) { 1948 mlx5_en_err(sq->ifp, 1949 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error); 1950 } 1951 1952 /* wait till SQ is empty */ 1953 mtx_lock(&sq->lock); 1954 while (sq->cc != sq->pc && 1955 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR && 1956 pci_channel_offline(mdev->pdev) == 0) { 1957 mtx_unlock(&sq->lock); 1958 msleep(1); 1959 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1960 mtx_lock(&sq->lock); 1961 } 1962 mtx_unlock(&sq->lock); 1963 } 1964 1965 static void 1966 mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1967 { 1968 1969 mlx5e_drain_sq(sq); 1970 mlx5e_disable_sq(sq); 1971 mlx5e_destroy_sq(sq); 1972 } 1973 1974 static int 1975 mlx5e_create_cq(struct mlx5e_priv *priv, 1976 struct mlx5e_cq_param *param, 1977 struct mlx5e_cq *cq, 1978 mlx5e_cq_comp_t *comp, 1979 int eq_ix) 1980 { 1981 struct mlx5_core_dev *mdev = priv->mdev; 1982 struct mlx5_core_cq *mcq = &cq->mcq; 1983 int eqn_not_used; 1984 int irqn; 1985 int err; 1986 u32 i; 1987 1988 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1989 if (err) 1990 return (err); 1991 1992 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1993 &cq->wq_ctrl); 1994 if (err) 1995 return (err); 1996 1997 mcq->cqe_sz = 64; 1998 mcq->set_ci_db = cq->wq_ctrl.db.db; 1999 mcq->arm_db = cq->wq_ctrl.db.db + 1; 2000 *mcq->set_ci_db = 0; 2001 *mcq->arm_db = 0; 2002 mcq->vector = eq_ix; 2003 mcq->comp = comp; 2004 mcq->event = mlx5e_cq_error_event; 2005 mcq->irqn = irqn; 2006 2007 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 2008 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 2009 2010 cqe->op_own = 0xf1; 2011 } 2012 2013 cq->priv = priv; 2014 2015 return (0); 2016 } 2017 2018 static void 2019 mlx5e_destroy_cq(struct mlx5e_cq *cq) 2020 { 2021 mlx5_wq_destroy(&cq->wq_ctrl); 2022 } 2023 2024 static int 2025 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 2026 { 2027 struct mlx5_core_cq *mcq = &cq->mcq; 2028 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 2029 void *in; 2030 void *cqc; 2031 int inlen; 2032 int irqn_not_used; 2033 int eqn; 2034 int err; 2035 2036 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 2037 sizeof(u64) * cq->wq_ctrl.buf.npages; 2038 in = mlx5_vzalloc(inlen); 2039 if (in == NULL) 2040 return (-ENOMEM); 2041 2042 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2043 2044 memcpy(cqc, param->cqc, sizeof(param->cqc)); 2045 2046 mlx5_fill_page_array(&cq->wq_ctrl.buf, 2047 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 2048 2049 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 2050 2051 MLX5_SET(cqc, cqc, c_eqn, eqn); 2052 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 2053 MLX5_ADAPTER_PAGE_SHIFT); 2054 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 2055 2056 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out)); 2057 2058 kvfree(in); 2059 2060 if (err) 2061 return (err); 2062 2063 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock)); 2064 2065 return (0); 2066 } 2067 2068 static void 2069 mlx5e_disable_cq(struct mlx5e_cq *cq) 2070 { 2071 2072 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 2073 } 2074 2075 int 2076 mlx5e_open_cq(struct mlx5e_priv *priv, 2077 struct mlx5e_cq_param *param, 2078 struct mlx5e_cq *cq, 2079 mlx5e_cq_comp_t *comp, 2080 int eq_ix) 2081 { 2082 int err; 2083 2084 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 2085 if (err) 2086 return (err); 2087 2088 err = mlx5e_enable_cq(cq, param, eq_ix); 2089 if (err) 2090 goto err_destroy_cq; 2091 2092 return (0); 2093 2094 err_destroy_cq: 2095 mlx5e_destroy_cq(cq); 2096 2097 return (err); 2098 } 2099 2100 void 2101 mlx5e_close_cq(struct mlx5e_cq *cq) 2102 { 2103 mlx5e_disable_cq(cq); 2104 mlx5e_destroy_cq(cq); 2105 } 2106 2107 static int 2108 mlx5e_open_tx_cqs(struct mlx5e_channel *c, 2109 struct mlx5e_channel_param *cparam) 2110 { 2111 int err; 2112 int tc; 2113 2114 for (tc = 0; tc < c->priv->num_tc; tc++) { 2115 /* open completion queue */ 2116 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 2117 &mlx5e_tx_cq_comp, c->ix); 2118 if (err) 2119 goto err_close_tx_cqs; 2120 } 2121 return (0); 2122 2123 err_close_tx_cqs: 2124 for (tc--; tc >= 0; tc--) 2125 mlx5e_close_cq(&c->sq[tc].cq); 2126 2127 return (err); 2128 } 2129 2130 static void 2131 mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2132 { 2133 int tc; 2134 2135 for (tc = 0; tc < c->priv->num_tc; tc++) 2136 mlx5e_close_cq(&c->sq[tc].cq); 2137 } 2138 2139 static int 2140 mlx5e_open_sqs(struct mlx5e_channel *c, 2141 struct mlx5e_channel_param *cparam) 2142 { 2143 int err; 2144 int tc; 2145 2146 for (tc = 0; tc < c->priv->num_tc; tc++) { 2147 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 2148 if (err) 2149 goto err_close_sqs; 2150 } 2151 2152 return (0); 2153 2154 err_close_sqs: 2155 for (tc--; tc >= 0; tc--) 2156 mlx5e_close_sq_wait(&c->sq[tc]); 2157 2158 return (err); 2159 } 2160 2161 static void 2162 mlx5e_close_sqs_wait(struct mlx5e_channel *c) 2163 { 2164 int tc; 2165 2166 for (tc = 0; tc < c->priv->num_tc; tc++) 2167 mlx5e_close_sq_wait(&c->sq[tc]); 2168 } 2169 2170 static void 2171 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix) 2172 { 2173 int tc; 2174 2175 /* setup priv and channel number */ 2176 c->priv = priv; 2177 c->ix = ix; 2178 2179 /* setup send tag */ 2180 m_snd_tag_init(&c->tag, c->priv->ifp, &mlx5e_ul_snd_tag_sw); 2181 2182 init_completion(&c->completion); 2183 2184 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 2185 2186 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 2187 2188 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2189 struct mlx5e_sq *sq = c->sq + tc; 2190 2191 mtx_init(&sq->lock, "mlx5tx", 2192 MTX_NETWORK_LOCK " TX", MTX_DEF); 2193 mtx_init(&sq->comp_lock, "mlx5comp", 2194 MTX_NETWORK_LOCK " TX", MTX_DEF); 2195 2196 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 2197 } 2198 2199 mlx5e_iq_static_init(&c->iq); 2200 } 2201 2202 static void 2203 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c) 2204 { 2205 2206 m_snd_tag_rele(&c->tag); 2207 wait_for_completion(&c->completion); 2208 } 2209 2210 static void 2211 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels) 2212 { 2213 uint32_t x; 2214 2215 for (x = 0; x != channels; x++) 2216 mlx5e_chan_wait_for_completion(&priv->channel[x]); 2217 } 2218 2219 static void 2220 mlx5e_chan_static_destroy(struct mlx5e_channel *c) 2221 { 2222 int tc; 2223 2224 callout_drain(&c->rq.watchdog); 2225 2226 mtx_destroy(&c->rq.mtx); 2227 2228 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2229 callout_drain(&c->sq[tc].cev_callout); 2230 mtx_destroy(&c->sq[tc].lock); 2231 mtx_destroy(&c->sq[tc].comp_lock); 2232 } 2233 2234 mlx5e_iq_static_destroy(&c->iq); 2235 } 2236 2237 static int 2238 mlx5e_open_channel(struct mlx5e_priv *priv, 2239 struct mlx5e_channel_param *cparam, 2240 struct mlx5e_channel *c) 2241 { 2242 struct epoch_tracker et; 2243 int i, err; 2244 2245 /* zero non-persistent data */ 2246 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start); 2247 for (i = 0; i != priv->num_tc; i++) 2248 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start); 2249 MLX5E_ZERO(&c->iq, mlx5e_iq_zero_start); 2250 2251 /* open transmit completion queue */ 2252 err = mlx5e_open_tx_cqs(c, cparam); 2253 if (err) 2254 goto err_free; 2255 2256 /* open receive completion queue */ 2257 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 2258 &mlx5e_rx_cq_comp, c->ix); 2259 if (err) 2260 goto err_close_tx_cqs; 2261 2262 err = mlx5e_open_sqs(c, cparam); 2263 if (err) 2264 goto err_close_rx_cq; 2265 2266 err = mlx5e_iq_open(c, &cparam->sq, &cparam->tx_cq, &c->iq); 2267 if (err) 2268 goto err_close_sqs; 2269 2270 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 2271 if (err) 2272 goto err_close_iq; 2273 2274 /* poll receive queue initially */ 2275 NET_EPOCH_ENTER(et); 2276 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL); 2277 NET_EPOCH_EXIT(et); 2278 2279 return (0); 2280 2281 err_close_iq: 2282 mlx5e_iq_close(&c->iq); 2283 2284 err_close_sqs: 2285 mlx5e_close_sqs_wait(c); 2286 2287 err_close_rx_cq: 2288 mlx5e_close_cq(&c->rq.cq); 2289 2290 err_close_tx_cqs: 2291 mlx5e_close_tx_cqs(c); 2292 2293 err_free: 2294 return (err); 2295 } 2296 2297 static void 2298 mlx5e_close_channel(struct mlx5e_channel *c) 2299 { 2300 mlx5e_close_rq(&c->rq); 2301 } 2302 2303 static void 2304 mlx5e_close_channel_wait(struct mlx5e_channel *c) 2305 { 2306 mlx5e_close_rq_wait(&c->rq); 2307 mlx5e_iq_close(&c->iq); 2308 mlx5e_close_sqs_wait(c); 2309 mlx5e_close_tx_cqs(c); 2310 } 2311 2312 static int 2313 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs) 2314 { 2315 u32 r, n; 2316 2317 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz : 2318 MLX5E_SW2MB_MTU(if_getmtu(priv->ifp)); 2319 if (r > MJUM16BYTES) 2320 return (-ENOMEM); 2321 2322 if (r > MJUM9BYTES) 2323 r = MJUM16BYTES; 2324 else if (r > MJUMPAGESIZE) 2325 r = MJUM9BYTES; 2326 else if (r > MCLBYTES) 2327 r = MJUMPAGESIZE; 2328 else 2329 r = MCLBYTES; 2330 2331 /* 2332 * n + 1 must be a power of two, because stride size must be. 2333 * Stride size is 16 * (n + 1), as the first segment is 2334 * control. 2335 */ 2336 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++) 2337 ; 2338 2339 if (n > MLX5E_MAX_BUSDMA_RX_SEGS) 2340 return (-ENOMEM); 2341 2342 *wqe_sz = r; 2343 *nsegs = n; 2344 return (0); 2345 } 2346 2347 static void 2348 mlx5e_build_rq_param(struct mlx5e_priv *priv, 2349 struct mlx5e_rq_param *param) 2350 { 2351 void *rqc = param->rqc; 2352 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2353 u32 wqe_sz, nsegs; 2354 2355 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 2356 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 2357 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 2358 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + 2359 nsegs * sizeof(struct mlx5_wqe_data_seg))); 2360 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 2361 MLX5_SET(wq, wq, pd, priv->pdn); 2362 2363 param->wq.linear = 1; 2364 } 2365 2366 static void 2367 mlx5e_build_sq_param(struct mlx5e_priv *priv, 2368 struct mlx5e_sq_param *param) 2369 { 2370 void *sqc = param->sqc; 2371 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2372 2373 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 2374 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 2375 MLX5_SET(wq, wq, pd, priv->pdn); 2376 2377 param->wq.linear = 1; 2378 } 2379 2380 static void 2381 mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 2382 struct mlx5e_cq_param *param) 2383 { 2384 void *cqc = param->cqc; 2385 2386 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); 2387 } 2388 2389 static void 2390 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr) 2391 { 2392 2393 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE); 2394 2395 /* apply LRO restrictions */ 2396 if (priv->params.hw_lro_en && 2397 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) { 2398 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO; 2399 } 2400 } 2401 2402 static void 2403 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 2404 struct mlx5e_cq_param *param) 2405 { 2406 struct net_dim_cq_moder curr; 2407 void *cqc = param->cqc; 2408 2409 /* 2410 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE 2411 * format is more beneficial for FreeBSD use case. 2412 * 2413 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes 2414 * in mlx5e_decompress_cqe. 2415 */ 2416 if (priv->params.cqe_zipping_en) { 2417 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH); 2418 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 2419 } 2420 2421 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 2422 2423 switch (priv->params.rx_cq_moderation_mode) { 2424 case 0: 2425 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2426 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2427 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2428 break; 2429 case 1: 2430 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2431 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2432 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2433 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2434 else 2435 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2436 break; 2437 case 2: 2438 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr); 2439 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2440 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2441 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2442 break; 2443 case 3: 2444 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr); 2445 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2446 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2447 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2448 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2449 else 2450 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2451 break; 2452 default: 2453 break; 2454 } 2455 2456 mlx5e_dim_build_cq_param(priv, param); 2457 2458 mlx5e_build_common_cq_param(priv, param); 2459 } 2460 2461 static void 2462 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 2463 struct mlx5e_cq_param *param) 2464 { 2465 void *cqc = param->cqc; 2466 2467 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 2468 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 2469 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 2470 2471 switch (priv->params.tx_cq_moderation_mode) { 2472 case 0: 2473 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2474 break; 2475 default: 2476 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2477 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2478 else 2479 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2480 break; 2481 } 2482 2483 mlx5e_build_common_cq_param(priv, param); 2484 } 2485 2486 static void 2487 mlx5e_build_channel_param(struct mlx5e_priv *priv, 2488 struct mlx5e_channel_param *cparam) 2489 { 2490 memset(cparam, 0, sizeof(*cparam)); 2491 2492 mlx5e_build_rq_param(priv, &cparam->rq); 2493 mlx5e_build_sq_param(priv, &cparam->sq); 2494 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 2495 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 2496 } 2497 2498 static int 2499 mlx5e_open_channels(struct mlx5e_priv *priv) 2500 { 2501 struct mlx5e_channel_param *cparam; 2502 int err; 2503 int i; 2504 2505 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK); 2506 2507 mlx5e_build_channel_param(priv, cparam); 2508 for (i = 0; i < priv->params.num_channels; i++) { 2509 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]); 2510 if (err) 2511 goto err_close_channels; 2512 2513 /* Bind interrupt vectors, if any. */ 2514 if (priv->params_ethtool.irq_cpu_base > -1) { 2515 cpuset_t cpuset; 2516 int cpu; 2517 int irq; 2518 int eqn; 2519 int nirq; 2520 2521 err = mlx5_vector2eqn(priv->mdev, i, 2522 &eqn, &nirq); 2523 2524 /* error here is non-fatal */ 2525 if (err != 0) 2526 continue; 2527 2528 irq = priv->mdev->priv.msix_arr[nirq].vector; 2529 cpu = (unsigned)(priv->params_ethtool.irq_cpu_base + 2530 i * priv->params_ethtool.irq_cpu_stride) % (unsigned)mp_ncpus; 2531 2532 CPU_ZERO(&cpuset); 2533 CPU_SET(cpu, &cpuset); 2534 intr_setaffinity(irq, CPU_WHICH_INTRHANDLER, &cpuset); 2535 } 2536 } 2537 free(cparam, M_MLX5EN); 2538 return (0); 2539 2540 err_close_channels: 2541 while (i--) { 2542 mlx5e_close_channel(&priv->channel[i]); 2543 mlx5e_close_channel_wait(&priv->channel[i]); 2544 } 2545 free(cparam, M_MLX5EN); 2546 return (err); 2547 } 2548 2549 static void 2550 mlx5e_close_channels(struct mlx5e_priv *priv) 2551 { 2552 int i; 2553 2554 for (i = 0; i < priv->params.num_channels; i++) 2555 mlx5e_close_channel(&priv->channel[i]); 2556 for (i = 0; i < priv->params.num_channels; i++) 2557 mlx5e_close_channel_wait(&priv->channel[i]); 2558 } 2559 2560 static int 2561 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 2562 { 2563 2564 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2565 uint8_t cq_mode; 2566 2567 switch (priv->params.tx_cq_moderation_mode) { 2568 case 0: 2569 case 2: 2570 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2571 break; 2572 default: 2573 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2574 break; 2575 } 2576 2577 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq, 2578 priv->params.tx_cq_moderation_usec, 2579 priv->params.tx_cq_moderation_pkts, 2580 cq_mode)); 2581 } 2582 2583 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 2584 priv->params.tx_cq_moderation_usec, 2585 priv->params.tx_cq_moderation_pkts)); 2586 } 2587 2588 static int 2589 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 2590 { 2591 2592 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2593 uint8_t cq_mode; 2594 uint8_t dim_mode; 2595 int retval; 2596 2597 switch (priv->params.rx_cq_moderation_mode) { 2598 case 0: 2599 case 2: 2600 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2601 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2602 break; 2603 default: 2604 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2605 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 2606 break; 2607 } 2608 2609 /* tear down dynamic interrupt moderation */ 2610 mtx_lock(&rq->mtx); 2611 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 2612 mtx_unlock(&rq->mtx); 2613 2614 /* wait for dynamic interrupt moderation work task, if any */ 2615 cancel_work_sync(&rq->dim.work); 2616 2617 if (priv->params.rx_cq_moderation_mode >= 2) { 2618 struct net_dim_cq_moder curr; 2619 2620 mlx5e_get_default_profile(priv, dim_mode, &curr); 2621 2622 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2623 curr.usec, curr.pkts, cq_mode); 2624 2625 /* set dynamic interrupt moderation mode and zero defaults */ 2626 mtx_lock(&rq->mtx); 2627 rq->dim.mode = dim_mode; 2628 rq->dim.state = 0; 2629 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE; 2630 mtx_unlock(&rq->mtx); 2631 } else { 2632 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2633 priv->params.rx_cq_moderation_usec, 2634 priv->params.rx_cq_moderation_pkts, 2635 cq_mode); 2636 } 2637 return (retval); 2638 } 2639 2640 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 2641 priv->params.rx_cq_moderation_usec, 2642 priv->params.rx_cq_moderation_pkts)); 2643 } 2644 2645 static int 2646 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 2647 { 2648 int err; 2649 int i; 2650 2651 err = mlx5e_refresh_rq_params(priv, &c->rq); 2652 if (err) 2653 goto done; 2654 2655 for (i = 0; i != priv->num_tc; i++) { 2656 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 2657 if (err) 2658 goto done; 2659 } 2660 done: 2661 return (err); 2662 } 2663 2664 int 2665 mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 2666 { 2667 int i; 2668 2669 /* check if channels are closed */ 2670 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2671 return (EINVAL); 2672 2673 for (i = 0; i < priv->params.num_channels; i++) { 2674 int err; 2675 2676 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]); 2677 if (err) 2678 return (err); 2679 } 2680 return (0); 2681 } 2682 2683 static int 2684 mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 2685 { 2686 struct mlx5_core_dev *mdev = priv->mdev; 2687 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 2688 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 2689 2690 memset(in, 0, sizeof(in)); 2691 2692 MLX5_SET(tisc, tisc, prio, tc); 2693 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 2694 2695 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 2696 } 2697 2698 static void 2699 mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 2700 { 2701 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc], 0); 2702 } 2703 2704 static int 2705 mlx5e_open_tises(struct mlx5e_priv *priv) 2706 { 2707 int num_tc = priv->num_tc; 2708 int err; 2709 int tc; 2710 2711 for (tc = 0; tc < num_tc; tc++) { 2712 err = mlx5e_open_tis(priv, tc); 2713 if (err) 2714 goto err_close_tises; 2715 } 2716 2717 return (0); 2718 2719 err_close_tises: 2720 for (tc--; tc >= 0; tc--) 2721 mlx5e_close_tis(priv, tc); 2722 2723 return (err); 2724 } 2725 2726 static void 2727 mlx5e_close_tises(struct mlx5e_priv *priv) 2728 { 2729 int num_tc = priv->num_tc; 2730 int tc; 2731 2732 for (tc = 0; tc < num_tc; tc++) 2733 mlx5e_close_tis(priv, tc); 2734 } 2735 2736 static int 2737 mlx5e_open_default_rqt(struct mlx5e_priv *priv, u32 *prqtn, int sz) 2738 { 2739 u32 *in; 2740 void *rqtc; 2741 int inlen; 2742 int err; 2743 int i; 2744 2745 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2746 in = mlx5_vzalloc(inlen); 2747 if (in == NULL) 2748 return (-ENOMEM); 2749 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2750 2751 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2752 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2753 2754 for (i = 0; i != sz; i++) 2755 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); 2756 2757 err = mlx5_core_create_rqt(priv->mdev, in, inlen, prqtn); 2758 kvfree(in); 2759 2760 return (err); 2761 } 2762 2763 static int 2764 mlx5e_open_rqts(struct mlx5e_priv *priv) 2765 { 2766 int err; 2767 int i; 2768 2769 err = mlx5e_open_default_rqt(priv, &priv->rqtn, 2770 1 << priv->params.rx_hash_log_tbl_sz); 2771 if (err) 2772 goto err_default; 2773 2774 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2775 err = mlx5e_open_default_rqt(priv, &priv->channel[i].rqtn, 1); 2776 if (err) 2777 goto err_channel; 2778 } 2779 return (0); 2780 2781 err_channel: 2782 while (i--) 2783 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0); 2784 2785 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0); 2786 2787 err_default: 2788 return (err); 2789 } 2790 2791 static void 2792 mlx5e_close_rqts(struct mlx5e_priv *priv) 2793 { 2794 int i; 2795 2796 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) 2797 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0); 2798 2799 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0); 2800 } 2801 2802 static int 2803 mlx5e_activate_rqt(struct mlx5e_priv *priv) 2804 { 2805 u32 *in; 2806 void *rqtc; 2807 int inlen; 2808 int err; 2809 int sz; 2810 int i; 2811 2812 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2813 2814 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; 2815 in = mlx5_vzalloc(inlen); 2816 if (in == NULL) 2817 return (-ENOMEM); 2818 2819 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); 2820 2821 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2822 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); 2823 2824 for (i = 0; i != sz; i++) { 2825 int ix; 2826 #ifdef RSS 2827 ix = rss_get_indirection_to_bucket(i); 2828 #else 2829 ix = i; 2830 #endif 2831 /* ensure we don't overflow */ 2832 ix %= priv->params.num_channels; 2833 2834 /* apply receive side scaling stride, if any */ 2835 ix -= ix % (int)priv->params.channels_rsss; 2836 2837 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn); 2838 } 2839 2840 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen); 2841 if (err) 2842 goto err_modify; 2843 2844 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32); 2845 2846 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1); 2847 2848 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2849 int ix; 2850 #ifdef RSS 2851 ix = rss_get_indirection_to_bucket(i); 2852 #else 2853 ix = i; 2854 #endif 2855 /* ensure we don't overflow */ 2856 ix %= priv->params.num_channels; 2857 2858 /* apply receive side scaling stride, if any */ 2859 ix -= ix % (int)priv->params.channels_rsss; 2860 2861 MLX5_SET(rqtc, rqtc, rq_num[0], priv->channel[ix].rq.rqn); 2862 2863 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen); 2864 if (err) 2865 goto err_modify; 2866 } 2867 2868 err_modify: 2869 kvfree(in); 2870 return (err); 2871 } 2872 2873 static int 2874 mlx5e_deactivate_rqt(struct mlx5e_priv *priv) 2875 { 2876 u32 *in; 2877 void *rqtc; 2878 int inlen; 2879 int err; 2880 int sz; 2881 int i; 2882 2883 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2884 2885 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; 2886 in = mlx5_vzalloc(inlen); 2887 if (in == NULL) 2888 return (-ENOMEM); 2889 2890 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); 2891 2892 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2893 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); 2894 2895 for (i = 0; i != sz; i++) 2896 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); 2897 2898 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen); 2899 if (err) 2900 goto err_modify; 2901 2902 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32); 2903 2904 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1); 2905 2906 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2907 MLX5_SET(rqtc, rqtc, rq_num[0], priv->drop_rq.rqn); 2908 2909 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen); 2910 if (err) 2911 goto err_modify; 2912 } 2913 2914 err_modify: 2915 kvfree(in); 2916 return (err); 2917 } 2918 2919 #define MLX5E_RSS_KEY_SIZE (10 * 4) /* bytes */ 2920 2921 static void 2922 mlx5e_get_rss_key(void *key_ptr) 2923 { 2924 #ifdef RSS 2925 rss_getkey(key_ptr); 2926 #else 2927 static const u32 rsskey[] = { 2928 cpu_to_be32(0xD181C62C), 2929 cpu_to_be32(0xF7F4DB5B), 2930 cpu_to_be32(0x1983A2FC), 2931 cpu_to_be32(0x943E1ADB), 2932 cpu_to_be32(0xD9389E6B), 2933 cpu_to_be32(0xD1039C2C), 2934 cpu_to_be32(0xA74499AD), 2935 cpu_to_be32(0x593D56D9), 2936 cpu_to_be32(0xF3253C06), 2937 cpu_to_be32(0x2ADC1FFC), 2938 }; 2939 CTASSERT(sizeof(rsskey) == MLX5E_RSS_KEY_SIZE); 2940 memcpy(key_ptr, rsskey, MLX5E_RSS_KEY_SIZE); 2941 #endif 2942 } 2943 2944 static void 2945 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt, bool inner_vxlan) 2946 { 2947 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2948 void *hfsi = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 2949 void *hfs = inner_vxlan ? hfsi : hfso; 2950 __be32 *hkey; 2951 2952 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 2953 2954 #define ROUGH_MAX_L2_L3_HDR_SZ 256 2955 2956 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2957 MLX5_HASH_FIELD_SEL_DST_IP) 2958 2959 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2960 MLX5_HASH_FIELD_SEL_DST_IP |\ 2961 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 2962 MLX5_HASH_FIELD_SEL_L4_DPORT) 2963 2964 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2965 MLX5_HASH_FIELD_SEL_DST_IP |\ 2966 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 2967 2968 if (priv->params.hw_lro_en) { 2969 MLX5_SET(tirc, tirc, lro_enable_mask, 2970 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2971 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2972 MLX5_SET(tirc, tirc, lro_max_msg_sz, 2973 (priv->params.lro_wqe_sz - 2974 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2975 /* TODO: add the option to choose timer value dynamically */ 2976 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 2977 MLX5_CAP_ETH(priv->mdev, 2978 lro_timer_supported_periods[2])); 2979 } 2980 2981 if (inner_vxlan) 2982 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 2983 2984 /* 2985 * All packets must go through the indirection table, RQT, 2986 * because it is not possible to modify the RQN of the TIR 2987 * for direct dispatchment after it is created, typically 2988 * when the link goes up and down. 2989 */ 2990 MLX5_SET(tirc, tirc, disp_type, 2991 MLX5_TIRC_DISP_TYPE_INDIRECT); 2992 MLX5_SET(tirc, tirc, indirect_table, 2993 priv->rqtn); 2994 MLX5_SET(tirc, tirc, rx_hash_fn, 2995 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 2996 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 2997 2998 CTASSERT(MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key) >= 2999 MLX5E_RSS_KEY_SIZE); 3000 #ifdef RSS 3001 /* 3002 * The FreeBSD RSS implementation does currently not 3003 * support symmetric Toeplitz hashes: 3004 */ 3005 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 3006 #else 3007 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 3008 #endif 3009 mlx5e_get_rss_key(hkey); 3010 3011 switch (tt) { 3012 case MLX5E_TT_IPV4_TCP: 3013 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3014 MLX5_L3_PROT_TYPE_IPV4); 3015 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3016 MLX5_L4_PROT_TYPE_TCP); 3017 #ifdef RSS 3018 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 3019 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3020 MLX5_HASH_IP); 3021 } else 3022 #endif 3023 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3024 MLX5_HASH_ALL); 3025 break; 3026 3027 case MLX5E_TT_IPV6_TCP: 3028 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3029 MLX5_L3_PROT_TYPE_IPV6); 3030 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3031 MLX5_L4_PROT_TYPE_TCP); 3032 #ifdef RSS 3033 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 3034 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3035 MLX5_HASH_IP); 3036 } else 3037 #endif 3038 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3039 MLX5_HASH_ALL); 3040 break; 3041 3042 case MLX5E_TT_IPV4_UDP: 3043 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3044 MLX5_L3_PROT_TYPE_IPV4); 3045 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3046 MLX5_L4_PROT_TYPE_UDP); 3047 #ifdef RSS 3048 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 3049 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3050 MLX5_HASH_IP); 3051 } else 3052 #endif 3053 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3054 MLX5_HASH_ALL); 3055 break; 3056 3057 case MLX5E_TT_IPV6_UDP: 3058 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3059 MLX5_L3_PROT_TYPE_IPV6); 3060 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3061 MLX5_L4_PROT_TYPE_UDP); 3062 #ifdef RSS 3063 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 3064 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3065 MLX5_HASH_IP); 3066 } else 3067 #endif 3068 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3069 MLX5_HASH_ALL); 3070 break; 3071 3072 case MLX5E_TT_IPV4_IPSEC_AH: 3073 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3074 MLX5_L3_PROT_TYPE_IPV4); 3075 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3076 MLX5_HASH_IP_IPSEC_SPI); 3077 break; 3078 3079 case MLX5E_TT_IPV6_IPSEC_AH: 3080 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3081 MLX5_L3_PROT_TYPE_IPV6); 3082 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3083 MLX5_HASH_IP_IPSEC_SPI); 3084 break; 3085 3086 case MLX5E_TT_IPV4_IPSEC_ESP: 3087 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3088 MLX5_L3_PROT_TYPE_IPV4); 3089 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3090 MLX5_HASH_IP_IPSEC_SPI); 3091 break; 3092 3093 case MLX5E_TT_IPV6_IPSEC_ESP: 3094 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3095 MLX5_L3_PROT_TYPE_IPV6); 3096 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3097 MLX5_HASH_IP_IPSEC_SPI); 3098 break; 3099 3100 case MLX5E_TT_IPV4: 3101 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3102 MLX5_L3_PROT_TYPE_IPV4); 3103 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3104 MLX5_HASH_IP); 3105 break; 3106 3107 case MLX5E_TT_IPV6: 3108 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3109 MLX5_L3_PROT_TYPE_IPV6); 3110 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3111 MLX5_HASH_IP); 3112 break; 3113 3114 default: 3115 break; 3116 } 3117 } 3118 3119 static int 3120 mlx5e_open_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 3121 { 3122 struct mlx5_core_dev *mdev = priv->mdev; 3123 u32 *in; 3124 void *tirc; 3125 int inlen; 3126 int err; 3127 3128 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 3129 in = mlx5_vzalloc(inlen); 3130 if (in == NULL) 3131 return (-ENOMEM); 3132 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 3133 3134 mlx5e_build_tir_ctx(priv, tirc, tt, inner_vxlan); 3135 3136 err = mlx5_core_create_tir(mdev, in, inlen, inner_vxlan ? 3137 &priv->tirn_inner_vxlan[tt] : &priv->tirn[tt]); 3138 3139 kvfree(in); 3140 3141 return (err); 3142 } 3143 3144 static void 3145 mlx5e_close_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 3146 { 3147 mlx5_core_destroy_tir(priv->mdev, inner_vxlan ? 3148 priv->tirn_inner_vxlan[tt] : priv->tirn[tt], 0); 3149 } 3150 3151 static int 3152 mlx5e_open_tirs(struct mlx5e_priv *priv) 3153 { 3154 int err; 3155 int i; 3156 3157 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) { 3158 err = mlx5e_open_tir(priv, i / 2, (i % 2) ? true : false); 3159 if (err) 3160 goto err_close_tirs; 3161 } 3162 3163 return (0); 3164 3165 err_close_tirs: 3166 for (i--; i >= 0; i--) 3167 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false); 3168 3169 return (err); 3170 } 3171 3172 static void 3173 mlx5e_close_tirs(struct mlx5e_priv *priv) 3174 { 3175 int i; 3176 3177 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) 3178 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false); 3179 } 3180 3181 /* 3182 * SW MTU does not include headers, 3183 * HW MTU includes all headers and checksums. 3184 */ 3185 static int 3186 mlx5e_set_dev_port_mtu(if_t ifp, int sw_mtu) 3187 { 3188 struct mlx5e_priv *priv = if_getsoftc(ifp); 3189 struct mlx5_core_dev *mdev = priv->mdev; 3190 int hw_mtu; 3191 int err; 3192 3193 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu); 3194 3195 err = mlx5_set_port_mtu(mdev, hw_mtu); 3196 if (err) { 3197 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n", 3198 sw_mtu, err); 3199 return (err); 3200 } 3201 3202 /* Update vport context MTU */ 3203 err = mlx5_set_vport_mtu(mdev, hw_mtu); 3204 if (err) { 3205 mlx5_en_err(ifp, 3206 "Failed updating vport context with MTU size, err=%d\n", 3207 err); 3208 } 3209 3210 if_setmtu(ifp, sw_mtu); 3211 3212 err = mlx5_query_vport_mtu(mdev, &hw_mtu); 3213 if (err || !hw_mtu) { 3214 /* fallback to port oper mtu */ 3215 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 3216 } 3217 if (err) { 3218 mlx5_en_err(ifp, 3219 "Query port MTU, after setting new MTU value, failed\n"); 3220 return (err); 3221 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 3222 err = -E2BIG, 3223 mlx5_en_err(ifp, 3224 "Port MTU %d is smaller than ifp mtu %d\n", 3225 hw_mtu, sw_mtu); 3226 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 3227 err = -EINVAL; 3228 mlx5_en_err(ifp, 3229 "Port MTU %d is bigger than ifp mtu %d\n", 3230 hw_mtu, sw_mtu); 3231 } 3232 priv->params_ethtool.hw_mtu = hw_mtu; 3233 3234 /* compute MSB */ 3235 while (hw_mtu & (hw_mtu - 1)) 3236 hw_mtu &= (hw_mtu - 1); 3237 priv->params_ethtool.hw_mtu_msb = hw_mtu; 3238 3239 return (err); 3240 } 3241 3242 int 3243 mlx5e_open_locked(if_t ifp) 3244 { 3245 struct mlx5e_priv *priv = if_getsoftc(ifp); 3246 int err; 3247 u16 set_id; 3248 3249 /* check if already opened */ 3250 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3251 return (0); 3252 3253 #ifdef RSS 3254 if (rss_getnumbuckets() > priv->params.num_channels) { 3255 mlx5_en_info(ifp, 3256 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n", 3257 rss_getnumbuckets(), priv->params.num_channels); 3258 } 3259 #endif 3260 err = mlx5e_open_tises(priv); 3261 if (err) { 3262 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err); 3263 return (err); 3264 } 3265 err = mlx5_vport_alloc_q_counter(priv->mdev, 3266 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 3267 if (err) { 3268 mlx5_en_err(priv->ifp, 3269 "mlx5_vport_alloc_q_counter failed: %d\n", err); 3270 goto err_close_tises; 3271 } 3272 /* store counter set ID */ 3273 priv->counter_set_id = set_id; 3274 3275 err = mlx5e_open_channels(priv); 3276 if (err) { 3277 mlx5_en_err(ifp, 3278 "mlx5e_open_channels failed, %d\n", err); 3279 goto err_dalloc_q_counter; 3280 } 3281 err = mlx5e_activate_rqt(priv); 3282 if (err) { 3283 mlx5_en_err(ifp, "mlx5e_activate_rqt failed, %d\n", err); 3284 goto err_close_channels; 3285 } 3286 3287 set_bit(MLX5E_STATE_OPENED, &priv->state); 3288 3289 mlx5e_update_carrier(priv); 3290 3291 return (0); 3292 3293 err_close_channels: 3294 mlx5e_close_channels(priv); 3295 3296 err_dalloc_q_counter: 3297 mlx5_vport_dealloc_q_counter(priv->mdev, 3298 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3299 3300 err_close_tises: 3301 mlx5e_close_tises(priv); 3302 3303 return (err); 3304 } 3305 3306 static void 3307 mlx5e_open(void *arg) 3308 { 3309 struct mlx5e_priv *priv = arg; 3310 3311 PRIV_LOCK(priv); 3312 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 3313 mlx5_en_err(priv->ifp, 3314 "Setting port status to up failed\n"); 3315 3316 mlx5e_open_locked(priv->ifp); 3317 if_setdrvflagbits(priv->ifp, IFF_DRV_RUNNING, 0); 3318 PRIV_UNLOCK(priv); 3319 } 3320 3321 int 3322 mlx5e_close_locked(if_t ifp) 3323 { 3324 struct mlx5e_priv *priv = if_getsoftc(ifp); 3325 3326 /* check if already closed */ 3327 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3328 return (0); 3329 3330 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3331 3332 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 3333 3334 mlx5e_deactivate_rqt(priv); 3335 mlx5e_close_channels(priv); 3336 mlx5_vport_dealloc_q_counter(priv->mdev, 3337 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3338 mlx5e_close_tises(priv); 3339 3340 return (0); 3341 } 3342 3343 static uint64_t 3344 mlx5e_get_counter(if_t ifp, ift_counter cnt) 3345 { 3346 struct mlx5e_priv *priv = if_getsoftc(ifp); 3347 u64 retval; 3348 3349 /* PRIV_LOCK(priv); XXX not allowed */ 3350 switch (cnt) { 3351 case IFCOUNTER_IPACKETS: 3352 retval = priv->stats.vport.rx_packets; 3353 break; 3354 case IFCOUNTER_IERRORS: 3355 retval = priv->stats.pport.in_range_len_errors + 3356 priv->stats.pport.out_of_range_len + 3357 priv->stats.pport.too_long_errors + 3358 priv->stats.pport.check_seq_err + 3359 priv->stats.pport.alignment_err; 3360 break; 3361 case IFCOUNTER_IQDROPS: 3362 retval = priv->stats.vport.rx_out_of_buffer; 3363 break; 3364 case IFCOUNTER_OPACKETS: 3365 retval = priv->stats.vport.tx_packets; 3366 break; 3367 case IFCOUNTER_OERRORS: 3368 retval = priv->stats.port_stats_debug.out_discards; 3369 break; 3370 case IFCOUNTER_IBYTES: 3371 retval = priv->stats.vport.rx_bytes; 3372 break; 3373 case IFCOUNTER_OBYTES: 3374 retval = priv->stats.vport.tx_bytes; 3375 break; 3376 case IFCOUNTER_IMCASTS: 3377 retval = priv->stats.vport.rx_multicast_packets; 3378 break; 3379 case IFCOUNTER_OMCASTS: 3380 retval = priv->stats.vport.tx_multicast_packets; 3381 break; 3382 case IFCOUNTER_OQDROPS: 3383 retval = priv->stats.vport.tx_queue_dropped; 3384 break; 3385 case IFCOUNTER_COLLISIONS: 3386 retval = priv->stats.pport.collisions; 3387 break; 3388 default: 3389 retval = if_get_counter_default(ifp, cnt); 3390 break; 3391 } 3392 /* PRIV_UNLOCK(priv); XXX not allowed */ 3393 return (retval); 3394 } 3395 3396 static void 3397 mlx5e_set_rx_mode(if_t ifp) 3398 { 3399 struct mlx5e_priv *priv = if_getsoftc(ifp); 3400 3401 queue_work(priv->wq, &priv->set_rx_mode_work); 3402 } 3403 3404 static int 3405 mlx5e_ioctl(if_t ifp, u_long command, caddr_t data) 3406 { 3407 struct mlx5e_priv *priv; 3408 struct ifreq *ifr; 3409 struct ifdownreason *ifdr; 3410 struct ifi2creq i2c; 3411 struct ifrsskey *ifrk; 3412 struct ifrsshash *ifrh; 3413 struct siocsifcapnv_driver_data *drv_ioctl_data, drv_ioctl_data_d; 3414 int error = 0; 3415 int mask; 3416 int size_read = 0; 3417 int module_status; 3418 int module_num; 3419 int max_mtu; 3420 uint8_t read_addr; 3421 3422 priv = if_getsoftc(ifp); 3423 3424 /* check if detaching */ 3425 if (priv == NULL || priv->gone != 0) 3426 return (ENXIO); 3427 3428 switch (command) { 3429 case SIOCSIFMTU: 3430 ifr = (struct ifreq *)data; 3431 3432 PRIV_LOCK(priv); 3433 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 3434 3435 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 3436 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 3437 int was_opened; 3438 3439 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3440 if (was_opened) 3441 mlx5e_close_locked(ifp); 3442 3443 /* set new MTU */ 3444 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 3445 3446 if (was_opened) 3447 mlx5e_open_locked(ifp); 3448 } else { 3449 error = EINVAL; 3450 mlx5_en_err(ifp, 3451 "Invalid MTU value. Min val: %d, Max val: %d\n", 3452 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 3453 } 3454 PRIV_UNLOCK(priv); 3455 break; 3456 case SIOCSIFFLAGS: 3457 if ((if_getflags(ifp) & IFF_UP) && 3458 (if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 3459 mlx5e_set_rx_mode(ifp); 3460 break; 3461 } 3462 PRIV_LOCK(priv); 3463 if (if_getflags(ifp) & IFF_UP) { 3464 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 3465 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3466 mlx5e_open_locked(ifp); 3467 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3468 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 3469 } 3470 } else { 3471 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3472 mlx5_set_port_status(priv->mdev, 3473 MLX5_PORT_DOWN); 3474 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3475 mlx5e_close_locked(ifp); 3476 mlx5e_update_carrier(priv); 3477 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3478 } 3479 } 3480 PRIV_UNLOCK(priv); 3481 break; 3482 case SIOCADDMULTI: 3483 case SIOCDELMULTI: 3484 mlx5e_set_rx_mode(ifp); 3485 break; 3486 case SIOCSIFMEDIA: 3487 case SIOCGIFMEDIA: 3488 case SIOCGIFXMEDIA: 3489 ifr = (struct ifreq *)data; 3490 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 3491 break; 3492 case SIOCGIFCAPNV: 3493 error = 0; 3494 break; 3495 case SIOCSIFCAP: 3496 ifr = (struct ifreq *)data; 3497 drv_ioctl_data = &drv_ioctl_data_d; 3498 drv_ioctl_data->reqcap = ifr->ifr_reqcap; 3499 PRIV_LOCK(priv); 3500 drv_ioctl_data->reqcap2 = if_getcapenable2(ifp); 3501 drv_ioctl_data->nvcap = NULL; 3502 goto siocsifcap_driver; 3503 case SIOCSIFCAPNV: 3504 drv_ioctl_data = (struct siocsifcapnv_driver_data *)data; 3505 PRIV_LOCK(priv); 3506 siocsifcap_driver: 3507 mask = drv_ioctl_data->reqcap ^ if_getcapenable(ifp); 3508 3509 if (mask & IFCAP_TXCSUM) { 3510 if_togglecapenable(ifp, IFCAP_TXCSUM); 3511 if_togglehwassist(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP)); 3512 3513 if (IFCAP_TSO4 & if_getcapenable(ifp) && 3514 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 3515 mask &= ~IFCAP_TSO4; 3516 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3517 if_sethwassistbits(ifp, 0, CSUM_IP_TSO); 3518 mlx5_en_err(ifp, 3519 "tso4 disabled due to -txcsum.\n"); 3520 } 3521 } 3522 if (mask & IFCAP_TXCSUM_IPV6) { 3523 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6); 3524 if_togglehwassist(ifp, (CSUM_UDP_IPV6 | CSUM_TCP_IPV6)); 3525 3526 if (IFCAP_TSO6 & if_getcapenable(ifp) && 3527 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 3528 mask &= ~IFCAP_TSO6; 3529 if_setcapenablebit(ifp, 0, IFCAP_TSO6); 3530 if_sethwassistbits(ifp, 0, CSUM_IP6_TSO); 3531 mlx5_en_err(ifp, 3532 "tso6 disabled due to -txcsum6.\n"); 3533 } 3534 } 3535 if (mask & IFCAP_MEXTPG) 3536 if_togglecapenable(ifp, IFCAP_MEXTPG); 3537 if (mask & IFCAP_TXTLS4) 3538 if_togglecapenable(ifp, IFCAP_TXTLS4); 3539 if (mask & IFCAP_TXTLS6) 3540 if_togglecapenable(ifp, IFCAP_TXTLS6); 3541 #ifdef RATELIMIT 3542 if (mask & IFCAP_TXTLS_RTLMT) 3543 if_togglecapenable(ifp, IFCAP_TXTLS_RTLMT); 3544 #endif 3545 if (mask & IFCAP_RXCSUM) 3546 if_togglecapenable(ifp, IFCAP_RXCSUM); 3547 if (mask & IFCAP_RXCSUM_IPV6) 3548 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6); 3549 if (mask & IFCAP_TSO4) { 3550 if (!(IFCAP_TSO4 & if_getcapenable(ifp)) && 3551 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 3552 mlx5_en_err(ifp, "enable txcsum first.\n"); 3553 error = EAGAIN; 3554 goto out; 3555 } 3556 if_togglecapenable(ifp, IFCAP_TSO4); 3557 if_togglehwassist(ifp, CSUM_IP_TSO); 3558 } 3559 if (mask & IFCAP_TSO6) { 3560 if (!(IFCAP_TSO6 & if_getcapenable(ifp)) && 3561 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 3562 mlx5_en_err(ifp, "enable txcsum6 first.\n"); 3563 error = EAGAIN; 3564 goto out; 3565 } 3566 if_togglecapenable(ifp, IFCAP_TSO6); 3567 if_togglehwassist(ifp, CSUM_IP6_TSO); 3568 } 3569 if (mask & IFCAP_VLAN_HWTSO) 3570 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3571 if (mask & IFCAP_VLAN_HWFILTER) { 3572 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3573 mlx5e_disable_vlan_filter(priv); 3574 else 3575 mlx5e_enable_vlan_filter(priv); 3576 3577 if_togglecapenable(ifp, IFCAP_VLAN_HWFILTER); 3578 } 3579 if (mask & IFCAP_VLAN_HWTAGGING) 3580 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3581 if (mask & IFCAP_WOL_MAGIC) 3582 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3583 if (mask & IFCAP_VXLAN_HWCSUM) { 3584 const bool was_enabled = 3585 (if_getcapenable(ifp) & IFCAP_VXLAN_HWCSUM) != 0; 3586 if (was_enabled) 3587 mlx5e_del_all_vxlan_rules(priv); 3588 if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM); 3589 if_togglehwassist(ifp, CSUM_INNER_IP | CSUM_INNER_IP_UDP | 3590 CSUM_INNER_IP_TCP | CSUM_INNER_IP6_UDP | 3591 CSUM_INNER_IP6_TCP); 3592 if (!was_enabled) { 3593 int err = mlx5e_add_all_vxlan_rules(priv); 3594 if (err != 0) { 3595 mlx5_en_err(ifp, 3596 "mlx5e_add_all_vxlan_rules() failed, %d (ignored)\n", err); 3597 } 3598 } 3599 } 3600 if (mask & IFCAP_VXLAN_HWTSO) { 3601 if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO); 3602 if_togglehwassist(ifp, CSUM_INNER_IP_TSO | 3603 CSUM_INNER_IP6_TSO); 3604 } 3605 3606 VLAN_CAPABILITIES(ifp); 3607 /* turn off LRO means also turn of HW LRO - if it's on */ 3608 if (mask & IFCAP_LRO) { 3609 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3610 bool need_restart = false; 3611 3612 if_togglecapenable(ifp, IFCAP_LRO); 3613 3614 /* figure out if updating HW LRO is needed */ 3615 if (!(if_getcapenable(ifp) & IFCAP_LRO)) { 3616 if (priv->params.hw_lro_en) { 3617 priv->params.hw_lro_en = false; 3618 need_restart = true; 3619 } 3620 } else { 3621 if (priv->params.hw_lro_en == false && 3622 priv->params_ethtool.hw_lro != 0) { 3623 priv->params.hw_lro_en = true; 3624 need_restart = true; 3625 } 3626 } 3627 if (was_opened && need_restart) { 3628 mlx5e_close_locked(ifp); 3629 mlx5e_open_locked(ifp); 3630 } 3631 } 3632 if (mask & IFCAP_HWRXTSTMP) { 3633 if_togglecapenable(ifp, IFCAP_HWRXTSTMP); 3634 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) { 3635 if (priv->clbr_done == 0) 3636 mlx5e_reset_calibration_callout(priv); 3637 } else { 3638 callout_drain(&priv->tstmp_clbr); 3639 priv->clbr_done = 0; 3640 } 3641 } 3642 mask = drv_ioctl_data->reqcap2 ^ if_getcapenable2(ifp); 3643 if ((mask & IFCAP2_BIT(IFCAP2_RXTLS4)) != 0) 3644 if_togglecapenable2(ifp, IFCAP2_BIT(IFCAP2_RXTLS4)); 3645 if ((mask & IFCAP2_BIT(IFCAP2_RXTLS6)) != 0) 3646 if_togglecapenable2(ifp, IFCAP2_BIT(IFCAP2_RXTLS6)); 3647 out: 3648 PRIV_UNLOCK(priv); 3649 break; 3650 3651 case SIOCGI2C: 3652 ifr = (struct ifreq *)data; 3653 3654 /* 3655 * Copy from the user-space address ifr_data to the 3656 * kernel-space address i2c 3657 */ 3658 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3659 if (error) 3660 break; 3661 3662 if (i2c.len > sizeof(i2c.data)) { 3663 error = EINVAL; 3664 break; 3665 } 3666 3667 PRIV_LOCK(priv); 3668 /* Get module_num which is required for the query_eeprom */ 3669 error = mlx5_query_module_num(priv->mdev, &module_num); 3670 if (error) { 3671 mlx5_en_err(ifp, 3672 "Query module num failed, eeprom reading is not supported\n"); 3673 error = EINVAL; 3674 goto err_i2c; 3675 } 3676 /* Check if module is present before doing an access */ 3677 module_status = mlx5_query_module_status(priv->mdev, module_num); 3678 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) { 3679 error = EINVAL; 3680 goto err_i2c; 3681 } 3682 /* 3683 * Currently 0XA0 and 0xA2 are the only addresses permitted. 3684 * The internal conversion is as follows: 3685 */ 3686 if (i2c.dev_addr == 0xA0) 3687 read_addr = MLX5_I2C_ADDR_LOW; 3688 else if (i2c.dev_addr == 0xA2) 3689 read_addr = MLX5_I2C_ADDR_HIGH; 3690 else { 3691 mlx5_en_err(ifp, 3692 "Query eeprom failed, Invalid Address: %X\n", 3693 i2c.dev_addr); 3694 error = EINVAL; 3695 goto err_i2c; 3696 } 3697 error = mlx5_query_eeprom(priv->mdev, 3698 read_addr, MLX5_EEPROM_LOW_PAGE, 3699 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 3700 (uint32_t *)i2c.data, &size_read); 3701 if (error) { 3702 mlx5_en_err(ifp, 3703 "Query eeprom failed, eeprom reading is not supported\n"); 3704 error = EINVAL; 3705 goto err_i2c; 3706 } 3707 3708 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 3709 error = mlx5_query_eeprom(priv->mdev, 3710 read_addr, MLX5_EEPROM_LOW_PAGE, 3711 (uint32_t)(i2c.offset + size_read), 3712 (uint32_t)(i2c.len - size_read), module_num, 3713 (uint32_t *)(i2c.data + size_read), &size_read); 3714 } 3715 if (error) { 3716 mlx5_en_err(ifp, 3717 "Query eeprom failed, eeprom reading is not supported\n"); 3718 error = EINVAL; 3719 goto err_i2c; 3720 } 3721 3722 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3723 err_i2c: 3724 PRIV_UNLOCK(priv); 3725 break; 3726 case SIOCGIFDOWNREASON: 3727 ifdr = (struct ifdownreason *)data; 3728 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3729 PRIV_LOCK(priv); 3730 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL, 3731 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3732 PRIV_UNLOCK(priv); 3733 if (error == 0) 3734 ifdr->ifdr_reason = IFDR_REASON_MSG; 3735 break; 3736 3737 case SIOCGIFRSSKEY: 3738 ifrk = (struct ifrsskey *)data; 3739 ifrk->ifrk_func = RSS_FUNC_TOEPLITZ; 3740 ifrk->ifrk_keylen = MLX5E_RSS_KEY_SIZE; 3741 CTASSERT(sizeof(ifrk->ifrk_key) >= MLX5E_RSS_KEY_SIZE); 3742 mlx5e_get_rss_key(ifrk->ifrk_key); 3743 break; 3744 3745 case SIOCGIFRSSHASH: 3746 ifrh = (struct ifrsshash *)data; 3747 ifrh->ifrh_func = RSS_FUNC_TOEPLITZ; 3748 ifrh->ifrh_types = 3749 RSS_TYPE_IPV4 | 3750 RSS_TYPE_TCP_IPV4 | 3751 RSS_TYPE_UDP_IPV4 | 3752 RSS_TYPE_IPV6 | 3753 RSS_TYPE_TCP_IPV6 | 3754 RSS_TYPE_UDP_IPV6; 3755 break; 3756 3757 default: 3758 error = ether_ioctl(ifp, command, data); 3759 break; 3760 } 3761 return (error); 3762 } 3763 3764 static int 3765 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 3766 { 3767 /* 3768 * TODO: uncoment once FW really sets all these bits if 3769 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 3770 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 3771 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 3772 * -ENOTSUPP; 3773 */ 3774 3775 /* TODO: add more must-to-have features */ 3776 3777 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 3778 return (-ENODEV); 3779 3780 return (0); 3781 } 3782 3783 static u16 3784 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) 3785 { 3786 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN; 3787 const int max_size = MLX5E_MAX_TX_INLINE; 3788 const int bf_buf_size = 3789 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) - 3790 (sizeof(struct mlx5e_tx_wqe) - 2); 3791 3792 /* verify against driver limits */ 3793 if (bf_buf_size > max_size) 3794 return (max_size); 3795 else if (bf_buf_size < min_size) 3796 return (min_size); 3797 else 3798 return (bf_buf_size); 3799 } 3800 3801 static int 3802 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 3803 struct mlx5e_priv *priv, 3804 int num_comp_vectors) 3805 { 3806 int err; 3807 3808 /* 3809 * TODO: Consider link speed for setting "log_sq_size", 3810 * "log_rq_size" and "cq_moderation_xxx": 3811 */ 3812 priv->params.log_sq_size = 3813 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 3814 priv->params.log_rq_size = 3815 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 3816 priv->params.rx_cq_moderation_usec = 3817 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 3818 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 3819 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 3820 priv->params.rx_cq_moderation_mode = 3821 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 3822 priv->params.rx_cq_moderation_pkts = 3823 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 3824 priv->params.tx_cq_moderation_usec = 3825 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 3826 priv->params.tx_cq_moderation_pkts = 3827 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 3828 priv->params.rx_hash_log_tbl_sz = 3829 (order_base_2(num_comp_vectors) > 3830 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 3831 order_base_2(num_comp_vectors) : 3832 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 3833 priv->params.num_tc = 1; 3834 priv->params.default_vlan_prio = 0; 3835 priv->counter_set_id = -1; 3836 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); 3837 3838 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode); 3839 if (err) 3840 return (err); 3841 3842 /* 3843 * hw lro is currently defaulted to off. when it won't anymore we 3844 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 3845 */ 3846 priv->params.hw_lro_en = false; 3847 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 3848 3849 /* 3850 * CQE zipping is off, because the per-packet 32-bit Toeplitz hash 3851 * is then not supported. The 32-bit Toeplitz hash is needed to 3852 * correctly demultiplex incoming traffic into the expected 3853 * network queues. 3854 */ 3855 priv->params.cqe_zipping_en = false; 3856 3857 priv->mdev = mdev; 3858 priv->params.num_channels = num_comp_vectors; 3859 priv->params.channels_rsss = 1; 3860 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 3861 priv->queue_mapping_channel_mask = 3862 roundup_pow_of_two(num_comp_vectors) - 1; 3863 priv->num_tc = priv->params.num_tc; 3864 priv->default_vlan_prio = priv->params.default_vlan_prio; 3865 3866 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 3867 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 3868 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 3869 3870 return (0); 3871 } 3872 3873 static void 3874 mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc) 3875 { 3876 bool ro_pci_enable = 3877 pci_get_relaxed_ordering_enabled(mdev->pdev->dev.bsddev); 3878 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write); 3879 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read); 3880 3881 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read); 3882 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write); 3883 } 3884 3885 static int 3886 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 3887 struct mlx5_core_mkey *mkey) 3888 { 3889 if_t ifp = priv->ifp; 3890 struct mlx5_core_dev *mdev = priv->mdev; 3891 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3892 void *mkc; 3893 u32 *in; 3894 int err; 3895 3896 in = mlx5_vzalloc(inlen); 3897 if (in == NULL) { 3898 mlx5_en_err(ifp, "failed to allocate inbox\n"); 3899 return (-ENOMEM); 3900 } 3901 3902 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3903 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA); 3904 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */ 3905 MLX5_SET(mkc, mkc, lw, 1); 3906 MLX5_SET(mkc, mkc, lr, 1); 3907 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 3908 MLX5_SET(mkc, mkc, pd, pdn); 3909 MLX5_SET(mkc, mkc, length64, 1); 3910 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3911 3912 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 3913 if (err) 3914 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n", 3915 err); 3916 3917 kvfree(in); 3918 return (err); 3919 } 3920 3921 static const char *mlx5e_vport_stats_desc[] = { 3922 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 3923 }; 3924 3925 static const char *mlx5e_pport_stats_desc[] = { 3926 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 3927 }; 3928 3929 static int 3930 mlx5e_priv_static_init(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev, 3931 const uint32_t channels) 3932 { 3933 uint32_t x; 3934 int err; 3935 3936 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 3937 sx_init(&priv->state_lock, "mlx5state"); 3938 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 3939 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 3940 for (x = 0; x != channels; x++) 3941 mlx5e_chan_static_init(priv, &priv->channel[x], x); 3942 3943 for (x = 0; x != channels; x++) { 3944 err = mlx5_alloc_bfreg(mdev, &priv->channel[x].bfreg, false, false); 3945 if (err) 3946 goto err_alloc_bfreg; 3947 } 3948 return (0); 3949 3950 err_alloc_bfreg: 3951 while (x--) 3952 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg); 3953 3954 for (x = 0; x != channels; x++) 3955 mlx5e_chan_static_destroy(&priv->channel[x]); 3956 callout_drain(&priv->watchdog); 3957 mtx_destroy(&priv->async_events_mtx); 3958 sx_destroy(&priv->state_lock); 3959 return (err); 3960 } 3961 3962 static void 3963 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev, 3964 const uint32_t channels) 3965 { 3966 uint32_t x; 3967 3968 for (x = 0; x != channels; x++) 3969 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg); 3970 for (x = 0; x != channels; x++) 3971 mlx5e_chan_static_destroy(&priv->channel[x]); 3972 callout_drain(&priv->watchdog); 3973 mtx_destroy(&priv->async_events_mtx); 3974 sx_destroy(&priv->state_lock); 3975 } 3976 3977 static int 3978 sysctl_firmware(SYSCTL_HANDLER_ARGS) 3979 { 3980 /* 3981 * %d.%d%.d the string format. 3982 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 3983 * We need at most 5 chars to store that. 3984 * It also has: two "." and NULL at the end, which means we need 18 3985 * (5*3 + 3) chars at most. 3986 */ 3987 char fw[18]; 3988 struct mlx5e_priv *priv = arg1; 3989 int error; 3990 3991 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 3992 fw_rev_sub(priv->mdev)); 3993 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 3994 return (error); 3995 } 3996 3997 static void 3998 mlx5e_disable_tx_dma(struct mlx5e_channel *ch) 3999 { 4000 int i; 4001 4002 for (i = 0; i < ch->priv->num_tc; i++) 4003 mlx5e_drain_sq(&ch->sq[i]); 4004 } 4005 4006 static void 4007 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq) 4008 { 4009 4010 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP); 4011 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8); 4012 mlx5e_tx_notify_hw(sq, true); 4013 } 4014 4015 void 4016 mlx5e_resume_sq(struct mlx5e_sq *sq) 4017 { 4018 int err; 4019 4020 /* check if already enabled */ 4021 if (READ_ONCE(sq->running) != 0) 4022 return; 4023 4024 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR, 4025 MLX5_SQC_STATE_RST); 4026 if (err != 0) { 4027 mlx5_en_err(sq->ifp, 4028 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err); 4029 } 4030 4031 sq->cc = 0; 4032 sq->pc = 0; 4033 4034 /* reset doorbell prior to moving from RST to RDY */ 4035 mlx5e_reset_sq_doorbell_record(sq); 4036 4037 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, 4038 MLX5_SQC_STATE_RDY); 4039 if (err != 0) { 4040 mlx5_en_err(sq->ifp, 4041 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err); 4042 } 4043 4044 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 4045 WRITE_ONCE(sq->running, 1); 4046 } 4047 4048 static void 4049 mlx5e_enable_tx_dma(struct mlx5e_channel *ch) 4050 { 4051 int i; 4052 4053 for (i = 0; i < ch->priv->num_tc; i++) 4054 mlx5e_resume_sq(&ch->sq[i]); 4055 } 4056 4057 static void 4058 mlx5e_disable_rx_dma(struct mlx5e_channel *ch) 4059 { 4060 struct mlx5e_rq *rq = &ch->rq; 4061 struct epoch_tracker et; 4062 int err; 4063 4064 mtx_lock(&rq->mtx); 4065 rq->enabled = 0; 4066 callout_stop(&rq->watchdog); 4067 mtx_unlock(&rq->mtx); 4068 4069 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 4070 if (err != 0) { 4071 mlx5_en_err(rq->ifp, 4072 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err); 4073 } 4074 4075 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 4076 msleep(1); 4077 NET_EPOCH_ENTER(et); 4078 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 4079 NET_EPOCH_EXIT(et); 4080 } 4081 4082 /* 4083 * Transitioning into RST state will allow the FW to track less ERR state queues, 4084 * thus reducing the recv queue flushing time 4085 */ 4086 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST); 4087 if (err != 0) { 4088 mlx5_en_err(rq->ifp, 4089 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err); 4090 } 4091 } 4092 4093 static void 4094 mlx5e_enable_rx_dma(struct mlx5e_channel *ch) 4095 { 4096 struct mlx5e_rq *rq = &ch->rq; 4097 struct epoch_tracker et; 4098 int err; 4099 4100 rq->wq.wqe_ctr = 0; 4101 mlx5_wq_ll_update_db_record(&rq->wq); 4102 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 4103 if (err != 0) { 4104 mlx5_en_err(rq->ifp, 4105 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err); 4106 } 4107 4108 rq->enabled = 1; 4109 4110 NET_EPOCH_ENTER(et); 4111 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 4112 NET_EPOCH_EXIT(et); 4113 } 4114 4115 void 4116 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value) 4117 { 4118 int i; 4119 4120 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 4121 return; 4122 4123 for (i = 0; i < priv->params.num_channels; i++) { 4124 if (value) 4125 mlx5e_disable_tx_dma(&priv->channel[i]); 4126 else 4127 mlx5e_enable_tx_dma(&priv->channel[i]); 4128 } 4129 } 4130 4131 void 4132 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value) 4133 { 4134 int i; 4135 4136 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 4137 return; 4138 4139 for (i = 0; i < priv->params.num_channels; i++) { 4140 if (value) 4141 mlx5e_disable_rx_dma(&priv->channel[i]); 4142 else 4143 mlx5e_enable_rx_dma(&priv->channel[i]); 4144 } 4145 } 4146 4147 static void 4148 mlx5e_add_hw_stats(struct mlx5e_priv *priv) 4149 { 4150 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 4151 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 4152 priv, 0, sysctl_firmware, "A", "HCA firmware version"); 4153 4154 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 4155 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 4156 "Board ID"); 4157 } 4158 4159 static int 4160 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS) 4161 { 4162 struct mlx5e_priv *priv = arg1; 4163 uint8_t temp[MLX5E_MAX_PRIORITY]; 4164 uint32_t tx_pfc; 4165 int err; 4166 int i; 4167 4168 PRIV_LOCK(priv); 4169 4170 tx_pfc = priv->params.tx_priority_flow_control; 4171 4172 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4173 temp[i] = (tx_pfc >> i) & 1; 4174 4175 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4176 if (err || !req->newptr) 4177 goto done; 4178 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4179 if (err) 4180 goto done; 4181 4182 priv->params.tx_priority_flow_control = 0; 4183 4184 /* range check input value */ 4185 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4186 if (temp[i] > 1) { 4187 err = ERANGE; 4188 goto done; 4189 } 4190 priv->params.tx_priority_flow_control |= (temp[i] << i); 4191 } 4192 4193 /* check if update is required */ 4194 if (tx_pfc != priv->params.tx_priority_flow_control) 4195 err = -mlx5e_set_port_pfc(priv); 4196 done: 4197 if (err != 0) 4198 priv->params.tx_priority_flow_control= tx_pfc; 4199 PRIV_UNLOCK(priv); 4200 4201 return (err); 4202 } 4203 4204 static int 4205 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS) 4206 { 4207 struct mlx5e_priv *priv = arg1; 4208 uint8_t temp[MLX5E_MAX_PRIORITY]; 4209 uint32_t rx_pfc; 4210 int err; 4211 int i; 4212 4213 PRIV_LOCK(priv); 4214 4215 rx_pfc = priv->params.rx_priority_flow_control; 4216 4217 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4218 temp[i] = (rx_pfc >> i) & 1; 4219 4220 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4221 if (err || !req->newptr) 4222 goto done; 4223 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4224 if (err) 4225 goto done; 4226 4227 priv->params.rx_priority_flow_control = 0; 4228 4229 /* range check input value */ 4230 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4231 if (temp[i] > 1) { 4232 err = ERANGE; 4233 goto done; 4234 } 4235 priv->params.rx_priority_flow_control |= (temp[i] << i); 4236 } 4237 4238 /* check if update is required */ 4239 if (rx_pfc != priv->params.rx_priority_flow_control) { 4240 err = -mlx5e_set_port_pfc(priv); 4241 if (err == 0 && priv->sw_is_port_buf_owner) 4242 err = mlx5e_update_buf_lossy(priv); 4243 } 4244 done: 4245 if (err != 0) 4246 priv->params.rx_priority_flow_control= rx_pfc; 4247 PRIV_UNLOCK(priv); 4248 4249 return (err); 4250 } 4251 4252 static void 4253 mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 4254 { 4255 int error; 4256 4257 /* enable pauseframes by default */ 4258 priv->params.tx_pauseframe_control = 1; 4259 priv->params.rx_pauseframe_control = 1; 4260 4261 /* disable ports flow control, PFC, by default */ 4262 priv->params.tx_priority_flow_control = 0; 4263 priv->params.rx_priority_flow_control = 0; 4264 4265 /* register pauseframe SYSCTLs */ 4266 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4267 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 4268 &priv->params.tx_pauseframe_control, 0, 4269 "Set to enable TX pause frames. Clear to disable."); 4270 4271 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4272 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 4273 &priv->params.rx_pauseframe_control, 0, 4274 "Set to enable RX pause frames. Clear to disable."); 4275 4276 /* register priority flow control, PFC, SYSCTLs */ 4277 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4278 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4279 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU", 4280 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable."); 4281 4282 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4283 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4284 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU", 4285 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable."); 4286 4287 PRIV_LOCK(priv); 4288 4289 /* range check */ 4290 priv->params.tx_pauseframe_control = 4291 priv->params.tx_pauseframe_control ? 1 : 0; 4292 priv->params.rx_pauseframe_control = 4293 priv->params.rx_pauseframe_control ? 1 : 0; 4294 4295 /* update firmware */ 4296 error = mlx5e_set_port_pause_and_pfc(priv); 4297 if (error == -EINVAL) { 4298 mlx5_en_err(priv->ifp, 4299 "Global pauseframes must be disabled before enabling PFC.\n"); 4300 priv->params.rx_priority_flow_control = 0; 4301 priv->params.tx_priority_flow_control = 0; 4302 4303 /* update firmware */ 4304 (void) mlx5e_set_port_pause_and_pfc(priv); 4305 } 4306 PRIV_UNLOCK(priv); 4307 } 4308 4309 static int 4310 mlx5e_ul_snd_tag_alloc(if_t ifp, 4311 union if_snd_tag_alloc_params *params, 4312 struct m_snd_tag **ppmt) 4313 { 4314 struct mlx5e_priv *priv; 4315 struct mlx5e_channel *pch; 4316 4317 priv = if_getsoftc(ifp); 4318 4319 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) { 4320 return (EOPNOTSUPP); 4321 } else { 4322 /* keep this code synced with mlx5e_select_queue() */ 4323 u32 ch = priv->params.num_channels; 4324 #ifdef RSS 4325 u32 temp; 4326 4327 if (rss_hash2bucket(params->hdr.flowid, 4328 params->hdr.flowtype, &temp) == 0) 4329 ch = temp % ch; 4330 else 4331 #endif 4332 ch = (params->hdr.flowid % 128) % ch; 4333 4334 /* 4335 * NOTE: The channels array is only freed at detach 4336 * and it safe to return a pointer to the send tag 4337 * inside the channels structure as long as we 4338 * reference the priv. 4339 */ 4340 pch = priv->channel + ch; 4341 4342 /* check if send queue is not running */ 4343 if (unlikely(pch->sq[0].running == 0)) 4344 return (ENXIO); 4345 m_snd_tag_ref(&pch->tag); 4346 *ppmt = &pch->tag; 4347 return (0); 4348 } 4349 } 4350 4351 static int 4352 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4353 { 4354 struct mlx5e_channel *pch = 4355 container_of(pmt, struct mlx5e_channel, tag); 4356 4357 params->unlimited.max_rate = -1ULL; 4358 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]); 4359 return (0); 4360 } 4361 4362 static void 4363 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt) 4364 { 4365 struct mlx5e_channel *pch = 4366 container_of(pmt, struct mlx5e_channel, tag); 4367 4368 complete(&pch->completion); 4369 } 4370 4371 static int 4372 mlx5e_snd_tag_alloc(if_t ifp, 4373 union if_snd_tag_alloc_params *params, 4374 struct m_snd_tag **ppmt) 4375 { 4376 4377 switch (params->hdr.type) { 4378 #ifdef RATELIMIT 4379 case IF_SND_TAG_TYPE_RATE_LIMIT: 4380 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt)); 4381 #ifdef KERN_TLS 4382 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4383 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4384 #endif 4385 #endif 4386 case IF_SND_TAG_TYPE_UNLIMITED: 4387 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt)); 4388 #ifdef KERN_TLS 4389 case IF_SND_TAG_TYPE_TLS: 4390 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4391 case IF_SND_TAG_TYPE_TLS_RX: 4392 return (mlx5e_tls_rx_snd_tag_alloc(ifp, params, ppmt)); 4393 #endif 4394 default: 4395 return (EOPNOTSUPP); 4396 } 4397 } 4398 4399 #ifdef RATELIMIT 4400 #define NUM_HDWR_RATES_MLX 13 4401 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = { 4402 135375, /* 1,083,000 */ 4403 180500, /* 1,444,000 */ 4404 270750, /* 2,166,000 */ 4405 361000, /* 2,888,000 */ 4406 541500, /* 4,332,000 */ 4407 721875, /* 5,775,000 */ 4408 1082875, /* 8,663,000 */ 4409 1443875, /* 11,551,000 */ 4410 2165750, /* 17,326,000 */ 4411 2887750, /* 23,102,000 */ 4412 4331625, /* 34,653,000 */ 4413 5775500, /* 46,204,000 */ 4414 8663125 /* 69,305,000 */ 4415 }; 4416 4417 static void 4418 mlx5e_ratelimit_query(if_t ifp __unused, struct if_ratelimit_query_results *q) 4419 { 4420 /* 4421 * This function needs updating by the driver maintainer! 4422 * For the MLX card there are currently (ConectX-4?) 13 4423 * pre-set rates and others i.e. ConnectX-5, 6, 7?? 4424 * 4425 * This will change based on later adapters 4426 * and this code should be updated to look at ifp 4427 * and figure out the specific adapter type 4428 * settings i.e. how many rates as well 4429 * as if they are fixed (as is shown here) or 4430 * if they are dynamic (example chelsio t4). Also if there 4431 * is a maximum number of flows that the adapter 4432 * can handle that too needs to be updated in 4433 * the max_flows field. 4434 */ 4435 q->rate_table = adapter_rates_mlx; 4436 q->flags = RT_IS_FIXED_TABLE; 4437 q->max_flows = 0; /* mlx has no limit */ 4438 q->number_of_rates = NUM_HDWR_RATES_MLX; 4439 q->min_segment_burst = 1; 4440 } 4441 #endif 4442 4443 static void 4444 mlx5e_ifm_add(struct mlx5e_priv *priv, int type) 4445 { 4446 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL); 4447 ifmedia_add(&priv->media, type | IFM_ETHER | 4448 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4449 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL); 4450 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL); 4451 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL); 4452 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4453 IFM_ETH_RXPAUSE, 0, NULL); 4454 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4455 IFM_ETH_TXPAUSE, 0, NULL); 4456 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4457 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4458 } 4459 4460 static void * 4461 mlx5e_create_ifp(struct mlx5_core_dev *mdev) 4462 { 4463 if_t ifp; 4464 struct mlx5e_priv *priv; 4465 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 4466 struct sysctl_oid_list *child; 4467 int ncv = mdev->priv.eq_table.num_comp_vectors; 4468 char unit[16]; 4469 struct pfil_head_args pa; 4470 int err; 4471 u32 eth_proto_cap; 4472 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 4473 bool ext; 4474 struct media media_entry = {}; 4475 4476 if (mlx5e_check_required_hca_cap(mdev)) { 4477 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 4478 return (NULL); 4479 } 4480 4481 /* 4482 * Try to allocate the priv and make room for worst-case 4483 * number of channel structures: 4484 */ 4485 priv = malloc_domainset(sizeof(*priv) + 4486 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors), 4487 M_MLX5EN, mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO); 4488 4489 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev); 4490 if (ifp == NULL) { 4491 mlx5_core_err(mdev, "if_alloc() failed\n"); 4492 goto err_free_priv; 4493 } 4494 /* setup all static fields */ 4495 if (mlx5e_priv_static_init(priv, mdev, mdev->priv.eq_table.num_comp_vectors)) { 4496 mlx5_core_err(mdev, "mlx5e_priv_static_init() failed\n"); 4497 goto err_free_ifp; 4498 } 4499 4500 if_setsoftc(ifp, priv); 4501 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev)); 4502 if_setmtu(ifp, ETHERMTU); 4503 if_setinitfn(ifp, mlx5e_open); 4504 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4505 if_setioctlfn(ifp, mlx5e_ioctl); 4506 if_settransmitfn(ifp, mlx5e_xmit); 4507 if_setqflushfn(ifp, if_qflush); 4508 if_setgetcounterfn(ifp, mlx5e_get_counter); 4509 if_setsendqlen(ifp, ifqmaxlen); 4510 /* 4511 * Set driver features 4512 */ 4513 if_setcapabilities(ifp, IFCAP_NV); 4514 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6, 0); 4515 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0); 4516 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER, 0); 4517 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE | IFCAP_JUMBO_MTU, 0); 4518 if_setcapabilitiesbit(ifp, IFCAP_LRO, 0); 4519 if_setcapabilitiesbit(ifp, IFCAP_TSO | IFCAP_VLAN_HWTSO, 0); 4520 if_setcapabilitiesbit(ifp, IFCAP_HWSTATS | IFCAP_HWRXTSTMP, 0); 4521 if_setcapabilitiesbit(ifp, IFCAP_MEXTPG, 0); 4522 if_setcapabilitiesbit(ifp, IFCAP_TXTLS4 | IFCAP_TXTLS6, 0); 4523 #ifdef RATELIMIT 4524 if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT | IFCAP_TXTLS_RTLMT, 0); 4525 #endif 4526 if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 4527 if_setcapabilities2bit(ifp, IFCAP2_BIT(IFCAP2_RXTLS4) | 4528 IFCAP2_BIT(IFCAP2_RXTLS6), 0); 4529 if_setsndtagallocfn(ifp, mlx5e_snd_tag_alloc); 4530 #ifdef RATELIMIT 4531 if_setratelimitqueryfn(ifp, mlx5e_ratelimit_query); 4532 #endif 4533 /* set TSO limits so that we don't have to drop TX packets */ 4534 if_sethwtsomax(ifp, MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)); 4535 if_sethwtsomaxsegcount(ifp, MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */); 4536 if_sethwtsomaxsegsize(ifp, MLX5E_MAX_TX_MBUF_SIZE); 4537 4538 if_setcapenable(ifp, if_getcapabilities(ifp)); 4539 if_setcapenable2(ifp, if_getcapabilities2(ifp)); 4540 if_sethwassist(ifp, 0); 4541 if (if_getcapenable(ifp) & IFCAP_TSO) 4542 if_sethwassistbits(ifp, CSUM_TSO, 0); 4543 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 4544 if_sethwassistbits(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP), 0); 4545 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 4546 if_sethwassistbits(ifp, (CSUM_UDP_IPV6 | CSUM_TCP_IPV6), 0); 4547 if (if_getcapabilities(ifp) & IFCAP_VXLAN_HWCSUM) 4548 if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 4549 CSUM_INNER_IP | CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | 4550 CSUM_ENCAP_VXLAN, 0); 4551 if (if_getcapabilities(ifp) & IFCAP_VXLAN_HWTSO) 4552 if_sethwassistbits(ifp, CSUM_INNER_IP6_TSO | CSUM_INNER_IP_TSO, 0); 4553 4554 /* ifnet sysctl tree */ 4555 sysctl_ctx_init(&priv->sysctl_ctx); 4556 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 4557 OID_AUTO, if_getdname(ifp), CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4558 "MLX5 ethernet - interface name"); 4559 if (priv->sysctl_ifnet == NULL) { 4560 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4561 goto err_free_sysctl; 4562 } 4563 snprintf(unit, sizeof(unit), "%d", if_getdunit(ifp)); 4564 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4565 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4566 "MLX5 ethernet - interface unit"); 4567 if (priv->sysctl_ifnet == NULL) { 4568 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4569 goto err_free_sysctl; 4570 } 4571 4572 /* HW sysctl tree */ 4573 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 4574 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 4575 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4576 "MLX5 ethernet dev hw"); 4577 if (priv->sysctl_hw == NULL) { 4578 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4579 goto err_free_sysctl; 4580 } 4581 4582 err = mlx5e_build_ifp_priv(mdev, priv, ncv); 4583 if (err) { 4584 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err); 4585 goto err_free_sysctl; 4586 } 4587 4588 /* reuse mlx5core's watchdog workqueue */ 4589 priv->wq = mdev->priv.health.wq_watchdog; 4590 4591 err = mlx5_core_alloc_pd(mdev, &priv->pdn, 0); 4592 if (err) { 4593 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err); 4594 goto err_free_wq; 4595 } 4596 err = mlx5_alloc_transport_domain(mdev, &priv->tdn, 0); 4597 if (err) { 4598 mlx5_en_err(ifp, 4599 "mlx5_alloc_transport_domain failed, %d\n", err); 4600 goto err_dealloc_pd; 4601 } 4602 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 4603 if (err) { 4604 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err); 4605 goto err_dealloc_transport_domain; 4606 } 4607 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 4608 4609 /* check if we should generate a random MAC address */ 4610 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 4611 is_zero_ether_addr(dev_addr)) { 4612 random_ether_addr(dev_addr); 4613 mlx5_en_err(ifp, "Assigned random MAC address\n"); 4614 } 4615 4616 err = mlx5e_rl_init(priv); 4617 if (err) { 4618 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err); 4619 goto err_create_mkey; 4620 } 4621 4622 err = mlx5e_tls_init(priv); 4623 if (err) { 4624 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__); 4625 goto err_rl_init; 4626 } 4627 4628 err = mlx5e_open_drop_rq(priv, &priv->drop_rq); 4629 if (err) { 4630 if_printf(ifp, "%s: mlx5e_open_drop_rq failed (%d)\n", __func__, err); 4631 goto err_tls_init; 4632 } 4633 4634 err = mlx5e_open_rqts(priv); 4635 if (err) { 4636 if_printf(ifp, "%s: mlx5e_open_rqts failed (%d)\n", __func__, err); 4637 goto err_open_drop_rq; 4638 } 4639 4640 err = mlx5e_open_tirs(priv); 4641 if (err) { 4642 mlx5_en_err(ifp, "mlx5e_open_tirs() failed, %d\n", err); 4643 goto err_open_rqts; 4644 } 4645 4646 err = mlx5e_open_flow_tables(priv); 4647 if (err) { 4648 if_printf(ifp, "%s: mlx5e_open_flow_tables failed (%d)\n", __func__, err); 4649 goto err_open_tirs; 4650 } 4651 4652 err = mlx5e_tls_rx_init(priv); 4653 if (err) { 4654 if_printf(ifp, "%s: mlx5e_tls_rx_init() failed, %d\n", __func__, err); 4655 goto err_open_flow_tables; 4656 } 4657 4658 /* set default MTU */ 4659 mlx5e_set_dev_port_mtu(ifp, if_getmtu(ifp)); 4660 4661 /* Set default media status */ 4662 priv->media_status_last = IFM_AVALID; 4663 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX; 4664 4665 /* setup default pauseframes configuration */ 4666 mlx5e_setup_pauseframes(priv); 4667 4668 /* Setup supported medias */ 4669 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) { 4670 ext = MLX5_CAP_PCAM_FEATURE(mdev, 4671 ptys_extended_ethernet); 4672 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 4673 eth_proto_capability); 4674 } else { 4675 ext = false; 4676 eth_proto_cap = 0; 4677 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err); 4678 } 4679 4680 ifmedia_init(&priv->media, IFM_IMASK, 4681 mlx5e_media_change, mlx5e_media_status); 4682 4683 if (ext) { 4684 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) { 4685 /* check if hardware has the right capability */ 4686 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap) 4687 continue; 4688 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) { 4689 media_entry = mlx5e_ext_mode_table[i][j]; 4690 if (media_entry.subtype == 0) 4691 continue; 4692 /* check if this subtype was already added */ 4693 for (unsigned k = 0; k != i; k++) { 4694 /* check if hardware has the right capability */ 4695 if (MLX5E_PROT_MASK(k) & ~eth_proto_cap) 4696 continue; 4697 for (unsigned m = 0; m != MLX5E_CABLE_TYPE_NUMBER; m++) { 4698 if (media_entry.subtype == mlx5e_ext_mode_table[k][m].subtype) 4699 goto skip_ext_media; 4700 } 4701 } 4702 mlx5e_ifm_add(priv, media_entry.subtype); 4703 skip_ext_media:; 4704 } 4705 } 4706 } else { 4707 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) { 4708 media_entry = mlx5e_mode_table[i]; 4709 if (media_entry.subtype == 0) 4710 continue; 4711 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap) 4712 continue; 4713 /* check if this subtype was already added */ 4714 for (unsigned k = 0; k != i; k++) { 4715 if (media_entry.subtype == mlx5e_mode_table[k].subtype) 4716 goto skip_media; 4717 } 4718 mlx5e_ifm_add(priv, media_entry.subtype); 4719 4720 /* NOTE: 10G ER and LR shares the same entry */ 4721 if (media_entry.subtype == IFM_10G_ER) 4722 mlx5e_ifm_add(priv, IFM_10G_LR); 4723 skip_media:; 4724 } 4725 } 4726 4727 mlx5e_ifm_add(priv, IFM_AUTO); 4728 4729 /* Set autoselect by default */ 4730 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4731 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 4732 4733 DEBUGNET_SET(ifp, mlx5_en); 4734 4735 ether_ifattach(ifp, dev_addr); 4736 4737 /* Register for VLAN events */ 4738 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 4739 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 4740 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 4741 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 4742 4743 /* Register for VxLAN events */ 4744 priv->vxlan_start = EVENTHANDLER_REGISTER(vxlan_start, 4745 mlx5e_vxlan_start, priv, EVENTHANDLER_PRI_ANY); 4746 priv->vxlan_stop = EVENTHANDLER_REGISTER(vxlan_stop, 4747 mlx5e_vxlan_stop, priv, EVENTHANDLER_PRI_ANY); 4748 4749 /* Link is down by default */ 4750 if_link_state_change(ifp, LINK_STATE_DOWN); 4751 4752 mlx5e_enable_async_events(priv); 4753 4754 mlx5e_add_hw_stats(priv); 4755 4756 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4757 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 4758 priv->stats.vport.arg); 4759 4760 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4761 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 4762 priv->stats.pport.arg); 4763 4764 mlx5e_create_ethtool(priv); 4765 4766 mtx_lock(&priv->async_events_mtx); 4767 mlx5e_update_stats(priv); 4768 mtx_unlock(&priv->async_events_mtx); 4769 4770 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4771 OID_AUTO, "rx_clbr_done", CTLFLAG_RD, 4772 &priv->clbr_done, 0, 4773 "RX timestamps calibration state"); 4774 callout_init(&priv->tstmp_clbr, 1); 4775 /* Pull out the frequency of the clock in hz */ 4776 priv->cclk = (uint64_t)MLX5_CAP_GEN(mdev, device_frequency_khz) * 1000ULL; 4777 mlx5e_reset_calibration_callout(priv); 4778 4779 pa.pa_version = PFIL_VERSION; 4780 pa.pa_flags = PFIL_IN; 4781 pa.pa_type = PFIL_TYPE_ETHERNET; 4782 pa.pa_headname = if_name(ifp); 4783 priv->pfil = pfil_head_register(&pa); 4784 4785 PRIV_LOCK(priv); 4786 err = mlx5e_open_flow_rules(priv); 4787 if (err) { 4788 mlx5_en_err(ifp, 4789 "mlx5e_open_flow_rules() failed, %d (ignored)\n", err); 4790 } 4791 PRIV_UNLOCK(priv); 4792 4793 return (priv); 4794 4795 err_open_flow_tables: 4796 mlx5e_close_flow_tables(priv); 4797 4798 err_open_tirs: 4799 mlx5e_close_tirs(priv); 4800 4801 err_open_rqts: 4802 mlx5e_close_rqts(priv); 4803 4804 err_open_drop_rq: 4805 mlx5e_close_drop_rq(&priv->drop_rq); 4806 4807 err_tls_init: 4808 mlx5e_tls_cleanup(priv); 4809 4810 err_rl_init: 4811 mlx5e_rl_cleanup(priv); 4812 4813 err_create_mkey: 4814 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4815 4816 err_dealloc_transport_domain: 4817 mlx5_dealloc_transport_domain(mdev, priv->tdn, 0); 4818 4819 err_dealloc_pd: 4820 mlx5_core_dealloc_pd(mdev, priv->pdn, 0); 4821 4822 err_free_wq: 4823 flush_workqueue(priv->wq); 4824 4825 err_free_sysctl: 4826 sysctl_ctx_free(&priv->sysctl_ctx); 4827 if (priv->sysctl_debug) 4828 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4829 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors); 4830 4831 err_free_ifp: 4832 if_free(ifp); 4833 4834 err_free_priv: 4835 free(priv, M_MLX5EN); 4836 return (NULL); 4837 } 4838 4839 static void 4840 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 4841 { 4842 struct mlx5e_priv *priv = vpriv; 4843 if_t ifp = priv->ifp; 4844 4845 /* don't allow more IOCTLs */ 4846 priv->gone = 1; 4847 4848 /* XXX wait a bit to allow IOCTL handlers to complete */ 4849 pause("W", hz); 4850 4851 #ifdef RATELIMIT 4852 /* 4853 * The kernel can have reference(s) via the m_snd_tag's into 4854 * the ratelimit channels, and these must go away before 4855 * detaching: 4856 */ 4857 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) { 4858 mlx5_en_err(priv->ifp, 4859 "Waiting for all ratelimit connections to terminate\n"); 4860 pause("W", hz); 4861 } 4862 #endif 4863 4864 #ifdef KERN_TLS 4865 /* wait for all TLS tags to get freed */ 4866 while (priv->tls.init != 0 && 4867 uma_zone_get_cur(priv->tls.zone) != 0) { 4868 mlx5_en_err(priv->ifp, 4869 "Waiting for all TLS connections to terminate\n"); 4870 pause("W", hz); 4871 } 4872 4873 /* wait for all TLS RX tags to get freed */ 4874 while (priv->tls_rx.init != 0 && 4875 uma_zone_get_cur(priv->tls_rx.zone) != 0) { 4876 mlx5_en_err(priv->ifp, 4877 "Waiting for all TLS RX connections to terminate\n"); 4878 pause("W", hz); 4879 } 4880 #endif 4881 /* wait for all unlimited send tags to complete */ 4882 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors); 4883 4884 /* stop watchdog timer */ 4885 callout_drain(&priv->watchdog); 4886 4887 callout_drain(&priv->tstmp_clbr); 4888 4889 if (priv->vlan_attach != NULL) 4890 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 4891 if (priv->vlan_detach != NULL) 4892 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 4893 if (priv->vxlan_start != NULL) 4894 EVENTHANDLER_DEREGISTER(vxlan_start, priv->vxlan_start); 4895 if (priv->vxlan_stop != NULL) 4896 EVENTHANDLER_DEREGISTER(vxlan_stop, priv->vxlan_stop); 4897 4898 /* make sure device gets closed */ 4899 PRIV_LOCK(priv); 4900 mlx5e_close_locked(ifp); 4901 mlx5e_close_flow_rules(priv); 4902 PRIV_UNLOCK(priv); 4903 4904 /* deregister pfil */ 4905 if (priv->pfil != NULL) { 4906 pfil_head_unregister(priv->pfil); 4907 priv->pfil = NULL; 4908 } 4909 4910 /* unregister device */ 4911 ifmedia_removeall(&priv->media); 4912 ether_ifdetach(ifp); 4913 4914 mlx5e_tls_rx_cleanup(priv); 4915 mlx5e_close_flow_tables(priv); 4916 mlx5e_close_tirs(priv); 4917 mlx5e_close_rqts(priv); 4918 mlx5e_close_drop_rq(&priv->drop_rq); 4919 mlx5e_tls_cleanup(priv); 4920 mlx5e_rl_cleanup(priv); 4921 4922 /* destroy all remaining sysctl nodes */ 4923 sysctl_ctx_free(&priv->stats.vport.ctx); 4924 sysctl_ctx_free(&priv->stats.pport.ctx); 4925 if (priv->sysctl_debug) 4926 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4927 sysctl_ctx_free(&priv->sysctl_ctx); 4928 4929 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4930 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn, 0); 4931 mlx5_core_dealloc_pd(priv->mdev, priv->pdn, 0); 4932 mlx5e_disable_async_events(priv); 4933 flush_workqueue(priv->wq); 4934 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors); 4935 if_free(ifp); 4936 free(priv, M_MLX5EN); 4937 } 4938 4939 #ifdef DEBUGNET 4940 static void 4941 mlx5_en_debugnet_init(if_t dev, int *nrxr, int *ncl, int *clsize) 4942 { 4943 struct mlx5e_priv *priv = if_getsoftc(dev); 4944 4945 PRIV_LOCK(priv); 4946 *nrxr = priv->params.num_channels; 4947 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4948 *clsize = MLX5E_MAX_RX_BYTES; 4949 PRIV_UNLOCK(priv); 4950 } 4951 4952 static void 4953 mlx5_en_debugnet_event(if_t dev, enum debugnet_ev event) 4954 { 4955 } 4956 4957 static int 4958 mlx5_en_debugnet_transmit(if_t dev, struct mbuf *m) 4959 { 4960 struct mlx5e_priv *priv = if_getsoftc(dev); 4961 struct mlx5e_sq *sq; 4962 int err; 4963 4964 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4965 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0) 4966 return (ENOENT); 4967 4968 sq = &priv->channel[0].sq[0]; 4969 4970 if (sq->running == 0) { 4971 m_freem(m); 4972 return (ENOENT); 4973 } 4974 4975 if (mlx5e_sq_xmit(sq, &m) != 0) { 4976 m_freem(m); 4977 err = ENOBUFS; 4978 } else { 4979 err = 0; 4980 } 4981 4982 mlx5e_tx_notify_hw(sq, true); 4983 4984 return (err); 4985 } 4986 4987 static int 4988 mlx5_en_debugnet_poll(if_t dev, int count) 4989 { 4990 struct mlx5e_priv *priv = if_getsoftc(dev); 4991 4992 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 || 4993 (priv->media_status_last & IFM_ACTIVE) == 0) 4994 return (ENOENT); 4995 4996 mlx5_poll_interrupts(priv->mdev); 4997 4998 return (0); 4999 } 5000 #endif /* DEBUGNET */ 5001 5002 static void * 5003 mlx5e_get_ifp(void *vpriv) 5004 { 5005 struct mlx5e_priv *priv = vpriv; 5006 5007 return (priv->ifp); 5008 } 5009 5010 static struct mlx5_interface mlx5e_interface = { 5011 .add = mlx5e_create_ifp, 5012 .remove = mlx5e_destroy_ifp, 5013 .event = mlx5e_async_event, 5014 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 5015 .get_dev = mlx5e_get_ifp, 5016 }; 5017 5018 void 5019 mlx5e_init(void) 5020 { 5021 mlx5_register_interface(&mlx5e_interface); 5022 } 5023 5024 void 5025 mlx5e_cleanup(void) 5026 { 5027 mlx5_unregister_interface(&mlx5e_interface); 5028 } 5029 5030 module_init_order(mlx5e_init, SI_ORDER_SIXTH); 5031 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH); 5032 5033 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 5034 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 5035 MODULE_VERSION(mlx5en, 1); 5036