1e9dcd831SSlava Shwartsman /*- 2e9dcd831SSlava Shwartsman * Copyright (c) 2017 Mellanox Technologies. All rights reserved. 3e9dcd831SSlava Shwartsman * 4e9dcd831SSlava Shwartsman * This software is available to you under a choice of one of two 5e9dcd831SSlava Shwartsman * licenses. You may choose to be licensed under the terms of the GNU 6e9dcd831SSlava Shwartsman * General Public License (GPL) Version 2, available from the file 7e9dcd831SSlava Shwartsman * COPYING in the main directory of this source tree, or the 8e9dcd831SSlava Shwartsman * OpenIB.org BSD license below: 9e9dcd831SSlava Shwartsman * 10e9dcd831SSlava Shwartsman * Redistribution and use in source and binary forms, with or 11e9dcd831SSlava Shwartsman * without modification, are permitted provided that the following 12e9dcd831SSlava Shwartsman * conditions are met: 13e9dcd831SSlava Shwartsman * 14e9dcd831SSlava Shwartsman * - Redistributions of source code must retain the above 15e9dcd831SSlava Shwartsman * copyright notice, this list of conditions and the following 16e9dcd831SSlava Shwartsman * disclaimer. 17e9dcd831SSlava Shwartsman * 18e9dcd831SSlava Shwartsman * - Redistributions in binary form must reproduce the above 19e9dcd831SSlava Shwartsman * copyright notice, this list of conditions and the following 20e9dcd831SSlava Shwartsman * disclaimer in the documentation and/or other materials 21e9dcd831SSlava Shwartsman * provided with the distribution. 22e9dcd831SSlava Shwartsman * 23e9dcd831SSlava Shwartsman * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e9dcd831SSlava Shwartsman * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e9dcd831SSlava Shwartsman * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e9dcd831SSlava Shwartsman * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e9dcd831SSlava Shwartsman * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e9dcd831SSlava Shwartsman * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e9dcd831SSlava Shwartsman * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e9dcd831SSlava Shwartsman * SOFTWARE. 31e9dcd831SSlava Shwartsman * 32e9dcd831SSlava Shwartsman * $FreeBSD$ 33e9dcd831SSlava Shwartsman */ 34e9dcd831SSlava Shwartsman 35e9dcd831SSlava Shwartsman #include <dev/mlx5/driver.h> 36e9dcd831SSlava Shwartsman 37e9dcd831SSlava Shwartsman #include <dev/mlx5/mlx5_core/mlx5_core.h> 38e9dcd831SSlava Shwartsman #include <dev/mlx5/mlx5_fpga/ipsec.h> 39e9dcd831SSlava Shwartsman #include <dev/mlx5/mlx5_fpga/sdk.h> 40e9dcd831SSlava Shwartsman #include <dev/mlx5/mlx5_fpga/core.h> 41e9dcd831SSlava Shwartsman 42e9dcd831SSlava Shwartsman #define SBU_QP_QUEUE_SIZE 8 43e9dcd831SSlava Shwartsman 44e9dcd831SSlava Shwartsman enum mlx5_ipsec_response_syndrome { 45e9dcd831SSlava Shwartsman MLX5_IPSEC_RESPONSE_SUCCESS = 0, 46e9dcd831SSlava Shwartsman MLX5_IPSEC_RESPONSE_ILLEGAL_REQUEST = 1, 47e9dcd831SSlava Shwartsman MLX5_IPSEC_RESPONSE_SADB_ISSUE = 2, 48e9dcd831SSlava Shwartsman MLX5_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE = 3, 49e9dcd831SSlava Shwartsman }; 50e9dcd831SSlava Shwartsman 51e9dcd831SSlava Shwartsman enum mlx5_fpga_ipsec_sacmd_status { 52e9dcd831SSlava Shwartsman MLX5_FPGA_IPSEC_SACMD_PENDING, 53e9dcd831SSlava Shwartsman MLX5_FPGA_IPSEC_SACMD_SEND_FAIL, 54e9dcd831SSlava Shwartsman MLX5_FPGA_IPSEC_SACMD_COMPLETE, 55e9dcd831SSlava Shwartsman }; 56e9dcd831SSlava Shwartsman 57e9dcd831SSlava Shwartsman struct mlx5_ipsec_command_context { 58e9dcd831SSlava Shwartsman struct mlx5_fpga_dma_buf buf; 59e9dcd831SSlava Shwartsman struct mlx5_accel_ipsec_sa sa; 60e9dcd831SSlava Shwartsman enum mlx5_fpga_ipsec_sacmd_status status; 61e9dcd831SSlava Shwartsman int status_code; 62e9dcd831SSlava Shwartsman struct completion complete; 63e9dcd831SSlava Shwartsman struct mlx5_fpga_device *dev; 64e9dcd831SSlava Shwartsman struct list_head list; /* Item in pending_cmds */ 65e9dcd831SSlava Shwartsman }; 66e9dcd831SSlava Shwartsman 67e9dcd831SSlava Shwartsman struct mlx5_ipsec_sadb_resp { 68e9dcd831SSlava Shwartsman __be32 syndrome; 69e9dcd831SSlava Shwartsman __be32 sw_sa_handle; 70e9dcd831SSlava Shwartsman u8 reserved[24]; 71e9dcd831SSlava Shwartsman } __packed; 72e9dcd831SSlava Shwartsman 73e9dcd831SSlava Shwartsman struct mlx5_fpga_ipsec { 74e9dcd831SSlava Shwartsman struct list_head pending_cmds; 75e9dcd831SSlava Shwartsman spinlock_t pending_cmds_lock; /* Protects pending_cmds */ 76e9dcd831SSlava Shwartsman u32 caps[MLX5_ST_SZ_DW(ipsec_extended_cap)]; 77e9dcd831SSlava Shwartsman struct mlx5_fpga_conn *conn; 78e9dcd831SSlava Shwartsman }; 79e9dcd831SSlava Shwartsman 80e9dcd831SSlava Shwartsman static bool mlx5_fpga_is_ipsec_device(struct mlx5_core_dev *mdev) 81e9dcd831SSlava Shwartsman { 82e9dcd831SSlava Shwartsman if (!mdev->fpga || !MLX5_CAP_GEN(mdev, fpga)) 83e9dcd831SSlava Shwartsman return false; 84e9dcd831SSlava Shwartsman 85e9dcd831SSlava Shwartsman if (MLX5_CAP_FPGA(mdev, ieee_vendor_id) != 86e9dcd831SSlava Shwartsman MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX) 87e9dcd831SSlava Shwartsman return false; 88e9dcd831SSlava Shwartsman 89e9dcd831SSlava Shwartsman if (MLX5_CAP_FPGA(mdev, sandbox_product_id) != 90e9dcd831SSlava Shwartsman MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC) 91e9dcd831SSlava Shwartsman return false; 92e9dcd831SSlava Shwartsman 93e9dcd831SSlava Shwartsman return true; 94e9dcd831SSlava Shwartsman } 95e9dcd831SSlava Shwartsman 96e9dcd831SSlava Shwartsman static void mlx5_fpga_ipsec_send_complete(struct mlx5_fpga_conn *conn, 97e9dcd831SSlava Shwartsman struct mlx5_fpga_device *fdev, 98e9dcd831SSlava Shwartsman struct mlx5_fpga_dma_buf *buf, 99e9dcd831SSlava Shwartsman u8 status) 100e9dcd831SSlava Shwartsman { 101e9dcd831SSlava Shwartsman struct mlx5_ipsec_command_context *context; 102e9dcd831SSlava Shwartsman 103e9dcd831SSlava Shwartsman if (status) { 104e9dcd831SSlava Shwartsman context = container_of(buf, struct mlx5_ipsec_command_context, 105e9dcd831SSlava Shwartsman buf); 106e9dcd831SSlava Shwartsman mlx5_fpga_warn(fdev, "IPSec command send failed with status %u\n", 107e9dcd831SSlava Shwartsman status); 108e9dcd831SSlava Shwartsman context->status = MLX5_FPGA_IPSEC_SACMD_SEND_FAIL; 109e9dcd831SSlava Shwartsman complete(&context->complete); 110e9dcd831SSlava Shwartsman } 111e9dcd831SSlava Shwartsman } 112e9dcd831SSlava Shwartsman 113e9dcd831SSlava Shwartsman static inline int syndrome_to_errno(enum mlx5_ipsec_response_syndrome syndrome) 114e9dcd831SSlava Shwartsman { 115e9dcd831SSlava Shwartsman switch (syndrome) { 116e9dcd831SSlava Shwartsman case MLX5_IPSEC_RESPONSE_SUCCESS: 117e9dcd831SSlava Shwartsman return 0; 118e9dcd831SSlava Shwartsman case MLX5_IPSEC_RESPONSE_SADB_ISSUE: 119e9dcd831SSlava Shwartsman return -EEXIST; 120e9dcd831SSlava Shwartsman case MLX5_IPSEC_RESPONSE_ILLEGAL_REQUEST: 121e9dcd831SSlava Shwartsman return -EINVAL; 122e9dcd831SSlava Shwartsman case MLX5_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE: 123e9dcd831SSlava Shwartsman return -EIO; 124e9dcd831SSlava Shwartsman } 125e9dcd831SSlava Shwartsman return -EIO; 126e9dcd831SSlava Shwartsman } 127e9dcd831SSlava Shwartsman 128e9dcd831SSlava Shwartsman static void mlx5_fpga_ipsec_recv(void *cb_arg, struct mlx5_fpga_dma_buf *buf) 129e9dcd831SSlava Shwartsman { 130e9dcd831SSlava Shwartsman struct mlx5_ipsec_sadb_resp *resp = buf->sg[0].data; 131e9dcd831SSlava Shwartsman struct mlx5_ipsec_command_context *context; 132e9dcd831SSlava Shwartsman enum mlx5_ipsec_response_syndrome syndrome; 133e9dcd831SSlava Shwartsman struct mlx5_fpga_device *fdev = cb_arg; 134e9dcd831SSlava Shwartsman unsigned long flags; 135e9dcd831SSlava Shwartsman 136e9dcd831SSlava Shwartsman if (buf->sg[0].size < sizeof(*resp)) { 137e9dcd831SSlava Shwartsman mlx5_fpga_warn(fdev, "Short receive from FPGA IPSec: %u < %zu bytes\n", 138e9dcd831SSlava Shwartsman buf->sg[0].size, sizeof(*resp)); 139e9dcd831SSlava Shwartsman return; 140e9dcd831SSlava Shwartsman } 141e9dcd831SSlava Shwartsman 142e9dcd831SSlava Shwartsman mlx5_fpga_dbg(fdev, "mlx5_ipsec recv_cb syndrome %08x sa_id %x\n", 143e9dcd831SSlava Shwartsman ntohl(resp->syndrome), ntohl(resp->sw_sa_handle)); 144e9dcd831SSlava Shwartsman 145e9dcd831SSlava Shwartsman spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags); 146e9dcd831SSlava Shwartsman context = list_first_entry_or_null(&fdev->ipsec->pending_cmds, 147e9dcd831SSlava Shwartsman struct mlx5_ipsec_command_context, 148e9dcd831SSlava Shwartsman list); 149e9dcd831SSlava Shwartsman if (context) 150e9dcd831SSlava Shwartsman list_del(&context->list); 151e9dcd831SSlava Shwartsman spin_unlock_irqrestore(&fdev->ipsec->pending_cmds_lock, flags); 152e9dcd831SSlava Shwartsman 153e9dcd831SSlava Shwartsman if (!context) { 154e9dcd831SSlava Shwartsman mlx5_fpga_warn(fdev, "Received IPSec offload response without pending command request\n"); 155e9dcd831SSlava Shwartsman return; 156e9dcd831SSlava Shwartsman } 157e9dcd831SSlava Shwartsman mlx5_fpga_dbg(fdev, "Handling response for %p\n", context); 158e9dcd831SSlava Shwartsman 159e9dcd831SSlava Shwartsman if (context->sa.sw_sa_handle != resp->sw_sa_handle) { 160e9dcd831SSlava Shwartsman mlx5_fpga_err(fdev, "mismatch SA handle. cmd 0x%08x vs resp 0x%08x\n", 161e9dcd831SSlava Shwartsman ntohl(context->sa.sw_sa_handle), 162e9dcd831SSlava Shwartsman ntohl(resp->sw_sa_handle)); 163e9dcd831SSlava Shwartsman return; 164e9dcd831SSlava Shwartsman } 165e9dcd831SSlava Shwartsman 166e9dcd831SSlava Shwartsman syndrome = ntohl(resp->syndrome); 167e9dcd831SSlava Shwartsman context->status_code = syndrome_to_errno(syndrome); 168e9dcd831SSlava Shwartsman context->status = MLX5_FPGA_IPSEC_SACMD_COMPLETE; 169e9dcd831SSlava Shwartsman 170e9dcd831SSlava Shwartsman if (context->status_code) 171e9dcd831SSlava Shwartsman mlx5_fpga_warn(fdev, "IPSec SADB command failed with syndrome %08x\n", 172e9dcd831SSlava Shwartsman syndrome); 173e9dcd831SSlava Shwartsman complete(&context->complete); 174e9dcd831SSlava Shwartsman } 175e9dcd831SSlava Shwartsman 176e9dcd831SSlava Shwartsman void *mlx5_fpga_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, 177e9dcd831SSlava Shwartsman struct mlx5_accel_ipsec_sa *cmd) 178e9dcd831SSlava Shwartsman { 179e9dcd831SSlava Shwartsman struct mlx5_ipsec_command_context *context; 180e9dcd831SSlava Shwartsman struct mlx5_fpga_device *fdev = mdev->fpga; 181e9dcd831SSlava Shwartsman unsigned long flags; 182e9dcd831SSlava Shwartsman int res = 0; 183e9dcd831SSlava Shwartsman 184e9dcd831SSlava Shwartsman BUILD_BUG_ON((sizeof(struct mlx5_accel_ipsec_sa) & 3) != 0); 185e9dcd831SSlava Shwartsman if (!fdev || !fdev->ipsec) 186e9dcd831SSlava Shwartsman return ERR_PTR(-EOPNOTSUPP); 187e9dcd831SSlava Shwartsman 188e9dcd831SSlava Shwartsman context = kzalloc(sizeof(*context), GFP_ATOMIC); 189e9dcd831SSlava Shwartsman if (!context) 190e9dcd831SSlava Shwartsman return ERR_PTR(-ENOMEM); 191e9dcd831SSlava Shwartsman 192e9dcd831SSlava Shwartsman memcpy(&context->sa, cmd, sizeof(*cmd)); 193e9dcd831SSlava Shwartsman context->buf.complete = mlx5_fpga_ipsec_send_complete; 194e9dcd831SSlava Shwartsman context->buf.sg[0].size = sizeof(context->sa); 195e9dcd831SSlava Shwartsman context->buf.sg[0].data = &context->sa; 196e9dcd831SSlava Shwartsman init_completion(&context->complete); 197e9dcd831SSlava Shwartsman context->dev = fdev; 198e9dcd831SSlava Shwartsman spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags); 199e9dcd831SSlava Shwartsman list_add_tail(&context->list, &fdev->ipsec->pending_cmds); 200e9dcd831SSlava Shwartsman spin_unlock_irqrestore(&fdev->ipsec->pending_cmds_lock, flags); 201e9dcd831SSlava Shwartsman 202e9dcd831SSlava Shwartsman context->status = MLX5_FPGA_IPSEC_SACMD_PENDING; 203e9dcd831SSlava Shwartsman 204e9dcd831SSlava Shwartsman res = mlx5_fpga_sbu_conn_sendmsg(fdev->ipsec->conn, &context->buf); 205e9dcd831SSlava Shwartsman if (res) { 206e9dcd831SSlava Shwartsman mlx5_fpga_warn(fdev, "Failure sending IPSec command: %d\n", 207e9dcd831SSlava Shwartsman res); 208e9dcd831SSlava Shwartsman spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags); 209e9dcd831SSlava Shwartsman list_del(&context->list); 210e9dcd831SSlava Shwartsman spin_unlock_irqrestore(&fdev->ipsec->pending_cmds_lock, flags); 211e9dcd831SSlava Shwartsman kfree(context); 212e9dcd831SSlava Shwartsman return ERR_PTR(res); 213e9dcd831SSlava Shwartsman } 214e9dcd831SSlava Shwartsman /* Context will be freed by wait func after completion */ 215e9dcd831SSlava Shwartsman return context; 216e9dcd831SSlava Shwartsman } 217e9dcd831SSlava Shwartsman 218e9dcd831SSlava Shwartsman int mlx5_fpga_ipsec_sa_cmd_wait(void *ctx) 219e9dcd831SSlava Shwartsman { 220e9dcd831SSlava Shwartsman struct mlx5_ipsec_command_context *context = ctx; 221e9dcd831SSlava Shwartsman int res; 222e9dcd831SSlava Shwartsman 223e9dcd831SSlava Shwartsman res = wait_for_completion/*_killable XXXKIB*/(&context->complete); 224e9dcd831SSlava Shwartsman if (res) { 225e9dcd831SSlava Shwartsman mlx5_fpga_warn(context->dev, "Failure waiting for IPSec command response\n"); 226e9dcd831SSlava Shwartsman return -EINTR; 227e9dcd831SSlava Shwartsman } 228e9dcd831SSlava Shwartsman 229e9dcd831SSlava Shwartsman if (context->status == MLX5_FPGA_IPSEC_SACMD_COMPLETE) 230e9dcd831SSlava Shwartsman res = context->status_code; 231e9dcd831SSlava Shwartsman else 232e9dcd831SSlava Shwartsman res = -EIO; 233e9dcd831SSlava Shwartsman 234e9dcd831SSlava Shwartsman kfree(context); 235e9dcd831SSlava Shwartsman return res; 236e9dcd831SSlava Shwartsman } 237e9dcd831SSlava Shwartsman 238e9dcd831SSlava Shwartsman u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev) 239e9dcd831SSlava Shwartsman { 240e9dcd831SSlava Shwartsman struct mlx5_fpga_device *fdev = mdev->fpga; 241e9dcd831SSlava Shwartsman u32 ret = 0; 242e9dcd831SSlava Shwartsman 243e9dcd831SSlava Shwartsman if (mlx5_fpga_is_ipsec_device(mdev)) 244e9dcd831SSlava Shwartsman ret |= MLX5_ACCEL_IPSEC_DEVICE; 245e9dcd831SSlava Shwartsman else 246e9dcd831SSlava Shwartsman return ret; 247e9dcd831SSlava Shwartsman 248e9dcd831SSlava Shwartsman if (!fdev->ipsec) 249e9dcd831SSlava Shwartsman return ret; 250e9dcd831SSlava Shwartsman 251e9dcd831SSlava Shwartsman if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, esp)) 252e9dcd831SSlava Shwartsman ret |= MLX5_ACCEL_IPSEC_ESP; 253e9dcd831SSlava Shwartsman 254e9dcd831SSlava Shwartsman if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, ipv6)) 255e9dcd831SSlava Shwartsman ret |= MLX5_ACCEL_IPSEC_IPV6; 256e9dcd831SSlava Shwartsman 257e9dcd831SSlava Shwartsman if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, lso)) 258e9dcd831SSlava Shwartsman ret |= MLX5_ACCEL_IPSEC_LSO; 259e9dcd831SSlava Shwartsman 260e9dcd831SSlava Shwartsman return ret; 261e9dcd831SSlava Shwartsman } 262e9dcd831SSlava Shwartsman 263e9dcd831SSlava Shwartsman unsigned int mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev) 264e9dcd831SSlava Shwartsman { 265e9dcd831SSlava Shwartsman struct mlx5_fpga_device *fdev = mdev->fpga; 266e9dcd831SSlava Shwartsman 267e9dcd831SSlava Shwartsman if (!fdev || !fdev->ipsec) 268e9dcd831SSlava Shwartsman return 0; 269e9dcd831SSlava Shwartsman 270e9dcd831SSlava Shwartsman return MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, 271e9dcd831SSlava Shwartsman number_of_ipsec_counters); 272e9dcd831SSlava Shwartsman } 273e9dcd831SSlava Shwartsman 274e9dcd831SSlava Shwartsman int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters, 275e9dcd831SSlava Shwartsman unsigned int counters_count) 276e9dcd831SSlava Shwartsman { 277e9dcd831SSlava Shwartsman struct mlx5_fpga_device *fdev = mdev->fpga; 278e9dcd831SSlava Shwartsman unsigned int i; 279e9dcd831SSlava Shwartsman __be32 *data; 280e9dcd831SSlava Shwartsman u32 count; 281e9dcd831SSlava Shwartsman u64 addr; 282e9dcd831SSlava Shwartsman int ret; 283e9dcd831SSlava Shwartsman 284e9dcd831SSlava Shwartsman if (!fdev || !fdev->ipsec) 285e9dcd831SSlava Shwartsman return 0; 286e9dcd831SSlava Shwartsman 287e9dcd831SSlava Shwartsman addr = (u64)MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, 288e9dcd831SSlava Shwartsman ipsec_counters_addr_low) + 289e9dcd831SSlava Shwartsman ((u64)MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, 290e9dcd831SSlava Shwartsman ipsec_counters_addr_high) << 32); 291e9dcd831SSlava Shwartsman 292e9dcd831SSlava Shwartsman count = mlx5_fpga_ipsec_counters_count(mdev); 293e9dcd831SSlava Shwartsman 294e9dcd831SSlava Shwartsman data = kzalloc(sizeof(*data) * count * 2, GFP_KERNEL); 295e9dcd831SSlava Shwartsman if (!data) { 296e9dcd831SSlava Shwartsman ret = -ENOMEM; 297e9dcd831SSlava Shwartsman goto out; 298e9dcd831SSlava Shwartsman } 299e9dcd831SSlava Shwartsman 300e9dcd831SSlava Shwartsman ret = mlx5_fpga_mem_read(fdev, count * sizeof(u64), addr, data, 301e9dcd831SSlava Shwartsman MLX5_FPGA_ACCESS_TYPE_DONTCARE); 302e9dcd831SSlava Shwartsman if (ret < 0) { 303e9dcd831SSlava Shwartsman mlx5_fpga_err(fdev, "Failed to read IPSec counters from HW: %d\n", 304e9dcd831SSlava Shwartsman ret); 305e9dcd831SSlava Shwartsman goto out; 306e9dcd831SSlava Shwartsman } 307e9dcd831SSlava Shwartsman ret = 0; 308e9dcd831SSlava Shwartsman 309e9dcd831SSlava Shwartsman if (count > counters_count) 310e9dcd831SSlava Shwartsman count = counters_count; 311e9dcd831SSlava Shwartsman 312e9dcd831SSlava Shwartsman /* Each counter is low word, then high. But each word is big-endian */ 313e9dcd831SSlava Shwartsman for (i = 0; i < count; i++) 314e9dcd831SSlava Shwartsman counters[i] = (u64)ntohl(data[i * 2]) | 315e9dcd831SSlava Shwartsman ((u64)ntohl(data[i * 2 + 1]) << 32); 316e9dcd831SSlava Shwartsman 317e9dcd831SSlava Shwartsman out: 318e9dcd831SSlava Shwartsman kfree(data); 319e9dcd831SSlava Shwartsman return ret; 320e9dcd831SSlava Shwartsman } 321e9dcd831SSlava Shwartsman 322e9dcd831SSlava Shwartsman int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev) 323e9dcd831SSlava Shwartsman { 324e9dcd831SSlava Shwartsman struct mlx5_fpga_conn_attr init_attr = {0}; 325e9dcd831SSlava Shwartsman struct mlx5_fpga_device *fdev = mdev->fpga; 326e9dcd831SSlava Shwartsman struct mlx5_fpga_conn *conn; 327e9dcd831SSlava Shwartsman int err; 328e9dcd831SSlava Shwartsman 329e9dcd831SSlava Shwartsman if (!mlx5_fpga_is_ipsec_device(mdev)) 330e9dcd831SSlava Shwartsman return 0; 331e9dcd831SSlava Shwartsman 332e9dcd831SSlava Shwartsman fdev->ipsec = kzalloc(sizeof(*fdev->ipsec), GFP_KERNEL); 333e9dcd831SSlava Shwartsman if (!fdev->ipsec) 334e9dcd831SSlava Shwartsman return -ENOMEM; 335e9dcd831SSlava Shwartsman 336e9dcd831SSlava Shwartsman err = mlx5_fpga_get_sbu_caps(fdev, sizeof(fdev->ipsec->caps), 337e9dcd831SSlava Shwartsman fdev->ipsec->caps); 338e9dcd831SSlava Shwartsman if (err) { 339e9dcd831SSlava Shwartsman mlx5_fpga_err(fdev, "Failed to retrieve IPSec extended capabilities: %d\n", 340e9dcd831SSlava Shwartsman err); 341e9dcd831SSlava Shwartsman goto error; 342e9dcd831SSlava Shwartsman } 343e9dcd831SSlava Shwartsman 344e9dcd831SSlava Shwartsman INIT_LIST_HEAD(&fdev->ipsec->pending_cmds); 345e9dcd831SSlava Shwartsman spin_lock_init(&fdev->ipsec->pending_cmds_lock); 346e9dcd831SSlava Shwartsman 347e9dcd831SSlava Shwartsman init_attr.rx_size = SBU_QP_QUEUE_SIZE; 348e9dcd831SSlava Shwartsman init_attr.tx_size = SBU_QP_QUEUE_SIZE; 349e9dcd831SSlava Shwartsman init_attr.recv_cb = mlx5_fpga_ipsec_recv; 350e9dcd831SSlava Shwartsman init_attr.cb_arg = fdev; 351e9dcd831SSlava Shwartsman conn = mlx5_fpga_sbu_conn_create(fdev, &init_attr); 352e9dcd831SSlava Shwartsman if (IS_ERR(conn)) { 353e9dcd831SSlava Shwartsman err = PTR_ERR(conn); 354e9dcd831SSlava Shwartsman mlx5_fpga_err(fdev, "Error creating IPSec command connection %d\n", 355e9dcd831SSlava Shwartsman err); 356e9dcd831SSlava Shwartsman goto error; 357e9dcd831SSlava Shwartsman } 358e9dcd831SSlava Shwartsman fdev->ipsec->conn = conn; 359e9dcd831SSlava Shwartsman return 0; 360e9dcd831SSlava Shwartsman 361e9dcd831SSlava Shwartsman error: 362e9dcd831SSlava Shwartsman kfree(fdev->ipsec); 363e9dcd831SSlava Shwartsman fdev->ipsec = NULL; 364e9dcd831SSlava Shwartsman return err; 365e9dcd831SSlava Shwartsman } 366e9dcd831SSlava Shwartsman 367e9dcd831SSlava Shwartsman void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev) 368e9dcd831SSlava Shwartsman { 369e9dcd831SSlava Shwartsman struct mlx5_fpga_device *fdev = mdev->fpga; 370e9dcd831SSlava Shwartsman 371e9dcd831SSlava Shwartsman if (!mlx5_fpga_is_ipsec_device(mdev)) 372e9dcd831SSlava Shwartsman return; 373e9dcd831SSlava Shwartsman 374e9dcd831SSlava Shwartsman mlx5_fpga_sbu_conn_destroy(fdev->ipsec->conn); 375e9dcd831SSlava Shwartsman kfree(fdev->ipsec); 376e9dcd831SSlava Shwartsman fdev->ipsec = NULL; 377e9dcd831SSlava Shwartsman } 378