1 /*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/module.h> 29 #include <linux/errno.h> 30 #include <linux/pci.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/slab.h> 33 #if defined(CONFIG_X86) 34 #include <asm/pat.h> 35 #endif 36 #include <linux/sched.h> 37 #include <linux/delay.h> 38 #include <linux/fs.h> 39 #undef inode 40 #include <rdma/ib_user_verbs.h> 41 #include <rdma/ib_addr.h> 42 #include <rdma/ib_cache.h> 43 #include <dev/mlx5/port.h> 44 #include <dev/mlx5/vport.h> 45 #include <linux/list.h> 46 #include <rdma/ib_smi.h> 47 #include <rdma/ib_umem.h> 48 #include <linux/in.h> 49 #include <linux/etherdevice.h> 50 #include <dev/mlx5/fs.h> 51 #include "mlx5_ib.h" 52 53 #define DRIVER_NAME "mlx5ib" 54 #ifndef DRIVER_VERSION 55 #define DRIVER_VERSION "3.5.0" 56 #endif 57 #define DRIVER_RELDATE "November 2018" 58 59 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 60 MODULE_LICENSE("Dual BSD/GPL"); 61 MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1); 62 MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1); 63 MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1); 64 MODULE_VERSION(mlx5ib, 1); 65 66 static int deprecated_prof_sel = 2; 67 module_param_named(prof_sel, deprecated_prof_sel, int, 0444); 68 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core"); 69 70 static const char mlx5_version[] = 71 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver " 72 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 73 74 enum { 75 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 76 }; 77 78 static enum rdma_link_layer 79 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 80 { 81 switch (port_type_cap) { 82 case MLX5_CAP_PORT_TYPE_IB: 83 return IB_LINK_LAYER_INFINIBAND; 84 case MLX5_CAP_PORT_TYPE_ETH: 85 return IB_LINK_LAYER_ETHERNET; 86 default: 87 return IB_LINK_LAYER_UNSPECIFIED; 88 } 89 } 90 91 static enum rdma_link_layer 92 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 93 { 94 struct mlx5_ib_dev *dev = to_mdev(device); 95 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 96 97 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 98 } 99 100 static bool mlx5_netdev_match(struct net_device *ndev, 101 struct mlx5_core_dev *mdev, 102 const char *dname) 103 { 104 return ndev->if_type == IFT_ETHER && 105 ndev->if_dname != NULL && 106 strcmp(ndev->if_dname, dname) == 0 && 107 ndev->if_softc != NULL && 108 *(struct mlx5_core_dev **)ndev->if_softc == mdev; 109 } 110 111 static int mlx5_netdev_event(struct notifier_block *this, 112 unsigned long event, void *ptr) 113 { 114 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 115 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 116 roce.nb); 117 118 switch (event) { 119 case NETDEV_REGISTER: 120 case NETDEV_UNREGISTER: 121 write_lock(&ibdev->roce.netdev_lock); 122 /* check if network interface belongs to mlx5en */ 123 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce")) 124 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 125 NULL : ndev; 126 write_unlock(&ibdev->roce.netdev_lock); 127 break; 128 129 case NETDEV_UP: 130 case NETDEV_DOWN: { 131 struct net_device *upper = NULL; 132 133 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 134 && ibdev->ib_active) { 135 struct ib_event ibev = {0}; 136 137 ibev.device = &ibdev->ib_dev; 138 ibev.event = (event == NETDEV_UP) ? 139 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 140 ibev.element.port_num = 1; 141 ib_dispatch_event(&ibev); 142 } 143 break; 144 } 145 146 default: 147 break; 148 } 149 150 return NOTIFY_DONE; 151 } 152 153 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 154 u8 port_num) 155 { 156 struct mlx5_ib_dev *ibdev = to_mdev(device); 157 struct net_device *ndev; 158 159 /* Ensure ndev does not disappear before we invoke dev_hold() 160 */ 161 read_lock(&ibdev->roce.netdev_lock); 162 ndev = ibdev->roce.netdev; 163 if (ndev) 164 dev_hold(ndev); 165 read_unlock(&ibdev->roce.netdev_lock); 166 167 return ndev; 168 } 169 170 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 171 u8 *active_width) 172 { 173 switch (eth_proto_oper) { 174 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 175 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 176 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 177 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 178 *active_width = IB_WIDTH_1X; 179 *active_speed = IB_SPEED_SDR; 180 break; 181 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 182 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 183 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 184 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 185 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 186 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 187 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 188 *active_width = IB_WIDTH_1X; 189 *active_speed = IB_SPEED_QDR; 190 break; 191 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 192 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 193 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 194 *active_width = IB_WIDTH_1X; 195 *active_speed = IB_SPEED_EDR; 196 break; 197 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 198 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 199 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 200 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 201 *active_width = IB_WIDTH_4X; 202 *active_speed = IB_SPEED_QDR; 203 break; 204 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 205 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 206 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 207 *active_width = IB_WIDTH_1X; 208 *active_speed = IB_SPEED_HDR; 209 break; 210 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 211 *active_width = IB_WIDTH_4X; 212 *active_speed = IB_SPEED_FDR; 213 break; 214 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 215 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 216 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 217 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 218 *active_width = IB_WIDTH_4X; 219 *active_speed = IB_SPEED_EDR; 220 break; 221 default: 222 *active_width = IB_WIDTH_4X; 223 *active_speed = IB_SPEED_QDR; 224 return -EINVAL; 225 } 226 227 return 0; 228 } 229 230 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 231 struct ib_port_attr *props) 232 { 233 struct mlx5_ib_dev *dev = to_mdev(device); 234 struct net_device *ndev; 235 enum ib_mtu ndev_ib_mtu; 236 u16 qkey_viol_cntr; 237 u32 eth_prot_oper; 238 int err; 239 240 memset(props, 0, sizeof(*props)); 241 242 /* Possible bad flows are checked before filling out props so in case 243 * of an error it will still be zeroed out. 244 */ 245 err = mlx5_query_port_eth_proto_oper(dev->mdev, ð_prot_oper, port_num); 246 if (err) 247 return err; 248 249 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 250 &props->active_width); 251 252 props->port_cap_flags |= IB_PORT_CM_SUP; 253 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 254 255 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 256 roce_address_table_size); 257 props->max_mtu = IB_MTU_4096; 258 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 259 props->pkey_tbl_len = 1; 260 props->state = IB_PORT_DOWN; 261 props->phys_state = 3; 262 263 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 264 props->qkey_viol_cntr = qkey_viol_cntr; 265 266 ndev = mlx5_ib_get_netdev(device, port_num); 267 if (!ndev) 268 return 0; 269 270 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 271 props->state = IB_PORT_ACTIVE; 272 props->phys_state = 5; 273 } 274 275 ndev_ib_mtu = iboe_get_mtu(ndev->if_mtu); 276 277 dev_put(ndev); 278 279 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 280 return 0; 281 } 282 283 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 284 const struct ib_gid_attr *attr, 285 void *mlx5_addr) 286 { 287 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 288 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 289 source_l3_address); 290 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 291 source_mac_47_32); 292 u16 vlan_id; 293 294 if (!gid) 295 return; 296 ether_addr_copy(mlx5_addr_mac, IF_LLADDR(attr->ndev)); 297 298 vlan_id = rdma_vlan_dev_vlan_id(attr->ndev); 299 if (vlan_id != 0xffff) { 300 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 301 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_id); 302 } 303 304 switch (attr->gid_type) { 305 case IB_GID_TYPE_IB: 306 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 307 break; 308 case IB_GID_TYPE_ROCE_UDP_ENCAP: 309 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 310 break; 311 312 default: 313 WARN_ON(true); 314 } 315 316 if (attr->gid_type != IB_GID_TYPE_IB) { 317 if (ipv6_addr_v4mapped((void *)gid)) 318 MLX5_SET_RA(mlx5_addr, roce_l3_type, 319 MLX5_ROCE_L3_TYPE_IPV4); 320 else 321 MLX5_SET_RA(mlx5_addr, roce_l3_type, 322 MLX5_ROCE_L3_TYPE_IPV6); 323 } 324 325 if ((attr->gid_type == IB_GID_TYPE_IB) || 326 !ipv6_addr_v4mapped((void *)gid)) 327 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 328 else 329 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 330 } 331 332 static int set_roce_addr(struct ib_device *device, u8 port_num, 333 unsigned int index, 334 const union ib_gid *gid, 335 const struct ib_gid_attr *attr) 336 { 337 struct mlx5_ib_dev *dev = to_mdev(device); 338 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 339 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 340 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 341 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 342 343 if (ll != IB_LINK_LAYER_ETHERNET) 344 return -EINVAL; 345 346 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 347 348 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 349 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 350 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 351 } 352 353 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 354 unsigned int index, const union ib_gid *gid, 355 const struct ib_gid_attr *attr, 356 __always_unused void **context) 357 { 358 return set_roce_addr(device, port_num, index, gid, attr); 359 } 360 361 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 362 unsigned int index, __always_unused void **context) 363 { 364 return set_roce_addr(device, port_num, index, NULL, NULL); 365 } 366 367 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 368 int index) 369 { 370 struct ib_gid_attr attr; 371 union ib_gid gid; 372 373 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 374 return 0; 375 376 if (!attr.ndev) 377 return 0; 378 379 dev_put(attr.ndev); 380 381 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 382 return 0; 383 384 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 385 } 386 387 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 388 int index, enum ib_gid_type *gid_type) 389 { 390 struct ib_gid_attr attr; 391 union ib_gid gid; 392 int ret; 393 394 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 395 if (ret) 396 return ret; 397 398 if (!attr.ndev) 399 return -ENODEV; 400 401 dev_put(attr.ndev); 402 403 *gid_type = attr.gid_type; 404 405 return 0; 406 } 407 408 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 409 { 410 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 411 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 412 return 0; 413 } 414 415 enum { 416 MLX5_VPORT_ACCESS_METHOD_MAD, 417 MLX5_VPORT_ACCESS_METHOD_HCA, 418 MLX5_VPORT_ACCESS_METHOD_NIC, 419 }; 420 421 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 422 { 423 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 424 return MLX5_VPORT_ACCESS_METHOD_MAD; 425 426 if (mlx5_ib_port_link_layer(ibdev, 1) == 427 IB_LINK_LAYER_ETHERNET) 428 return MLX5_VPORT_ACCESS_METHOD_NIC; 429 430 return MLX5_VPORT_ACCESS_METHOD_HCA; 431 } 432 433 static void get_atomic_caps(struct mlx5_ib_dev *dev, 434 struct ib_device_attr *props) 435 { 436 u8 tmp; 437 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 438 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 439 u8 atomic_req_8B_endianness_mode = 440 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 441 442 /* Check if HW supports 8 bytes standard atomic operations and capable 443 * of host endianness respond 444 */ 445 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 446 if (((atomic_operations & tmp) == tmp) && 447 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 448 (atomic_req_8B_endianness_mode)) { 449 props->atomic_cap = IB_ATOMIC_HCA; 450 } else { 451 props->atomic_cap = IB_ATOMIC_NONE; 452 } 453 } 454 455 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 456 __be64 *sys_image_guid) 457 { 458 struct mlx5_ib_dev *dev = to_mdev(ibdev); 459 struct mlx5_core_dev *mdev = dev->mdev; 460 u64 tmp; 461 int err; 462 463 switch (mlx5_get_vport_access_method(ibdev)) { 464 case MLX5_VPORT_ACCESS_METHOD_MAD: 465 return mlx5_query_mad_ifc_system_image_guid(ibdev, 466 sys_image_guid); 467 468 case MLX5_VPORT_ACCESS_METHOD_HCA: 469 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 470 break; 471 472 case MLX5_VPORT_ACCESS_METHOD_NIC: 473 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 474 break; 475 476 default: 477 return -EINVAL; 478 } 479 480 if (!err) 481 *sys_image_guid = cpu_to_be64(tmp); 482 483 return err; 484 485 } 486 487 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 488 u16 *max_pkeys) 489 { 490 struct mlx5_ib_dev *dev = to_mdev(ibdev); 491 struct mlx5_core_dev *mdev = dev->mdev; 492 493 switch (mlx5_get_vport_access_method(ibdev)) { 494 case MLX5_VPORT_ACCESS_METHOD_MAD: 495 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 496 497 case MLX5_VPORT_ACCESS_METHOD_HCA: 498 case MLX5_VPORT_ACCESS_METHOD_NIC: 499 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 500 pkey_table_size)); 501 return 0; 502 503 default: 504 return -EINVAL; 505 } 506 } 507 508 static int mlx5_query_vendor_id(struct ib_device *ibdev, 509 u32 *vendor_id) 510 { 511 struct mlx5_ib_dev *dev = to_mdev(ibdev); 512 513 switch (mlx5_get_vport_access_method(ibdev)) { 514 case MLX5_VPORT_ACCESS_METHOD_MAD: 515 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 516 517 case MLX5_VPORT_ACCESS_METHOD_HCA: 518 case MLX5_VPORT_ACCESS_METHOD_NIC: 519 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 520 521 default: 522 return -EINVAL; 523 } 524 } 525 526 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 527 __be64 *node_guid) 528 { 529 u64 tmp; 530 int err; 531 532 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 533 case MLX5_VPORT_ACCESS_METHOD_MAD: 534 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 535 536 case MLX5_VPORT_ACCESS_METHOD_HCA: 537 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 538 break; 539 540 case MLX5_VPORT_ACCESS_METHOD_NIC: 541 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 542 break; 543 544 default: 545 return -EINVAL; 546 } 547 548 if (!err) 549 *node_guid = cpu_to_be64(tmp); 550 551 return err; 552 } 553 554 struct mlx5_reg_node_desc { 555 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 556 }; 557 558 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 559 { 560 struct mlx5_reg_node_desc in; 561 562 if (mlx5_use_mad_ifc(dev)) 563 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 564 565 memset(&in, 0, sizeof(in)); 566 567 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 568 sizeof(struct mlx5_reg_node_desc), 569 MLX5_REG_NODE_DESC, 0, 0); 570 } 571 572 static int mlx5_ib_query_device(struct ib_device *ibdev, 573 struct ib_device_attr *props, 574 struct ib_udata *uhw) 575 { 576 struct mlx5_ib_dev *dev = to_mdev(ibdev); 577 struct mlx5_core_dev *mdev = dev->mdev; 578 int err = -ENOMEM; 579 int max_rq_sg; 580 int max_sq_sg; 581 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 582 struct mlx5_ib_query_device_resp resp = {}; 583 size_t resp_len; 584 u64 max_tso; 585 586 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 587 if (uhw->outlen && uhw->outlen < resp_len) 588 return -EINVAL; 589 else 590 resp.response_length = resp_len; 591 592 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 593 return -EINVAL; 594 595 memset(props, 0, sizeof(*props)); 596 err = mlx5_query_system_image_guid(ibdev, 597 &props->sys_image_guid); 598 if (err) 599 return err; 600 601 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 602 if (err) 603 return err; 604 605 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 606 if (err) 607 return err; 608 609 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 610 ((u32)fw_rev_min(dev->mdev) << 16) | 611 fw_rev_sub(dev->mdev); 612 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 613 IB_DEVICE_PORT_ACTIVE_EVENT | 614 IB_DEVICE_SYS_IMAGE_GUID | 615 IB_DEVICE_RC_RNR_NAK_GEN; 616 617 if (MLX5_CAP_GEN(mdev, pkv)) 618 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 619 if (MLX5_CAP_GEN(mdev, qkv)) 620 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 621 if (MLX5_CAP_GEN(mdev, apm)) 622 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 623 if (MLX5_CAP_GEN(mdev, xrc)) 624 props->device_cap_flags |= IB_DEVICE_XRC; 625 if (MLX5_CAP_GEN(mdev, imaicl)) { 626 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 627 IB_DEVICE_MEM_WINDOW_TYPE_2B; 628 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 629 /* We support 'Gappy' memory registration too */ 630 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 631 } 632 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 633 if (MLX5_CAP_GEN(mdev, sho)) { 634 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 635 /* At this stage no support for signature handover */ 636 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 637 IB_PROT_T10DIF_TYPE_2 | 638 IB_PROT_T10DIF_TYPE_3; 639 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 640 IB_GUARD_T10DIF_CSUM; 641 } 642 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 643 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 644 645 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 646 if (MLX5_CAP_ETH(mdev, csum_cap)) 647 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 648 649 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 650 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 651 if (max_tso) { 652 resp.tso_caps.max_tso = 1 << max_tso; 653 resp.tso_caps.supported_qpts |= 654 1 << IB_QPT_RAW_PACKET; 655 resp.response_length += sizeof(resp.tso_caps); 656 } 657 } 658 659 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 660 resp.rss_caps.rx_hash_function = 661 MLX5_RX_HASH_FUNC_TOEPLITZ; 662 resp.rss_caps.rx_hash_fields_mask = 663 MLX5_RX_HASH_SRC_IPV4 | 664 MLX5_RX_HASH_DST_IPV4 | 665 MLX5_RX_HASH_SRC_IPV6 | 666 MLX5_RX_HASH_DST_IPV6 | 667 MLX5_RX_HASH_SRC_PORT_TCP | 668 MLX5_RX_HASH_DST_PORT_TCP | 669 MLX5_RX_HASH_SRC_PORT_UDP | 670 MLX5_RX_HASH_DST_PORT_UDP; 671 resp.response_length += sizeof(resp.rss_caps); 672 } 673 } else { 674 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 675 resp.response_length += sizeof(resp.tso_caps); 676 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 677 resp.response_length += sizeof(resp.rss_caps); 678 } 679 680 if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 681 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 682 props->device_cap_flags |= IB_DEVICE_UD_TSO; 683 } 684 685 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 686 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) 687 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 688 689 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 690 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 691 692 props->vendor_part_id = mdev->pdev->device; 693 props->hw_ver = mdev->pdev->revision; 694 695 props->max_mr_size = ~0ull; 696 props->page_size_cap = ~(min_page_size - 1); 697 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 698 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 699 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 700 sizeof(struct mlx5_wqe_data_seg); 701 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) - 702 sizeof(struct mlx5_wqe_ctrl_seg)) / 703 sizeof(struct mlx5_wqe_data_seg); 704 props->max_sge = min(max_rq_sg, max_sq_sg); 705 props->max_sge_rd = MLX5_MAX_SGE_RD; 706 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 707 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 708 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 709 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 710 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 711 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 712 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 713 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 714 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 715 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 716 props->max_srq_sge = max_rq_sg - 1; 717 props->max_fast_reg_page_list_len = 718 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 719 get_atomic_caps(dev, props); 720 props->masked_atomic_cap = IB_ATOMIC_NONE; 721 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 722 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 723 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 724 props->max_mcast_grp; 725 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 726 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 727 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 728 729 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 730 if (MLX5_CAP_GEN(mdev, pg)) 731 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 732 props->odp_caps = dev->odp_caps; 733 #endif 734 735 if (MLX5_CAP_GEN(mdev, cd)) 736 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 737 738 if (!mlx5_core_is_pf(mdev)) 739 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 740 741 if (mlx5_ib_port_link_layer(ibdev, 1) == 742 IB_LINK_LAYER_ETHERNET) { 743 props->rss_caps.max_rwq_indirection_tables = 744 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 745 props->rss_caps.max_rwq_indirection_table_size = 746 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 747 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 748 props->max_wq_type_rq = 749 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 750 } 751 752 if (uhw->outlen) { 753 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 754 755 if (err) 756 return err; 757 } 758 759 return 0; 760 } 761 762 enum mlx5_ib_width { 763 MLX5_IB_WIDTH_1X = 1 << 0, 764 MLX5_IB_WIDTH_2X = 1 << 1, 765 MLX5_IB_WIDTH_4X = 1 << 2, 766 MLX5_IB_WIDTH_8X = 1 << 3, 767 MLX5_IB_WIDTH_12X = 1 << 4 768 }; 769 770 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 771 u8 *ib_width) 772 { 773 struct mlx5_ib_dev *dev = to_mdev(ibdev); 774 int err = 0; 775 776 if (active_width & MLX5_IB_WIDTH_1X) { 777 *ib_width = IB_WIDTH_1X; 778 } else if (active_width & MLX5_IB_WIDTH_2X) { 779 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 780 (int)active_width); 781 err = -EINVAL; 782 } else if (active_width & MLX5_IB_WIDTH_4X) { 783 *ib_width = IB_WIDTH_4X; 784 } else if (active_width & MLX5_IB_WIDTH_8X) { 785 *ib_width = IB_WIDTH_8X; 786 } else if (active_width & MLX5_IB_WIDTH_12X) { 787 *ib_width = IB_WIDTH_12X; 788 } else { 789 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 790 (int)active_width); 791 err = -EINVAL; 792 } 793 794 return err; 795 } 796 797 enum ib_max_vl_num { 798 __IB_MAX_VL_0 = 1, 799 __IB_MAX_VL_0_1 = 2, 800 __IB_MAX_VL_0_3 = 3, 801 __IB_MAX_VL_0_7 = 4, 802 __IB_MAX_VL_0_14 = 5, 803 }; 804 805 enum mlx5_vl_hw_cap { 806 MLX5_VL_HW_0 = 1, 807 MLX5_VL_HW_0_1 = 2, 808 MLX5_VL_HW_0_2 = 3, 809 MLX5_VL_HW_0_3 = 4, 810 MLX5_VL_HW_0_4 = 5, 811 MLX5_VL_HW_0_5 = 6, 812 MLX5_VL_HW_0_6 = 7, 813 MLX5_VL_HW_0_7 = 8, 814 MLX5_VL_HW_0_14 = 15 815 }; 816 817 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 818 u8 *max_vl_num) 819 { 820 switch (vl_hw_cap) { 821 case MLX5_VL_HW_0: 822 *max_vl_num = __IB_MAX_VL_0; 823 break; 824 case MLX5_VL_HW_0_1: 825 *max_vl_num = __IB_MAX_VL_0_1; 826 break; 827 case MLX5_VL_HW_0_3: 828 *max_vl_num = __IB_MAX_VL_0_3; 829 break; 830 case MLX5_VL_HW_0_7: 831 *max_vl_num = __IB_MAX_VL_0_7; 832 break; 833 case MLX5_VL_HW_0_14: 834 *max_vl_num = __IB_MAX_VL_0_14; 835 break; 836 837 default: 838 return -EINVAL; 839 } 840 841 return 0; 842 } 843 844 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 845 struct ib_port_attr *props) 846 { 847 struct mlx5_ib_dev *dev = to_mdev(ibdev); 848 struct mlx5_core_dev *mdev = dev->mdev; 849 u32 *rep; 850 int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out); 851 struct mlx5_ptys_reg *ptys; 852 struct mlx5_pmtu_reg *pmtu; 853 struct mlx5_pvlc_reg pvlc; 854 void *ctx; 855 int err; 856 857 rep = mlx5_vzalloc(replen); 858 ptys = kzalloc(sizeof(*ptys), GFP_KERNEL); 859 pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL); 860 if (!rep || !ptys || !pmtu) { 861 err = -ENOMEM; 862 goto out; 863 } 864 865 memset(props, 0, sizeof(*props)); 866 867 err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen); 868 if (err) 869 goto out; 870 871 ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context); 872 873 props->lid = MLX5_GET(hca_vport_context, ctx, lid); 874 props->lmc = MLX5_GET(hca_vport_context, ctx, lmc); 875 props->sm_lid = MLX5_GET(hca_vport_context, ctx, sm_lid); 876 props->sm_sl = MLX5_GET(hca_vport_context, ctx, sm_sl); 877 props->state = MLX5_GET(hca_vport_context, ctx, vport_state); 878 props->phys_state = MLX5_GET(hca_vport_context, ctx, 879 port_physical_state); 880 props->port_cap_flags = MLX5_GET(hca_vport_context, ctx, cap_mask1); 881 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 882 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 883 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 884 props->bad_pkey_cntr = MLX5_GET(hca_vport_context, ctx, 885 pkey_violation_counter); 886 props->qkey_viol_cntr = MLX5_GET(hca_vport_context, ctx, 887 qkey_violation_counter); 888 props->subnet_timeout = MLX5_GET(hca_vport_context, ctx, 889 subnet_timeout); 890 props->init_type_reply = MLX5_GET(hca_vport_context, ctx, 891 init_type_reply); 892 props->grh_required = MLX5_GET(hca_vport_context, ctx, grh_required); 893 894 ptys->proto_mask |= MLX5_PTYS_IB; 895 ptys->local_port = port; 896 err = mlx5_core_access_ptys(mdev, ptys, 0); 897 if (err) 898 goto out; 899 900 err = translate_active_width(ibdev, ptys->ib_link_width_oper, 901 &props->active_width); 902 if (err) 903 goto out; 904 905 props->active_speed = (u8)ptys->ib_proto_oper; 906 907 pmtu->local_port = port; 908 err = mlx5_core_access_pmtu(mdev, pmtu, 0); 909 if (err) 910 goto out; 911 912 props->max_mtu = pmtu->max_mtu; 913 props->active_mtu = pmtu->oper_mtu; 914 915 memset(&pvlc, 0, sizeof(pvlc)); 916 pvlc.local_port = port; 917 err = mlx5_core_access_pvlc(mdev, &pvlc, 0); 918 if (err) 919 goto out; 920 921 err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap, 922 &props->max_vl_num); 923 out: 924 kvfree(rep); 925 kfree(ptys); 926 kfree(pmtu); 927 return err; 928 } 929 930 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 931 struct ib_port_attr *props) 932 { 933 switch (mlx5_get_vport_access_method(ibdev)) { 934 case MLX5_VPORT_ACCESS_METHOD_MAD: 935 return mlx5_query_mad_ifc_port(ibdev, port, props); 936 937 case MLX5_VPORT_ACCESS_METHOD_HCA: 938 return mlx5_query_hca_port(ibdev, port, props); 939 940 case MLX5_VPORT_ACCESS_METHOD_NIC: 941 return mlx5_query_port_roce(ibdev, port, props); 942 943 default: 944 return -EINVAL; 945 } 946 } 947 948 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 949 union ib_gid *gid) 950 { 951 struct mlx5_ib_dev *dev = to_mdev(ibdev); 952 struct mlx5_core_dev *mdev = dev->mdev; 953 954 switch (mlx5_get_vport_access_method(ibdev)) { 955 case MLX5_VPORT_ACCESS_METHOD_MAD: 956 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 957 958 case MLX5_VPORT_ACCESS_METHOD_HCA: 959 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid); 960 961 default: 962 return -EINVAL; 963 } 964 965 } 966 967 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 968 u16 *pkey) 969 { 970 struct mlx5_ib_dev *dev = to_mdev(ibdev); 971 struct mlx5_core_dev *mdev = dev->mdev; 972 973 switch (mlx5_get_vport_access_method(ibdev)) { 974 case MLX5_VPORT_ACCESS_METHOD_MAD: 975 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 976 977 case MLX5_VPORT_ACCESS_METHOD_HCA: 978 case MLX5_VPORT_ACCESS_METHOD_NIC: 979 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 980 pkey); 981 default: 982 return -EINVAL; 983 } 984 } 985 986 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 987 struct ib_device_modify *props) 988 { 989 struct mlx5_ib_dev *dev = to_mdev(ibdev); 990 struct mlx5_reg_node_desc in; 991 struct mlx5_reg_node_desc out; 992 int err; 993 994 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 995 return -EOPNOTSUPP; 996 997 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 998 return 0; 999 1000 /* 1001 * If possible, pass node desc to FW, so it can generate 1002 * a 144 trap. If cmd fails, just ignore. 1003 */ 1004 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1005 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1006 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1007 if (err) 1008 return err; 1009 1010 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1011 1012 return err; 1013 } 1014 1015 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1016 struct ib_port_modify *props) 1017 { 1018 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1019 struct ib_port_attr attr; 1020 u32 tmp; 1021 int err; 1022 1023 mutex_lock(&dev->cap_mask_mutex); 1024 1025 err = mlx5_ib_query_port(ibdev, port, &attr); 1026 if (err) 1027 goto out; 1028 1029 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1030 ~props->clr_port_cap_mask; 1031 1032 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1033 1034 out: 1035 mutex_unlock(&dev->cap_mask_mutex); 1036 return err; 1037 } 1038 1039 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1040 struct ib_udata *udata) 1041 { 1042 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1043 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1044 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1045 struct mlx5_ib_ucontext *context; 1046 struct mlx5_uuar_info *uuari; 1047 struct mlx5_uar *uars; 1048 int gross_uuars; 1049 int num_uars; 1050 int ver; 1051 int uuarn; 1052 int err; 1053 int i; 1054 size_t reqlen; 1055 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1056 max_cqe_version); 1057 1058 if (!dev->ib_active) 1059 return ERR_PTR(-EAGAIN); 1060 1061 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 1062 return ERR_PTR(-EINVAL); 1063 1064 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 1065 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1066 ver = 0; 1067 else if (reqlen >= min_req_v2) 1068 ver = 2; 1069 else 1070 return ERR_PTR(-EINVAL); 1071 1072 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 1073 if (err) 1074 return ERR_PTR(err); 1075 1076 if (req.flags) 1077 return ERR_PTR(-EINVAL); 1078 1079 if (req.total_num_uuars > MLX5_MAX_UUARS) 1080 return ERR_PTR(-ENOMEM); 1081 1082 if (req.total_num_uuars == 0) 1083 return ERR_PTR(-EINVAL); 1084 1085 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1086 return ERR_PTR(-EOPNOTSUPP); 1087 1088 if (reqlen > sizeof(req) && 1089 !ib_is_udata_cleared(udata, sizeof(req), 1090 reqlen - sizeof(req))) 1091 return ERR_PTR(-EOPNOTSUPP); 1092 1093 req.total_num_uuars = ALIGN(req.total_num_uuars, 1094 MLX5_NON_FP_BF_REGS_PER_PAGE); 1095 if (req.num_low_latency_uuars > req.total_num_uuars - 1) 1096 return ERR_PTR(-EINVAL); 1097 1098 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; 1099 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; 1100 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1101 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1102 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1103 resp.cache_line_size = cache_line_size(); 1104 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1105 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1106 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1107 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1108 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1109 resp.cqe_version = min_t(__u8, 1110 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1111 req.max_cqe_version); 1112 resp.response_length = min(offsetof(typeof(resp), response_length) + 1113 sizeof(resp.response_length), udata->outlen); 1114 1115 context = kzalloc(sizeof(*context), GFP_KERNEL); 1116 if (!context) 1117 return ERR_PTR(-ENOMEM); 1118 1119 uuari = &context->uuari; 1120 mutex_init(&uuari->lock); 1121 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); 1122 if (!uars) { 1123 err = -ENOMEM; 1124 goto out_ctx; 1125 } 1126 1127 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), 1128 sizeof(*uuari->bitmap), 1129 GFP_KERNEL); 1130 if (!uuari->bitmap) { 1131 err = -ENOMEM; 1132 goto out_uar_ctx; 1133 } 1134 /* 1135 * clear all fast path uuars 1136 */ 1137 for (i = 0; i < gross_uuars; i++) { 1138 uuarn = i & 3; 1139 if (uuarn == 2 || uuarn == 3) 1140 set_bit(i, uuari->bitmap); 1141 } 1142 1143 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); 1144 if (!uuari->count) { 1145 err = -ENOMEM; 1146 goto out_bitmap; 1147 } 1148 1149 for (i = 0; i < num_uars; i++) { 1150 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); 1151 if (err) 1152 goto out_count; 1153 } 1154 1155 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1156 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1157 #endif 1158 1159 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1160 err = mlx5_alloc_transport_domain(dev->mdev, 1161 &context->tdn); 1162 if (err) 1163 goto out_uars; 1164 } 1165 1166 INIT_LIST_HEAD(&context->vma_private_list); 1167 INIT_LIST_HEAD(&context->db_page_list); 1168 mutex_init(&context->db_page_mutex); 1169 1170 resp.tot_uuars = req.total_num_uuars; 1171 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1172 1173 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1174 resp.response_length += sizeof(resp.cqe_version); 1175 1176 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1177 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1178 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1179 resp.response_length += sizeof(resp.cmds_supp_uhw); 1180 } 1181 1182 /* 1183 * We don't want to expose information from the PCI bar that is located 1184 * after 4096 bytes, so if the arch only supports larger pages, let's 1185 * pretend we don't support reading the HCA's core clock. This is also 1186 * forced by mmap function. 1187 */ 1188 if (PAGE_SIZE <= 4096 && 1189 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1190 resp.comp_mask |= 1191 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1192 resp.hca_core_clock_offset = 1193 offsetof(struct mlx5_init_seg, internal_timer_h) % 1194 PAGE_SIZE; 1195 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1196 sizeof(resp.reserved2); 1197 } 1198 1199 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1200 if (err) 1201 goto out_td; 1202 1203 uuari->ver = ver; 1204 uuari->num_low_latency_uuars = req.num_low_latency_uuars; 1205 uuari->uars = uars; 1206 uuari->num_uars = num_uars; 1207 context->cqe_version = resp.cqe_version; 1208 1209 return &context->ibucontext; 1210 1211 out_td: 1212 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1213 mlx5_dealloc_transport_domain(dev->mdev, context->tdn); 1214 1215 out_uars: 1216 for (i--; i >= 0; i--) 1217 mlx5_cmd_free_uar(dev->mdev, uars[i].index); 1218 out_count: 1219 kfree(uuari->count); 1220 1221 out_bitmap: 1222 kfree(uuari->bitmap); 1223 1224 out_uar_ctx: 1225 kfree(uars); 1226 1227 out_ctx: 1228 kfree(context); 1229 return ERR_PTR(err); 1230 } 1231 1232 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1233 { 1234 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1235 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1236 struct mlx5_uuar_info *uuari = &context->uuari; 1237 int i; 1238 1239 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1240 mlx5_dealloc_transport_domain(dev->mdev, context->tdn); 1241 1242 for (i = 0; i < uuari->num_uars; i++) { 1243 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) 1244 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); 1245 } 1246 1247 kfree(uuari->count); 1248 kfree(uuari->bitmap); 1249 kfree(uuari->uars); 1250 kfree(context); 1251 1252 return 0; 1253 } 1254 1255 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) 1256 { 1257 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; 1258 } 1259 1260 static int get_command(unsigned long offset) 1261 { 1262 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1263 } 1264 1265 static int get_arg(unsigned long offset) 1266 { 1267 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1268 } 1269 1270 static int get_index(unsigned long offset) 1271 { 1272 return get_arg(offset); 1273 } 1274 1275 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1276 { 1277 /* vma_open is called when a new VMA is created on top of our VMA. This 1278 * is done through either mremap flow or split_vma (usually due to 1279 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1280 * as this VMA is strongly hardware related. Therefore we set the 1281 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1282 * calling us again and trying to do incorrect actions. We assume that 1283 * the original VMA size is exactly a single page, and therefore all 1284 * "splitting" operation will not happen to it. 1285 */ 1286 area->vm_ops = NULL; 1287 } 1288 1289 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1290 { 1291 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1292 1293 /* It's guaranteed that all VMAs opened on a FD are closed before the 1294 * file itself is closed, therefore no sync is needed with the regular 1295 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1296 * However need a sync with accessing the vma as part of 1297 * mlx5_ib_disassociate_ucontext. 1298 * The close operation is usually called under mm->mmap_sem except when 1299 * process is exiting. 1300 * The exiting case is handled explicitly as part of 1301 * mlx5_ib_disassociate_ucontext. 1302 */ 1303 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1304 1305 /* setting the vma context pointer to null in the mlx5_ib driver's 1306 * private data, to protect a race condition in 1307 * mlx5_ib_disassociate_ucontext(). 1308 */ 1309 mlx5_ib_vma_priv_data->vma = NULL; 1310 list_del(&mlx5_ib_vma_priv_data->list); 1311 kfree(mlx5_ib_vma_priv_data); 1312 } 1313 1314 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1315 .open = mlx5_ib_vma_open, 1316 .close = mlx5_ib_vma_close 1317 }; 1318 1319 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1320 struct mlx5_ib_ucontext *ctx) 1321 { 1322 struct mlx5_ib_vma_private_data *vma_prv; 1323 struct list_head *vma_head = &ctx->vma_private_list; 1324 1325 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1326 if (!vma_prv) 1327 return -ENOMEM; 1328 1329 vma_prv->vma = vma; 1330 vma->vm_private_data = vma_prv; 1331 vma->vm_ops = &mlx5_ib_vm_ops; 1332 1333 list_add(&vma_prv->list, vma_head); 1334 1335 return 0; 1336 } 1337 1338 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1339 { 1340 switch (cmd) { 1341 case MLX5_IB_MMAP_WC_PAGE: 1342 return "WC"; 1343 case MLX5_IB_MMAP_REGULAR_PAGE: 1344 return "best effort WC"; 1345 case MLX5_IB_MMAP_NC_PAGE: 1346 return "NC"; 1347 default: 1348 return NULL; 1349 } 1350 } 1351 1352 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1353 struct vm_area_struct *vma, 1354 struct mlx5_ib_ucontext *context) 1355 { 1356 struct mlx5_uuar_info *uuari = &context->uuari; 1357 int err; 1358 unsigned long idx; 1359 phys_addr_t pfn, pa; 1360 pgprot_t prot; 1361 1362 switch (cmd) { 1363 case MLX5_IB_MMAP_WC_PAGE: 1364 /* Some architectures don't support WC memory */ 1365 #if defined(CONFIG_X86) 1366 if (!pat_enabled()) 1367 return -EPERM; 1368 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1369 return -EPERM; 1370 #endif 1371 /* fall through */ 1372 case MLX5_IB_MMAP_REGULAR_PAGE: 1373 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1374 prot = pgprot_writecombine(vma->vm_page_prot); 1375 break; 1376 case MLX5_IB_MMAP_NC_PAGE: 1377 prot = pgprot_noncached(vma->vm_page_prot); 1378 break; 1379 default: 1380 return -EINVAL; 1381 } 1382 1383 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1384 return -EINVAL; 1385 1386 idx = get_index(vma->vm_pgoff); 1387 if (idx >= uuari->num_uars) 1388 return -EINVAL; 1389 1390 pfn = uar_index2pfn(dev, uuari->uars[idx].index); 1391 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1392 1393 vma->vm_page_prot = prot; 1394 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1395 PAGE_SIZE, vma->vm_page_prot); 1396 if (err) { 1397 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%llx, pfn=%pa, mmap_cmd=%s\n", 1398 err, (unsigned long long)vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1399 return -EAGAIN; 1400 } 1401 1402 pa = pfn << PAGE_SHIFT; 1403 mlx5_ib_dbg(dev, "mapped %s at 0x%llx, PA %pa\n", mmap_cmd2str(cmd), 1404 (unsigned long long)vma->vm_start, &pa); 1405 1406 return mlx5_ib_set_vma_data(vma, context); 1407 } 1408 1409 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1410 { 1411 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1412 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1413 unsigned long command; 1414 phys_addr_t pfn; 1415 1416 command = get_command(vma->vm_pgoff); 1417 switch (command) { 1418 case MLX5_IB_MMAP_WC_PAGE: 1419 case MLX5_IB_MMAP_NC_PAGE: 1420 case MLX5_IB_MMAP_REGULAR_PAGE: 1421 return uar_mmap(dev, command, vma, context); 1422 1423 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1424 return -ENOSYS; 1425 1426 case MLX5_IB_MMAP_CORE_CLOCK: 1427 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1428 return -EINVAL; 1429 1430 if (vma->vm_flags & VM_WRITE) 1431 return -EPERM; 1432 1433 /* Don't expose to user-space information it shouldn't have */ 1434 if (PAGE_SIZE > 4096) 1435 return -EOPNOTSUPP; 1436 1437 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1438 pfn = (dev->mdev->iseg_base + 1439 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1440 PAGE_SHIFT; 1441 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1442 PAGE_SIZE, vma->vm_page_prot)) 1443 return -EAGAIN; 1444 1445 mlx5_ib_dbg(dev, "mapped internal timer at 0x%llx, PA 0x%llx\n", 1446 (unsigned long long)vma->vm_start, 1447 (unsigned long long)pfn << PAGE_SHIFT); 1448 break; 1449 1450 default: 1451 return -EINVAL; 1452 } 1453 1454 return 0; 1455 } 1456 1457 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1458 struct ib_ucontext *context, 1459 struct ib_udata *udata) 1460 { 1461 struct mlx5_ib_alloc_pd_resp resp; 1462 struct mlx5_ib_pd *pd; 1463 int err; 1464 1465 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1466 if (!pd) 1467 return ERR_PTR(-ENOMEM); 1468 1469 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1470 if (err) { 1471 kfree(pd); 1472 return ERR_PTR(err); 1473 } 1474 1475 if (context) { 1476 resp.pdn = pd->pdn; 1477 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1478 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1479 kfree(pd); 1480 return ERR_PTR(-EFAULT); 1481 } 1482 } 1483 1484 return &pd->ibpd; 1485 } 1486 1487 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1488 { 1489 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1490 struct mlx5_ib_pd *mpd = to_mpd(pd); 1491 1492 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1493 kfree(mpd); 1494 1495 return 0; 1496 } 1497 1498 enum { 1499 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1500 MATCH_CRITERIA_ENABLE_MISC_BIT, 1501 MATCH_CRITERIA_ENABLE_INNER_BIT 1502 }; 1503 1504 #define HEADER_IS_ZERO(match_criteria, headers) \ 1505 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1506 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1507 1508 static u8 get_match_criteria_enable(u32 *match_criteria) 1509 { 1510 u8 match_criteria_enable; 1511 1512 match_criteria_enable = 1513 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1514 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1515 match_criteria_enable |= 1516 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1517 MATCH_CRITERIA_ENABLE_MISC_BIT; 1518 match_criteria_enable |= 1519 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1520 MATCH_CRITERIA_ENABLE_INNER_BIT; 1521 1522 return match_criteria_enable; 1523 } 1524 1525 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1526 { 1527 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1528 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1529 } 1530 1531 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1532 { 1533 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1534 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1535 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1536 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1537 } 1538 1539 #define LAST_ETH_FIELD vlan_tag 1540 #define LAST_IB_FIELD sl 1541 #define LAST_IPV4_FIELD tos 1542 #define LAST_IPV6_FIELD traffic_class 1543 #define LAST_TCP_UDP_FIELD src_port 1544 1545 /* Field is the last supported field */ 1546 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1547 memchr_inv((void *)&filter.field +\ 1548 sizeof(filter.field), 0,\ 1549 sizeof(filter) -\ 1550 offsetof(typeof(filter), field) -\ 1551 sizeof(filter.field)) 1552 1553 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1554 const union ib_flow_spec *ib_spec) 1555 { 1556 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1557 outer_headers); 1558 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1559 outer_headers); 1560 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1561 misc_parameters); 1562 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1563 misc_parameters); 1564 1565 switch (ib_spec->type) { 1566 case IB_FLOW_SPEC_ETH: 1567 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1568 return -ENOTSUPP; 1569 1570 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1571 dmac_47_16), 1572 ib_spec->eth.mask.dst_mac); 1573 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1574 dmac_47_16), 1575 ib_spec->eth.val.dst_mac); 1576 1577 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1578 smac_47_16), 1579 ib_spec->eth.mask.src_mac); 1580 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1581 smac_47_16), 1582 ib_spec->eth.val.src_mac); 1583 1584 if (ib_spec->eth.mask.vlan_tag) { 1585 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1586 cvlan_tag, 1); 1587 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1588 cvlan_tag, 1); 1589 1590 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1591 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1592 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1593 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1594 1595 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1596 first_cfi, 1597 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1598 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1599 first_cfi, 1600 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1601 1602 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1603 first_prio, 1604 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1605 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1606 first_prio, 1607 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1608 } 1609 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1610 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1611 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1612 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1613 break; 1614 case IB_FLOW_SPEC_IPV4: 1615 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1616 return -ENOTSUPP; 1617 1618 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1619 ethertype, 0xffff); 1620 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1621 ethertype, ETH_P_IP); 1622 1623 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1624 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1625 &ib_spec->ipv4.mask.src_ip, 1626 sizeof(ib_spec->ipv4.mask.src_ip)); 1627 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1628 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1629 &ib_spec->ipv4.val.src_ip, 1630 sizeof(ib_spec->ipv4.val.src_ip)); 1631 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1632 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1633 &ib_spec->ipv4.mask.dst_ip, 1634 sizeof(ib_spec->ipv4.mask.dst_ip)); 1635 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1636 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1637 &ib_spec->ipv4.val.dst_ip, 1638 sizeof(ib_spec->ipv4.val.dst_ip)); 1639 1640 set_tos(outer_headers_c, outer_headers_v, 1641 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1642 1643 set_proto(outer_headers_c, outer_headers_v, 1644 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1645 break; 1646 case IB_FLOW_SPEC_IPV6: 1647 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1648 return -ENOTSUPP; 1649 1650 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1651 ethertype, 0xffff); 1652 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1653 ethertype, IPPROTO_IPV6); 1654 1655 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1656 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1657 &ib_spec->ipv6.mask.src_ip, 1658 sizeof(ib_spec->ipv6.mask.src_ip)); 1659 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1660 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1661 &ib_spec->ipv6.val.src_ip, 1662 sizeof(ib_spec->ipv6.val.src_ip)); 1663 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1664 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1665 &ib_spec->ipv6.mask.dst_ip, 1666 sizeof(ib_spec->ipv6.mask.dst_ip)); 1667 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1668 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1669 &ib_spec->ipv6.val.dst_ip, 1670 sizeof(ib_spec->ipv6.val.dst_ip)); 1671 1672 set_tos(outer_headers_c, outer_headers_v, 1673 ib_spec->ipv6.mask.traffic_class, 1674 ib_spec->ipv6.val.traffic_class); 1675 1676 set_proto(outer_headers_c, outer_headers_v, 1677 ib_spec->ipv6.mask.next_hdr, 1678 ib_spec->ipv6.val.next_hdr); 1679 1680 MLX5_SET(fte_match_set_misc, misc_params_c, 1681 outer_ipv6_flow_label, 1682 ntohl(ib_spec->ipv6.mask.flow_label)); 1683 MLX5_SET(fte_match_set_misc, misc_params_v, 1684 outer_ipv6_flow_label, 1685 ntohl(ib_spec->ipv6.val.flow_label)); 1686 break; 1687 case IB_FLOW_SPEC_TCP: 1688 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1689 LAST_TCP_UDP_FIELD)) 1690 return -ENOTSUPP; 1691 1692 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1693 0xff); 1694 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1695 IPPROTO_TCP); 1696 1697 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1698 ntohs(ib_spec->tcp_udp.mask.src_port)); 1699 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1700 ntohs(ib_spec->tcp_udp.val.src_port)); 1701 1702 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1703 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1704 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1705 ntohs(ib_spec->tcp_udp.val.dst_port)); 1706 break; 1707 case IB_FLOW_SPEC_UDP: 1708 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1709 LAST_TCP_UDP_FIELD)) 1710 return -ENOTSUPP; 1711 1712 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1713 0xff); 1714 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1715 IPPROTO_UDP); 1716 1717 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1718 ntohs(ib_spec->tcp_udp.mask.src_port)); 1719 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1720 ntohs(ib_spec->tcp_udp.val.src_port)); 1721 1722 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1723 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1724 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1725 ntohs(ib_spec->tcp_udp.val.dst_port)); 1726 break; 1727 default: 1728 return -EINVAL; 1729 } 1730 1731 return 0; 1732 } 1733 1734 /* If a flow could catch both multicast and unicast packets, 1735 * it won't fall into the multicast flow steering table and this rule 1736 * could steal other multicast packets. 1737 */ 1738 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1739 { 1740 struct ib_flow_spec_eth *eth_spec; 1741 1742 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1743 ib_attr->size < sizeof(struct ib_flow_attr) + 1744 sizeof(struct ib_flow_spec_eth) || 1745 ib_attr->num_of_specs < 1) 1746 return false; 1747 1748 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1749 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1750 eth_spec->size != sizeof(*eth_spec)) 1751 return false; 1752 1753 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1754 is_multicast_ether_addr(eth_spec->val.dst_mac); 1755 } 1756 1757 static bool is_valid_attr(const struct ib_flow_attr *flow_attr) 1758 { 1759 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1760 bool has_ipv4_spec = false; 1761 bool eth_type_ipv4 = true; 1762 unsigned int spec_index; 1763 1764 /* Validate that ethertype is correct */ 1765 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1766 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1767 ib_spec->eth.mask.ether_type) { 1768 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1769 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1770 eth_type_ipv4 = false; 1771 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1772 has_ipv4_spec = true; 1773 } 1774 ib_spec = (void *)ib_spec + ib_spec->size; 1775 } 1776 return !has_ipv4_spec || eth_type_ipv4; 1777 } 1778 1779 static void put_flow_table(struct mlx5_ib_dev *dev, 1780 struct mlx5_ib_flow_prio *prio, bool ft_added) 1781 { 1782 prio->refcount -= !!ft_added; 1783 if (!prio->refcount) { 1784 mlx5_destroy_flow_table(prio->flow_table); 1785 prio->flow_table = NULL; 1786 } 1787 } 1788 1789 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 1790 { 1791 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 1792 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 1793 struct mlx5_ib_flow_handler, 1794 ibflow); 1795 struct mlx5_ib_flow_handler *iter, *tmp; 1796 1797 mutex_lock(&dev->flow_db.lock); 1798 1799 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 1800 mlx5_del_flow_rule(iter->rule); 1801 put_flow_table(dev, iter->prio, true); 1802 list_del(&iter->list); 1803 kfree(iter); 1804 } 1805 1806 mlx5_del_flow_rule(handler->rule); 1807 put_flow_table(dev, handler->prio, true); 1808 mutex_unlock(&dev->flow_db.lock); 1809 1810 kfree(handler); 1811 1812 return 0; 1813 } 1814 1815 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 1816 { 1817 priority *= 2; 1818 if (!dont_trap) 1819 priority++; 1820 return priority; 1821 } 1822 1823 enum flow_table_type { 1824 MLX5_IB_FT_RX, 1825 MLX5_IB_FT_TX 1826 }; 1827 1828 #define MLX5_FS_MAX_TYPES 10 1829 #define MLX5_FS_MAX_ENTRIES 32000UL 1830 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 1831 struct ib_flow_attr *flow_attr, 1832 enum flow_table_type ft_type) 1833 { 1834 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 1835 struct mlx5_flow_namespace *ns = NULL; 1836 struct mlx5_ib_flow_prio *prio; 1837 struct mlx5_flow_table *ft; 1838 int num_entries; 1839 int num_groups; 1840 int priority; 1841 int err = 0; 1842 1843 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1844 if (flow_is_multicast_only(flow_attr) && 1845 !dont_trap) 1846 priority = MLX5_IB_FLOW_MCAST_PRIO; 1847 else 1848 priority = ib_prio_to_core_prio(flow_attr->priority, 1849 dont_trap); 1850 ns = mlx5_get_flow_namespace(dev->mdev, 1851 MLX5_FLOW_NAMESPACE_BYPASS); 1852 num_entries = MLX5_FS_MAX_ENTRIES; 1853 num_groups = MLX5_FS_MAX_TYPES; 1854 prio = &dev->flow_db.prios[priority]; 1855 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1856 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1857 ns = mlx5_get_flow_namespace(dev->mdev, 1858 MLX5_FLOW_NAMESPACE_LEFTOVERS); 1859 build_leftovers_ft_param("bypass", &priority, 1860 &num_entries, 1861 &num_groups); 1862 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 1863 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 1864 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 1865 allow_sniffer_and_nic_rx_shared_tir)) 1866 return ERR_PTR(-ENOTSUPP); 1867 1868 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 1869 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 1870 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 1871 1872 prio = &dev->flow_db.sniffer[ft_type]; 1873 priority = 0; 1874 num_entries = 1; 1875 num_groups = 1; 1876 } 1877 1878 if (!ns) 1879 return ERR_PTR(-ENOTSUPP); 1880 1881 ft = prio->flow_table; 1882 if (!ft) { 1883 ft = mlx5_create_auto_grouped_flow_table(ns, priority, "bypass", 1884 num_entries, 1885 num_groups); 1886 1887 if (!IS_ERR(ft)) { 1888 prio->refcount = 0; 1889 prio->flow_table = ft; 1890 } else { 1891 err = PTR_ERR(ft); 1892 } 1893 } 1894 1895 return err ? ERR_PTR(err) : prio; 1896 } 1897 1898 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 1899 struct mlx5_ib_flow_prio *ft_prio, 1900 const struct ib_flow_attr *flow_attr, 1901 struct mlx5_flow_destination *dst) 1902 { 1903 struct mlx5_flow_table *ft = ft_prio->flow_table; 1904 struct mlx5_ib_flow_handler *handler; 1905 struct mlx5_flow_spec *spec; 1906 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 1907 unsigned int spec_index; 1908 u32 action; 1909 int err = 0; 1910 1911 if (!is_valid_attr(flow_attr)) 1912 return ERR_PTR(-EINVAL); 1913 1914 spec = mlx5_vzalloc(sizeof(*spec)); 1915 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 1916 if (!handler || !spec) { 1917 err = -ENOMEM; 1918 goto free; 1919 } 1920 1921 INIT_LIST_HEAD(&handler->list); 1922 1923 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1924 err = parse_flow_attr(spec->match_criteria, 1925 spec->match_value, ib_flow); 1926 if (err < 0) 1927 goto free; 1928 1929 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 1930 } 1931 1932 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 1933 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 1934 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 1935 handler->rule = mlx5_add_flow_rule(ft, spec->match_criteria_enable, 1936 spec->match_criteria, 1937 spec->match_value, 1938 action, 1939 MLX5_FS_DEFAULT_FLOW_TAG, 1940 dst); 1941 1942 if (IS_ERR(handler->rule)) { 1943 err = PTR_ERR(handler->rule); 1944 goto free; 1945 } 1946 1947 ft_prio->refcount++; 1948 handler->prio = ft_prio; 1949 1950 ft_prio->flow_table = ft; 1951 free: 1952 if (err) 1953 kfree(handler); 1954 kvfree(spec); 1955 return err ? ERR_PTR(err) : handler; 1956 } 1957 1958 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 1959 struct mlx5_ib_flow_prio *ft_prio, 1960 struct ib_flow_attr *flow_attr, 1961 struct mlx5_flow_destination *dst) 1962 { 1963 struct mlx5_ib_flow_handler *handler_dst = NULL; 1964 struct mlx5_ib_flow_handler *handler = NULL; 1965 1966 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 1967 if (!IS_ERR(handler)) { 1968 handler_dst = create_flow_rule(dev, ft_prio, 1969 flow_attr, dst); 1970 if (IS_ERR(handler_dst)) { 1971 mlx5_del_flow_rule(handler->rule); 1972 ft_prio->refcount--; 1973 kfree(handler); 1974 handler = handler_dst; 1975 } else { 1976 list_add(&handler_dst->list, &handler->list); 1977 } 1978 } 1979 1980 return handler; 1981 } 1982 enum { 1983 LEFTOVERS_MC, 1984 LEFTOVERS_UC, 1985 }; 1986 1987 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 1988 struct mlx5_ib_flow_prio *ft_prio, 1989 struct ib_flow_attr *flow_attr, 1990 struct mlx5_flow_destination *dst) 1991 { 1992 struct mlx5_ib_flow_handler *handler_ucast = NULL; 1993 struct mlx5_ib_flow_handler *handler = NULL; 1994 1995 static struct { 1996 struct ib_flow_attr flow_attr; 1997 struct ib_flow_spec_eth eth_flow; 1998 } leftovers_specs[] = { 1999 [LEFTOVERS_MC] = { 2000 .flow_attr = { 2001 .num_of_specs = 1, 2002 .size = sizeof(leftovers_specs[0]) 2003 }, 2004 .eth_flow = { 2005 .type = IB_FLOW_SPEC_ETH, 2006 .size = sizeof(struct ib_flow_spec_eth), 2007 .mask = {.dst_mac = {0x1} }, 2008 .val = {.dst_mac = {0x1} } 2009 } 2010 }, 2011 [LEFTOVERS_UC] = { 2012 .flow_attr = { 2013 .num_of_specs = 1, 2014 .size = sizeof(leftovers_specs[0]) 2015 }, 2016 .eth_flow = { 2017 .type = IB_FLOW_SPEC_ETH, 2018 .size = sizeof(struct ib_flow_spec_eth), 2019 .mask = {.dst_mac = {0x1} }, 2020 .val = {.dst_mac = {} } 2021 } 2022 } 2023 }; 2024 2025 handler = create_flow_rule(dev, ft_prio, 2026 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2027 dst); 2028 if (!IS_ERR(handler) && 2029 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2030 handler_ucast = create_flow_rule(dev, ft_prio, 2031 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2032 dst); 2033 if (IS_ERR(handler_ucast)) { 2034 mlx5_del_flow_rule(handler->rule); 2035 ft_prio->refcount--; 2036 kfree(handler); 2037 handler = handler_ucast; 2038 } else { 2039 list_add(&handler_ucast->list, &handler->list); 2040 } 2041 } 2042 2043 return handler; 2044 } 2045 2046 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2047 struct mlx5_ib_flow_prio *ft_rx, 2048 struct mlx5_ib_flow_prio *ft_tx, 2049 struct mlx5_flow_destination *dst) 2050 { 2051 struct mlx5_ib_flow_handler *handler_rx; 2052 struct mlx5_ib_flow_handler *handler_tx; 2053 int err; 2054 static const struct ib_flow_attr flow_attr = { 2055 .num_of_specs = 0, 2056 .size = sizeof(flow_attr) 2057 }; 2058 2059 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2060 if (IS_ERR(handler_rx)) { 2061 err = PTR_ERR(handler_rx); 2062 goto err; 2063 } 2064 2065 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2066 if (IS_ERR(handler_tx)) { 2067 err = PTR_ERR(handler_tx); 2068 goto err_tx; 2069 } 2070 2071 list_add(&handler_tx->list, &handler_rx->list); 2072 2073 return handler_rx; 2074 2075 err_tx: 2076 mlx5_del_flow_rule(handler_rx->rule); 2077 ft_rx->refcount--; 2078 kfree(handler_rx); 2079 err: 2080 return ERR_PTR(err); 2081 } 2082 2083 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2084 struct ib_flow_attr *flow_attr, 2085 int domain) 2086 { 2087 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2088 struct mlx5_ib_qp *mqp = to_mqp(qp); 2089 struct mlx5_ib_flow_handler *handler = NULL; 2090 struct mlx5_flow_destination *dst = NULL; 2091 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2092 struct mlx5_ib_flow_prio *ft_prio; 2093 int err; 2094 2095 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2096 return ERR_PTR(-ENOSPC); 2097 2098 if (domain != IB_FLOW_DOMAIN_USER || 2099 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2100 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2101 return ERR_PTR(-EINVAL); 2102 2103 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2104 if (!dst) 2105 return ERR_PTR(-ENOMEM); 2106 2107 mutex_lock(&dev->flow_db.lock); 2108 2109 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2110 if (IS_ERR(ft_prio)) { 2111 err = PTR_ERR(ft_prio); 2112 goto unlock; 2113 } 2114 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2115 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2116 if (IS_ERR(ft_prio_tx)) { 2117 err = PTR_ERR(ft_prio_tx); 2118 ft_prio_tx = NULL; 2119 goto destroy_ft; 2120 } 2121 } 2122 2123 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2124 if (mqp->flags & MLX5_IB_QP_RSS) 2125 dst->tir_num = mqp->rss_qp.tirn; 2126 else 2127 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2128 2129 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2130 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2131 handler = create_dont_trap_rule(dev, ft_prio, 2132 flow_attr, dst); 2133 } else { 2134 handler = create_flow_rule(dev, ft_prio, flow_attr, 2135 dst); 2136 } 2137 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2138 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2139 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2140 dst); 2141 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2142 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2143 } else { 2144 err = -EINVAL; 2145 goto destroy_ft; 2146 } 2147 2148 if (IS_ERR(handler)) { 2149 err = PTR_ERR(handler); 2150 handler = NULL; 2151 goto destroy_ft; 2152 } 2153 2154 mutex_unlock(&dev->flow_db.lock); 2155 kfree(dst); 2156 2157 return &handler->ibflow; 2158 2159 destroy_ft: 2160 put_flow_table(dev, ft_prio, false); 2161 if (ft_prio_tx) 2162 put_flow_table(dev, ft_prio_tx, false); 2163 unlock: 2164 mutex_unlock(&dev->flow_db.lock); 2165 kfree(dst); 2166 kfree(handler); 2167 return ERR_PTR(err); 2168 } 2169 2170 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2171 { 2172 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2173 int err; 2174 2175 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2176 if (err) 2177 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2178 ibqp->qp_num, gid->raw); 2179 2180 return err; 2181 } 2182 2183 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2184 { 2185 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2186 int err; 2187 2188 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2189 if (err) 2190 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2191 ibqp->qp_num, gid->raw); 2192 2193 return err; 2194 } 2195 2196 static int init_node_data(struct mlx5_ib_dev *dev) 2197 { 2198 int err; 2199 2200 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2201 if (err) 2202 return err; 2203 2204 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2205 } 2206 2207 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2208 char *buf) 2209 { 2210 struct mlx5_ib_dev *dev = 2211 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2212 2213 return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages); 2214 } 2215 2216 static ssize_t show_reg_pages(struct device *device, 2217 struct device_attribute *attr, char *buf) 2218 { 2219 struct mlx5_ib_dev *dev = 2220 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2221 2222 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2223 } 2224 2225 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2226 char *buf) 2227 { 2228 struct mlx5_ib_dev *dev = 2229 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2230 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2231 } 2232 2233 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2234 char *buf) 2235 { 2236 struct mlx5_ib_dev *dev = 2237 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2238 return sprintf(buf, "%x\n", dev->mdev->pdev->revision); 2239 } 2240 2241 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2242 char *buf) 2243 { 2244 struct mlx5_ib_dev *dev = 2245 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2246 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2247 dev->mdev->board_id); 2248 } 2249 2250 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2251 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2252 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2253 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2254 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2255 2256 static struct device_attribute *mlx5_class_attributes[] = { 2257 &dev_attr_hw_rev, 2258 &dev_attr_hca_type, 2259 &dev_attr_board_id, 2260 &dev_attr_fw_pages, 2261 &dev_attr_reg_pages, 2262 }; 2263 2264 static void pkey_change_handler(struct work_struct *work) 2265 { 2266 struct mlx5_ib_port_resources *ports = 2267 container_of(work, struct mlx5_ib_port_resources, 2268 pkey_change_work); 2269 2270 mutex_lock(&ports->devr->mutex); 2271 mlx5_ib_gsi_pkey_change(ports->gsi); 2272 mutex_unlock(&ports->devr->mutex); 2273 } 2274 2275 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2276 { 2277 struct mlx5_ib_qp *mqp; 2278 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2279 struct mlx5_core_cq *mcq; 2280 struct list_head cq_armed_list; 2281 unsigned long flags_qp; 2282 unsigned long flags_cq; 2283 unsigned long flags; 2284 2285 INIT_LIST_HEAD(&cq_armed_list); 2286 2287 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2288 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2289 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2290 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2291 if (mqp->sq.tail != mqp->sq.head) { 2292 send_mcq = to_mcq(mqp->ibqp.send_cq); 2293 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2294 if (send_mcq->mcq.comp && 2295 mqp->ibqp.send_cq->comp_handler) { 2296 if (!send_mcq->mcq.reset_notify_added) { 2297 send_mcq->mcq.reset_notify_added = 1; 2298 list_add_tail(&send_mcq->mcq.reset_notify, 2299 &cq_armed_list); 2300 } 2301 } 2302 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2303 } 2304 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2305 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2306 /* no handling is needed for SRQ */ 2307 if (!mqp->ibqp.srq) { 2308 if (mqp->rq.tail != mqp->rq.head) { 2309 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2310 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2311 if (recv_mcq->mcq.comp && 2312 mqp->ibqp.recv_cq->comp_handler) { 2313 if (!recv_mcq->mcq.reset_notify_added) { 2314 recv_mcq->mcq.reset_notify_added = 1; 2315 list_add_tail(&recv_mcq->mcq.reset_notify, 2316 &cq_armed_list); 2317 } 2318 } 2319 spin_unlock_irqrestore(&recv_mcq->lock, 2320 flags_cq); 2321 } 2322 } 2323 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2324 } 2325 /*At that point all inflight post send were put to be executed as of we 2326 * lock/unlock above locks Now need to arm all involved CQs. 2327 */ 2328 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2329 mcq->comp(mcq); 2330 } 2331 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2332 } 2333 2334 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2335 enum mlx5_dev_event event, unsigned long param) 2336 { 2337 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2338 struct ib_event ibev; 2339 bool fatal = false; 2340 u8 port = (u8)param; 2341 2342 switch (event) { 2343 case MLX5_DEV_EVENT_SYS_ERROR: 2344 ibev.event = IB_EVENT_DEVICE_FATAL; 2345 mlx5_ib_handle_internal_error(ibdev); 2346 fatal = true; 2347 break; 2348 2349 case MLX5_DEV_EVENT_PORT_UP: 2350 case MLX5_DEV_EVENT_PORT_DOWN: 2351 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2352 /* In RoCE, port up/down events are handled in 2353 * mlx5_netdev_event(). 2354 */ 2355 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2356 IB_LINK_LAYER_ETHERNET) 2357 return; 2358 2359 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2360 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2361 break; 2362 2363 case MLX5_DEV_EVENT_LID_CHANGE: 2364 ibev.event = IB_EVENT_LID_CHANGE; 2365 break; 2366 2367 case MLX5_DEV_EVENT_PKEY_CHANGE: 2368 ibev.event = IB_EVENT_PKEY_CHANGE; 2369 2370 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2371 break; 2372 2373 case MLX5_DEV_EVENT_GUID_CHANGE: 2374 ibev.event = IB_EVENT_GID_CHANGE; 2375 break; 2376 2377 case MLX5_DEV_EVENT_CLIENT_REREG: 2378 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2379 break; 2380 2381 default: 2382 /* unsupported event */ 2383 return; 2384 } 2385 2386 ibev.device = &ibdev->ib_dev; 2387 ibev.element.port_num = port; 2388 2389 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 2390 mlx5_ib_warn(ibdev, "warning: event(%d) on port %d\n", event, port); 2391 return; 2392 } 2393 2394 if (ibdev->ib_active) 2395 ib_dispatch_event(&ibev); 2396 2397 if (fatal) 2398 ibdev->ib_active = false; 2399 } 2400 2401 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2402 { 2403 int port; 2404 2405 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2406 mlx5_query_ext_port_caps(dev, port); 2407 } 2408 2409 static int get_port_caps(struct mlx5_ib_dev *dev) 2410 { 2411 struct ib_device_attr *dprops = NULL; 2412 struct ib_port_attr *pprops = NULL; 2413 int err = -ENOMEM; 2414 int port; 2415 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2416 2417 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2418 if (!pprops) 2419 goto out; 2420 2421 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2422 if (!dprops) 2423 goto out; 2424 2425 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2426 if (err) { 2427 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2428 goto out; 2429 } 2430 2431 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2432 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2433 if (err) { 2434 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2435 port, err); 2436 break; 2437 } 2438 dev->mdev->port_caps[port - 1].pkey_table_len = 2439 dprops->max_pkeys; 2440 dev->mdev->port_caps[port - 1].gid_table_len = 2441 pprops->gid_tbl_len; 2442 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2443 dprops->max_pkeys, pprops->gid_tbl_len); 2444 } 2445 2446 out: 2447 kfree(pprops); 2448 kfree(dprops); 2449 2450 return err; 2451 } 2452 2453 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2454 { 2455 int err; 2456 2457 err = mlx5_mr_cache_cleanup(dev); 2458 if (err) 2459 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2460 2461 mlx5_ib_destroy_qp(dev->umrc.qp); 2462 ib_free_cq(dev->umrc.cq); 2463 ib_dealloc_pd(dev->umrc.pd); 2464 } 2465 2466 enum { 2467 MAX_UMR_WR = 128, 2468 }; 2469 2470 static int create_umr_res(struct mlx5_ib_dev *dev) 2471 { 2472 struct ib_qp_init_attr *init_attr = NULL; 2473 struct ib_qp_attr *attr = NULL; 2474 struct ib_pd *pd; 2475 struct ib_cq *cq; 2476 struct ib_qp *qp; 2477 int ret; 2478 2479 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2480 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2481 if (!attr || !init_attr) { 2482 ret = -ENOMEM; 2483 goto error_0; 2484 } 2485 2486 pd = ib_alloc_pd(&dev->ib_dev, 0); 2487 if (IS_ERR(pd)) { 2488 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2489 ret = PTR_ERR(pd); 2490 goto error_0; 2491 } 2492 2493 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2494 if (IS_ERR(cq)) { 2495 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2496 ret = PTR_ERR(cq); 2497 goto error_2; 2498 } 2499 2500 init_attr->send_cq = cq; 2501 init_attr->recv_cq = cq; 2502 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2503 init_attr->cap.max_send_wr = MAX_UMR_WR; 2504 init_attr->cap.max_send_sge = 1; 2505 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2506 init_attr->port_num = 1; 2507 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2508 if (IS_ERR(qp)) { 2509 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2510 ret = PTR_ERR(qp); 2511 goto error_3; 2512 } 2513 qp->device = &dev->ib_dev; 2514 qp->real_qp = qp; 2515 qp->uobject = NULL; 2516 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2517 2518 attr->qp_state = IB_QPS_INIT; 2519 attr->port_num = 1; 2520 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2521 IB_QP_PORT, NULL); 2522 if (ret) { 2523 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2524 goto error_4; 2525 } 2526 2527 memset(attr, 0, sizeof(*attr)); 2528 attr->qp_state = IB_QPS_RTR; 2529 attr->path_mtu = IB_MTU_256; 2530 2531 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2532 if (ret) { 2533 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2534 goto error_4; 2535 } 2536 2537 memset(attr, 0, sizeof(*attr)); 2538 attr->qp_state = IB_QPS_RTS; 2539 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2540 if (ret) { 2541 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2542 goto error_4; 2543 } 2544 2545 dev->umrc.qp = qp; 2546 dev->umrc.cq = cq; 2547 dev->umrc.pd = pd; 2548 2549 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2550 ret = mlx5_mr_cache_init(dev); 2551 if (ret) { 2552 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2553 goto error_4; 2554 } 2555 2556 kfree(attr); 2557 kfree(init_attr); 2558 2559 return 0; 2560 2561 error_4: 2562 mlx5_ib_destroy_qp(qp); 2563 2564 error_3: 2565 ib_free_cq(cq); 2566 2567 error_2: 2568 ib_dealloc_pd(pd); 2569 2570 error_0: 2571 kfree(attr); 2572 kfree(init_attr); 2573 return ret; 2574 } 2575 2576 static int create_dev_resources(struct mlx5_ib_resources *devr) 2577 { 2578 struct ib_srq_init_attr attr; 2579 struct mlx5_ib_dev *dev; 2580 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2581 int port; 2582 int ret = 0; 2583 2584 dev = container_of(devr, struct mlx5_ib_dev, devr); 2585 2586 mutex_init(&devr->mutex); 2587 2588 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2589 if (IS_ERR(devr->p0)) { 2590 ret = PTR_ERR(devr->p0); 2591 goto error0; 2592 } 2593 devr->p0->device = &dev->ib_dev; 2594 devr->p0->uobject = NULL; 2595 atomic_set(&devr->p0->usecnt, 0); 2596 2597 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 2598 if (IS_ERR(devr->c0)) { 2599 ret = PTR_ERR(devr->c0); 2600 goto error1; 2601 } 2602 devr->c0->device = &dev->ib_dev; 2603 devr->c0->uobject = NULL; 2604 devr->c0->comp_handler = NULL; 2605 devr->c0->event_handler = NULL; 2606 devr->c0->cq_context = NULL; 2607 atomic_set(&devr->c0->usecnt, 0); 2608 2609 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2610 if (IS_ERR(devr->x0)) { 2611 ret = PTR_ERR(devr->x0); 2612 goto error2; 2613 } 2614 devr->x0->device = &dev->ib_dev; 2615 devr->x0->inode = NULL; 2616 atomic_set(&devr->x0->usecnt, 0); 2617 mutex_init(&devr->x0->tgt_qp_mutex); 2618 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2619 2620 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2621 if (IS_ERR(devr->x1)) { 2622 ret = PTR_ERR(devr->x1); 2623 goto error3; 2624 } 2625 devr->x1->device = &dev->ib_dev; 2626 devr->x1->inode = NULL; 2627 atomic_set(&devr->x1->usecnt, 0); 2628 mutex_init(&devr->x1->tgt_qp_mutex); 2629 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2630 2631 memset(&attr, 0, sizeof(attr)); 2632 attr.attr.max_sge = 1; 2633 attr.attr.max_wr = 1; 2634 attr.srq_type = IB_SRQT_XRC; 2635 attr.ext.xrc.cq = devr->c0; 2636 attr.ext.xrc.xrcd = devr->x0; 2637 2638 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2639 if (IS_ERR(devr->s0)) { 2640 ret = PTR_ERR(devr->s0); 2641 goto error4; 2642 } 2643 devr->s0->device = &dev->ib_dev; 2644 devr->s0->pd = devr->p0; 2645 devr->s0->uobject = NULL; 2646 devr->s0->event_handler = NULL; 2647 devr->s0->srq_context = NULL; 2648 devr->s0->srq_type = IB_SRQT_XRC; 2649 devr->s0->ext.xrc.xrcd = devr->x0; 2650 devr->s0->ext.xrc.cq = devr->c0; 2651 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2652 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2653 atomic_inc(&devr->p0->usecnt); 2654 atomic_set(&devr->s0->usecnt, 0); 2655 2656 memset(&attr, 0, sizeof(attr)); 2657 attr.attr.max_sge = 1; 2658 attr.attr.max_wr = 1; 2659 attr.srq_type = IB_SRQT_BASIC; 2660 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2661 if (IS_ERR(devr->s1)) { 2662 ret = PTR_ERR(devr->s1); 2663 goto error5; 2664 } 2665 devr->s1->device = &dev->ib_dev; 2666 devr->s1->pd = devr->p0; 2667 devr->s1->uobject = NULL; 2668 devr->s1->event_handler = NULL; 2669 devr->s1->srq_context = NULL; 2670 devr->s1->srq_type = IB_SRQT_BASIC; 2671 devr->s1->ext.xrc.cq = devr->c0; 2672 atomic_inc(&devr->p0->usecnt); 2673 atomic_set(&devr->s0->usecnt, 0); 2674 2675 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 2676 INIT_WORK(&devr->ports[port].pkey_change_work, 2677 pkey_change_handler); 2678 devr->ports[port].devr = devr; 2679 } 2680 2681 return 0; 2682 2683 error5: 2684 mlx5_ib_destroy_srq(devr->s0); 2685 error4: 2686 mlx5_ib_dealloc_xrcd(devr->x1); 2687 error3: 2688 mlx5_ib_dealloc_xrcd(devr->x0); 2689 error2: 2690 mlx5_ib_destroy_cq(devr->c0); 2691 error1: 2692 mlx5_ib_dealloc_pd(devr->p0); 2693 error0: 2694 return ret; 2695 } 2696 2697 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2698 { 2699 struct mlx5_ib_dev *dev = 2700 container_of(devr, struct mlx5_ib_dev, devr); 2701 int port; 2702 2703 mlx5_ib_destroy_srq(devr->s1); 2704 mlx5_ib_destroy_srq(devr->s0); 2705 mlx5_ib_dealloc_xrcd(devr->x0); 2706 mlx5_ib_dealloc_xrcd(devr->x1); 2707 mlx5_ib_destroy_cq(devr->c0); 2708 mlx5_ib_dealloc_pd(devr->p0); 2709 2710 /* Make sure no change P_Key work items are still executing */ 2711 for (port = 0; port < dev->num_ports; ++port) 2712 cancel_work_sync(&devr->ports[port].pkey_change_work); 2713 } 2714 2715 static u32 get_core_cap_flags(struct ib_device *ibdev) 2716 { 2717 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2718 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2719 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2720 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2721 u32 ret = 0; 2722 2723 if (ll == IB_LINK_LAYER_INFINIBAND) 2724 return RDMA_CORE_PORT_IBA_IB; 2725 2726 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2727 return 0; 2728 2729 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2730 return 0; 2731 2732 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2733 ret |= RDMA_CORE_PORT_IBA_ROCE; 2734 2735 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2736 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2737 2738 return ret; 2739 } 2740 2741 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2742 struct ib_port_immutable *immutable) 2743 { 2744 struct ib_port_attr attr; 2745 int err; 2746 2747 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2748 if (err) 2749 return err; 2750 2751 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2752 immutable->gid_tbl_len = attr.gid_tbl_len; 2753 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2754 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2755 2756 return 0; 2757 } 2758 2759 static void get_dev_fw_str(struct ib_device *ibdev, char *str, 2760 size_t str_len) 2761 { 2762 struct mlx5_ib_dev *dev = 2763 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2764 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 2765 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 2766 } 2767 2768 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev) 2769 { 2770 return 0; 2771 } 2772 2773 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev) 2774 { 2775 } 2776 2777 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev) 2778 { 2779 if (dev->roce.nb.notifier_call) { 2780 unregister_netdevice_notifier(&dev->roce.nb); 2781 dev->roce.nb.notifier_call = NULL; 2782 } 2783 } 2784 2785 static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 2786 { 2787 VNET_ITERATOR_DECL(vnet_iter); 2788 struct net_device *idev; 2789 int err; 2790 2791 /* Check if mlx5en net device already exists */ 2792 VNET_LIST_RLOCK(); 2793 VNET_FOREACH(vnet_iter) { 2794 IFNET_RLOCK(); 2795 CURVNET_SET_QUIET(vnet_iter); 2796 CK_STAILQ_FOREACH(idev, &V_ifnet, if_link) { 2797 /* check if network interface belongs to mlx5en */ 2798 if (!mlx5_netdev_match(idev, dev->mdev, "mce")) 2799 continue; 2800 write_lock(&dev->roce.netdev_lock); 2801 dev->roce.netdev = idev; 2802 write_unlock(&dev->roce.netdev_lock); 2803 } 2804 CURVNET_RESTORE(); 2805 IFNET_RUNLOCK(); 2806 } 2807 VNET_LIST_RUNLOCK(); 2808 2809 dev->roce.nb.notifier_call = mlx5_netdev_event; 2810 err = register_netdevice_notifier(&dev->roce.nb); 2811 if (err) { 2812 dev->roce.nb.notifier_call = NULL; 2813 return err; 2814 } 2815 2816 err = mlx5_nic_vport_enable_roce(dev->mdev); 2817 if (err) 2818 goto err_unregister_netdevice_notifier; 2819 2820 err = mlx5_roce_lag_init(dev); 2821 if (err) 2822 goto err_disable_roce; 2823 2824 return 0; 2825 2826 err_disable_roce: 2827 mlx5_nic_vport_disable_roce(dev->mdev); 2828 2829 err_unregister_netdevice_notifier: 2830 mlx5_remove_roce_notifier(dev); 2831 return err; 2832 } 2833 2834 static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 2835 { 2836 mlx5_roce_lag_cleanup(dev); 2837 mlx5_nic_vport_disable_roce(dev->mdev); 2838 } 2839 2840 static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num) 2841 { 2842 mlx5_vport_dealloc_q_counter(dev->mdev, 2843 MLX5_INTERFACE_PROTOCOL_IB, 2844 dev->port[port_num].q_cnt_id); 2845 dev->port[port_num].q_cnt_id = 0; 2846 } 2847 2848 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 2849 { 2850 unsigned int i; 2851 2852 for (i = 0; i < dev->num_ports; i++) 2853 mlx5_ib_dealloc_q_port_counter(dev, i); 2854 } 2855 2856 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) 2857 { 2858 int i; 2859 int ret; 2860 2861 for (i = 0; i < dev->num_ports; i++) { 2862 ret = mlx5_vport_alloc_q_counter(dev->mdev, 2863 MLX5_INTERFACE_PROTOCOL_IB, 2864 &dev->port[i].q_cnt_id); 2865 if (ret) { 2866 mlx5_ib_warn(dev, 2867 "couldn't allocate queue counter for port %d, err %d\n", 2868 i + 1, ret); 2869 goto dealloc_counters; 2870 } 2871 } 2872 2873 return 0; 2874 2875 dealloc_counters: 2876 while (--i >= 0) 2877 mlx5_ib_dealloc_q_port_counter(dev, i); 2878 2879 return ret; 2880 } 2881 2882 static const char * const names[] = { 2883 "rx_write_requests", 2884 "rx_read_requests", 2885 "rx_atomic_requests", 2886 "out_of_buffer", 2887 "out_of_sequence", 2888 "duplicate_request", 2889 "rnr_nak_retry_err", 2890 "packet_seq_err", 2891 "implied_nak_seq_err", 2892 "local_ack_timeout_err", 2893 }; 2894 2895 static const size_t stats_offsets[] = { 2896 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests), 2897 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests), 2898 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests), 2899 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer), 2900 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence), 2901 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request), 2902 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err), 2903 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err), 2904 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err), 2905 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err), 2906 }; 2907 2908 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 2909 u8 port_num) 2910 { 2911 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets)); 2912 2913 /* We support only per port stats */ 2914 if (port_num == 0) 2915 return NULL; 2916 2917 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names), 2918 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2919 } 2920 2921 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 2922 struct rdma_hw_stats *stats, 2923 u8 port, int index) 2924 { 2925 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2926 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 2927 void *out; 2928 __be32 val; 2929 int ret; 2930 int i; 2931 2932 if (!port || !stats) 2933 return -ENOSYS; 2934 2935 out = mlx5_vzalloc(outlen); 2936 if (!out) 2937 return -ENOMEM; 2938 2939 ret = mlx5_vport_query_q_counter(dev->mdev, 2940 dev->port[port - 1].q_cnt_id, 0, 2941 out, outlen); 2942 if (ret) 2943 goto free; 2944 2945 for (i = 0; i < ARRAY_SIZE(names); i++) { 2946 val = *(__be32 *)(out + stats_offsets[i]); 2947 stats->value[i] = (u64)be32_to_cpu(val); 2948 } 2949 free: 2950 kvfree(out); 2951 return ARRAY_SIZE(names); 2952 } 2953 2954 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 2955 { 2956 struct mlx5_ib_dev *dev; 2957 enum rdma_link_layer ll; 2958 int port_type_cap; 2959 int err; 2960 int i; 2961 2962 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 2963 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 2964 2965 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) 2966 return NULL; 2967 2968 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 2969 if (!dev) 2970 return NULL; 2971 2972 dev->mdev = mdev; 2973 2974 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 2975 GFP_KERNEL); 2976 if (!dev->port) 2977 goto err_dealloc; 2978 2979 rwlock_init(&dev->roce.netdev_lock); 2980 err = get_port_caps(dev); 2981 if (err) 2982 goto err_free_port; 2983 2984 if (mlx5_use_mad_ifc(dev)) 2985 get_ext_port_caps(dev); 2986 2987 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 2988 2989 snprintf(dev->ib_dev.name, IB_DEVICE_NAME_MAX, "mlx5_%d", device_get_unit(mdev->pdev->dev.bsddev)); 2990 dev->ib_dev.owner = THIS_MODULE; 2991 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 2992 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 2993 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 2994 dev->ib_dev.phys_port_cnt = dev->num_ports; 2995 dev->ib_dev.num_comp_vectors = 2996 dev->mdev->priv.eq_table.num_comp_vectors; 2997 dev->ib_dev.dma_device = &mdev->pdev->dev; 2998 2999 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3000 dev->ib_dev.uverbs_cmd_mask = 3001 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3002 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3003 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3004 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3005 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3006 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3007 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3008 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3009 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3010 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3011 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3012 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3013 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3014 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3015 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3016 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3017 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3018 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3019 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3020 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3021 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3022 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3023 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3024 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3025 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3026 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3027 dev->ib_dev.uverbs_ex_cmd_mask = 3028 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3029 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3030 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 3031 3032 dev->ib_dev.query_device = mlx5_ib_query_device; 3033 dev->ib_dev.query_port = mlx5_ib_query_port; 3034 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3035 if (ll == IB_LINK_LAYER_ETHERNET) 3036 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3037 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3038 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3039 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3040 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3041 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3042 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3043 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3044 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3045 dev->ib_dev.mmap = mlx5_ib_mmap; 3046 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3047 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3048 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3049 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3050 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3051 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3052 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3053 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3054 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3055 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3056 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3057 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3058 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3059 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3060 dev->ib_dev.post_send = mlx5_ib_post_send; 3061 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3062 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3063 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3064 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3065 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3066 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3067 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3068 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3069 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3070 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3071 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3072 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3073 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3074 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3075 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3076 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3077 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3078 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3079 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3080 if (mlx5_core_is_pf(mdev)) { 3081 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3082 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3083 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3084 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3085 } 3086 3087 mlx5_ib_internal_fill_odp_caps(dev); 3088 3089 if (MLX5_CAP_GEN(mdev, imaicl)) { 3090 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3091 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3092 dev->ib_dev.uverbs_cmd_mask |= 3093 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3094 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3095 } 3096 3097 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) && 3098 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3099 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3100 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3101 } 3102 3103 if (MLX5_CAP_GEN(mdev, xrc)) { 3104 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3105 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3106 dev->ib_dev.uverbs_cmd_mask |= 3107 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3108 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3109 } 3110 3111 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3112 IB_LINK_LAYER_ETHERNET) { 3113 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3114 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3115 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3116 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3117 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3118 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3119 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3120 dev->ib_dev.uverbs_ex_cmd_mask |= 3121 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3122 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3123 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3124 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3125 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3126 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3127 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3128 } 3129 err = init_node_data(dev); 3130 if (err) 3131 goto err_free_port; 3132 3133 mutex_init(&dev->flow_db.lock); 3134 mutex_init(&dev->cap_mask_mutex); 3135 INIT_LIST_HEAD(&dev->qp_list); 3136 spin_lock_init(&dev->reset_flow_resource_lock); 3137 3138 if (ll == IB_LINK_LAYER_ETHERNET) { 3139 err = mlx5_enable_roce(dev); 3140 if (err) 3141 goto err_free_port; 3142 } 3143 3144 err = create_dev_resources(&dev->devr); 3145 if (err) 3146 goto err_disable_roce; 3147 3148 err = mlx5_ib_odp_init_one(dev); 3149 if (err) 3150 goto err_rsrc; 3151 3152 err = mlx5_ib_alloc_q_counters(dev); 3153 if (err) 3154 goto err_odp; 3155 3156 err = ib_register_device(&dev->ib_dev, NULL); 3157 if (err) 3158 goto err_q_cnt; 3159 3160 err = create_umr_res(dev); 3161 if (err) 3162 goto err_dev; 3163 3164 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3165 err = device_create_file(&dev->ib_dev.dev, 3166 mlx5_class_attributes[i]); 3167 if (err) 3168 goto err_umrc; 3169 } 3170 3171 err = mlx5_ib_init_congestion(dev); 3172 if (err) 3173 goto err_umrc; 3174 3175 dev->ib_active = true; 3176 3177 return dev; 3178 3179 err_umrc: 3180 destroy_umrc_res(dev); 3181 3182 err_dev: 3183 ib_unregister_device(&dev->ib_dev); 3184 3185 err_q_cnt: 3186 mlx5_ib_dealloc_q_counters(dev); 3187 3188 err_odp: 3189 mlx5_ib_odp_remove_one(dev); 3190 3191 err_rsrc: 3192 destroy_dev_resources(&dev->devr); 3193 3194 err_disable_roce: 3195 if (ll == IB_LINK_LAYER_ETHERNET) { 3196 mlx5_disable_roce(dev); 3197 mlx5_remove_roce_notifier(dev); 3198 } 3199 3200 err_free_port: 3201 kfree(dev->port); 3202 3203 err_dealloc: 3204 ib_dealloc_device((struct ib_device *)dev); 3205 3206 return NULL; 3207 } 3208 3209 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3210 { 3211 struct mlx5_ib_dev *dev = context; 3212 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3213 3214 mlx5_ib_cleanup_congestion(dev); 3215 mlx5_remove_roce_notifier(dev); 3216 ib_unregister_device(&dev->ib_dev); 3217 mlx5_ib_dealloc_q_counters(dev); 3218 destroy_umrc_res(dev); 3219 mlx5_ib_odp_remove_one(dev); 3220 destroy_dev_resources(&dev->devr); 3221 if (ll == IB_LINK_LAYER_ETHERNET) 3222 mlx5_disable_roce(dev); 3223 kfree(dev->port); 3224 ib_dealloc_device(&dev->ib_dev); 3225 } 3226 3227 static struct mlx5_interface mlx5_ib_interface = { 3228 .add = mlx5_ib_add, 3229 .remove = mlx5_ib_remove, 3230 .event = mlx5_ib_event, 3231 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3232 }; 3233 3234 static int __init mlx5_ib_init(void) 3235 { 3236 int err; 3237 3238 if (deprecated_prof_sel != 2) 3239 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n"); 3240 3241 err = mlx5_ib_odp_init(); 3242 if (err) 3243 return err; 3244 3245 err = mlx5_register_interface(&mlx5_ib_interface); 3246 if (err) 3247 goto clean_odp; 3248 3249 return err; 3250 3251 clean_odp: 3252 mlx5_ib_odp_cleanup(); 3253 return err; 3254 } 3255 3256 static void __exit mlx5_ib_cleanup(void) 3257 { 3258 mlx5_unregister_interface(&mlx5_ib_interface); 3259 mlx5_ib_odp_cleanup(); 3260 } 3261 3262 static void 3263 mlx5_ib_show_version(void __unused *arg) 3264 { 3265 3266 printf("%s", mlx5_version); 3267 } 3268 SYSINIT(mlx5_ib_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5_ib_show_version, NULL); 3269 3270 module_init_order(mlx5_ib_init, SI_ORDER_THIRD); 3271 module_exit_order(mlx5_ib_cleanup, SI_ORDER_THIRD); 3272