1 /*- 2 * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/module.h> 29 #include <linux/errno.h> 30 #include <linux/pci.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/slab.h> 33 #if defined(CONFIG_X86) 34 #include <asm/pat.h> 35 #endif 36 #include <linux/sched.h> 37 #include <linux/delay.h> 38 #include <linux/fs.h> 39 #undef inode 40 #include <rdma/ib_user_verbs.h> 41 #include <rdma/ib_addr.h> 42 #include <rdma/ib_cache.h> 43 #include <dev/mlx5/port.h> 44 #include <dev/mlx5/vport.h> 45 #include <linux/list.h> 46 #include <rdma/ib_smi.h> 47 #include <rdma/ib_umem.h> 48 #include <rdma/uverbs_ioctl.h> 49 #include <linux/in.h> 50 #include <linux/etherdevice.h> 51 #include <dev/mlx5/fs.h> 52 #include "mlx5_ib.h" 53 54 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 55 MODULE_LICENSE("Dual BSD/GPL"); 56 MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1); 57 MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1); 58 MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1); 59 MODULE_VERSION(mlx5ib, 1); 60 61 enum { 62 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 63 }; 64 65 static enum rdma_link_layer 66 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 67 { 68 switch (port_type_cap) { 69 case MLX5_CAP_PORT_TYPE_IB: 70 return IB_LINK_LAYER_INFINIBAND; 71 case MLX5_CAP_PORT_TYPE_ETH: 72 return IB_LINK_LAYER_ETHERNET; 73 default: 74 return IB_LINK_LAYER_UNSPECIFIED; 75 } 76 } 77 78 static enum rdma_link_layer 79 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 80 { 81 struct mlx5_ib_dev *dev = to_mdev(device); 82 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 83 84 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 85 } 86 87 static bool mlx5_netdev_match(struct ifnet *ndev, 88 struct mlx5_core_dev *mdev, 89 const char *dname) 90 { 91 return ndev->if_type == IFT_ETHER && 92 ndev->if_dname != NULL && 93 strcmp(ndev->if_dname, dname) == 0 && 94 ndev->if_softc != NULL && 95 *(struct mlx5_core_dev **)ndev->if_softc == mdev; 96 } 97 98 static int mlx5_netdev_event(struct notifier_block *this, 99 unsigned long event, void *ptr) 100 { 101 struct ifnet *ndev = netdev_notifier_info_to_ifp(ptr); 102 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 103 roce.nb); 104 105 switch (event) { 106 case NETDEV_REGISTER: 107 case NETDEV_UNREGISTER: 108 write_lock(&ibdev->roce.netdev_lock); 109 /* check if network interface belongs to mlx5en */ 110 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce")) 111 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 112 NULL : ndev; 113 write_unlock(&ibdev->roce.netdev_lock); 114 break; 115 116 case NETDEV_UP: 117 case NETDEV_DOWN: { 118 struct ifnet *upper = NULL; 119 120 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 121 && ibdev->ib_active) { 122 struct ib_event ibev = {0}; 123 124 ibev.device = &ibdev->ib_dev; 125 ibev.event = (event == NETDEV_UP) ? 126 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 127 ibev.element.port_num = 1; 128 ib_dispatch_event(&ibev); 129 } 130 break; 131 } 132 133 default: 134 break; 135 } 136 137 return NOTIFY_DONE; 138 } 139 140 static struct ifnet *mlx5_ib_get_netdev(struct ib_device *device, 141 u8 port_num) 142 { 143 struct mlx5_ib_dev *ibdev = to_mdev(device); 144 struct ifnet *ndev; 145 146 /* Ensure ndev does not disappear before we invoke if_ref() 147 */ 148 read_lock(&ibdev->roce.netdev_lock); 149 ndev = ibdev->roce.netdev; 150 if (ndev) 151 if_ref(ndev); 152 read_unlock(&ibdev->roce.netdev_lock); 153 154 return ndev; 155 } 156 157 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 158 u8 *active_width) 159 { 160 switch (eth_proto_oper) { 161 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 162 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 163 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 164 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 165 *active_width = IB_WIDTH_1X; 166 *active_speed = IB_SPEED_SDR; 167 break; 168 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 169 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 170 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 171 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 172 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 173 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 174 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER_LR): 175 *active_width = IB_WIDTH_1X; 176 *active_speed = IB_SPEED_QDR; 177 break; 178 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 179 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 180 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 181 *active_width = IB_WIDTH_1X; 182 *active_speed = IB_SPEED_EDR; 183 break; 184 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 185 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 186 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 187 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4_ER4): 188 *active_width = IB_WIDTH_4X; 189 *active_speed = IB_SPEED_QDR; 190 break; 191 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 192 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 193 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR4): 194 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 195 *active_width = IB_WIDTH_1X; 196 *active_speed = IB_SPEED_HDR; 197 break; 198 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 199 *active_width = IB_WIDTH_4X; 200 *active_speed = IB_SPEED_FDR; 201 break; 202 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 203 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 204 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 205 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 206 *active_width = IB_WIDTH_4X; 207 *active_speed = IB_SPEED_EDR; 208 break; 209 default: 210 *active_width = IB_WIDTH_4X; 211 *active_speed = IB_SPEED_QDR; 212 return -EINVAL; 213 } 214 215 return 0; 216 } 217 218 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed, 219 u8 *active_width) 220 { 221 switch (eth_proto_oper) { 222 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 223 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 224 *active_width = IB_WIDTH_1X; 225 *active_speed = IB_SPEED_SDR; 226 break; 227 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 228 *active_width = IB_WIDTH_1X; 229 *active_speed = IB_SPEED_DDR; 230 break; 231 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 232 *active_width = IB_WIDTH_1X; 233 *active_speed = IB_SPEED_QDR; 234 break; 235 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 236 *active_width = IB_WIDTH_4X; 237 *active_speed = IB_SPEED_QDR; 238 break; 239 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 240 *active_width = IB_WIDTH_1X; 241 *active_speed = IB_SPEED_EDR; 242 break; 243 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 244 *active_width = IB_WIDTH_2X; 245 *active_speed = IB_SPEED_EDR; 246 break; 247 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 248 *active_width = IB_WIDTH_1X; 249 *active_speed = IB_SPEED_HDR; 250 break; 251 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 252 *active_width = IB_WIDTH_4X; 253 *active_speed = IB_SPEED_EDR; 254 break; 255 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 256 *active_width = IB_WIDTH_2X; 257 *active_speed = IB_SPEED_HDR; 258 break; 259 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 260 *active_width = IB_WIDTH_4X; 261 *active_speed = IB_SPEED_HDR; 262 break; 263 default: 264 *active_width = IB_WIDTH_4X; 265 *active_speed = IB_SPEED_QDR; 266 return -EINVAL; 267 } 268 269 return 0; 270 } 271 272 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 273 struct ib_port_attr *props) 274 { 275 struct mlx5_ib_dev *dev = to_mdev(device); 276 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {}; 277 struct ifnet *ndev; 278 enum ib_mtu ndev_ib_mtu; 279 u16 qkey_viol_cntr; 280 u32 eth_prot_oper; 281 bool ext; 282 int err; 283 284 memset(props, 0, sizeof(*props)); 285 286 /* Possible bad flows are checked before filling out props so in case 287 * of an error it will still be zeroed out. 288 */ 289 err = mlx5_query_port_ptys(dev->mdev, out, sizeof(out), MLX5_PTYS_EN, 290 port_num); 291 if (err) 292 return err; 293 294 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet); 295 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 296 297 if (ext) 298 translate_eth_ext_proto_oper(eth_prot_oper, &props->active_speed, 299 &props->active_width); 300 else 301 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 302 &props->active_width); 303 304 props->port_cap_flags |= IB_PORT_CM_SUP; 305 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 306 307 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 308 roce_address_table_size); 309 props->max_mtu = IB_MTU_4096; 310 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 311 props->pkey_tbl_len = 1; 312 props->state = IB_PORT_DOWN; 313 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 314 315 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 316 props->qkey_viol_cntr = qkey_viol_cntr; 317 318 ndev = mlx5_ib_get_netdev(device, port_num); 319 if (!ndev) 320 return 0; 321 322 if (ndev->if_drv_flags & IFF_DRV_RUNNING && 323 ndev->if_link_state == LINK_STATE_UP) { 324 props->state = IB_PORT_ACTIVE; 325 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 326 } 327 328 ndev_ib_mtu = iboe_get_mtu(ndev->if_mtu); 329 330 if_rele(ndev); 331 332 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 333 return 0; 334 } 335 336 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 337 const struct ib_gid_attr *attr, 338 void *mlx5_addr) 339 { 340 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 341 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 342 source_l3_address); 343 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 344 source_mac_47_32); 345 u16 vlan_id; 346 347 if (!gid) 348 return; 349 ether_addr_copy(mlx5_addr_mac, IF_LLADDR(attr->ndev)); 350 351 vlan_id = rdma_vlan_dev_vlan_id(attr->ndev); 352 if (vlan_id != 0xffff) { 353 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 354 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_id); 355 } 356 357 switch (attr->gid_type) { 358 case IB_GID_TYPE_IB: 359 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 360 break; 361 case IB_GID_TYPE_ROCE_UDP_ENCAP: 362 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 363 break; 364 365 default: 366 WARN_ON(true); 367 } 368 369 if (attr->gid_type != IB_GID_TYPE_IB) { 370 if (ipv6_addr_v4mapped((void *)gid)) 371 MLX5_SET_RA(mlx5_addr, roce_l3_type, 372 MLX5_ROCE_L3_TYPE_IPV4); 373 else 374 MLX5_SET_RA(mlx5_addr, roce_l3_type, 375 MLX5_ROCE_L3_TYPE_IPV6); 376 } 377 378 if ((attr->gid_type == IB_GID_TYPE_IB) || 379 !ipv6_addr_v4mapped((void *)gid)) 380 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 381 else 382 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 383 } 384 385 static int set_roce_addr(struct ib_device *device, u8 port_num, 386 unsigned int index, 387 const union ib_gid *gid, 388 const struct ib_gid_attr *attr) 389 { 390 struct mlx5_ib_dev *dev = to_mdev(device); 391 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 392 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 393 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 394 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 395 396 if (ll != IB_LINK_LAYER_ETHERNET) 397 return -EINVAL; 398 399 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 400 401 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 402 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 403 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 404 } 405 406 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 407 unsigned int index, const union ib_gid *gid, 408 const struct ib_gid_attr *attr, 409 __always_unused void **context) 410 { 411 return set_roce_addr(device, port_num, index, gid, attr); 412 } 413 414 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 415 unsigned int index, __always_unused void **context) 416 { 417 return set_roce_addr(device, port_num, index, NULL, NULL); 418 } 419 420 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 421 int index) 422 { 423 struct ib_gid_attr attr; 424 union ib_gid gid; 425 426 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 427 return 0; 428 429 if (!attr.ndev) 430 return 0; 431 432 if_rele(attr.ndev); 433 434 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 435 return 0; 436 437 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 438 } 439 440 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 441 int index, enum ib_gid_type *gid_type) 442 { 443 struct ib_gid_attr attr; 444 union ib_gid gid; 445 int ret; 446 447 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 448 if (ret) 449 return ret; 450 451 if (!attr.ndev) 452 return -ENODEV; 453 454 if_rele(attr.ndev); 455 456 *gid_type = attr.gid_type; 457 458 return 0; 459 } 460 461 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 462 { 463 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 464 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 465 return 0; 466 } 467 468 enum { 469 MLX5_VPORT_ACCESS_METHOD_MAD, 470 MLX5_VPORT_ACCESS_METHOD_HCA, 471 MLX5_VPORT_ACCESS_METHOD_NIC, 472 }; 473 474 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 475 { 476 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 477 return MLX5_VPORT_ACCESS_METHOD_MAD; 478 479 if (mlx5_ib_port_link_layer(ibdev, 1) == 480 IB_LINK_LAYER_ETHERNET) 481 return MLX5_VPORT_ACCESS_METHOD_NIC; 482 483 return MLX5_VPORT_ACCESS_METHOD_HCA; 484 } 485 486 static void get_atomic_caps(struct mlx5_ib_dev *dev, 487 struct ib_device_attr *props) 488 { 489 u8 tmp; 490 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 491 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 492 u8 atomic_req_8B_endianness_mode = 493 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 494 495 /* Check if HW supports 8 bytes standard atomic operations and capable 496 * of host endianness respond 497 */ 498 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 499 if (((atomic_operations & tmp) == tmp) && 500 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 501 (atomic_req_8B_endianness_mode)) { 502 props->atomic_cap = IB_ATOMIC_HCA; 503 } else { 504 props->atomic_cap = IB_ATOMIC_NONE; 505 } 506 } 507 508 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 509 __be64 *sys_image_guid) 510 { 511 struct mlx5_ib_dev *dev = to_mdev(ibdev); 512 struct mlx5_core_dev *mdev = dev->mdev; 513 u64 tmp; 514 int err; 515 516 switch (mlx5_get_vport_access_method(ibdev)) { 517 case MLX5_VPORT_ACCESS_METHOD_MAD: 518 return mlx5_query_mad_ifc_system_image_guid(ibdev, 519 sys_image_guid); 520 521 case MLX5_VPORT_ACCESS_METHOD_HCA: 522 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 523 break; 524 525 case MLX5_VPORT_ACCESS_METHOD_NIC: 526 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 527 break; 528 529 default: 530 return -EINVAL; 531 } 532 533 if (!err) 534 *sys_image_guid = cpu_to_be64(tmp); 535 536 return err; 537 538 } 539 540 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 541 u16 *max_pkeys) 542 { 543 struct mlx5_ib_dev *dev = to_mdev(ibdev); 544 struct mlx5_core_dev *mdev = dev->mdev; 545 546 switch (mlx5_get_vport_access_method(ibdev)) { 547 case MLX5_VPORT_ACCESS_METHOD_MAD: 548 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 549 550 case MLX5_VPORT_ACCESS_METHOD_HCA: 551 case MLX5_VPORT_ACCESS_METHOD_NIC: 552 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 553 pkey_table_size)); 554 return 0; 555 556 default: 557 return -EINVAL; 558 } 559 } 560 561 static int mlx5_query_vendor_id(struct ib_device *ibdev, 562 u32 *vendor_id) 563 { 564 struct mlx5_ib_dev *dev = to_mdev(ibdev); 565 566 switch (mlx5_get_vport_access_method(ibdev)) { 567 case MLX5_VPORT_ACCESS_METHOD_MAD: 568 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 569 570 case MLX5_VPORT_ACCESS_METHOD_HCA: 571 case MLX5_VPORT_ACCESS_METHOD_NIC: 572 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 573 574 default: 575 return -EINVAL; 576 } 577 } 578 579 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 580 __be64 *node_guid) 581 { 582 u64 tmp; 583 int err; 584 585 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 586 case MLX5_VPORT_ACCESS_METHOD_MAD: 587 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 588 589 case MLX5_VPORT_ACCESS_METHOD_HCA: 590 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 591 break; 592 593 case MLX5_VPORT_ACCESS_METHOD_NIC: 594 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 595 break; 596 597 default: 598 return -EINVAL; 599 } 600 601 if (!err) 602 *node_guid = cpu_to_be64(tmp); 603 604 return err; 605 } 606 607 struct mlx5_reg_node_desc { 608 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 609 }; 610 611 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 612 { 613 struct mlx5_reg_node_desc in; 614 615 if (mlx5_use_mad_ifc(dev)) 616 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 617 618 memset(&in, 0, sizeof(in)); 619 620 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 621 sizeof(struct mlx5_reg_node_desc), 622 MLX5_REG_NODE_DESC, 0, 0); 623 } 624 625 static int mlx5_ib_query_device(struct ib_device *ibdev, 626 struct ib_device_attr *props, 627 struct ib_udata *uhw) 628 { 629 struct mlx5_ib_dev *dev = to_mdev(ibdev); 630 struct mlx5_core_dev *mdev = dev->mdev; 631 int err = -ENOMEM; 632 int max_sq_desc; 633 int max_rq_sg; 634 int max_sq_sg; 635 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 636 struct mlx5_ib_query_device_resp resp = {}; 637 size_t resp_len; 638 u64 max_tso; 639 640 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 641 if (uhw->outlen && uhw->outlen < resp_len) 642 return -EINVAL; 643 else 644 resp.response_length = resp_len; 645 646 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 647 return -EINVAL; 648 649 memset(props, 0, sizeof(*props)); 650 err = mlx5_query_system_image_guid(ibdev, 651 &props->sys_image_guid); 652 if (err) 653 return err; 654 655 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 656 if (err) 657 return err; 658 659 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 660 if (err) 661 return err; 662 663 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 664 ((u32)fw_rev_min(dev->mdev) << 16) | 665 fw_rev_sub(dev->mdev); 666 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 667 IB_DEVICE_PORT_ACTIVE_EVENT | 668 IB_DEVICE_SYS_IMAGE_GUID | 669 IB_DEVICE_RC_RNR_NAK_GEN; 670 671 if (MLX5_CAP_GEN(mdev, pkv)) 672 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 673 if (MLX5_CAP_GEN(mdev, qkv)) 674 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 675 if (MLX5_CAP_GEN(mdev, apm)) 676 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 677 if (MLX5_CAP_GEN(mdev, xrc)) 678 props->device_cap_flags |= IB_DEVICE_XRC; 679 if (MLX5_CAP_GEN(mdev, imaicl)) { 680 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 681 IB_DEVICE_MEM_WINDOW_TYPE_2B; 682 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 683 /* We support 'Gappy' memory registration too */ 684 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 685 } 686 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 687 if (MLX5_CAP_GEN(mdev, sho)) { 688 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 689 /* At this stage no support for signature handover */ 690 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 691 IB_PROT_T10DIF_TYPE_2 | 692 IB_PROT_T10DIF_TYPE_3; 693 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 694 IB_GUARD_T10DIF_CSUM; 695 } 696 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 697 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 698 699 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 700 if (MLX5_CAP_ETH(mdev, csum_cap)) 701 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 702 703 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 704 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 705 if (max_tso) { 706 resp.tso_caps.max_tso = 1 << max_tso; 707 resp.tso_caps.supported_qpts |= 708 1 << IB_QPT_RAW_PACKET; 709 resp.response_length += sizeof(resp.tso_caps); 710 } 711 } 712 713 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 714 resp.rss_caps.rx_hash_function = 715 MLX5_RX_HASH_FUNC_TOEPLITZ; 716 resp.rss_caps.rx_hash_fields_mask = 717 MLX5_RX_HASH_SRC_IPV4 | 718 MLX5_RX_HASH_DST_IPV4 | 719 MLX5_RX_HASH_SRC_IPV6 | 720 MLX5_RX_HASH_DST_IPV6 | 721 MLX5_RX_HASH_SRC_PORT_TCP | 722 MLX5_RX_HASH_DST_PORT_TCP | 723 MLX5_RX_HASH_SRC_PORT_UDP | 724 MLX5_RX_HASH_DST_PORT_UDP; 725 resp.response_length += sizeof(resp.rss_caps); 726 } 727 } else { 728 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 729 resp.response_length += sizeof(resp.tso_caps); 730 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 731 resp.response_length += sizeof(resp.rss_caps); 732 } 733 734 if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 735 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 736 props->device_cap_flags |= IB_DEVICE_UD_TSO; 737 } 738 739 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 740 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) 741 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 742 743 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 744 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 745 746 props->vendor_part_id = mdev->pdev->device; 747 props->hw_ver = mdev->pdev->revision; 748 749 props->max_mr_size = ~0ull; 750 props->page_size_cap = ~(min_page_size - 1); 751 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 752 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 753 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 754 sizeof(struct mlx5_wqe_data_seg); 755 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 756 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 757 sizeof(struct mlx5_wqe_raddr_seg)) / 758 sizeof(struct mlx5_wqe_data_seg); 759 props->max_sge = min(max_rq_sg, max_sq_sg); 760 props->max_sge_rd = MLX5_MAX_SGE_RD; 761 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 762 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 763 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 764 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 765 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 766 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 767 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 768 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 769 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 770 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 771 props->max_srq_sge = max_rq_sg - 1; 772 props->max_fast_reg_page_list_len = 773 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 774 get_atomic_caps(dev, props); 775 props->masked_atomic_cap = IB_ATOMIC_NONE; 776 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 777 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 778 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 779 props->max_mcast_grp; 780 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 781 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 782 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 783 784 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 785 if (MLX5_CAP_GEN(mdev, pg)) 786 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 787 props->odp_caps = dev->odp_caps; 788 #endif 789 790 if (MLX5_CAP_GEN(mdev, cd)) 791 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 792 793 if (!mlx5_core_is_pf(mdev)) 794 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 795 796 if (mlx5_ib_port_link_layer(ibdev, 1) == 797 IB_LINK_LAYER_ETHERNET) { 798 props->rss_caps.max_rwq_indirection_tables = 799 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 800 props->rss_caps.max_rwq_indirection_table_size = 801 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 802 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 803 props->max_wq_type_rq = 804 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 805 } 806 807 if (uhw->outlen) { 808 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 809 810 if (err) 811 return err; 812 } 813 814 return 0; 815 } 816 817 enum mlx5_ib_width { 818 MLX5_IB_WIDTH_1X = 1 << 0, 819 MLX5_IB_WIDTH_2X = 1 << 1, 820 MLX5_IB_WIDTH_4X = 1 << 2, 821 MLX5_IB_WIDTH_8X = 1 << 3, 822 MLX5_IB_WIDTH_12X = 1 << 4 823 }; 824 825 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 826 u8 *ib_width) 827 { 828 struct mlx5_ib_dev *dev = to_mdev(ibdev); 829 int err = 0; 830 831 if (active_width & MLX5_IB_WIDTH_1X) { 832 *ib_width = IB_WIDTH_1X; 833 } else if (active_width & MLX5_IB_WIDTH_2X) { 834 *ib_width = IB_WIDTH_2X; 835 } else if (active_width & MLX5_IB_WIDTH_4X) { 836 *ib_width = IB_WIDTH_4X; 837 } else if (active_width & MLX5_IB_WIDTH_8X) { 838 *ib_width = IB_WIDTH_8X; 839 } else if (active_width & MLX5_IB_WIDTH_12X) { 840 *ib_width = IB_WIDTH_12X; 841 } else { 842 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 843 (int)active_width); 844 err = -EINVAL; 845 } 846 847 return err; 848 } 849 850 enum ib_max_vl_num { 851 __IB_MAX_VL_0 = 1, 852 __IB_MAX_VL_0_1 = 2, 853 __IB_MAX_VL_0_3 = 3, 854 __IB_MAX_VL_0_7 = 4, 855 __IB_MAX_VL_0_14 = 5, 856 }; 857 858 enum mlx5_vl_hw_cap { 859 MLX5_VL_HW_0 = 1, 860 MLX5_VL_HW_0_1 = 2, 861 MLX5_VL_HW_0_2 = 3, 862 MLX5_VL_HW_0_3 = 4, 863 MLX5_VL_HW_0_4 = 5, 864 MLX5_VL_HW_0_5 = 6, 865 MLX5_VL_HW_0_6 = 7, 866 MLX5_VL_HW_0_7 = 8, 867 MLX5_VL_HW_0_14 = 15 868 }; 869 870 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 871 u8 *max_vl_num) 872 { 873 switch (vl_hw_cap) { 874 case MLX5_VL_HW_0: 875 *max_vl_num = __IB_MAX_VL_0; 876 break; 877 case MLX5_VL_HW_0_1: 878 *max_vl_num = __IB_MAX_VL_0_1; 879 break; 880 case MLX5_VL_HW_0_3: 881 *max_vl_num = __IB_MAX_VL_0_3; 882 break; 883 case MLX5_VL_HW_0_7: 884 *max_vl_num = __IB_MAX_VL_0_7; 885 break; 886 case MLX5_VL_HW_0_14: 887 *max_vl_num = __IB_MAX_VL_0_14; 888 break; 889 890 default: 891 return -EINVAL; 892 } 893 894 return 0; 895 } 896 897 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 898 struct ib_port_attr *props) 899 { 900 struct mlx5_ib_dev *dev = to_mdev(ibdev); 901 struct mlx5_core_dev *mdev = dev->mdev; 902 u32 *rep; 903 int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out); 904 struct mlx5_ptys_reg *ptys; 905 struct mlx5_pmtu_reg *pmtu; 906 struct mlx5_pvlc_reg pvlc; 907 void *ctx; 908 int err; 909 910 rep = mlx5_vzalloc(replen); 911 ptys = kzalloc(sizeof(*ptys), GFP_KERNEL); 912 pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL); 913 if (!rep || !ptys || !pmtu) { 914 err = -ENOMEM; 915 goto out; 916 } 917 918 memset(props, 0, sizeof(*props)); 919 920 err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen); 921 if (err) 922 goto out; 923 924 ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context); 925 926 props->lid = MLX5_GET(hca_vport_context, ctx, lid); 927 props->lmc = MLX5_GET(hca_vport_context, ctx, lmc); 928 props->sm_lid = MLX5_GET(hca_vport_context, ctx, sm_lid); 929 props->sm_sl = MLX5_GET(hca_vport_context, ctx, sm_sl); 930 props->state = MLX5_GET(hca_vport_context, ctx, vport_state); 931 props->phys_state = MLX5_GET(hca_vport_context, ctx, 932 port_physical_state); 933 props->port_cap_flags = MLX5_GET(hca_vport_context, ctx, cap_mask1); 934 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 935 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 936 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 937 props->bad_pkey_cntr = MLX5_GET(hca_vport_context, ctx, 938 pkey_violation_counter); 939 props->qkey_viol_cntr = MLX5_GET(hca_vport_context, ctx, 940 qkey_violation_counter); 941 props->subnet_timeout = MLX5_GET(hca_vport_context, ctx, 942 subnet_timeout); 943 props->init_type_reply = MLX5_GET(hca_vport_context, ctx, 944 init_type_reply); 945 props->grh_required = MLX5_GET(hca_vport_context, ctx, grh_required); 946 947 ptys->proto_mask |= MLX5_PTYS_IB; 948 ptys->local_port = port; 949 err = mlx5_core_access_ptys(mdev, ptys, 0); 950 if (err) 951 goto out; 952 953 err = translate_active_width(ibdev, ptys->ib_link_width_oper, 954 &props->active_width); 955 if (err) 956 goto out; 957 958 props->active_speed = (u8)ptys->ib_proto_oper; 959 960 pmtu->local_port = port; 961 err = mlx5_core_access_pmtu(mdev, pmtu, 0); 962 if (err) 963 goto out; 964 965 props->max_mtu = pmtu->max_mtu; 966 props->active_mtu = pmtu->oper_mtu; 967 968 memset(&pvlc, 0, sizeof(pvlc)); 969 pvlc.local_port = port; 970 err = mlx5_core_access_pvlc(mdev, &pvlc, 0); 971 if (err) 972 goto out; 973 974 err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap, 975 &props->max_vl_num); 976 out: 977 kvfree(rep); 978 kfree(ptys); 979 kfree(pmtu); 980 return err; 981 } 982 983 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 984 struct ib_port_attr *props) 985 { 986 switch (mlx5_get_vport_access_method(ibdev)) { 987 case MLX5_VPORT_ACCESS_METHOD_MAD: 988 return mlx5_query_mad_ifc_port(ibdev, port, props); 989 990 case MLX5_VPORT_ACCESS_METHOD_HCA: 991 return mlx5_query_hca_port(ibdev, port, props); 992 993 case MLX5_VPORT_ACCESS_METHOD_NIC: 994 return mlx5_query_port_roce(ibdev, port, props); 995 996 default: 997 return -EINVAL; 998 } 999 } 1000 1001 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1002 union ib_gid *gid) 1003 { 1004 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1005 struct mlx5_core_dev *mdev = dev->mdev; 1006 1007 switch (mlx5_get_vport_access_method(ibdev)) { 1008 case MLX5_VPORT_ACCESS_METHOD_MAD: 1009 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1010 1011 case MLX5_VPORT_ACCESS_METHOD_HCA: 1012 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid); 1013 1014 default: 1015 return -EINVAL; 1016 } 1017 1018 } 1019 1020 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1021 u16 *pkey) 1022 { 1023 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1024 struct mlx5_core_dev *mdev = dev->mdev; 1025 1026 switch (mlx5_get_vport_access_method(ibdev)) { 1027 case MLX5_VPORT_ACCESS_METHOD_MAD: 1028 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1029 1030 case MLX5_VPORT_ACCESS_METHOD_HCA: 1031 case MLX5_VPORT_ACCESS_METHOD_NIC: 1032 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1033 pkey); 1034 default: 1035 return -EINVAL; 1036 } 1037 } 1038 1039 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1040 struct ib_device_modify *props) 1041 { 1042 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1043 struct mlx5_reg_node_desc in; 1044 struct mlx5_reg_node_desc out; 1045 int err; 1046 1047 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1048 return -EOPNOTSUPP; 1049 1050 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1051 return 0; 1052 1053 /* 1054 * If possible, pass node desc to FW, so it can generate 1055 * a 144 trap. If cmd fails, just ignore. 1056 */ 1057 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1058 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1059 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1060 if (err) 1061 return err; 1062 1063 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1064 1065 return err; 1066 } 1067 1068 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1069 struct ib_port_modify *props) 1070 { 1071 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1072 struct ib_port_attr attr; 1073 u32 tmp; 1074 int err; 1075 1076 /* 1077 * CM layer calls ib_modify_port() regardless of the link 1078 * layer. For Ethernet ports, qkey violation and Port 1079 * capabilities are meaningless. 1080 */ 1081 if (mlx5_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_ETHERNET) 1082 return 0; 1083 1084 mutex_lock(&dev->cap_mask_mutex); 1085 1086 err = mlx5_ib_query_port(ibdev, port, &attr); 1087 if (err) 1088 goto out; 1089 1090 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1091 ~props->clr_port_cap_mask; 1092 1093 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1094 1095 out: 1096 mutex_unlock(&dev->cap_mask_mutex); 1097 return err; 1098 } 1099 1100 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1101 { 1102 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1103 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1104 } 1105 1106 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1107 { 1108 /* Large page with non 4k uar support might limit the dynamic size */ 1109 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1110 return MLX5_MIN_DYN_BFREGS; 1111 1112 return MLX5_MAX_DYN_BFREGS; 1113 } 1114 1115 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1116 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1117 struct mlx5_bfreg_info *bfregi) 1118 { 1119 int uars_per_sys_page; 1120 int bfregs_per_sys_page; 1121 int ref_bfregs = req->total_num_bfregs; 1122 1123 if (req->total_num_bfregs == 0) 1124 return -EINVAL; 1125 1126 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1127 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1128 1129 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1130 return -ENOMEM; 1131 1132 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1133 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1134 /* This holds the required static allocation asked by the user */ 1135 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1136 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1137 return -EINVAL; 1138 1139 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1140 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1141 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1142 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1143 1144 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1145 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1146 lib_uar_4k ? "yes" : "no", ref_bfregs, 1147 req->total_num_bfregs, bfregi->total_num_bfregs, 1148 bfregi->num_sys_pages); 1149 1150 return 0; 1151 } 1152 1153 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1154 { 1155 struct mlx5_bfreg_info *bfregi; 1156 int err; 1157 int i; 1158 1159 bfregi = &context->bfregi; 1160 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1161 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1162 if (err) 1163 goto error; 1164 1165 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1166 } 1167 1168 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1169 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1170 1171 return 0; 1172 1173 error: 1174 for (--i; i >= 0; i--) 1175 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1176 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1177 1178 return err; 1179 } 1180 1181 static void deallocate_uars(struct mlx5_ib_dev *dev, 1182 struct mlx5_ib_ucontext *context) 1183 { 1184 struct mlx5_bfreg_info *bfregi; 1185 int i; 1186 1187 bfregi = &context->bfregi; 1188 for (i = 0; i < bfregi->num_sys_pages; i++) 1189 if (i < bfregi->num_static_sys_pages || 1190 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1191 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1192 } 1193 1194 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1195 u16 uid) 1196 { 1197 int err; 1198 1199 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1200 return 0; 1201 1202 err = mlx5_alloc_transport_domain(dev->mdev, tdn, uid); 1203 if (err) 1204 return err; 1205 1206 return 0; 1207 } 1208 1209 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1210 u16 uid) 1211 { 1212 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1213 return; 1214 1215 mlx5_dealloc_transport_domain(dev->mdev, tdn, uid); 1216 } 1217 1218 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1219 struct ib_udata *udata) 1220 { 1221 struct ib_device *ibdev = uctx->device; 1222 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1223 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1224 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1225 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1226 struct mlx5_bfreg_info *bfregi; 1227 int ver; 1228 int err; 1229 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1230 max_cqe_version); 1231 bool lib_uar_4k; 1232 bool lib_uar_dyn; 1233 1234 if (!dev->ib_active) 1235 return -EAGAIN; 1236 1237 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1238 ver = 0; 1239 else if (udata->inlen >= min_req_v2) 1240 ver = 2; 1241 else 1242 return -EINVAL; 1243 1244 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1245 if (err) 1246 return err; 1247 1248 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1249 return -EOPNOTSUPP; 1250 1251 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1252 return -EOPNOTSUPP; 1253 1254 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1255 MLX5_NON_FP_BFREGS_PER_UAR); 1256 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1257 return -EINVAL; 1258 1259 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1260 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1261 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1262 resp.cache_line_size = cache_line_size(); 1263 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1264 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1265 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1266 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1267 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1268 resp.cqe_version = min_t(__u8, 1269 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1270 req.max_cqe_version); 1271 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1272 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1273 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1274 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1275 resp.response_length = min(offsetof(typeof(resp), response_length) + 1276 sizeof(resp.response_length), udata->outlen); 1277 1278 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1279 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1280 bfregi = &context->bfregi; 1281 1282 if (lib_uar_dyn) { 1283 bfregi->lib_uar_dyn = lib_uar_dyn; 1284 goto uar_done; 1285 } 1286 1287 /* updates req->total_num_bfregs */ 1288 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1289 if (err) 1290 goto out_ctx; 1291 1292 mutex_init(&bfregi->lock); 1293 bfregi->lib_uar_4k = lib_uar_4k; 1294 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1295 GFP_KERNEL); 1296 if (!bfregi->count) { 1297 err = -ENOMEM; 1298 goto out_ctx; 1299 } 1300 1301 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1302 sizeof(*bfregi->sys_pages), 1303 GFP_KERNEL); 1304 if (!bfregi->sys_pages) { 1305 err = -ENOMEM; 1306 goto out_count; 1307 } 1308 1309 err = allocate_uars(dev, context); 1310 if (err) 1311 goto out_sys_pages; 1312 1313 uar_done: 1314 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1315 err = mlx5_ib_devx_create(dev, true); 1316 if (err < 0) 1317 goto out_uars; 1318 context->devx_uid = err; 1319 } 1320 1321 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1322 context->devx_uid); 1323 if (err) 1324 goto out_devx; 1325 1326 INIT_LIST_HEAD(&context->db_page_list); 1327 mutex_init(&context->db_page_mutex); 1328 1329 resp.tot_bfregs = lib_uar_dyn ? 0 : req.total_num_bfregs; 1330 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1331 1332 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1333 resp.response_length += sizeof(resp.cqe_version); 1334 1335 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1336 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1337 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1338 resp.response_length += sizeof(resp.cmds_supp_uhw); 1339 } 1340 1341 /* 1342 * We don't want to expose information from the PCI bar that is located 1343 * after 4096 bytes, so if the arch only supports larger pages, let's 1344 * pretend we don't support reading the HCA's core clock. This is also 1345 * forced by mmap function. 1346 */ 1347 if (offsetofend(typeof(resp), hca_core_clock_offset) <= udata->outlen) { 1348 if (PAGE_SIZE <= 4096) { 1349 resp.comp_mask |= 1350 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1351 resp.hca_core_clock_offset = 1352 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1353 } 1354 resp.response_length += sizeof(resp.hca_core_clock_offset); 1355 } 1356 1357 if (offsetofend(typeof(resp), log_uar_size) <= udata->outlen) 1358 resp.response_length += sizeof(resp.log_uar_size); 1359 1360 if (offsetofend(typeof(resp), num_uars_per_page) <= udata->outlen) 1361 resp.response_length += sizeof(resp.num_uars_per_page); 1362 1363 if (offsetofend(typeof(resp), num_dyn_bfregs) <= udata->outlen) { 1364 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1365 resp.response_length += sizeof(resp.num_dyn_bfregs); 1366 } 1367 1368 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1369 if (err) 1370 goto out_mdev; 1371 1372 bfregi->ver = ver; 1373 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1374 context->cqe_version = resp.cqe_version; 1375 context->lib_caps = req.lib_caps; 1376 print_lib_caps(dev, context->lib_caps); 1377 1378 return 0; 1379 1380 out_mdev: 1381 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1382 out_devx: 1383 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1384 mlx5_ib_devx_destroy(dev, context->devx_uid); 1385 1386 out_uars: 1387 deallocate_uars(dev, context); 1388 1389 out_sys_pages: 1390 kfree(bfregi->sys_pages); 1391 1392 out_count: 1393 kfree(bfregi->count); 1394 1395 out_ctx: 1396 return err; 1397 } 1398 1399 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1400 { 1401 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1402 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1403 struct mlx5_bfreg_info *bfregi; 1404 1405 bfregi = &context->bfregi; 1406 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1407 1408 if (context->devx_uid) 1409 mlx5_ib_devx_destroy(dev, context->devx_uid); 1410 1411 deallocate_uars(dev, context); 1412 kfree(bfregi->sys_pages); 1413 kfree(bfregi->count); 1414 } 1415 1416 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1417 int uar_idx) 1418 { 1419 int fw_uars_per_page; 1420 1421 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1422 1423 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 1424 } 1425 1426 static int get_command(unsigned long offset) 1427 { 1428 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1429 } 1430 1431 static int get_arg(unsigned long offset) 1432 { 1433 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1434 } 1435 1436 static int get_index(unsigned long offset) 1437 { 1438 return get_arg(offset); 1439 } 1440 1441 /* Index resides in an extra byte to enable larger values than 255 */ 1442 static int get_extended_index(unsigned long offset) 1443 { 1444 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 1445 } 1446 1447 1448 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1449 { 1450 } 1451 1452 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1453 { 1454 switch (cmd) { 1455 case MLX5_IB_MMAP_WC_PAGE: 1456 return "WC"; 1457 case MLX5_IB_MMAP_REGULAR_PAGE: 1458 return "best effort WC"; 1459 case MLX5_IB_MMAP_NC_PAGE: 1460 return "NC"; 1461 default: 1462 return NULL; 1463 } 1464 } 1465 1466 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 1467 struct vm_area_struct *vma, 1468 struct mlx5_ib_ucontext *context) 1469 { 1470 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 1471 !(vma->vm_flags & VM_SHARED)) 1472 return -EINVAL; 1473 1474 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 1475 return -EOPNOTSUPP; 1476 1477 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 1478 return -EPERM; 1479 1480 return -EOPNOTSUPP; 1481 } 1482 1483 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 1484 { 1485 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 1486 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 1487 1488 switch (mentry->mmap_flag) { 1489 case MLX5_IB_MMAP_TYPE_UAR_WC: 1490 case MLX5_IB_MMAP_TYPE_UAR_NC: 1491 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx); 1492 kfree(mentry); 1493 break; 1494 default: 1495 WARN_ON(true); 1496 } 1497 } 1498 1499 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1500 struct vm_area_struct *vma, 1501 struct mlx5_ib_ucontext *context) 1502 { 1503 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1504 int err; 1505 unsigned long idx; 1506 phys_addr_t pfn; 1507 pgprot_t prot; 1508 u32 bfreg_dyn_idx = 0; 1509 u32 uar_index; 1510 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 1511 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 1512 bfregi->num_static_sys_pages; 1513 1514 if (bfregi->lib_uar_dyn) 1515 return -EINVAL; 1516 1517 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1518 return -EINVAL; 1519 1520 if (dyn_uar) 1521 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 1522 else 1523 idx = get_index(vma->vm_pgoff); 1524 1525 if (idx >= max_valid_idx) { 1526 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 1527 idx, max_valid_idx); 1528 return -EINVAL; 1529 } 1530 1531 switch (cmd) { 1532 case MLX5_IB_MMAP_WC_PAGE: 1533 case MLX5_IB_MMAP_ALLOC_WC: 1534 case MLX5_IB_MMAP_REGULAR_PAGE: 1535 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1536 prot = pgprot_writecombine(vma->vm_page_prot); 1537 break; 1538 case MLX5_IB_MMAP_NC_PAGE: 1539 prot = pgprot_noncached(vma->vm_page_prot); 1540 break; 1541 default: 1542 return -EINVAL; 1543 } 1544 1545 if (dyn_uar) { 1546 int uars_per_page; 1547 1548 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 1549 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 1550 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 1551 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 1552 bfreg_dyn_idx, bfregi->total_num_bfregs); 1553 return -EINVAL; 1554 } 1555 1556 mutex_lock(&bfregi->lock); 1557 /* Fail if uar already allocated, first bfreg index of each 1558 * page holds its count. 1559 */ 1560 if (bfregi->count[bfreg_dyn_idx]) { 1561 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 1562 mutex_unlock(&bfregi->lock); 1563 return -EINVAL; 1564 } 1565 1566 bfregi->count[bfreg_dyn_idx]++; 1567 mutex_unlock(&bfregi->lock); 1568 1569 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 1570 if (err) { 1571 mlx5_ib_warn(dev, "UAR alloc failed\n"); 1572 goto free_bfreg; 1573 } 1574 } else { 1575 uar_index = bfregi->sys_pages[idx]; 1576 } 1577 1578 pfn = uar_index2pfn(dev, uar_index); 1579 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1580 1581 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 1582 prot, NULL); 1583 if (err) { 1584 mlx5_ib_err(dev, 1585 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 1586 err, mmap_cmd2str(cmd)); 1587 goto err; 1588 } 1589 1590 if (dyn_uar) 1591 bfregi->sys_pages[idx] = uar_index; 1592 return 0; 1593 1594 err: 1595 if (!dyn_uar) 1596 return err; 1597 1598 mlx5_cmd_free_uar(dev->mdev, idx); 1599 1600 free_bfreg: 1601 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 1602 1603 return err; 1604 } 1605 1606 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 1607 { 1608 unsigned long idx; 1609 u8 command; 1610 1611 command = get_command(vma->vm_pgoff); 1612 idx = get_extended_index(vma->vm_pgoff); 1613 1614 return (command << 16 | idx); 1615 } 1616 1617 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 1618 struct vm_area_struct *vma, 1619 struct ib_ucontext *ucontext) 1620 { 1621 struct mlx5_user_mmap_entry *mentry; 1622 struct rdma_user_mmap_entry *entry; 1623 unsigned long pgoff; 1624 pgprot_t prot; 1625 phys_addr_t pfn; 1626 int ret; 1627 1628 pgoff = mlx5_vma_to_pgoff(vma); 1629 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 1630 if (!entry) 1631 return -EINVAL; 1632 1633 mentry = to_mmmap(entry); 1634 pfn = (mentry->address >> PAGE_SHIFT); 1635 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 1636 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 1637 prot = pgprot_noncached(vma->vm_page_prot); 1638 else 1639 prot = pgprot_writecombine(vma->vm_page_prot); 1640 ret = rdma_user_mmap_io(ucontext, vma, pfn, 1641 entry->npages * PAGE_SIZE, 1642 prot, 1643 entry); 1644 rdma_user_mmap_entry_put(&mentry->rdma_entry); 1645 return ret; 1646 } 1647 1648 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1649 { 1650 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1651 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1652 unsigned long command; 1653 phys_addr_t pfn; 1654 1655 command = get_command(vma->vm_pgoff); 1656 switch (command) { 1657 case MLX5_IB_MMAP_WC_PAGE: 1658 case MLX5_IB_MMAP_ALLOC_WC: 1659 if (!dev->wc_support) 1660 return -EPERM; 1661 /* FALLTHROUGH */ 1662 case MLX5_IB_MMAP_NC_PAGE: 1663 case MLX5_IB_MMAP_REGULAR_PAGE: 1664 return uar_mmap(dev, command, vma, context); 1665 1666 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1667 return -ENOSYS; 1668 1669 case MLX5_IB_MMAP_CORE_CLOCK: 1670 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1671 return -EINVAL; 1672 1673 if (vma->vm_flags & VM_WRITE) 1674 return -EPERM; 1675 1676 /* Don't expose to user-space information it shouldn't have */ 1677 if (PAGE_SIZE > 4096) 1678 return -EOPNOTSUPP; 1679 1680 pfn = (dev->mdev->iseg_base + 1681 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1682 PAGE_SHIFT; 1683 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 1684 PAGE_SIZE, 1685 pgprot_noncached(vma->vm_page_prot), 1686 NULL); 1687 case MLX5_IB_MMAP_CLOCK_INFO: 1688 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 1689 1690 default: 1691 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 1692 } 1693 1694 return 0; 1695 } 1696 1697 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 1698 { 1699 struct mlx5_ib_pd *pd = to_mpd(ibpd); 1700 struct ib_device *ibdev = ibpd->device; 1701 struct mlx5_ib_alloc_pd_resp resp; 1702 int err; 1703 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1704 udata, struct mlx5_ib_ucontext, ibucontext); 1705 u16 uid = context ? context->devx_uid : 0; 1706 1707 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn, uid); 1708 if (err) 1709 return (err); 1710 1711 pd->uid = uid; 1712 if (udata) { 1713 resp.pdn = pd->pdn; 1714 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1715 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 1716 return -EFAULT; 1717 } 1718 } 1719 1720 return 0; 1721 } 1722 1723 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 1724 { 1725 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1726 struct mlx5_ib_pd *mpd = to_mpd(pd); 1727 1728 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 1729 } 1730 1731 enum { 1732 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1733 MATCH_CRITERIA_ENABLE_MISC_BIT, 1734 MATCH_CRITERIA_ENABLE_INNER_BIT 1735 }; 1736 1737 #define HEADER_IS_ZERO(match_criteria, headers) \ 1738 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1739 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1740 1741 static u8 get_match_criteria_enable(u32 *match_criteria) 1742 { 1743 u8 match_criteria_enable; 1744 1745 match_criteria_enable = 1746 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1747 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1748 match_criteria_enable |= 1749 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1750 MATCH_CRITERIA_ENABLE_MISC_BIT; 1751 match_criteria_enable |= 1752 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1753 MATCH_CRITERIA_ENABLE_INNER_BIT; 1754 1755 return match_criteria_enable; 1756 } 1757 1758 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1759 { 1760 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1761 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1762 } 1763 1764 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1765 { 1766 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1767 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1768 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1769 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1770 } 1771 1772 #define LAST_ETH_FIELD vlan_tag 1773 #define LAST_IB_FIELD sl 1774 #define LAST_IPV4_FIELD tos 1775 #define LAST_IPV6_FIELD traffic_class 1776 #define LAST_TCP_UDP_FIELD src_port 1777 1778 /* Field is the last supported field */ 1779 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1780 memchr_inv((void *)&filter.field +\ 1781 sizeof(filter.field), 0,\ 1782 sizeof(filter) -\ 1783 offsetof(typeof(filter), field) -\ 1784 sizeof(filter.field)) 1785 1786 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1787 const union ib_flow_spec *ib_spec) 1788 { 1789 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1790 outer_headers); 1791 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1792 outer_headers); 1793 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1794 misc_parameters); 1795 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1796 misc_parameters); 1797 1798 switch (ib_spec->type) { 1799 case IB_FLOW_SPEC_ETH: 1800 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1801 return -ENOTSUPP; 1802 1803 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1804 dmac_47_16), 1805 ib_spec->eth.mask.dst_mac); 1806 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1807 dmac_47_16), 1808 ib_spec->eth.val.dst_mac); 1809 1810 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1811 smac_47_16), 1812 ib_spec->eth.mask.src_mac); 1813 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1814 smac_47_16), 1815 ib_spec->eth.val.src_mac); 1816 1817 if (ib_spec->eth.mask.vlan_tag) { 1818 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1819 cvlan_tag, 1); 1820 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1821 cvlan_tag, 1); 1822 1823 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1824 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1825 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1826 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1827 1828 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1829 first_cfi, 1830 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1831 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1832 first_cfi, 1833 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1834 1835 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1836 first_prio, 1837 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1838 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1839 first_prio, 1840 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1841 } 1842 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1843 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1844 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1845 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1846 break; 1847 case IB_FLOW_SPEC_IPV4: 1848 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1849 return -ENOTSUPP; 1850 1851 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1852 ethertype, 0xffff); 1853 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1854 ethertype, ETH_P_IP); 1855 1856 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1857 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1858 &ib_spec->ipv4.mask.src_ip, 1859 sizeof(ib_spec->ipv4.mask.src_ip)); 1860 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1861 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1862 &ib_spec->ipv4.val.src_ip, 1863 sizeof(ib_spec->ipv4.val.src_ip)); 1864 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1865 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1866 &ib_spec->ipv4.mask.dst_ip, 1867 sizeof(ib_spec->ipv4.mask.dst_ip)); 1868 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1869 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1870 &ib_spec->ipv4.val.dst_ip, 1871 sizeof(ib_spec->ipv4.val.dst_ip)); 1872 1873 set_tos(outer_headers_c, outer_headers_v, 1874 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1875 1876 set_proto(outer_headers_c, outer_headers_v, 1877 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1878 break; 1879 case IB_FLOW_SPEC_IPV6: 1880 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1881 return -ENOTSUPP; 1882 1883 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1884 ethertype, 0xffff); 1885 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1886 ethertype, IPPROTO_IPV6); 1887 1888 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1889 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1890 &ib_spec->ipv6.mask.src_ip, 1891 sizeof(ib_spec->ipv6.mask.src_ip)); 1892 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1893 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1894 &ib_spec->ipv6.val.src_ip, 1895 sizeof(ib_spec->ipv6.val.src_ip)); 1896 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1897 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1898 &ib_spec->ipv6.mask.dst_ip, 1899 sizeof(ib_spec->ipv6.mask.dst_ip)); 1900 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1901 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1902 &ib_spec->ipv6.val.dst_ip, 1903 sizeof(ib_spec->ipv6.val.dst_ip)); 1904 1905 set_tos(outer_headers_c, outer_headers_v, 1906 ib_spec->ipv6.mask.traffic_class, 1907 ib_spec->ipv6.val.traffic_class); 1908 1909 set_proto(outer_headers_c, outer_headers_v, 1910 ib_spec->ipv6.mask.next_hdr, 1911 ib_spec->ipv6.val.next_hdr); 1912 1913 MLX5_SET(fte_match_set_misc, misc_params_c, 1914 outer_ipv6_flow_label, 1915 ntohl(ib_spec->ipv6.mask.flow_label)); 1916 MLX5_SET(fte_match_set_misc, misc_params_v, 1917 outer_ipv6_flow_label, 1918 ntohl(ib_spec->ipv6.val.flow_label)); 1919 break; 1920 case IB_FLOW_SPEC_TCP: 1921 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1922 LAST_TCP_UDP_FIELD)) 1923 return -ENOTSUPP; 1924 1925 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1926 0xff); 1927 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1928 IPPROTO_TCP); 1929 1930 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1931 ntohs(ib_spec->tcp_udp.mask.src_port)); 1932 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1933 ntohs(ib_spec->tcp_udp.val.src_port)); 1934 1935 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1936 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1937 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1938 ntohs(ib_spec->tcp_udp.val.dst_port)); 1939 break; 1940 case IB_FLOW_SPEC_UDP: 1941 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1942 LAST_TCP_UDP_FIELD)) 1943 return -ENOTSUPP; 1944 1945 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1946 0xff); 1947 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1948 IPPROTO_UDP); 1949 1950 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1951 ntohs(ib_spec->tcp_udp.mask.src_port)); 1952 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1953 ntohs(ib_spec->tcp_udp.val.src_port)); 1954 1955 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1956 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1957 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1958 ntohs(ib_spec->tcp_udp.val.dst_port)); 1959 break; 1960 default: 1961 return -EINVAL; 1962 } 1963 1964 return 0; 1965 } 1966 1967 /* If a flow could catch both multicast and unicast packets, 1968 * it won't fall into the multicast flow steering table and this rule 1969 * could steal other multicast packets. 1970 */ 1971 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1972 { 1973 struct ib_flow_spec_eth *eth_spec; 1974 1975 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1976 ib_attr->size < sizeof(struct ib_flow_attr) + 1977 sizeof(struct ib_flow_spec_eth) || 1978 ib_attr->num_of_specs < 1) 1979 return false; 1980 1981 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1982 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1983 eth_spec->size != sizeof(*eth_spec)) 1984 return false; 1985 1986 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1987 is_multicast_ether_addr(eth_spec->val.dst_mac); 1988 } 1989 1990 static bool is_valid_attr(const struct ib_flow_attr *flow_attr) 1991 { 1992 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1993 bool has_ipv4_spec = false; 1994 bool eth_type_ipv4 = true; 1995 unsigned int spec_index; 1996 1997 /* Validate that ethertype is correct */ 1998 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1999 if (ib_spec->type == IB_FLOW_SPEC_ETH && 2000 ib_spec->eth.mask.ether_type) { 2001 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 2002 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 2003 eth_type_ipv4 = false; 2004 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 2005 has_ipv4_spec = true; 2006 } 2007 ib_spec = (void *)ib_spec + ib_spec->size; 2008 } 2009 return !has_ipv4_spec || eth_type_ipv4; 2010 } 2011 2012 static void put_flow_table(struct mlx5_ib_dev *dev, 2013 struct mlx5_ib_flow_prio *prio, bool ft_added) 2014 { 2015 prio->refcount -= !!ft_added; 2016 if (!prio->refcount) { 2017 mlx5_destroy_flow_table(prio->flow_table); 2018 prio->flow_table = NULL; 2019 } 2020 } 2021 2022 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2023 { 2024 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2025 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2026 struct mlx5_ib_flow_handler, 2027 ibflow); 2028 struct mlx5_ib_flow_handler *iter, *tmp; 2029 2030 mutex_lock(&dev->flow_db.lock); 2031 2032 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2033 mlx5_del_flow_rule(iter->rule); 2034 put_flow_table(dev, iter->prio, true); 2035 list_del(&iter->list); 2036 kfree(iter); 2037 } 2038 2039 mlx5_del_flow_rule(handler->rule); 2040 put_flow_table(dev, handler->prio, true); 2041 mutex_unlock(&dev->flow_db.lock); 2042 2043 kfree(handler); 2044 2045 return 0; 2046 } 2047 2048 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2049 { 2050 priority *= 2; 2051 if (!dont_trap) 2052 priority++; 2053 return priority; 2054 } 2055 2056 enum flow_table_type { 2057 MLX5_IB_FT_RX, 2058 MLX5_IB_FT_TX 2059 }; 2060 2061 #define MLX5_FS_MAX_TYPES 10 2062 #define MLX5_FS_MAX_ENTRIES 32000UL 2063 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2064 struct ib_flow_attr *flow_attr, 2065 enum flow_table_type ft_type) 2066 { 2067 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2068 struct mlx5_flow_namespace *ns = NULL; 2069 struct mlx5_ib_flow_prio *prio; 2070 struct mlx5_flow_table *ft; 2071 int num_entries; 2072 int num_groups; 2073 int priority; 2074 int err = 0; 2075 2076 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2077 if (flow_is_multicast_only(flow_attr) && 2078 !dont_trap) 2079 priority = MLX5_IB_FLOW_MCAST_PRIO; 2080 else 2081 priority = ib_prio_to_core_prio(flow_attr->priority, 2082 dont_trap); 2083 ns = mlx5_get_flow_namespace(dev->mdev, 2084 MLX5_FLOW_NAMESPACE_BYPASS); 2085 num_entries = MLX5_FS_MAX_ENTRIES; 2086 num_groups = MLX5_FS_MAX_TYPES; 2087 prio = &dev->flow_db.prios[priority]; 2088 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2089 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2090 ns = mlx5_get_flow_namespace(dev->mdev, 2091 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2092 build_leftovers_ft_param("bypass", &priority, 2093 &num_entries, 2094 &num_groups); 2095 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2096 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2097 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2098 allow_sniffer_and_nic_rx_shared_tir)) 2099 return ERR_PTR(-ENOTSUPP); 2100 2101 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2102 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2103 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2104 2105 prio = &dev->flow_db.sniffer[ft_type]; 2106 priority = 0; 2107 num_entries = 1; 2108 num_groups = 1; 2109 } 2110 2111 if (!ns) 2112 return ERR_PTR(-ENOTSUPP); 2113 2114 ft = prio->flow_table; 2115 if (!ft) { 2116 ft = mlx5_create_auto_grouped_flow_table(ns, priority, "bypass", 2117 num_entries, 2118 num_groups); 2119 2120 if (!IS_ERR(ft)) { 2121 prio->refcount = 0; 2122 prio->flow_table = ft; 2123 } else { 2124 err = PTR_ERR(ft); 2125 } 2126 } 2127 2128 return err ? ERR_PTR(err) : prio; 2129 } 2130 2131 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2132 struct mlx5_ib_flow_prio *ft_prio, 2133 const struct ib_flow_attr *flow_attr, 2134 struct mlx5_flow_destination *dst) 2135 { 2136 struct mlx5_flow_table *ft = ft_prio->flow_table; 2137 struct mlx5_ib_flow_handler *handler; 2138 struct mlx5_flow_spec *spec; 2139 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2140 unsigned int spec_index; 2141 u32 action; 2142 int err = 0; 2143 2144 if (!is_valid_attr(flow_attr)) 2145 return ERR_PTR(-EINVAL); 2146 2147 spec = mlx5_vzalloc(sizeof(*spec)); 2148 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2149 if (!handler || !spec) { 2150 err = -ENOMEM; 2151 goto free; 2152 } 2153 2154 INIT_LIST_HEAD(&handler->list); 2155 2156 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2157 err = parse_flow_attr(spec->match_criteria, 2158 spec->match_value, ib_flow); 2159 if (err < 0) 2160 goto free; 2161 2162 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2163 } 2164 2165 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2166 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2167 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2168 handler->rule = mlx5_add_flow_rule(ft, spec->match_criteria_enable, 2169 spec->match_criteria, 2170 spec->match_value, 2171 action, 2172 MLX5_FS_DEFAULT_FLOW_TAG, 2173 dst); 2174 2175 if (IS_ERR(handler->rule)) { 2176 err = PTR_ERR(handler->rule); 2177 goto free; 2178 } 2179 2180 ft_prio->refcount++; 2181 handler->prio = ft_prio; 2182 2183 ft_prio->flow_table = ft; 2184 free: 2185 if (err) 2186 kfree(handler); 2187 kvfree(spec); 2188 return err ? ERR_PTR(err) : handler; 2189 } 2190 2191 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2192 struct mlx5_ib_flow_prio *ft_prio, 2193 struct ib_flow_attr *flow_attr, 2194 struct mlx5_flow_destination *dst) 2195 { 2196 struct mlx5_ib_flow_handler *handler_dst = NULL; 2197 struct mlx5_ib_flow_handler *handler = NULL; 2198 2199 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2200 if (!IS_ERR(handler)) { 2201 handler_dst = create_flow_rule(dev, ft_prio, 2202 flow_attr, dst); 2203 if (IS_ERR(handler_dst)) { 2204 mlx5_del_flow_rule(handler->rule); 2205 ft_prio->refcount--; 2206 kfree(handler); 2207 handler = handler_dst; 2208 } else { 2209 list_add(&handler_dst->list, &handler->list); 2210 } 2211 } 2212 2213 return handler; 2214 } 2215 enum { 2216 LEFTOVERS_MC, 2217 LEFTOVERS_UC, 2218 }; 2219 2220 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2221 struct mlx5_ib_flow_prio *ft_prio, 2222 struct ib_flow_attr *flow_attr, 2223 struct mlx5_flow_destination *dst) 2224 { 2225 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2226 struct mlx5_ib_flow_handler *handler = NULL; 2227 2228 static struct { 2229 struct ib_flow_attr flow_attr; 2230 struct ib_flow_spec_eth eth_flow; 2231 } leftovers_specs[] = { 2232 [LEFTOVERS_MC] = { 2233 .flow_attr = { 2234 .num_of_specs = 1, 2235 .size = sizeof(leftovers_specs[0]) 2236 }, 2237 .eth_flow = { 2238 .type = IB_FLOW_SPEC_ETH, 2239 .size = sizeof(struct ib_flow_spec_eth), 2240 .mask = {.dst_mac = {0x1} }, 2241 .val = {.dst_mac = {0x1} } 2242 } 2243 }, 2244 [LEFTOVERS_UC] = { 2245 .flow_attr = { 2246 .num_of_specs = 1, 2247 .size = sizeof(leftovers_specs[0]) 2248 }, 2249 .eth_flow = { 2250 .type = IB_FLOW_SPEC_ETH, 2251 .size = sizeof(struct ib_flow_spec_eth), 2252 .mask = {.dst_mac = {0x1} }, 2253 .val = {.dst_mac = {} } 2254 } 2255 } 2256 }; 2257 2258 handler = create_flow_rule(dev, ft_prio, 2259 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2260 dst); 2261 if (!IS_ERR(handler) && 2262 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2263 handler_ucast = create_flow_rule(dev, ft_prio, 2264 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2265 dst); 2266 if (IS_ERR(handler_ucast)) { 2267 mlx5_del_flow_rule(handler->rule); 2268 ft_prio->refcount--; 2269 kfree(handler); 2270 handler = handler_ucast; 2271 } else { 2272 list_add(&handler_ucast->list, &handler->list); 2273 } 2274 } 2275 2276 return handler; 2277 } 2278 2279 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2280 struct mlx5_ib_flow_prio *ft_rx, 2281 struct mlx5_ib_flow_prio *ft_tx, 2282 struct mlx5_flow_destination *dst) 2283 { 2284 struct mlx5_ib_flow_handler *handler_rx; 2285 struct mlx5_ib_flow_handler *handler_tx; 2286 int err; 2287 static const struct ib_flow_attr flow_attr = { 2288 .num_of_specs = 0, 2289 .size = sizeof(flow_attr) 2290 }; 2291 2292 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2293 if (IS_ERR(handler_rx)) { 2294 err = PTR_ERR(handler_rx); 2295 goto err; 2296 } 2297 2298 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2299 if (IS_ERR(handler_tx)) { 2300 err = PTR_ERR(handler_tx); 2301 goto err_tx; 2302 } 2303 2304 list_add(&handler_tx->list, &handler_rx->list); 2305 2306 return handler_rx; 2307 2308 err_tx: 2309 mlx5_del_flow_rule(handler_rx->rule); 2310 ft_rx->refcount--; 2311 kfree(handler_rx); 2312 err: 2313 return ERR_PTR(err); 2314 } 2315 2316 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2317 struct ib_flow_attr *flow_attr, 2318 int domain, 2319 struct ib_udata *udata) 2320 { 2321 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2322 struct mlx5_ib_qp *mqp = to_mqp(qp); 2323 struct mlx5_ib_flow_handler *handler = NULL; 2324 struct mlx5_flow_destination *dst = NULL; 2325 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2326 struct mlx5_ib_flow_prio *ft_prio; 2327 int err; 2328 2329 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2330 return ERR_PTR(-ENOSPC); 2331 2332 if (domain != IB_FLOW_DOMAIN_USER || 2333 udata != NULL || 2334 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2335 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2336 return ERR_PTR(-EINVAL); 2337 2338 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2339 if (!dst) 2340 return ERR_PTR(-ENOMEM); 2341 2342 mutex_lock(&dev->flow_db.lock); 2343 2344 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2345 if (IS_ERR(ft_prio)) { 2346 err = PTR_ERR(ft_prio); 2347 goto unlock; 2348 } 2349 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2350 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2351 if (IS_ERR(ft_prio_tx)) { 2352 err = PTR_ERR(ft_prio_tx); 2353 ft_prio_tx = NULL; 2354 goto destroy_ft; 2355 } 2356 } 2357 2358 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2359 if (mqp->flags & MLX5_IB_QP_RSS) 2360 dst->tir_num = mqp->rss_qp.tirn; 2361 else 2362 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2363 2364 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2365 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2366 handler = create_dont_trap_rule(dev, ft_prio, 2367 flow_attr, dst); 2368 } else { 2369 handler = create_flow_rule(dev, ft_prio, flow_attr, 2370 dst); 2371 } 2372 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2373 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2374 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2375 dst); 2376 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2377 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2378 } else { 2379 err = -EINVAL; 2380 goto destroy_ft; 2381 } 2382 2383 if (IS_ERR(handler)) { 2384 err = PTR_ERR(handler); 2385 handler = NULL; 2386 goto destroy_ft; 2387 } 2388 2389 mutex_unlock(&dev->flow_db.lock); 2390 kfree(dst); 2391 2392 return &handler->ibflow; 2393 2394 destroy_ft: 2395 put_flow_table(dev, ft_prio, false); 2396 if (ft_prio_tx) 2397 put_flow_table(dev, ft_prio_tx, false); 2398 unlock: 2399 mutex_unlock(&dev->flow_db.lock); 2400 kfree(dst); 2401 kfree(handler); 2402 return ERR_PTR(err); 2403 } 2404 2405 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2406 { 2407 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2408 int err; 2409 2410 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2411 if (err) 2412 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2413 ibqp->qp_num, gid->raw); 2414 2415 return err; 2416 } 2417 2418 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2419 { 2420 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2421 int err; 2422 2423 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2424 if (err) 2425 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2426 ibqp->qp_num, gid->raw); 2427 2428 return err; 2429 } 2430 2431 static int init_node_data(struct mlx5_ib_dev *dev) 2432 { 2433 int err; 2434 2435 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2436 if (err) 2437 return err; 2438 2439 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2440 } 2441 2442 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2443 char *buf) 2444 { 2445 struct mlx5_ib_dev *dev = 2446 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2447 2448 return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages); 2449 } 2450 2451 static ssize_t show_reg_pages(struct device *device, 2452 struct device_attribute *attr, char *buf) 2453 { 2454 struct mlx5_ib_dev *dev = 2455 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2456 2457 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2458 } 2459 2460 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2461 char *buf) 2462 { 2463 struct mlx5_ib_dev *dev = 2464 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2465 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2466 } 2467 2468 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2469 char *buf) 2470 { 2471 struct mlx5_ib_dev *dev = 2472 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2473 return sprintf(buf, "%x\n", dev->mdev->pdev->revision); 2474 } 2475 2476 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2477 char *buf) 2478 { 2479 struct mlx5_ib_dev *dev = 2480 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2481 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2482 dev->mdev->board_id); 2483 } 2484 2485 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2486 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2487 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2488 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2489 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2490 2491 static struct device_attribute *mlx5_class_attributes[] = { 2492 &dev_attr_hw_rev, 2493 &dev_attr_hca_type, 2494 &dev_attr_board_id, 2495 &dev_attr_fw_pages, 2496 &dev_attr_reg_pages, 2497 }; 2498 2499 static void pkey_change_handler(struct work_struct *work) 2500 { 2501 struct mlx5_ib_port_resources *ports = 2502 container_of(work, struct mlx5_ib_port_resources, 2503 pkey_change_work); 2504 2505 mutex_lock(&ports->devr->mutex); 2506 mlx5_ib_gsi_pkey_change(ports->gsi); 2507 mutex_unlock(&ports->devr->mutex); 2508 } 2509 2510 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2511 { 2512 struct mlx5_ib_qp *mqp; 2513 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2514 struct mlx5_core_cq *mcq; 2515 struct list_head cq_armed_list; 2516 unsigned long flags_qp; 2517 unsigned long flags_cq; 2518 unsigned long flags; 2519 2520 INIT_LIST_HEAD(&cq_armed_list); 2521 2522 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2523 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2524 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2525 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2526 if (mqp->sq.tail != mqp->sq.head) { 2527 send_mcq = to_mcq(mqp->ibqp.send_cq); 2528 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2529 if (send_mcq->mcq.comp && 2530 mqp->ibqp.send_cq->comp_handler) { 2531 if (!send_mcq->mcq.reset_notify_added) { 2532 send_mcq->mcq.reset_notify_added = 1; 2533 list_add_tail(&send_mcq->mcq.reset_notify, 2534 &cq_armed_list); 2535 } 2536 } 2537 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2538 } 2539 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2540 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2541 /* no handling is needed for SRQ */ 2542 if (!mqp->ibqp.srq) { 2543 if (mqp->rq.tail != mqp->rq.head) { 2544 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2545 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2546 if (recv_mcq->mcq.comp && 2547 mqp->ibqp.recv_cq->comp_handler) { 2548 if (!recv_mcq->mcq.reset_notify_added) { 2549 recv_mcq->mcq.reset_notify_added = 1; 2550 list_add_tail(&recv_mcq->mcq.reset_notify, 2551 &cq_armed_list); 2552 } 2553 } 2554 spin_unlock_irqrestore(&recv_mcq->lock, 2555 flags_cq); 2556 } 2557 } 2558 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2559 } 2560 /*At that point all inflight post send were put to be executed as of we 2561 * lock/unlock above locks Now need to arm all involved CQs. 2562 */ 2563 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2564 mcq->comp(mcq, NULL); 2565 } 2566 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2567 } 2568 2569 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2570 enum mlx5_dev_event event, unsigned long param) 2571 { 2572 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2573 struct ib_event ibev; 2574 bool fatal = false; 2575 u8 port = (u8)param; 2576 2577 switch (event) { 2578 case MLX5_DEV_EVENT_SYS_ERROR: 2579 ibev.event = IB_EVENT_DEVICE_FATAL; 2580 mlx5_ib_handle_internal_error(ibdev); 2581 fatal = true; 2582 break; 2583 2584 case MLX5_DEV_EVENT_PORT_UP: 2585 case MLX5_DEV_EVENT_PORT_DOWN: 2586 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2587 /* In RoCE, port up/down events are handled in 2588 * mlx5_netdev_event(). 2589 */ 2590 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2591 IB_LINK_LAYER_ETHERNET) 2592 return; 2593 2594 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2595 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2596 break; 2597 2598 case MLX5_DEV_EVENT_LID_CHANGE: 2599 ibev.event = IB_EVENT_LID_CHANGE; 2600 break; 2601 2602 case MLX5_DEV_EVENT_PKEY_CHANGE: 2603 ibev.event = IB_EVENT_PKEY_CHANGE; 2604 2605 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2606 break; 2607 2608 case MLX5_DEV_EVENT_GUID_CHANGE: 2609 ibev.event = IB_EVENT_GID_CHANGE; 2610 break; 2611 2612 case MLX5_DEV_EVENT_CLIENT_REREG: 2613 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2614 break; 2615 2616 default: 2617 /* unsupported event */ 2618 return; 2619 } 2620 2621 ibev.device = &ibdev->ib_dev; 2622 ibev.element.port_num = port; 2623 2624 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 2625 mlx5_ib_warn(ibdev, "warning: event(%d) on port %d\n", event, port); 2626 return; 2627 } 2628 2629 if (ibdev->ib_active) 2630 ib_dispatch_event(&ibev); 2631 2632 if (fatal) 2633 ibdev->ib_active = false; 2634 } 2635 2636 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2637 { 2638 int port; 2639 2640 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2641 mlx5_query_ext_port_caps(dev, port); 2642 } 2643 2644 static int get_port_caps(struct mlx5_ib_dev *dev) 2645 { 2646 struct ib_device_attr *dprops = NULL; 2647 struct ib_port_attr *pprops = NULL; 2648 int err = -ENOMEM; 2649 int port; 2650 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2651 2652 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2653 if (!pprops) 2654 goto out; 2655 2656 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2657 if (!dprops) 2658 goto out; 2659 2660 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2661 if (err) { 2662 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2663 goto out; 2664 } 2665 2666 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2667 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2668 if (err) { 2669 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2670 port, err); 2671 break; 2672 } 2673 dev->mdev->port_caps[port - 1].pkey_table_len = 2674 dprops->max_pkeys; 2675 dev->mdev->port_caps[port - 1].gid_table_len = 2676 pprops->gid_tbl_len; 2677 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2678 dprops->max_pkeys, pprops->gid_tbl_len); 2679 } 2680 2681 out: 2682 kfree(pprops); 2683 kfree(dprops); 2684 2685 return err; 2686 } 2687 2688 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2689 { 2690 int err; 2691 2692 err = mlx5_mr_cache_cleanup(dev); 2693 if (err) 2694 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2695 2696 if (dev->umrc.qp) 2697 mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 2698 if (dev->umrc.cq) 2699 ib_free_cq(dev->umrc.cq); 2700 if (dev->umrc.pd) 2701 ib_dealloc_pd(dev->umrc.pd); 2702 } 2703 2704 enum { 2705 MAX_UMR_WR = 128, 2706 }; 2707 2708 static int create_umr_res(struct mlx5_ib_dev *dev) 2709 { 2710 struct ib_qp_init_attr *init_attr = NULL; 2711 struct ib_qp_attr *attr = NULL; 2712 struct ib_pd *pd; 2713 struct ib_cq *cq; 2714 struct ib_qp *qp; 2715 int ret; 2716 2717 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2718 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2719 if (!attr || !init_attr) { 2720 ret = -ENOMEM; 2721 goto error_0; 2722 } 2723 2724 pd = ib_alloc_pd(&dev->ib_dev, 0); 2725 if (IS_ERR(pd)) { 2726 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2727 ret = PTR_ERR(pd); 2728 goto error_0; 2729 } 2730 2731 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2732 if (IS_ERR(cq)) { 2733 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2734 ret = PTR_ERR(cq); 2735 goto error_2; 2736 } 2737 2738 init_attr->send_cq = cq; 2739 init_attr->recv_cq = cq; 2740 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2741 init_attr->cap.max_send_wr = MAX_UMR_WR; 2742 init_attr->cap.max_send_sge = 1; 2743 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2744 init_attr->port_num = 1; 2745 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2746 if (IS_ERR(qp)) { 2747 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2748 ret = PTR_ERR(qp); 2749 goto error_3; 2750 } 2751 qp->device = &dev->ib_dev; 2752 qp->real_qp = qp; 2753 qp->uobject = NULL; 2754 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2755 2756 attr->qp_state = IB_QPS_INIT; 2757 attr->port_num = 1; 2758 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2759 IB_QP_PORT, NULL); 2760 if (ret) { 2761 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2762 goto error_4; 2763 } 2764 2765 memset(attr, 0, sizeof(*attr)); 2766 attr->qp_state = IB_QPS_RTR; 2767 attr->path_mtu = IB_MTU_256; 2768 2769 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2770 if (ret) { 2771 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2772 goto error_4; 2773 } 2774 2775 memset(attr, 0, sizeof(*attr)); 2776 attr->qp_state = IB_QPS_RTS; 2777 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2778 if (ret) { 2779 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2780 goto error_4; 2781 } 2782 2783 dev->umrc.qp = qp; 2784 dev->umrc.cq = cq; 2785 dev->umrc.pd = pd; 2786 2787 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2788 ret = mlx5_mr_cache_init(dev); 2789 if (ret) { 2790 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2791 goto error_4; 2792 } 2793 2794 kfree(attr); 2795 kfree(init_attr); 2796 2797 return 0; 2798 2799 error_4: 2800 mlx5_ib_destroy_qp(qp, NULL); 2801 dev->umrc.qp = NULL; 2802 2803 error_3: 2804 ib_free_cq(cq); 2805 dev->umrc.cq = NULL; 2806 2807 error_2: 2808 ib_dealloc_pd(pd); 2809 dev->umrc.pd = NULL; 2810 2811 error_0: 2812 kfree(attr); 2813 kfree(init_attr); 2814 return ret; 2815 } 2816 2817 static int create_dev_resources(struct mlx5_ib_resources *devr) 2818 { 2819 struct ib_srq_init_attr attr; 2820 struct mlx5_ib_dev *dev; 2821 struct ib_device *ibdev; 2822 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2823 int port; 2824 int ret = 0; 2825 2826 dev = container_of(devr, struct mlx5_ib_dev, devr); 2827 ibdev = &dev->ib_dev; 2828 2829 mutex_init(&devr->mutex); 2830 2831 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 2832 if (!devr->p0) 2833 return -ENOMEM; 2834 2835 devr->p0->device = ibdev; 2836 devr->p0->uobject = NULL; 2837 atomic_set(&devr->p0->usecnt, 0); 2838 2839 ret = mlx5_ib_alloc_pd(devr->p0, NULL); 2840 if (ret) 2841 goto error0; 2842 2843 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq); 2844 if (!devr->c0) { 2845 ret = -ENOMEM; 2846 goto error1; 2847 } 2848 2849 devr->c0->device = &dev->ib_dev; 2850 atomic_set(&devr->c0->usecnt, 0); 2851 2852 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL); 2853 if (ret) 2854 goto err_create_cq; 2855 2856 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL); 2857 if (IS_ERR(devr->x0)) { 2858 ret = PTR_ERR(devr->x0); 2859 goto error2; 2860 } 2861 devr->x0->device = &dev->ib_dev; 2862 devr->x0->inode = NULL; 2863 atomic_set(&devr->x0->usecnt, 0); 2864 mutex_init(&devr->x0->tgt_qp_mutex); 2865 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2866 2867 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL); 2868 if (IS_ERR(devr->x1)) { 2869 ret = PTR_ERR(devr->x1); 2870 goto error3; 2871 } 2872 devr->x1->device = &dev->ib_dev; 2873 devr->x1->inode = NULL; 2874 atomic_set(&devr->x1->usecnt, 0); 2875 mutex_init(&devr->x1->tgt_qp_mutex); 2876 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2877 2878 memset(&attr, 0, sizeof(attr)); 2879 attr.attr.max_sge = 1; 2880 attr.attr.max_wr = 1; 2881 attr.srq_type = IB_SRQT_XRC; 2882 attr.ext.cq = devr->c0; 2883 attr.ext.xrc.xrcd = devr->x0; 2884 2885 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); 2886 if (!devr->s0) { 2887 ret = -ENOMEM; 2888 goto error4; 2889 } 2890 2891 devr->s0->device = &dev->ib_dev; 2892 devr->s0->pd = devr->p0; 2893 devr->s0->srq_type = IB_SRQT_XRC; 2894 devr->s0->ext.xrc.xrcd = devr->x0; 2895 devr->s0->ext.cq = devr->c0; 2896 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); 2897 if (ret) 2898 goto err_create; 2899 2900 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2901 atomic_inc(&devr->s0->ext.cq->usecnt); 2902 atomic_inc(&devr->p0->usecnt); 2903 atomic_set(&devr->s0->usecnt, 0); 2904 2905 memset(&attr, 0, sizeof(attr)); 2906 attr.attr.max_sge = 1; 2907 attr.attr.max_wr = 1; 2908 attr.srq_type = IB_SRQT_BASIC; 2909 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq); 2910 if (!devr->s1) { 2911 ret = -ENOMEM; 2912 goto error5; 2913 } 2914 2915 devr->s1->device = &dev->ib_dev; 2916 devr->s1->pd = devr->p0; 2917 devr->s1->srq_type = IB_SRQT_BASIC; 2918 devr->s1->ext.cq = devr->c0; 2919 2920 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL); 2921 if (ret) 2922 goto error6; 2923 2924 atomic_inc(&devr->p0->usecnt); 2925 atomic_set(&devr->s1->usecnt, 0); 2926 2927 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 2928 INIT_WORK(&devr->ports[port].pkey_change_work, 2929 pkey_change_handler); 2930 devr->ports[port].devr = devr; 2931 } 2932 2933 return 0; 2934 2935 error6: 2936 kfree(devr->s1); 2937 error5: 2938 mlx5_ib_destroy_srq(devr->s0, NULL); 2939 err_create: 2940 kfree(devr->s0); 2941 error4: 2942 mlx5_ib_dealloc_xrcd(devr->x1, NULL); 2943 error3: 2944 mlx5_ib_dealloc_xrcd(devr->x0, NULL); 2945 error2: 2946 mlx5_ib_destroy_cq(devr->c0, NULL); 2947 err_create_cq: 2948 kfree(devr->c0); 2949 error1: 2950 mlx5_ib_dealloc_pd(devr->p0, NULL); 2951 error0: 2952 kfree(devr->p0); 2953 return ret; 2954 } 2955 2956 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2957 { 2958 int port; 2959 2960 mlx5_ib_destroy_srq(devr->s1, NULL); 2961 kfree(devr->s1); 2962 mlx5_ib_destroy_srq(devr->s0, NULL); 2963 kfree(devr->s0); 2964 mlx5_ib_dealloc_xrcd(devr->x0, NULL); 2965 mlx5_ib_dealloc_xrcd(devr->x1, NULL); 2966 mlx5_ib_destroy_cq(devr->c0, NULL); 2967 kfree(devr->c0); 2968 mlx5_ib_dealloc_pd(devr->p0, NULL); 2969 kfree(devr->p0); 2970 2971 /* Make sure no change P_Key work items are still executing */ 2972 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2973 cancel_work_sync(&devr->ports[port].pkey_change_work); 2974 } 2975 2976 static u32 get_core_cap_flags(struct ib_device *ibdev) 2977 { 2978 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2979 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2980 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2981 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2982 u32 ret = 0; 2983 2984 if (ll == IB_LINK_LAYER_INFINIBAND) 2985 return RDMA_CORE_PORT_IBA_IB; 2986 2987 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2988 return 0; 2989 2990 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2991 return 0; 2992 2993 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2994 ret |= RDMA_CORE_PORT_IBA_ROCE; 2995 2996 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2997 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2998 2999 return ret; 3000 } 3001 3002 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3003 struct ib_port_immutable *immutable) 3004 { 3005 struct ib_port_attr attr; 3006 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3007 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3008 int err; 3009 3010 err = mlx5_ib_query_port(ibdev, port_num, &attr); 3011 if (err) 3012 return err; 3013 3014 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3015 immutable->gid_tbl_len = attr.gid_tbl_len; 3016 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3017 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3018 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3019 3020 return 0; 3021 } 3022 3023 static void get_dev_fw_str(struct ib_device *ibdev, char *str, 3024 size_t str_len) 3025 { 3026 struct mlx5_ib_dev *dev = 3027 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3028 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 3029 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 3030 } 3031 3032 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev) 3033 { 3034 return 0; 3035 } 3036 3037 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev) 3038 { 3039 } 3040 3041 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev) 3042 { 3043 if (dev->roce.nb.notifier_call) { 3044 unregister_netdevice_notifier(&dev->roce.nb); 3045 dev->roce.nb.notifier_call = NULL; 3046 } 3047 } 3048 3049 static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 3050 { 3051 VNET_ITERATOR_DECL(vnet_iter); 3052 struct ifnet *idev; 3053 int err; 3054 3055 /* Check if mlx5en net device already exists */ 3056 VNET_LIST_RLOCK(); 3057 VNET_FOREACH(vnet_iter) { 3058 IFNET_RLOCK(); 3059 CURVNET_SET_QUIET(vnet_iter); 3060 CK_STAILQ_FOREACH(idev, &V_ifnet, if_link) { 3061 /* check if network interface belongs to mlx5en */ 3062 if (!mlx5_netdev_match(idev, dev->mdev, "mce")) 3063 continue; 3064 write_lock(&dev->roce.netdev_lock); 3065 dev->roce.netdev = idev; 3066 write_unlock(&dev->roce.netdev_lock); 3067 } 3068 CURVNET_RESTORE(); 3069 IFNET_RUNLOCK(); 3070 } 3071 VNET_LIST_RUNLOCK(); 3072 3073 dev->roce.nb.notifier_call = mlx5_netdev_event; 3074 err = register_netdevice_notifier(&dev->roce.nb); 3075 if (err) { 3076 dev->roce.nb.notifier_call = NULL; 3077 return err; 3078 } 3079 3080 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3081 err = mlx5_nic_vport_enable_roce(dev->mdev); 3082 if (err) 3083 goto err_unregister_netdevice_notifier; 3084 } 3085 3086 err = mlx5_roce_lag_init(dev); 3087 if (err) 3088 goto err_disable_roce; 3089 3090 return 0; 3091 3092 err_disable_roce: 3093 if (MLX5_CAP_GEN(dev->mdev, roce)) 3094 mlx5_nic_vport_disable_roce(dev->mdev); 3095 3096 err_unregister_netdevice_notifier: 3097 mlx5_remove_roce_notifier(dev); 3098 return err; 3099 } 3100 3101 static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 3102 { 3103 mlx5_roce_lag_cleanup(dev); 3104 if (MLX5_CAP_GEN(dev->mdev, roce)) 3105 mlx5_nic_vport_disable_roce(dev->mdev); 3106 } 3107 3108 static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num) 3109 { 3110 mlx5_vport_dealloc_q_counter(dev->mdev, 3111 MLX5_INTERFACE_PROTOCOL_IB, 3112 dev->port[port_num].q_cnt_id); 3113 dev->port[port_num].q_cnt_id = 0; 3114 } 3115 3116 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 3117 { 3118 unsigned int i; 3119 3120 for (i = 0; i < dev->num_ports; i++) 3121 mlx5_ib_dealloc_q_port_counter(dev, i); 3122 } 3123 3124 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) 3125 { 3126 int i; 3127 int ret; 3128 3129 for (i = 0; i < dev->num_ports; i++) { 3130 ret = mlx5_vport_alloc_q_counter(dev->mdev, 3131 MLX5_INTERFACE_PROTOCOL_IB, 3132 &dev->port[i].q_cnt_id); 3133 if (ret) { 3134 mlx5_ib_warn(dev, 3135 "couldn't allocate queue counter for port %d, err %d\n", 3136 i + 1, ret); 3137 goto dealloc_counters; 3138 } 3139 } 3140 3141 return 0; 3142 3143 dealloc_counters: 3144 while (--i >= 0) 3145 mlx5_ib_dealloc_q_port_counter(dev, i); 3146 3147 return ret; 3148 } 3149 3150 static const char * const names[] = { 3151 "rx_write_requests", 3152 "rx_read_requests", 3153 "rx_atomic_requests", 3154 "out_of_buffer", 3155 "out_of_sequence", 3156 "duplicate_request", 3157 "rnr_nak_retry_err", 3158 "packet_seq_err", 3159 "implied_nak_seq_err", 3160 "local_ack_timeout_err", 3161 }; 3162 3163 static const size_t stats_offsets[] = { 3164 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests), 3165 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests), 3166 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests), 3167 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer), 3168 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence), 3169 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request), 3170 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err), 3171 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err), 3172 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err), 3173 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err), 3174 }; 3175 3176 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3177 u8 port_num) 3178 { 3179 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets)); 3180 3181 /* We support only per port stats */ 3182 if (port_num == 0) 3183 return NULL; 3184 3185 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names), 3186 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3187 } 3188 3189 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3190 struct rdma_hw_stats *stats, 3191 u8 port, int index) 3192 { 3193 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3194 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3195 void *out; 3196 __be32 val; 3197 int ret; 3198 int i; 3199 3200 if (!port || !stats) 3201 return -ENOSYS; 3202 3203 out = mlx5_vzalloc(outlen); 3204 if (!out) 3205 return -ENOMEM; 3206 3207 ret = mlx5_vport_query_q_counter(dev->mdev, 3208 dev->port[port - 1].q_cnt_id, 0, 3209 out, outlen); 3210 if (ret) 3211 goto free; 3212 3213 for (i = 0; i < ARRAY_SIZE(names); i++) { 3214 val = *(__be32 *)(out + stats_offsets[i]); 3215 stats->value[i] = (u64)be32_to_cpu(val); 3216 } 3217 free: 3218 kvfree(out); 3219 return ARRAY_SIZE(names); 3220 } 3221 3222 static int mlx5_ib_stage_bfreg_init(struct mlx5_ib_dev *dev) 3223 { 3224 int err; 3225 3226 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 3227 if (err) 3228 return err; 3229 3230 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 3231 if (err) { 3232 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3233 return err; 3234 } 3235 3236 err = mlx5_alloc_bfreg(dev->mdev, &dev->wc_bfreg, true, false); 3237 if (err) { 3238 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3239 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3240 } 3241 3242 return err; 3243 } 3244 3245 static void mlx5_ib_stage_bfreg_cleanup(struct mlx5_ib_dev *dev) 3246 { 3247 mlx5_free_bfreg(dev->mdev, &dev->wc_bfreg); 3248 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3249 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3250 } 3251 3252 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3253 { 3254 struct mlx5_ib_dev *dev; 3255 enum rdma_link_layer ll; 3256 int port_type_cap; 3257 int err; 3258 int i; 3259 3260 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3261 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3262 3263 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3264 if (!dev) 3265 return NULL; 3266 3267 dev->mdev = mdev; 3268 3269 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3270 GFP_KERNEL); 3271 if (!dev->port) 3272 goto err_dealloc; 3273 3274 rwlock_init(&dev->roce.netdev_lock); 3275 err = get_port_caps(dev); 3276 if (err) 3277 goto err_free_port; 3278 3279 if (mlx5_use_mad_ifc(dev)) 3280 get_ext_port_caps(dev); 3281 3282 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 3283 3284 INIT_IB_DEVICE_OPS(&dev->ib_dev.ops, mlx5, MLX5); 3285 snprintf(dev->ib_dev.name, IB_DEVICE_NAME_MAX, "mlx5_%d", device_get_unit(mdev->pdev->dev.bsddev)); 3286 dev->ib_dev.owner = THIS_MODULE; 3287 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3288 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3289 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3290 dev->ib_dev.phys_port_cnt = dev->num_ports; 3291 dev->ib_dev.num_comp_vectors = 3292 dev->mdev->priv.eq_table.num_comp_vectors; 3293 dev->ib_dev.dma_device = &mdev->pdev->dev; 3294 3295 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3296 dev->ib_dev.uverbs_cmd_mask = 3297 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3298 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3299 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3300 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3301 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3302 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3303 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3304 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3305 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3306 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3307 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3308 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3309 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3310 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3311 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3312 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3313 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3314 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3315 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3316 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3317 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3318 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3319 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3320 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3321 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3322 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3323 dev->ib_dev.uverbs_ex_cmd_mask = 3324 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3325 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3326 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 3327 3328 dev->ib_dev.query_device = mlx5_ib_query_device; 3329 dev->ib_dev.query_port = mlx5_ib_query_port; 3330 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3331 if (ll == IB_LINK_LAYER_ETHERNET) 3332 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3333 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3334 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3335 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3336 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3337 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3338 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3339 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3340 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3341 dev->ib_dev.mmap = mlx5_ib_mmap; 3342 dev->ib_dev.mmap_free = mlx5_ib_mmap_free; 3343 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3344 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3345 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3346 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3347 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3348 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3349 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3350 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3351 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3352 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3353 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3354 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3355 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3356 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3357 dev->ib_dev.post_send = mlx5_ib_post_send; 3358 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3359 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3360 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3361 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3362 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3363 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3364 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3365 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3366 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3367 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3368 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3369 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3370 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3371 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3372 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3373 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3374 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3375 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3376 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3377 if (mlx5_core_is_pf(mdev)) { 3378 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3379 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3380 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3381 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3382 } 3383 3384 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3385 3386 mlx5_ib_internal_fill_odp_caps(dev); 3387 3388 if (MLX5_CAP_GEN(mdev, imaicl)) { 3389 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3390 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3391 dev->ib_dev.uverbs_cmd_mask |= 3392 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3393 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3394 } 3395 3396 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) && 3397 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3398 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3399 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3400 } 3401 3402 if (MLX5_CAP_GEN(mdev, xrc)) { 3403 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3404 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3405 dev->ib_dev.uverbs_cmd_mask |= 3406 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3407 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3408 } 3409 3410 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3411 IB_LINK_LAYER_ETHERNET) { 3412 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3413 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3414 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3415 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3416 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3417 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3418 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3419 dev->ib_dev.uverbs_ex_cmd_mask |= 3420 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3421 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3422 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3423 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3424 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3425 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3426 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3427 } 3428 err = init_node_data(dev); 3429 if (err) 3430 goto err_free_port; 3431 3432 mutex_init(&dev->flow_db.lock); 3433 mutex_init(&dev->cap_mask_mutex); 3434 INIT_LIST_HEAD(&dev->qp_list); 3435 spin_lock_init(&dev->reset_flow_resource_lock); 3436 3437 if (ll == IB_LINK_LAYER_ETHERNET) { 3438 err = mlx5_enable_roce(dev); 3439 if (err) 3440 goto err_free_port; 3441 } 3442 3443 err = create_dev_resources(&dev->devr); 3444 if (err) 3445 goto err_disable_roce; 3446 3447 err = mlx5_ib_odp_init_one(dev); 3448 if (err) 3449 goto err_rsrc; 3450 3451 err = mlx5_ib_alloc_q_counters(dev); 3452 if (err) 3453 goto err_odp; 3454 3455 err = mlx5_ib_stage_bfreg_init(dev); 3456 if (err) 3457 goto err_q_cnt; 3458 3459 err = ib_register_device(&dev->ib_dev, NULL); 3460 if (err) 3461 goto err_bfreg; 3462 3463 err = create_umr_res(dev); 3464 if (err) 3465 goto err_dev; 3466 3467 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3468 err = device_create_file(&dev->ib_dev.dev, 3469 mlx5_class_attributes[i]); 3470 if (err) 3471 goto err_umrc; 3472 } 3473 3474 err = mlx5_ib_init_congestion(dev); 3475 if (err) 3476 goto err_umrc; 3477 3478 dev->ib_active = true; 3479 3480 return dev; 3481 3482 err_umrc: 3483 destroy_umrc_res(dev); 3484 3485 err_dev: 3486 ib_unregister_device(&dev->ib_dev); 3487 3488 err_bfreg: 3489 mlx5_ib_stage_bfreg_cleanup(dev); 3490 3491 err_q_cnt: 3492 mlx5_ib_dealloc_q_counters(dev); 3493 3494 err_odp: 3495 mlx5_ib_odp_remove_one(dev); 3496 3497 err_rsrc: 3498 destroy_dev_resources(&dev->devr); 3499 3500 err_disable_roce: 3501 if (ll == IB_LINK_LAYER_ETHERNET) { 3502 mlx5_disable_roce(dev); 3503 mlx5_remove_roce_notifier(dev); 3504 } 3505 3506 err_free_port: 3507 kfree(dev->port); 3508 3509 err_dealloc: 3510 ib_dealloc_device((struct ib_device *)dev); 3511 3512 return NULL; 3513 } 3514 3515 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3516 { 3517 struct mlx5_ib_dev *dev = context; 3518 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3519 3520 mlx5_ib_cleanup_congestion(dev); 3521 mlx5_remove_roce_notifier(dev); 3522 ib_unregister_device(&dev->ib_dev); 3523 mlx5_ib_stage_bfreg_cleanup(dev); 3524 mlx5_ib_dealloc_q_counters(dev); 3525 destroy_umrc_res(dev); 3526 mlx5_ib_odp_remove_one(dev); 3527 destroy_dev_resources(&dev->devr); 3528 if (ll == IB_LINK_LAYER_ETHERNET) 3529 mlx5_disable_roce(dev); 3530 kfree(dev->port); 3531 ib_dealloc_device(&dev->ib_dev); 3532 } 3533 3534 static struct mlx5_interface mlx5_ib_interface = { 3535 .add = mlx5_ib_add, 3536 .remove = mlx5_ib_remove, 3537 .event = mlx5_ib_event, 3538 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3539 }; 3540 3541 static int __init mlx5_ib_init(void) 3542 { 3543 int err; 3544 3545 err = mlx5_ib_odp_init(); 3546 if (err) 3547 return err; 3548 3549 err = mlx5_register_interface(&mlx5_ib_interface); 3550 if (err) 3551 goto clean_odp; 3552 3553 return err; 3554 3555 clean_odp: 3556 mlx5_ib_odp_cleanup(); 3557 return err; 3558 } 3559 3560 static void __exit mlx5_ib_cleanup(void) 3561 { 3562 mlx5_unregister_interface(&mlx5_ib_interface); 3563 mlx5_ib_odp_cleanup(); 3564 } 3565 3566 module_init_order(mlx5_ib_init, SI_ORDER_SEVENTH); 3567 module_exit_order(mlx5_ib_cleanup, SI_ORDER_SEVENTH); 3568