1 /* 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020-2023, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Authors: Sumit Saxena <sumit.saxena@broadcom.com> 8 * Chandrakanth Patil <chandrakanth.patil@broadcom.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are 12 * met: 13 * 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation and/or other 18 * materials provided with the distribution. 19 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 * The views and conclusions contained in the software and documentation are 36 * those of the authors and should not be interpreted as representing 37 * official policies,either expressed or implied, of the FreeBSD Project. 38 * 39 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 40 * 41 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 42 */ 43 44 #ifndef _MPI3MRVAR_H 45 #define _MPI3MRVAR_H 46 47 #include <sys/cdefs.h> 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/module.h> 53 #include <sys/bus.h> 54 #include <sys/conf.h> 55 #include <sys/malloc.h> 56 #include <sys/sysctl.h> 57 #include <sys/uio.h> 58 #include <sys/selinfo.h> 59 #include <sys/poll.h> 60 61 #include <sys/lock.h> 62 #include <sys/mutex.h> 63 #include <sys/endian.h> 64 #include <sys/sysent.h> 65 #include <sys/taskqueue.h> 66 #include <sys/smp.h> 67 68 #include <machine/bus.h> 69 #include <machine/resource.h> 70 #include <sys/rman.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pci_private.h> 75 76 #include <cam/cam.h> 77 #include <cam/cam_ccb.h> 78 #include <cam/cam_debug.h> 79 #include <cam/cam_sim.h> 80 #include <cam/cam_xpt_sim.h> 81 #include <cam/cam_xpt_periph.h> 82 #include <cam/cam_periph.h> 83 #include <cam/scsi/scsi_all.h> 84 #include <cam/scsi/scsi_message.h> 85 86 #include <cam/scsi/smp_all.h> 87 #include <sys/queue.h> 88 #include <sys/kthread.h> 89 #include "mpi/mpi30_api.h" 90 91 #define MPI3MR_DRIVER_VERSION "8.6.0.2.0" 92 #define MPI3MR_DRIVER_RELDATE "17th May 2023" 93 94 #define MPI3MR_DRIVER_NAME "mpi3mr" 95 96 #define MPI3MR_NAME_LENGTH 32 97 #define IOCNAME "%s: " 98 99 #define SAS4116_CHIP_REV_A0 0 100 #define SAS4116_CHIP_REV_B0 1 101 102 #define MPI3MR_SG_DEPTH (MPI3MR_4K_PGSZ/sizeof(Mpi3SGESimple_t)) 103 #define MPI3MR_MAX_SECTORS 2048 104 #define MPI3MR_MAX_CMDS_LUN 7 105 #define MPI3MR_MAX_CDB_LENGTH 16 106 #define MPI3MR_MAX_LUN 16895 107 108 #define MPI3MR_SATA_QDEPTH 32 109 #define MPI3MR_SAS_QDEPTH 64 110 #define MPI3MR_RAID_QDEPTH 128 111 #define MPI3MR_NVME_QDEPTH 128 112 113 #define MPI3MR_4K_PGSZ 4096 114 #define MPI3MR_AREQQ_SIZE (2 * MPI3MR_4K_PGSZ) 115 #define MPI3MR_AREPQ_SIZE (4 * MPI3MR_4K_PGSZ) 116 #define MPI3MR_AREQ_FRAME_SZ 128 117 #define MPI3MR_AREP_FRAME_SZ 16 118 119 #define MPI3MR_OPREQQ_SIZE (8 * MPI3MR_4K_PGSZ) 120 #define MPI3MR_OPREPQ_SIZE (4 * MPI3MR_4K_PGSZ) 121 122 /* Operational queue management definitions */ 123 #define MPI3MR_OP_REQ_Q_QD 512 124 #define MPI3MR_OP_REP_Q_QD 1024 125 #define MPI3MR_OP_REP_Q_QD_A0 4096 126 127 #define MPI3MR_CHAINSGE_SIZE MPI3MR_4K_PGSZ 128 129 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 130 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 131 MPI3_SGE_FLAGS_END_OF_LIST) 132 133 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 134 #define MPI3MR_HOSTTAG_INITCMDS 1 135 #define MPI3MR_HOSTTAG_IOCTLCMDS 2 136 #define MPI3MR_HOSTTAG_PELABORT 3 137 #define MPI3MR_HOSTTAG_PELWAIT 4 138 #define MPI3MR_HOSTTAG_TMS 5 139 140 #define MAX_MGMT_ADAPTERS 8 141 #define MPI3MR_WAIT_BEFORE_CTRL_RESET 5 142 143 144 struct mpi3mr_mgmt_info { 145 uint16_t count; 146 struct mpi3mr_softc *sc_ptr[MAX_MGMT_ADAPTERS]; 147 int max_index; 148 }; 149 150 extern char fmt_os_ver[16]; 151 152 #define MPI3MR_OS_VERSION(raw_os_ver, fmt_os_ver) sprintf(raw_os_ver, "%d", __FreeBSD_version); \ 153 sprintf(fmt_os_ver, "%c%c.%c%c.%c%c%c",\ 154 raw_os_ver[0], raw_os_ver[1], raw_os_ver[2],\ 155 raw_os_ver[3], raw_os_ver[4], raw_os_ver[5],\ 156 raw_os_ver[6]); 157 #define MPI3MR_NUM_DEVRMCMD 1 158 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TMS + 1) 159 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 160 MPI3MR_NUM_DEVRMCMD - 1) 161 #define MPI3MR_INTERNALCMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 162 163 #define MPI3MR_NUM_EVTACKCMD 4 164 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 165 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 166 MPI3MR_NUM_EVTACKCMD - 1) 167 168 /* command/controller interaction timeout definitions in seconds */ 169 #define MPI3MR_INTADMCMD_TIMEOUT 60 170 #define MPI3MR_PORTENABLE_TIMEOUT 300 171 #define MPI3MR_ABORTTM_TIMEOUT 60 172 #define MPI3MR_RESETTM_TIMEOUT 60 173 #define MPI3MR_TSUPDATE_INTERVAL 900 174 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 175 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 176 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 177 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 178 #define MPI3MR_RESET_ACK_TIMEOUT 30 179 #define MPI3MR_MUR_TIMEOUT 120 180 181 #define MPI3MR_CMD_NOTUSED 0x8000 182 #define MPI3MR_CMD_COMPLETE 0x0001 183 #define MPI3MR_CMD_PENDING 0x0002 184 #define MPI3MR_CMD_REPLYVALID 0x0004 185 #define MPI3MR_CMD_RESET 0x0008 186 187 #define MPI3MR_NUM_EVTREPLIES 64 188 #define MPI3MR_SENSEBUF_SZ 256 189 #define MPI3MR_SENSEBUF_FACTOR 3 190 #define MPI3MR_CHAINBUF_FACTOR 3 191 192 #define MPT3SAS_HOSTPGSZ_4KEXP 12 193 194 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 195 196 /* Controller Reset related definitions */ 197 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 198 #define MPI3MR_MAX_SHUTDOWN_RETRY_COUNT 2 199 200 /* ResponseCode values */ 201 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 202 #define MPI3MR_RSP_TM_COMPLETE 0x00 203 #define MPI3MR_RSP_INVALID_FRAME 0x02 204 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04 205 #define MPI3MR_RSP_TM_FAILED 0x05 206 #define MPI3MR_RSP_TM_SUCCEEDED 0x08 207 #define MPI3MR_RSP_TM_INVALID_LUN 0x09 208 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A 209 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 210 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 211 212 /* Definitions for the controller security status*/ 213 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 214 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 215 216 #define MPI3MR_INVALID_DEVICE 0x00 217 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 218 #define MPI3MR_HARD_SECURE_DEVICE 0x08 219 #define MPI3MR_TAMPERED_DEVICE 0x0C 220 221 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 222 #define MPI3MR_DEFAULT_PGSZEXP (12) 223 #define MPI3MR_MAX_IOCTL_TRANSFER_SIZE (1024 * 1024) 224 225 #define MPI3MR_DEVRMHS_RETRYCOUNT 3 226 #define MPI3MR_PELCMDS_RETRYCOUNT 3 227 228 #define MPI3MR_PERIODIC_DELAY 1 /* 1 second heartbeat/watchdog check */ 229 230 struct completion { 231 unsigned int done; 232 struct mtx lock; 233 }; 234 235 typedef union { 236 volatile unsigned int val; 237 unsigned int val_rdonly; 238 } mpi3mr_atomic_t; 239 240 #define mpi3mr_atomic_read(v) atomic_load_acq_int(&(v)->val) 241 #define mpi3mr_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 242 #define mpi3mr_atomic_dec(v) atomic_subtract_int(&(v)->val, 1) 243 #define mpi3mr_atomic_inc(v) atomic_add_int(&(v)->val, 1) 244 #define mpi3mr_atomic_add(v, u) atomic_add_int(&(v)->val, u) 245 #define mpi3mr_atomic_sub(v, u) atomic_subtract_int(&(v)->val, u) 246 247 /* IOCTL data transfer sge*/ 248 #define MPI3MR_NUM_IOCTL_SGE 256 249 #define MPI3MR_IOCTL_SGE_SIZE (8 * 1024) 250 251 struct dma_memory_desc { 252 U32 size; 253 void *addr; 254 bus_dma_tag_t tag; 255 bus_dmamap_t dmamap; 256 bus_addr_t dma_addr; 257 }; 258 259 enum mpi3mr_iocstate { 260 MRIOC_STATE_READY = 1, 261 MRIOC_STATE_RESET, 262 MRIOC_STATE_FAULT, 263 MRIOC_STATE_BECOMING_READY, 264 MRIOC_STATE_RESET_REQUESTED, 265 MRIOC_STATE_UNRECOVERABLE, 266 MRIOC_STATE_COUNT, 267 }; 268 269 /* Init type definitions */ 270 enum mpi3mr_init_type { 271 MPI3MR_INIT_TYPE_INIT = 0, 272 MPI3MR_INIT_TYPE_RESET, 273 MPI3MR_INIT_TYPE_RESUME, 274 }; 275 276 /* Reset reason code definitions*/ 277 enum mpi3mr_reset_reason { 278 MPI3MR_RESET_FROM_BRINGUP = 1, 279 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 280 MPI3MR_RESET_FROM_IOCTL = 3, 281 MPI3MR_RESET_FROM_EH_HOS = 4, 282 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 283 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6, 284 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 285 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 286 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 287 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 288 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 289 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 290 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 291 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 292 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 293 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 294 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 295 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 296 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 297 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 298 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 299 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 300 MPI3MR_RESET_FROM_SYSFS = 23, 301 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 302 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25, 303 MPI3MR_RESET_FROM_SCSIIO_TIMEOUT = 26, 304 MPI3MR_RESET_FROM_FIRMWARE = 27, 305 MPI3MR_DEFAULT_RESET_REASON = 28, 306 MPI3MR_RESET_REASON_COUNT, 307 }; 308 309 struct mpi3mr_compimg_ver 310 { 311 U16 build_num; 312 U16 cust_id; 313 U8 ph_minor; 314 U8 ph_major; 315 U8 gen_minor; 316 U8 gen_major; 317 }; 318 319 struct mpi3mr_ioc_facts 320 { 321 U32 ioc_capabilities; 322 struct mpi3mr_compimg_ver fw_ver; 323 U32 mpi_version; 324 U16 max_reqs; 325 U16 product_id; 326 U16 op_req_sz; 327 U16 reply_sz; 328 U16 exceptions; 329 U16 max_perids; 330 U16 max_pds; 331 U16 max_sasexpanders; 332 U16 max_sasinitiators; 333 U16 max_enclosures; 334 U16 max_pcieswitches; 335 U16 max_nvme; 336 U16 max_vds; 337 U16 max_hpds; 338 U16 max_advhpds; 339 U16 max_raidpds; 340 U16 min_devhandle; 341 U16 max_devhandle; 342 U16 max_op_req_q; 343 U16 max_op_reply_q; 344 U16 shutdown_timeout; 345 U8 ioc_num; 346 U8 who_init; 347 U16 max_msix_vectors; 348 U8 personality; 349 U8 dma_mask; 350 U8 protocol_flags; 351 U8 sge_mod_mask; 352 U8 sge_mod_value; 353 U8 sge_mod_shift; 354 U8 max_dev_per_tg; 355 U16 max_io_throttle_group; 356 U16 io_throttle_data_length; 357 U16 io_throttle_low; 358 U16 io_throttle_high; 359 }; 360 361 struct mpi3mr_op_req_queue { 362 U16 ci; 363 U16 pi; 364 U16 num_reqs; 365 U8 qid; 366 U8 reply_qid; 367 U32 qsz; 368 void *q_base; 369 bus_dma_tag_t q_base_tag; 370 bus_dmamap_t q_base_dmamap; 371 bus_addr_t q_base_phys; 372 struct mtx q_lock; 373 }; 374 375 struct mpi3mr_op_reply_queue { 376 U16 ci; 377 U8 ephase; 378 U8 qid; 379 U16 num_replies; 380 U32 qsz; 381 bus_dma_tag_t q_base_tag; 382 bus_dmamap_t q_base_dmamap; 383 void *q_base; 384 bus_addr_t q_base_phys; 385 mpi3mr_atomic_t pend_ios; 386 bool in_use; 387 struct mtx q_lock; 388 }; 389 390 struct irq_info { 391 MPI3_REPLY_DESCRIPTORS_UNION *post_queue; 392 bus_dma_tag_t buffer_dmat; 393 struct resource *irq; 394 void *intrhand; 395 int irq_rid; 396 }; 397 398 struct mpi3mr_irq_context { 399 struct mpi3mr_softc *sc; 400 U16 msix_index; 401 struct mpi3mr_op_reply_queue *op_reply_q; 402 char name[MPI3MR_NAME_LENGTH]; 403 struct irq_info irq_info; 404 }; 405 406 MALLOC_DECLARE(M_MPI3MR); 407 SYSCTL_DECL(_hw_mpi3mr); 408 409 typedef struct mpi3mr_drvr_cmd DRVR_CMD; 410 typedef void (*DRVR_CMD_CALLBACK)(struct mpi3mr_softc *mrioc, DRVR_CMD *drvrcmd); 411 struct mpi3mr_drvr_cmd { 412 struct mtx lock; 413 struct completion completion; 414 void *reply; 415 U8 *sensebuf; 416 U8 iou_rc; 417 U16 state; 418 U16 dev_handle; 419 U16 ioc_status; 420 U32 ioc_loginfo; 421 U8 is_waiting; 422 U8 is_senseprst; 423 U8 retry_count; 424 U16 host_tag; 425 DRVR_CMD_CALLBACK callback; 426 }; 427 428 struct mpi3mr_cmd; 429 typedef void mpi3mr_evt_callback_t(struct mpi3mr_softc *, uintptr_t, 430 Mpi3EventNotificationReply_t *reply); 431 typedef void mpi3mr_cmd_callback_t(struct mpi3mr_softc *, 432 struct mpi3mr_cmd *cmd); 433 434 #define MPI3MR_IOVEC_COUNT 2 435 436 enum mpi3mr_data_xfer_direction { 437 MPI3MR_READ = 1, 438 MPI3MR_WRITE, 439 }; 440 441 enum mpi3mr_cmd_state { 442 MPI3MR_CMD_STATE_FREE = 1, 443 MPI3MR_CMD_STATE_BUSY, 444 MPI3MR_CMD_STATE_IN_QUEUE, 445 MPI3MR_CMD_STATE_IN_TM, 446 }; 447 448 enum mpi3mr_target_state { 449 MPI3MR_DEV_CREATED = 1, 450 MPI3MR_DEV_REMOVE_HS_STARTED = 2, 451 MPI3MR_DEV_DELETED = 3, 452 }; 453 454 struct mpi3mr_cmd { 455 TAILQ_ENTRY(mpi3mr_cmd) next; 456 struct mpi3mr_softc *sc; 457 union ccb *ccb; 458 void *data; 459 u_int length; 460 u_int out_len; 461 struct uio uio; 462 struct iovec iovec[MPI3MR_IOVEC_COUNT]; 463 u_int max_segs; 464 struct mpi3mr_target *targ; 465 u_int lun; 466 u_int data_dir; 467 u_int state; 468 bus_dmamap_t dmamap; 469 struct scsi_sense_data *sense; 470 struct callout callout; 471 bool callout_owner; 472 mpi3mr_cmd_callback_t *timeout_handler; 473 U16 hosttag; 474 U8 req_qidx; 475 Mpi3SCSIIORequest_t io_request; 476 int error_code; 477 }; 478 479 struct mpi3mr_chain { 480 bus_dmamap_t buf_dmamap; 481 void *buf; 482 bus_addr_t buf_phys; 483 }; 484 485 struct mpi3mr_event_handle { 486 TAILQ_ENTRY(mpi3mr_event_handle) eh_list; 487 mpi3mr_evt_callback_t *callback; 488 void *data; 489 uint8_t mask[16]; 490 }; 491 492 struct mpi3mr_fw_event_work { 493 U16 event; 494 void *event_data; 495 TAILQ_ENTRY(mpi3mr_fw_event_work) ev_link; 496 U8 send_ack; 497 U8 process_event; 498 U32 event_context; 499 U16 event_data_size; 500 }; 501 502 /** 503 * struct delayed_dev_rmhs_node - Delayed device removal node 504 * 505 * @list: list head 506 * @handle: Device handle 507 * @iou_rc: IO Unit Control Reason Code 508 */ 509 struct delayed_dev_rmhs_node { 510 TAILQ_ENTRY(delayed_dev_rmhs_node) list; 511 U16 handle; 512 U8 iou_rc; 513 }; 514 515 /** 516 * struct delayed_evtack_node - Delayed event ack node 517 * 518 * @list: list head 519 * @event: MPI3 event ID 520 * @event_ctx: Event context 521 */ 522 struct delayed_evtack_node { 523 TAILQ_ENTRY(delayed_evtack_node) list; 524 U8 event; 525 U32 event_ctx; 526 }; 527 528 /* Reset types */ 529 enum reset_type { 530 MPI3MR_NO_RESET, 531 MPI3MR_TRIGGER_SOFT_RESET, 532 }; 533 534 struct mpi3mr_reset { 535 u_int type; 536 U32 reason; 537 int status; 538 bool ioctl_reset_snapdump; 539 }; 540 541 struct mpi3mr_softc { 542 device_t mpi3mr_dev; 543 struct cdev *mpi3mr_cdev; 544 u_int mpi3mr_flags; 545 #define MPI3MR_FLAGS_SHUTDOWN (1 << 0) 546 #define MPI3MR_FLAGS_DIAGRESET (1 << 1) 547 #define MPI3MR_FLAGS_ATTACH_DONE (1 << 2) 548 #define MPI3MR_FLAGS_PORT_ENABLE_DONE (1 << 3) 549 U8 id; 550 int cpu_count; 551 char name[MPI3MR_NAME_LENGTH]; 552 char driver_name[MPI3MR_NAME_LENGTH]; 553 int bars; 554 int dma_mask; 555 u_int mpi3mr_debug; 556 struct mpi3mr_reset reset; 557 int max_msix_vectors; 558 int msix_count; 559 bool msix_enable; 560 int io_cmds_highwater; 561 int max_chains; 562 uint32_t chain_frame_size; 563 struct sysctl_ctx_list sysctl_ctx; 564 struct sysctl_oid *sysctl_tree; 565 char fw_version[16]; 566 char msg_version[8]; 567 struct mpi3mr_chain *chains; 568 struct callout periodic; 569 struct callout device_check_callout; 570 571 struct mpi3mr_cam_softc *cam_sc; 572 struct mpi3mr_cmd **cmd_list; 573 TAILQ_HEAD(, mpi3mr_cmd) cmd_list_head; 574 struct mtx cmd_pool_lock; 575 576 struct resource *mpi3mr_regs_resource; 577 bus_space_handle_t mpi3mr_bhandle; 578 bus_space_tag_t mpi3mr_btag; 579 int mpi3mr_regs_rid; 580 581 bus_dma_tag_t mpi3mr_parent_dmat; 582 bus_dma_tag_t buffer_dmat; 583 584 int num_reqs; 585 int num_replies; 586 int num_chains; 587 588 TAILQ_HEAD(, mpi3mr_event_handle) event_list; 589 struct mpi3mr_event_handle *mpi3mr_log_eh; 590 struct intr_config_hook mpi3mr_ich; 591 592 struct mtx mpi3mr_mtx; 593 struct mtx io_lock; 594 U8 intr_enabled; 595 TAILQ_HEAD(, delayed_dev_rmhs_node) delayed_rmhs_list; 596 TAILQ_HEAD(, delayed_evtack_node) delayed_evtack_cmds_list; 597 598 U16 num_admin_reqs; 599 U32 admin_req_q_sz; 600 U16 admin_req_pi; 601 U16 admin_req_ci; 602 bus_dma_tag_t admin_req_tag; 603 bus_dmamap_t admin_req_dmamap; 604 bus_addr_t admin_req_phys; 605 U8 *admin_req; 606 struct mtx admin_req_lock; 607 608 U16 num_admin_replies; 609 U32 admin_reply_q_sz; 610 U16 admin_reply_ci; 611 U8 admin_reply_ephase; 612 bus_dma_tag_t admin_reply_tag; 613 bus_dmamap_t admin_reply_dmamap; 614 bus_addr_t admin_reply_phys; 615 U8 *admin_reply; 616 struct mtx admin_reply_lock; 617 bool admin_in_use; 618 619 U32 num_reply_bufs; 620 bus_dma_tag_t reply_buf_tag; 621 bus_dmamap_t reply_buf_dmamap; 622 bus_addr_t reply_buf_phys; 623 U8 *reply_buf; 624 bus_addr_t reply_buf_dma_max_address; 625 bus_addr_t reply_buf_dma_min_address; 626 627 U16 reply_free_q_sz; 628 bus_dma_tag_t reply_free_q_tag; 629 bus_dmamap_t reply_free_q_dmamap; 630 bus_addr_t reply_free_q_phys; 631 U64 *reply_free_q; 632 struct mtx reply_free_q_lock; 633 U32 reply_free_q_host_index; 634 635 U32 num_sense_bufs; 636 bus_dma_tag_t sense_buf_tag; 637 bus_dmamap_t sense_buf_dmamap; 638 bus_addr_t sense_buf_phys; 639 U8 *sense_buf; 640 641 U16 sense_buf_q_sz; 642 bus_dma_tag_t sense_buf_q_tag; 643 bus_dmamap_t sense_buf_q_dmamap; 644 bus_addr_t sense_buf_q_phys; 645 U64 *sense_buf_q; 646 struct mtx sense_buf_q_lock; 647 U32 sense_buf_q_host_index; 648 649 void *nvme_encap_prp_list; 650 bus_addr_t nvme_encap_prp_list_dma; 651 bus_dma_tag_t nvme_encap_prp_list_dmatag; 652 bus_dmamap_t nvme_encap_prp_list_dma_dmamap; 653 U32 nvme_encap_prp_sz; 654 655 U32 ready_timeout; 656 657 struct mpi3mr_irq_context *irq_ctx; 658 659 U16 num_queues; /* Number of request/reply queues */ 660 struct mpi3mr_op_req_queue *op_req_q; 661 struct mpi3mr_op_reply_queue *op_reply_q; 662 U16 num_hosttag_op_req_q; 663 664 struct mpi3mr_drvr_cmd init_cmds; 665 struct mpi3mr_ioc_facts facts; 666 U16 reply_sz; 667 U16 op_reply_sz; 668 669 U32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 670 671 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 672 struct workqueue_struct *fwevt_worker_thread; 673 struct mtx fwevt_lock; 674 struct mtx target_lock; 675 676 U16 max_host_ios; 677 bus_dma_tag_t chain_sgl_list_tag; 678 struct mpi3mr_chain *chain_sgl_list; 679 U16 chain_bitmap_sz; 680 void *chain_bitmap; 681 struct mtx chain_buf_lock; 682 U16 chain_buf_count; 683 684 struct mpi3mr_drvr_cmd ioctl_cmds; 685 struct mpi3mr_drvr_cmd host_tm_cmds; 686 struct mpi3mr_drvr_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 687 struct mpi3mr_drvr_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 688 689 U16 devrem_bitmap_sz; 690 void *devrem_bitmap; 691 692 U16 dev_handle_bitmap_sz; 693 void *removepend_bitmap; 694 695 U16 evtack_cmds_bitmap_sz; 696 void *evtack_cmds_bitmap; 697 698 U32 ts_update_counter; 699 U8 reset_in_progress; 700 U8 unrecoverable; 701 U8 block_ioctls; 702 U8 in_prep_ciactv_rst; 703 U16 prep_ciactv_rst_counter; 704 struct mtx reset_mutex; 705 706 U8 prepare_for_reset; 707 U16 prepare_for_reset_timeout_counter; 708 709 U16 diagsave_timeout; 710 int logging_level; 711 U16 flush_io_count; 712 713 Mpi3DriverInfoLayout_t driver_info; 714 715 U16 change_count; 716 717 U8 *log_data_buffer; 718 U16 log_data_buffer_index; 719 U16 log_data_entry_size; 720 721 U8 pel_wait_pend; 722 U8 pel_abort_requested; 723 U8 pel_class; 724 U16 pel_locale; 725 726 struct mpi3mr_drvr_cmd pel_cmds; 727 struct mpi3mr_drvr_cmd pel_abort_cmd; 728 U32 newest_seqnum; 729 void *pel_seq_number; 730 bus_addr_t pel_seq_number_dma; 731 bus_dma_tag_t pel_seq_num_dmatag; 732 bus_dmamap_t pel_seq_num_dmamap; 733 U32 pel_seq_number_sz; 734 735 struct selinfo mpi3mr_select; 736 U32 mpi3mr_poll_waiting; 737 U32 mpi3mr_aen_triggered; 738 739 U16 wait_for_port_enable; 740 U16 track_mapping_events; 741 U16 pending_map_events; 742 mpi3mr_atomic_t fw_outstanding; 743 mpi3mr_atomic_t pend_ioctls; 744 struct proc *watchdog_thread; 745 void *watchdog_chan; 746 void *tm_chan; 747 u_int8_t remove_in_progress; 748 u_int8_t watchdog_thread_active; 749 u_int8_t do_timedout_reset; 750 bool allow_ios; 751 bool secure_ctrl; 752 mpi3mr_atomic_t pend_large_data_sz; 753 754 u_int32_t io_throttle_data_length; 755 u_int32_t io_throttle_high; 756 u_int32_t io_throttle_low; 757 u_int16_t num_io_throttle_group; 758 u_int iot_enable; 759 struct mpi3mr_throttle_group_info *throttle_groups; 760 761 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE]; 762 struct dma_memory_desc ioctl_chain_sge; 763 struct dma_memory_desc ioctl_resp_sge; 764 bool ioctl_sges_allocated; 765 }; 766 767 static __inline uint64_t 768 mpi3mr_regread64(struct mpi3mr_softc *sc, uint32_t offset) 769 { 770 return bus_space_read_8(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset); 771 } 772 773 static __inline void 774 mpi3mr_regwrite64(struct mpi3mr_softc *sc, uint32_t offset, uint64_t val) 775 { 776 bus_space_write_8(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset, val); 777 } 778 779 static __inline uint32_t 780 mpi3mr_regread(struct mpi3mr_softc *sc, uint32_t offset) 781 { 782 return bus_space_read_4(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset); 783 } 784 785 static __inline void 786 mpi3mr_regwrite(struct mpi3mr_softc *sc, uint32_t offset, uint32_t val) 787 { 788 bus_space_write_4(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset, val); 789 } 790 791 #define MPI3MR_INFO (1 << 0) /* Basic info */ 792 #define MPI3MR_FAULT (1 << 1) /* Hardware faults */ 793 #define MPI3MR_EVENT (1 << 2) /* Event data from the controller */ 794 #define MPI3MR_LOG (1 << 3) /* Log data from the controller */ 795 #define MPI3MR_RECOVERY (1 << 4) /* Command error recovery tracing */ 796 #define MPI3MR_ERROR (1 << 5) /* Fatal driver/OS APIs failure */ 797 #define MPI3MR_XINFO (1 << 6) /* Additional info logs*/ 798 #define MPI3MR_TRACE (1 << 7) /* Trace functions */ 799 #define MPI3MR_IOT (1 << 8) /* IO throttling related debugs */ 800 #define MPI3MR_DEBUG_TM (1 << 9) /* Task management related debugs */ 801 #define MPI3MR_DEBUG_IOCTL (1 << 10) /* IOCTL related debugs */ 802 803 #define mpi3mr_printf(sc, args...) \ 804 device_printf((sc)->mpi3mr_dev, ##args) 805 806 #define mpi3mr_print_field(sc, msg, args...) \ 807 printf("\t" msg, ##args) 808 809 #define mpi3mr_vprintf(sc, args...) \ 810 do { \ 811 if (bootverbose) \ 812 mpi3mr_printf(sc, ##args); \ 813 } while (0) 814 815 #define mpi3mr_dprint(sc, level, msg, args...) \ 816 do { \ 817 if ((sc)->mpi3mr_debug & (level)) \ 818 device_printf((sc)->mpi3mr_dev, msg, ##args); \ 819 } while (0) 820 821 #define MPI3MR_PRINTFIELD_START(sc, tag...) \ 822 mpi3mr_printf((sc), ##tag); \ 823 mpi3mr_print_field((sc), ":\n") 824 #define MPI3MR_PRINTFIELD_END(sc, tag) \ 825 mpi3mr_printf((sc), tag "\n") 826 #define MPI3MR_PRINTFIELD(sc, facts, attr, fmt) \ 827 mpi3mr_print_field((sc), #attr ": " #fmt "\n", (facts)->attr) 828 829 #define mpi3mr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 830 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 831 #define mpi3mr_kproc_exit(arg) kproc_exit(arg) 832 833 #if defined(CAM_PRIORITY_XPT) 834 #define MPI3MR_PRIORITY_XPT CAM_PRIORITY_XPT 835 #else 836 #define MPI3MR_PRIORITY_XPT 5 837 #endif 838 839 static __inline void 840 mpi3mr_clear_bit(int b, volatile void *p) 841 { 842 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 843 } 844 845 static __inline void 846 mpi3mr_set_bit(int b, volatile void *p) 847 { 848 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 849 } 850 851 static __inline int 852 mpi3mr_test_bit(int b, volatile void *p) 853 { 854 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 855 } 856 857 static __inline int 858 mpi3mr_test_and_set_bit(int b, volatile void *p) 859 { 860 int ret = ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 861 862 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 863 return ret; 864 } 865 866 static __inline int 867 mpi3mr_find_first_zero_bit(void *p, int bit_count) 868 { 869 int i, sz, j=0; 870 U8 *loc; 871 872 sz = bit_count % 8 ? (bit_count / 8 + 1) : (bit_count / 8); 873 loc = malloc(sz, M_MPI3MR, M_NOWAIT | M_ZERO); 874 875 memcpy(loc, p, sz); 876 877 for (i = 0; i < sz; i++) { 878 j = 0; 879 while (j < 8) { 880 if (!((loc[i] >> j) & 0x1)) 881 goto out; 882 j++; 883 } 884 } 885 out: 886 free(loc, M_MPI3MR); 887 return (i + j); 888 } 889 890 #define MPI3MR_DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) 891 892 void 893 init_completion(struct completion *completion); 894 895 void 896 complete(struct completion *completion); 897 898 void wait_for_completion_timeout(struct completion *completion, 899 U32 timeout); 900 void wait_for_completion_timeout_tm(struct completion *completion, 901 U32 timeout, struct mpi3mr_softc *sc); 902 void mpi3mr_add_sg_single(void *paddr, U8 flags, U32 length, 903 bus_addr_t dma_addr); 904 void mpi3mr_enable_interrupts(struct mpi3mr_softc *sc); 905 void mpi3mr_disable_interrupts(struct mpi3mr_softc *sc); 906 void mpi3mr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 907 int mpi3mr_submit_admin_cmd(struct mpi3mr_softc *mrioc, void *admin_req, 908 U16 admin_req_sz); 909 int mpi3mr_submit_io(struct mpi3mr_softc *mrioc, 910 struct mpi3mr_op_req_queue *op_req_q, U8 *req); 911 int 912 mpi3mr_alloc_interrupts(struct mpi3mr_softc *sc, U16 setup_one); 913 914 void mpi3mr_cleanup_ioc(struct mpi3mr_softc *sc); 915 int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 reason); 916 void mpi3mr_build_zero_len_sge(void *paddr); 917 int mpi3mr_issue_event_notification(struct mpi3mr_softc *sc); 918 int 919 mpi3mr_register_events(struct mpi3mr_softc *sc); 920 void mpi3mr_process_op_reply_desc(struct mpi3mr_softc *sc, 921 Mpi3DefaultReplyDescriptor_t *reply_desc, U64 *reply_dma); 922 struct mpi3mr_cmd * 923 mpi3mr_get_command(struct mpi3mr_softc *sc); 924 void 925 mpi3mr_release_command(struct mpi3mr_cmd *cmd); 926 int 927 mpi3mr_complete_io_cmd(struct mpi3mr_softc *sc, 928 struct mpi3mr_irq_context *irq_context); 929 int 930 mpi3mr_cam_detach(struct mpi3mr_softc *sc); 931 int 932 mpi3mr_cam_attach(struct mpi3mr_softc *sc); 933 struct mpi3mr_target * 934 mpi3mr_find_target_by_per_id(struct mpi3mr_cam_softc *cam_sc, 935 uint16_t per_id); 936 struct mpi3mr_target * 937 mpi3mr_find_target_by_dev_handle(struct mpi3mr_cam_softc *cam_sc, 938 uint16_t dev_handle); 939 int mpi3mr_create_device(struct mpi3mr_softc *sc, 940 Mpi3DevicePage0_t *dev_pg0); 941 void 942 mpi3mr_unmap_request(struct mpi3mr_softc *sc, struct mpi3mr_cmd *cmd); 943 void 944 init_completion(struct completion *completion); 945 void 946 complete(struct completion *completion); 947 void wait_for_completion_timeout(struct completion *completion, 948 U32 timeout); 949 void 950 poll_for_command_completion(struct mpi3mr_softc *sc, 951 struct mpi3mr_drvr_cmd *cmd, U16 wait); 952 int 953 mpi3mr_alloc_requests(struct mpi3mr_softc *sc); 954 void 955 mpi3mr_watchdog(void *arg); 956 int mpi3mr_issue_port_enable(struct mpi3mr_softc *mrioc, U8 async); 957 void 958 mpi3mr_isr(void *privdata); 959 int 960 mpi3mr_alloc_msix_queues(struct mpi3mr_softc *sc); 961 void 962 mpi3mr_destory_mtx(struct mpi3mr_softc *sc); 963 void 964 mpi3mr_free_mem(struct mpi3mr_softc *sc); 965 void 966 mpi3mr_cleanup_interrupts(struct mpi3mr_softc *sc); 967 int mpi3mr_setup_irqs(struct mpi3mr_softc *sc); 968 void mpi3mr_cleanup_event_taskq(struct mpi3mr_softc *sc); 969 void 970 mpi3mr_hexdump(void *buf, int sz, int format); 971 int mpi3mr_soft_reset_handler(struct mpi3mr_softc *sc, 972 U32 reset_reason, bool snapdump); 973 void 974 mpi3mrsas_release_simq_reinit(struct mpi3mr_cam_softc *cam_sc); 975 void 976 mpi3mr_watchdog_thread(void *arg); 977 void mpi3mr_add_device(struct mpi3mr_softc *sc, U16 per_id); 978 int mpi3mr_remove_device(struct mpi3mr_softc *sc, U16 handle); 979 int 980 mpi3mrsas_register_events(struct mpi3mr_softc *sc); 981 int mpi3mr_process_event_ack(struct mpi3mr_softc *sc, U8 event, 982 U32 event_ctx); 983 int mpi3mr_remove_device_from_os(struct mpi3mr_softc *sc, U16 handle); 984 void mpi3mr_remove_device_from_list(struct mpi3mr_softc *sc, struct mpi3mr_target *target, 985 bool must_delete); 986 void mpi3mr_update_device(struct mpi3mr_softc *mrioc, 987 struct mpi3mr_target *tgtdev, Mpi3DevicePage0_t *dev_pg0, bool is_added); 988 void mpi3mr_app_save_logdata(struct mpi3mr_softc *sc, char *event_data, U16 event_data_size); 989 void mpi3mr_set_io_divert_for_all_vd_in_tg(struct mpi3mr_softc *sc, 990 struct mpi3mr_throttle_group_info *tg, U8 divert_value); 991 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_softc *sc); 992 void mpi3mr_poll_pend_io_completions(struct mpi3mr_softc *sc); 993 void int_to_lun(unsigned int lun, U8 *req_lun); 994 void trigger_reset_from_watchdog(struct mpi3mr_softc *sc, U8 reset_type, U32 reset_reason); 995 void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_softc *sc); 996 #endif /*MPI3MR_H_INCLUDED*/ 997