1 /*- 2 * Copyright (c) 2009 Yahoo! Inc. 3 * Copyright (c) 2011-2015 LSI Corp. 4 * Copyright (c) 2013-2016 Avago Technologies 5 * Copyright 2000-2020 Broadcom Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* Communications core for Avago Technologies (LSI) MPT3 */ 37 38 /* TODO Move headers to mprvar */ 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/selinfo.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 #include <sys/module.h> 47 #include <sys/bus.h> 48 #include <sys/conf.h> 49 #include <sys/bio.h> 50 #include <sys/malloc.h> 51 #include <sys/uio.h> 52 #include <sys/sysctl.h> 53 #include <sys/smp.h> 54 #include <sys/queue.h> 55 #include <sys/kthread.h> 56 #include <sys/taskqueue.h> 57 #include <sys/endian.h> 58 #include <sys/eventhandler.h> 59 #include <sys/sbuf.h> 60 #include <sys/priv.h> 61 62 #include <machine/bus.h> 63 #include <machine/resource.h> 64 #include <sys/rman.h> 65 #include <sys/proc.h> 66 67 #include <dev/pci/pcivar.h> 68 69 #include <cam/cam.h> 70 #include <cam/cam_ccb.h> 71 #include <cam/scsi/scsi_all.h> 72 73 #include <dev/mpr/mpi/mpi2_type.h> 74 #include <dev/mpr/mpi/mpi2.h> 75 #include <dev/mpr/mpi/mpi2_ioc.h> 76 #include <dev/mpr/mpi/mpi2_sas.h> 77 #include <dev/mpr/mpi/mpi2_pci.h> 78 #include <dev/mpr/mpi/mpi2_cnfg.h> 79 #include <dev/mpr/mpi/mpi2_init.h> 80 #include <dev/mpr/mpi/mpi2_tool.h> 81 #include <dev/mpr/mpr_ioctl.h> 82 #include <dev/mpr/mprvar.h> 83 #include <dev/mpr/mpr_table.h> 84 #include <dev/mpr/mpr_sas.h> 85 86 static int mpr_diag_reset(struct mpr_softc *sc, int sleep_flag); 87 static int mpr_init_queues(struct mpr_softc *sc); 88 static void mpr_resize_queues(struct mpr_softc *sc); 89 static int mpr_message_unit_reset(struct mpr_softc *sc, int sleep_flag); 90 static int mpr_transition_operational(struct mpr_softc *sc); 91 static int mpr_iocfacts_allocate(struct mpr_softc *sc, uint8_t attaching); 92 static void mpr_iocfacts_free(struct mpr_softc *sc); 93 static void mpr_startup(void *arg); 94 static int mpr_send_iocinit(struct mpr_softc *sc); 95 static int mpr_alloc_queues(struct mpr_softc *sc); 96 static int mpr_alloc_hw_queues(struct mpr_softc *sc); 97 static int mpr_alloc_replies(struct mpr_softc *sc); 98 static int mpr_alloc_requests(struct mpr_softc *sc); 99 static int mpr_alloc_nvme_prp_pages(struct mpr_softc *sc); 100 static int mpr_attach_log(struct mpr_softc *sc); 101 static __inline void mpr_complete_command(struct mpr_softc *sc, 102 struct mpr_command *cm); 103 static void mpr_dispatch_event(struct mpr_softc *sc, uintptr_t data, 104 MPI2_EVENT_NOTIFICATION_REPLY *reply); 105 static void mpr_config_complete(struct mpr_softc *sc, struct mpr_command *cm); 106 static void mpr_periodic(void *); 107 static int mpr_reregister_events(struct mpr_softc *sc); 108 static void mpr_enqueue_request(struct mpr_softc *sc, struct mpr_command *cm); 109 static int mpr_get_iocfacts(struct mpr_softc *sc, MPI2_IOC_FACTS_REPLY *facts); 110 static int mpr_wait_db_ack(struct mpr_softc *sc, int timeout, int sleep_flag); 111 static int mpr_debug_sysctl(SYSCTL_HANDLER_ARGS); 112 static int mpr_dump_reqs(SYSCTL_HANDLER_ARGS); 113 static void mpr_parse_debug(struct mpr_softc *sc, char *list); 114 115 SYSCTL_NODE(_hw, OID_AUTO, mpr, CTLFLAG_RD, 0, "MPR Driver Parameters"); 116 117 MALLOC_DEFINE(M_MPR, "mpr", "mpr driver memory"); 118 119 /* 120 * Do a "Diagnostic Reset" aka a hard reset. This should get the chip out of 121 * any state and back to its initialization state machine. 122 */ 123 static char mpt2_reset_magic[] = { 0x00, 0x0f, 0x04, 0x0b, 0x02, 0x07, 0x0d }; 124 125 /* 126 * Added this union to smoothly convert le64toh cm->cm_desc.Words. 127 * Compiler only supports uint64_t to be passed as an argument. 128 * Otherwise it will throw this error: 129 * "aggregate value used where an integer was expected" 130 */ 131 typedef union _reply_descriptor { 132 u64 word; 133 struct { 134 u32 low; 135 u32 high; 136 } u; 137 } reply_descriptor, request_descriptor; 138 139 /* Rate limit chain-fail messages to 1 per minute */ 140 static struct timeval mpr_chainfail_interval = { 60, 0 }; 141 142 /* 143 * sleep_flag can be either CAN_SLEEP or NO_SLEEP. 144 * If this function is called from process context, it can sleep 145 * and there is no harm to sleep, in case if this fuction is called 146 * from Interrupt handler, we can not sleep and need NO_SLEEP flag set. 147 * based on sleep flags driver will call either msleep, pause or DELAY. 148 * msleep and pause are of same variant, but pause is used when mpr_mtx 149 * is not hold by driver. 150 */ 151 static int 152 mpr_diag_reset(struct mpr_softc *sc,int sleep_flag) 153 { 154 uint32_t reg; 155 int i, error, tries = 0; 156 uint8_t first_wait_done = FALSE; 157 158 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 159 160 /* Clear any pending interrupts */ 161 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 162 163 /* 164 * Force NO_SLEEP for threads prohibited to sleep 165 * e.a Thread from interrupt handler are prohibited to sleep. 166 */ 167 #if __FreeBSD_version >= 1000029 168 if (curthread->td_no_sleeping) 169 #else //__FreeBSD_version < 1000029 170 if (curthread->td_pflags & TDP_NOSLEEPING) 171 #endif //__FreeBSD_version >= 1000029 172 sleep_flag = NO_SLEEP; 173 174 mpr_dprint(sc, MPR_INIT, "sequence start, sleep_flag=%d\n", sleep_flag); 175 /* Push the magic sequence */ 176 error = ETIMEDOUT; 177 while (tries++ < 20) { 178 for (i = 0; i < sizeof(mpt2_reset_magic); i++) 179 mpr_regwrite(sc, MPI2_WRITE_SEQUENCE_OFFSET, 180 mpt2_reset_magic[i]); 181 182 /* wait 100 msec */ 183 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) 184 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, 185 "mprdiag", hz/10); 186 else if (sleep_flag == CAN_SLEEP) 187 pause("mprdiag", hz/10); 188 else 189 DELAY(100 * 1000); 190 191 reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET); 192 if (reg & MPI2_DIAG_DIAG_WRITE_ENABLE) { 193 error = 0; 194 break; 195 } 196 } 197 if (error) { 198 mpr_dprint(sc, MPR_INIT, "sequence failed, error=%d, exit\n", 199 error); 200 return (error); 201 } 202 203 /* Send the actual reset. XXX need to refresh the reg? */ 204 reg |= MPI2_DIAG_RESET_ADAPTER; 205 mpr_dprint(sc, MPR_INIT, "sequence success, sending reset, reg= 0x%x\n", 206 reg); 207 mpr_regwrite(sc, MPI2_HOST_DIAGNOSTIC_OFFSET, reg); 208 209 /* Wait up to 300 seconds in 50ms intervals */ 210 error = ETIMEDOUT; 211 for (i = 0; i < 6000; i++) { 212 /* 213 * Wait 50 msec. If this is the first time through, wait 256 214 * msec to satisfy Diag Reset timing requirements. 215 */ 216 if (first_wait_done) { 217 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) 218 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, 219 "mprdiag", hz/20); 220 else if (sleep_flag == CAN_SLEEP) 221 pause("mprdiag", hz/20); 222 else 223 DELAY(50 * 1000); 224 } else { 225 DELAY(256 * 1000); 226 first_wait_done = TRUE; 227 } 228 /* 229 * Check for the RESET_ADAPTER bit to be cleared first, then 230 * wait for the RESET state to be cleared, which takes a little 231 * longer. 232 */ 233 reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET); 234 if (reg & MPI2_DIAG_RESET_ADAPTER) { 235 continue; 236 } 237 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 238 if ((reg & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_RESET) { 239 error = 0; 240 break; 241 } 242 } 243 if (error) { 244 mpr_dprint(sc, MPR_INIT, "reset failed, error= %d, exit\n", 245 error); 246 return (error); 247 } 248 249 mpr_regwrite(sc, MPI2_WRITE_SEQUENCE_OFFSET, 0x0); 250 mpr_dprint(sc, MPR_INIT, "diag reset success, exit\n"); 251 252 return (0); 253 } 254 255 static int 256 mpr_message_unit_reset(struct mpr_softc *sc, int sleep_flag) 257 { 258 int error; 259 260 MPR_FUNCTRACE(sc); 261 262 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 263 264 error = 0; 265 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET, 266 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET << 267 MPI2_DOORBELL_FUNCTION_SHIFT); 268 269 if (mpr_wait_db_ack(sc, 5, sleep_flag) != 0) { 270 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 271 "Doorbell handshake failed\n"); 272 error = ETIMEDOUT; 273 } 274 275 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 276 return (error); 277 } 278 279 static int 280 mpr_transition_ready(struct mpr_softc *sc) 281 { 282 uint32_t reg, state; 283 int error, tries = 0; 284 int sleep_flags; 285 286 MPR_FUNCTRACE(sc); 287 /* If we are in attach call, do not sleep */ 288 sleep_flags = (sc->mpr_flags & MPR_FLAGS_ATTACH_DONE) 289 ? CAN_SLEEP : NO_SLEEP; 290 291 error = 0; 292 293 mpr_dprint(sc, MPR_INIT, "%s entered, sleep_flags= %d\n", 294 __func__, sleep_flags); 295 296 while (tries++ < 1200) { 297 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 298 mpr_dprint(sc, MPR_INIT, " Doorbell= 0x%x\n", reg); 299 300 /* 301 * Ensure the IOC is ready to talk. If it's not, try 302 * resetting it. 303 */ 304 if (reg & MPI2_DOORBELL_USED) { 305 mpr_dprint(sc, MPR_INIT, " Not ready, sending diag " 306 "reset\n"); 307 mpr_diag_reset(sc, sleep_flags); 308 DELAY(50000); 309 continue; 310 } 311 312 /* Is the adapter owned by another peer? */ 313 if ((reg & MPI2_DOORBELL_WHO_INIT_MASK) == 314 (MPI2_WHOINIT_PCI_PEER << MPI2_DOORBELL_WHO_INIT_SHIFT)) { 315 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC is under the " 316 "control of another peer host, aborting " 317 "initialization.\n"); 318 error = ENXIO; 319 break; 320 } 321 322 state = reg & MPI2_IOC_STATE_MASK; 323 if (state == MPI2_IOC_STATE_READY) { 324 /* Ready to go! */ 325 error = 0; 326 break; 327 } else if (state == MPI2_IOC_STATE_FAULT) { 328 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC in fault " 329 "state 0x%x, resetting\n", 330 state & MPI2_DOORBELL_FAULT_CODE_MASK); 331 mpr_diag_reset(sc, sleep_flags); 332 } else if (state == MPI2_IOC_STATE_OPERATIONAL) { 333 /* Need to take ownership */ 334 mpr_message_unit_reset(sc, sleep_flags); 335 } else if (state == MPI2_IOC_STATE_RESET) { 336 /* Wait a bit, IOC might be in transition */ 337 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 338 "IOC in unexpected reset state\n"); 339 } else { 340 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 341 "IOC in unknown state 0x%x\n", state); 342 error = EINVAL; 343 break; 344 } 345 346 /* Wait 50ms for things to settle down. */ 347 DELAY(50000); 348 } 349 350 if (error) 351 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 352 "Cannot transition IOC to ready\n"); 353 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 354 return (error); 355 } 356 357 static int 358 mpr_transition_operational(struct mpr_softc *sc) 359 { 360 uint32_t reg, state; 361 int error; 362 363 MPR_FUNCTRACE(sc); 364 365 error = 0; 366 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 367 mpr_dprint(sc, MPR_INIT, "%s entered, Doorbell= 0x%x\n", __func__, reg); 368 369 state = reg & MPI2_IOC_STATE_MASK; 370 if (state != MPI2_IOC_STATE_READY) { 371 mpr_dprint(sc, MPR_INIT, "IOC not ready\n"); 372 if ((error = mpr_transition_ready(sc)) != 0) { 373 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 374 "failed to transition ready, exit\n"); 375 return (error); 376 } 377 } 378 379 error = mpr_send_iocinit(sc); 380 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 381 382 return (error); 383 } 384 385 static void 386 mpr_resize_queues(struct mpr_softc *sc) 387 { 388 u_int reqcr, prireqcr, maxio, sges_per_frame, chain_seg_size; 389 390 /* 391 * Size the queues. Since the reply queues always need one free 392 * entry, we'll deduct one reply message here. The LSI documents 393 * suggest instead to add a count to the request queue, but I think 394 * that it's better to deduct from reply queue. 395 */ 396 prireqcr = MAX(1, sc->max_prireqframes); 397 prireqcr = MIN(prireqcr, sc->facts->HighPriorityCredit); 398 399 reqcr = MAX(2, sc->max_reqframes); 400 reqcr = MIN(reqcr, sc->facts->RequestCredit); 401 402 sc->num_reqs = prireqcr + reqcr; 403 sc->num_prireqs = prireqcr; 404 sc->num_replies = MIN(sc->max_replyframes + sc->max_evtframes, 405 sc->facts->MaxReplyDescriptorPostQueueDepth) - 1; 406 407 /* Store the request frame size in bytes rather than as 32bit words */ 408 sc->reqframesz = sc->facts->IOCRequestFrameSize * 4; 409 410 /* 411 * Gen3 and beyond uses the IOCMaxChainSegmentSize from IOC Facts to 412 * get the size of a Chain Frame. Previous versions use the size as a 413 * Request Frame for the Chain Frame size. If IOCMaxChainSegmentSize 414 * is 0, use the default value. The IOCMaxChainSegmentSize is the 415 * number of 16-byte elelements that can fit in a Chain Frame, which is 416 * the size of an IEEE Simple SGE. 417 */ 418 if (sc->facts->MsgVersion >= MPI2_VERSION_02_05) { 419 chain_seg_size = htole16(sc->facts->IOCMaxChainSegmentSize); 420 if (chain_seg_size == 0) 421 chain_seg_size = MPR_DEFAULT_CHAIN_SEG_SIZE; 422 sc->chain_frame_size = chain_seg_size * 423 MPR_MAX_CHAIN_ELEMENT_SIZE; 424 } else { 425 sc->chain_frame_size = sc->reqframesz; 426 } 427 428 /* 429 * Max IO Size is Page Size * the following: 430 * ((SGEs per frame - 1 for chain element) * Max Chain Depth) 431 * + 1 for no chain needed in last frame 432 * 433 * If user suggests a Max IO size to use, use the smaller of the 434 * user's value and the calculated value as long as the user's 435 * value is larger than 0. The user's value is in pages. 436 */ 437 sges_per_frame = sc->chain_frame_size/sizeof(MPI2_IEEE_SGE_SIMPLE64)-1; 438 maxio = (sges_per_frame * sc->facts->MaxChainDepth + 1) * PAGE_SIZE; 439 440 /* 441 * If I/O size limitation requested then use it and pass up to CAM. 442 * If not, use MAXPHYS as an optimization hint, but report HW limit. 443 */ 444 if (sc->max_io_pages > 0) { 445 maxio = min(maxio, sc->max_io_pages * PAGE_SIZE); 446 sc->maxio = maxio; 447 } else { 448 sc->maxio = maxio; 449 maxio = min(maxio, MAXPHYS); 450 } 451 452 sc->num_chains = (maxio / PAGE_SIZE + sges_per_frame - 2) / 453 sges_per_frame * reqcr; 454 if (sc->max_chains > 0 && sc->max_chains < sc->num_chains) 455 sc->num_chains = sc->max_chains; 456 457 /* 458 * Figure out the number of MSIx-based queues. If the firmware or 459 * user has done something crazy and not allowed enough credit for 460 * the queues to be useful then don't enable multi-queue. 461 */ 462 if (sc->facts->MaxMSIxVectors < 2) 463 sc->msi_msgs = 1; 464 465 if (sc->msi_msgs > 1) { 466 sc->msi_msgs = MIN(sc->msi_msgs, mp_ncpus); 467 sc->msi_msgs = MIN(sc->msi_msgs, sc->facts->MaxMSIxVectors); 468 if (sc->num_reqs / sc->msi_msgs < 2) 469 sc->msi_msgs = 1; 470 } 471 472 mpr_dprint(sc, MPR_INIT, "Sized queues to q=%d reqs=%d replies=%d\n", 473 sc->msi_msgs, sc->num_reqs, sc->num_replies); 474 } 475 476 /* 477 * This is called during attach and when re-initializing due to a Diag Reset. 478 * IOC Facts is used to allocate many of the structures needed by the driver. 479 * If called from attach, de-allocation is not required because the driver has 480 * not allocated any structures yet, but if called from a Diag Reset, previously 481 * allocated structures based on IOC Facts will need to be freed and re- 482 * allocated bases on the latest IOC Facts. 483 */ 484 static int 485 mpr_iocfacts_allocate(struct mpr_softc *sc, uint8_t attaching) 486 { 487 int error; 488 Mpi2IOCFactsReply_t saved_facts; 489 uint8_t saved_mode, reallocating; 490 491 mpr_dprint(sc, MPR_INIT|MPR_TRACE, "%s entered\n", __func__); 492 493 /* Save old IOC Facts and then only reallocate if Facts have changed */ 494 if (!attaching) { 495 bcopy(sc->facts, &saved_facts, sizeof(MPI2_IOC_FACTS_REPLY)); 496 } 497 498 /* 499 * Get IOC Facts. In all cases throughout this function, panic if doing 500 * a re-initialization and only return the error if attaching so the OS 501 * can handle it. 502 */ 503 if ((error = mpr_get_iocfacts(sc, sc->facts)) != 0) { 504 if (attaching) { 505 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to get " 506 "IOC Facts with error %d, exit\n", error); 507 return (error); 508 } else { 509 panic("%s failed to get IOC Facts with error %d\n", 510 __func__, error); 511 } 512 } 513 514 MPR_DPRINT_PAGE(sc, MPR_XINFO, iocfacts, sc->facts); 515 516 snprintf(sc->fw_version, sizeof(sc->fw_version), 517 "%02d.%02d.%02d.%02d", 518 sc->facts->FWVersion.Struct.Major, 519 sc->facts->FWVersion.Struct.Minor, 520 sc->facts->FWVersion.Struct.Unit, 521 sc->facts->FWVersion.Struct.Dev); 522 523 mpr_dprint(sc, MPR_INFO, "Firmware: %s, Driver: %s\n", sc->fw_version, 524 MPR_DRIVER_VERSION); 525 mpr_dprint(sc, MPR_INFO, 526 "IOCCapabilities: %b\n", sc->facts->IOCCapabilities, 527 "\20" "\3ScsiTaskFull" "\4DiagTrace" "\5SnapBuf" "\6ExtBuf" 528 "\7EEDP" "\10BiDirTarg" "\11Multicast" "\14TransRetry" "\15IR" 529 "\16EventReplay" "\17RaidAccel" "\20MSIXIndex" "\21HostDisc" 530 "\22FastPath" "\23RDPQArray" "\24AtomicReqDesc" "\25PCIeSRIOV"); 531 532 /* 533 * If the chip doesn't support event replay then a hard reset will be 534 * required to trigger a full discovery. Do the reset here then 535 * retransition to Ready. A hard reset might have already been done, 536 * but it doesn't hurt to do it again. Only do this if attaching, not 537 * for a Diag Reset. 538 */ 539 if (attaching && ((sc->facts->IOCCapabilities & 540 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY) == 0)) { 541 mpr_dprint(sc, MPR_INIT, "No event replay, resetting\n"); 542 mpr_diag_reset(sc, NO_SLEEP); 543 if ((error = mpr_transition_ready(sc)) != 0) { 544 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to " 545 "transition to ready with error %d, exit\n", 546 error); 547 return (error); 548 } 549 } 550 551 /* 552 * Set flag if IR Firmware is loaded. If the RAID Capability has 553 * changed from the previous IOC Facts, log a warning, but only if 554 * checking this after a Diag Reset and not during attach. 555 */ 556 saved_mode = sc->ir_firmware; 557 if (sc->facts->IOCCapabilities & 558 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) 559 sc->ir_firmware = 1; 560 if (!attaching) { 561 if (sc->ir_firmware != saved_mode) { 562 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "new IR/IT mode " 563 "in IOC Facts does not match previous mode\n"); 564 } 565 } 566 567 /* Only deallocate and reallocate if relevant IOC Facts have changed */ 568 reallocating = FALSE; 569 sc->mpr_flags &= ~MPR_FLAGS_REALLOCATED; 570 571 if ((!attaching) && 572 ((saved_facts.MsgVersion != sc->facts->MsgVersion) || 573 (saved_facts.HeaderVersion != sc->facts->HeaderVersion) || 574 (saved_facts.MaxChainDepth != sc->facts->MaxChainDepth) || 575 (saved_facts.RequestCredit != sc->facts->RequestCredit) || 576 (saved_facts.ProductID != sc->facts->ProductID) || 577 (saved_facts.IOCCapabilities != sc->facts->IOCCapabilities) || 578 (saved_facts.IOCRequestFrameSize != 579 sc->facts->IOCRequestFrameSize) || 580 (saved_facts.IOCMaxChainSegmentSize != 581 sc->facts->IOCMaxChainSegmentSize) || 582 (saved_facts.MaxTargets != sc->facts->MaxTargets) || 583 (saved_facts.MaxSasExpanders != sc->facts->MaxSasExpanders) || 584 (saved_facts.MaxEnclosures != sc->facts->MaxEnclosures) || 585 (saved_facts.HighPriorityCredit != sc->facts->HighPriorityCredit) || 586 (saved_facts.MaxReplyDescriptorPostQueueDepth != 587 sc->facts->MaxReplyDescriptorPostQueueDepth) || 588 (saved_facts.ReplyFrameSize != sc->facts->ReplyFrameSize) || 589 (saved_facts.MaxVolumes != sc->facts->MaxVolumes) || 590 (saved_facts.MaxPersistentEntries != 591 sc->facts->MaxPersistentEntries))) { 592 reallocating = TRUE; 593 594 /* Record that we reallocated everything */ 595 sc->mpr_flags |= MPR_FLAGS_REALLOCATED; 596 } 597 598 /* 599 * Some things should be done if attaching or re-allocating after a Diag 600 * Reset, but are not needed after a Diag Reset if the FW has not 601 * changed. 602 */ 603 if (attaching || reallocating) { 604 /* 605 * Check if controller supports FW diag buffers and set flag to 606 * enable each type. 607 */ 608 if (sc->facts->IOCCapabilities & 609 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) 610 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_TRACE]. 611 enabled = TRUE; 612 if (sc->facts->IOCCapabilities & 613 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) 614 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_SNAPSHOT]. 615 enabled = TRUE; 616 if (sc->facts->IOCCapabilities & 617 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) 618 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_EXTENDED]. 619 enabled = TRUE; 620 621 /* 622 * Set flags for some supported items. 623 */ 624 if (sc->facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) 625 sc->eedp_enabled = TRUE; 626 if (sc->facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) 627 sc->control_TLR = TRUE; 628 if ((sc->facts->IOCCapabilities & 629 MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ) && 630 (sc->mpr_flags & MPR_FLAGS_SEA_IOC)) 631 sc->atomic_desc_capable = TRUE; 632 633 mpr_resize_queues(sc); 634 635 /* 636 * Initialize all Tail Queues 637 */ 638 TAILQ_INIT(&sc->req_list); 639 TAILQ_INIT(&sc->high_priority_req_list); 640 TAILQ_INIT(&sc->chain_list); 641 TAILQ_INIT(&sc->prp_page_list); 642 TAILQ_INIT(&sc->tm_list); 643 } 644 645 /* 646 * If doing a Diag Reset and the FW is significantly different 647 * (reallocating will be set above in IOC Facts comparison), then all 648 * buffers based on the IOC Facts will need to be freed before they are 649 * reallocated. 650 */ 651 if (reallocating) { 652 mpr_iocfacts_free(sc); 653 mprsas_realloc_targets(sc, saved_facts.MaxTargets + 654 saved_facts.MaxVolumes); 655 } 656 657 /* 658 * Any deallocation has been completed. Now start reallocating 659 * if needed. Will only need to reallocate if attaching or if the new 660 * IOC Facts are different from the previous IOC Facts after a Diag 661 * Reset. Targets have already been allocated above if needed. 662 */ 663 error = 0; 664 while (attaching || reallocating) { 665 if ((error = mpr_alloc_hw_queues(sc)) != 0) 666 break; 667 if ((error = mpr_alloc_replies(sc)) != 0) 668 break; 669 if ((error = mpr_alloc_requests(sc)) != 0) 670 break; 671 if ((error = mpr_alloc_queues(sc)) != 0) 672 break; 673 break; 674 } 675 if (error) { 676 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 677 "Failed to alloc queues with error %d\n", error); 678 mpr_free(sc); 679 return (error); 680 } 681 682 /* Always initialize the queues */ 683 bzero(sc->free_queue, sc->fqdepth * 4); 684 mpr_init_queues(sc); 685 686 /* 687 * Always get the chip out of the reset state, but only panic if not 688 * attaching. If attaching and there is an error, that is handled by 689 * the OS. 690 */ 691 error = mpr_transition_operational(sc); 692 if (error != 0) { 693 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to " 694 "transition to operational with error %d\n", error); 695 mpr_free(sc); 696 return (error); 697 } 698 699 /* 700 * Finish the queue initialization. 701 * These are set here instead of in mpr_init_queues() because the 702 * IOC resets these values during the state transition in 703 * mpr_transition_operational(). The free index is set to 1 704 * because the corresponding index in the IOC is set to 0, and the 705 * IOC treats the queues as full if both are set to the same value. 706 * Hence the reason that the queue can't hold all of the possible 707 * replies. 708 */ 709 sc->replypostindex = 0; 710 mpr_regwrite(sc, MPI2_REPLY_FREE_HOST_INDEX_OFFSET, sc->replyfreeindex); 711 mpr_regwrite(sc, MPI2_REPLY_POST_HOST_INDEX_OFFSET, 0); 712 713 /* 714 * Attach the subsystems so they can prepare their event masks. 715 * XXX Should be dynamic so that IM/IR and user modules can attach 716 */ 717 error = 0; 718 while (attaching) { 719 mpr_dprint(sc, MPR_INIT, "Attaching subsystems\n"); 720 if ((error = mpr_attach_log(sc)) != 0) 721 break; 722 if ((error = mpr_attach_sas(sc)) != 0) 723 break; 724 if ((error = mpr_attach_user(sc)) != 0) 725 break; 726 break; 727 } 728 if (error) { 729 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 730 "Failed to attach all subsystems: error %d\n", error); 731 mpr_free(sc); 732 return (error); 733 } 734 735 /* 736 * XXX If the number of MSI-X vectors changes during re-init, this 737 * won't see it and adjust. 738 */ 739 if (attaching && (error = mpr_pci_setup_interrupts(sc)) != 0) { 740 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 741 "Failed to setup interrupts\n"); 742 mpr_free(sc); 743 return (error); 744 } 745 746 return (error); 747 } 748 749 /* 750 * This is called if memory is being free (during detach for example) and when 751 * buffers need to be reallocated due to a Diag Reset. 752 */ 753 static void 754 mpr_iocfacts_free(struct mpr_softc *sc) 755 { 756 struct mpr_command *cm; 757 int i; 758 759 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 760 761 if (sc->free_busaddr != 0) 762 bus_dmamap_unload(sc->queues_dmat, sc->queues_map); 763 if (sc->free_queue != NULL) 764 bus_dmamem_free(sc->queues_dmat, sc->free_queue, 765 sc->queues_map); 766 if (sc->queues_dmat != NULL) 767 bus_dma_tag_destroy(sc->queues_dmat); 768 769 if (sc->chain_frames != NULL) { 770 bus_dmamap_unload(sc->chain_dmat, sc->chain_map); 771 bus_dmamem_free(sc->chain_dmat, sc->chain_frames, 772 sc->chain_map); 773 } 774 if (sc->chain_dmat != NULL) 775 bus_dma_tag_destroy(sc->chain_dmat); 776 777 if (sc->sense_busaddr != 0) 778 bus_dmamap_unload(sc->sense_dmat, sc->sense_map); 779 if (sc->sense_frames != NULL) 780 bus_dmamem_free(sc->sense_dmat, sc->sense_frames, 781 sc->sense_map); 782 if (sc->sense_dmat != NULL) 783 bus_dma_tag_destroy(sc->sense_dmat); 784 785 if (sc->prp_page_busaddr != 0) 786 bus_dmamap_unload(sc->prp_page_dmat, sc->prp_page_map); 787 if (sc->prp_pages != NULL) 788 bus_dmamem_free(sc->prp_page_dmat, sc->prp_pages, 789 sc->prp_page_map); 790 if (sc->prp_page_dmat != NULL) 791 bus_dma_tag_destroy(sc->prp_page_dmat); 792 793 if (sc->reply_busaddr != 0) 794 bus_dmamap_unload(sc->reply_dmat, sc->reply_map); 795 if (sc->reply_frames != NULL) 796 bus_dmamem_free(sc->reply_dmat, sc->reply_frames, 797 sc->reply_map); 798 if (sc->reply_dmat != NULL) 799 bus_dma_tag_destroy(sc->reply_dmat); 800 801 if (sc->req_busaddr != 0) 802 bus_dmamap_unload(sc->req_dmat, sc->req_map); 803 if (sc->req_frames != NULL) 804 bus_dmamem_free(sc->req_dmat, sc->req_frames, sc->req_map); 805 if (sc->req_dmat != NULL) 806 bus_dma_tag_destroy(sc->req_dmat); 807 808 if (sc->chains != NULL) 809 free(sc->chains, M_MPR); 810 if (sc->prps != NULL) 811 free(sc->prps, M_MPR); 812 if (sc->commands != NULL) { 813 for (i = 1; i < sc->num_reqs; i++) { 814 cm = &sc->commands[i]; 815 bus_dmamap_destroy(sc->buffer_dmat, cm->cm_dmamap); 816 } 817 free(sc->commands, M_MPR); 818 } 819 if (sc->buffer_dmat != NULL) 820 bus_dma_tag_destroy(sc->buffer_dmat); 821 822 mpr_pci_free_interrupts(sc); 823 free(sc->queues, M_MPR); 824 sc->queues = NULL; 825 } 826 827 /* 828 * The terms diag reset and hard reset are used interchangeably in the MPI 829 * docs to mean resetting the controller chip. In this code diag reset 830 * cleans everything up, and the hard reset function just sends the reset 831 * sequence to the chip. This should probably be refactored so that every 832 * subsystem gets a reset notification of some sort, and can clean up 833 * appropriately. 834 */ 835 int 836 mpr_reinit(struct mpr_softc *sc) 837 { 838 int error; 839 struct mprsas_softc *sassc; 840 841 sassc = sc->sassc; 842 843 MPR_FUNCTRACE(sc); 844 845 mtx_assert(&sc->mpr_mtx, MA_OWNED); 846 847 mpr_dprint(sc, MPR_INIT|MPR_INFO, "Reinitializing controller\n"); 848 if (sc->mpr_flags & MPR_FLAGS_DIAGRESET) { 849 mpr_dprint(sc, MPR_INIT, "Reset already in progress\n"); 850 return 0; 851 } 852 853 /* 854 * Make sure the completion callbacks can recognize they're getting 855 * a NULL cm_reply due to a reset. 856 */ 857 sc->mpr_flags |= MPR_FLAGS_DIAGRESET; 858 859 /* 860 * Mask interrupts here. 861 */ 862 mpr_dprint(sc, MPR_INIT, "Masking interrupts and resetting\n"); 863 mpr_mask_intr(sc); 864 865 error = mpr_diag_reset(sc, CAN_SLEEP); 866 if (error != 0) { 867 panic("%s hard reset failed with error %d\n", __func__, error); 868 } 869 870 /* Restore the PCI state, including the MSI-X registers */ 871 mpr_pci_restore(sc); 872 873 /* Give the I/O subsystem special priority to get itself prepared */ 874 mprsas_handle_reinit(sc); 875 876 /* 877 * Get IOC Facts and allocate all structures based on this information. 878 * The attach function will also call mpr_iocfacts_allocate at startup. 879 * If relevant values have changed in IOC Facts, this function will free 880 * all of the memory based on IOC Facts and reallocate that memory. 881 */ 882 if ((error = mpr_iocfacts_allocate(sc, FALSE)) != 0) { 883 panic("%s IOC Facts based allocation failed with error %d\n", 884 __func__, error); 885 } 886 887 /* 888 * Mapping structures will be re-allocated after getting IOC Page8, so 889 * free these structures here. 890 */ 891 mpr_mapping_exit(sc); 892 893 /* 894 * The static page function currently read is IOC Page8. Others can be 895 * added in future. It's possible that the values in IOC Page8 have 896 * changed after a Diag Reset due to user modification, so always read 897 * these. Interrupts are masked, so unmask them before getting config 898 * pages. 899 */ 900 mpr_unmask_intr(sc); 901 sc->mpr_flags &= ~MPR_FLAGS_DIAGRESET; 902 mpr_base_static_config_pages(sc); 903 904 /* 905 * Some mapping info is based in IOC Page8 data, so re-initialize the 906 * mapping tables. 907 */ 908 mpr_mapping_initialize(sc); 909 910 /* 911 * Restart will reload the event masks clobbered by the reset, and 912 * then enable the port. 913 */ 914 mpr_reregister_events(sc); 915 916 /* the end of discovery will release the simq, so we're done. */ 917 mpr_dprint(sc, MPR_INIT|MPR_XINFO, "Finished sc %p post %u free %u\n", 918 sc, sc->replypostindex, sc->replyfreeindex); 919 mprsas_release_simq_reinit(sassc); 920 mpr_dprint(sc, MPR_INIT, "%s exit error= %d\n", __func__, error); 921 922 return 0; 923 } 924 925 /* Wait for the chip to ACK a word that we've put into its FIFO 926 * Wait for <timeout> seconds. In single loop wait for busy loop 927 * for 500 microseconds. 928 * Total is [ 0.5 * (2000 * <timeout>) ] in miliseconds. 929 * */ 930 static int 931 mpr_wait_db_ack(struct mpr_softc *sc, int timeout, int sleep_flag) 932 { 933 u32 cntdn, count; 934 u32 int_status; 935 u32 doorbell; 936 937 count = 0; 938 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; 939 do { 940 int_status = mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET); 941 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { 942 mpr_dprint(sc, MPR_TRACE, "%s: successful count(%d), " 943 "timeout(%d)\n", __func__, count, timeout); 944 return 0; 945 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 946 doorbell = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 947 if ((doorbell & MPI2_IOC_STATE_MASK) == 948 MPI2_IOC_STATE_FAULT) { 949 mpr_dprint(sc, MPR_FAULT, 950 "fault_state(0x%04x)!\n", doorbell); 951 return (EFAULT); 952 } 953 } else if (int_status == 0xFFFFFFFF) 954 goto out; 955 956 /* 957 * If it can sleep, sleep for 1 milisecond, else busy loop for 958 * 0.5 milisecond 959 */ 960 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) 961 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, "mprdba", 962 hz/1000); 963 else if (sleep_flag == CAN_SLEEP) 964 pause("mprdba", hz/1000); 965 else 966 DELAY(500); 967 count++; 968 } while (--cntdn); 969 970 out: 971 mpr_dprint(sc, MPR_FAULT, "%s: failed due to timeout count(%d), " 972 "int_status(%x)!\n", __func__, count, int_status); 973 return (ETIMEDOUT); 974 } 975 976 /* Wait for the chip to signal that the next word in its FIFO can be fetched */ 977 static int 978 mpr_wait_db_int(struct mpr_softc *sc) 979 { 980 int retry; 981 982 for (retry = 0; retry < MPR_DB_MAX_WAIT; retry++) { 983 if ((mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET) & 984 MPI2_HIS_IOC2SYS_DB_STATUS) != 0) 985 return (0); 986 DELAY(2000); 987 } 988 return (ETIMEDOUT); 989 } 990 991 /* Step through the synchronous command state machine, i.e. "Doorbell mode" */ 992 static int 993 mpr_request_sync(struct mpr_softc *sc, void *req, MPI2_DEFAULT_REPLY *reply, 994 int req_sz, int reply_sz, int timeout) 995 { 996 uint32_t *data32; 997 uint16_t *data16; 998 int i, count, ioc_sz, residual; 999 int sleep_flags = CAN_SLEEP; 1000 1001 #if __FreeBSD_version >= 1000029 1002 if (curthread->td_no_sleeping) 1003 #else //__FreeBSD_version < 1000029 1004 if (curthread->td_pflags & TDP_NOSLEEPING) 1005 #endif //__FreeBSD_version >= 1000029 1006 sleep_flags = NO_SLEEP; 1007 1008 /* Step 1 */ 1009 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1010 1011 /* Step 2 */ 1012 if (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED) 1013 return (EBUSY); 1014 1015 /* Step 3 1016 * Announce that a message is coming through the doorbell. Messages 1017 * are pushed at 32bit words, so round up if needed. 1018 */ 1019 count = (req_sz + 3) / 4; 1020 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET, 1021 (MPI2_FUNCTION_HANDSHAKE << MPI2_DOORBELL_FUNCTION_SHIFT) | 1022 (count << MPI2_DOORBELL_ADD_DWORDS_SHIFT)); 1023 1024 /* Step 4 */ 1025 if (mpr_wait_db_int(sc) || 1026 (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED) == 0) { 1027 mpr_dprint(sc, MPR_FAULT, "Doorbell failed to activate\n"); 1028 return (ENXIO); 1029 } 1030 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1031 if (mpr_wait_db_ack(sc, 5, sleep_flags) != 0) { 1032 mpr_dprint(sc, MPR_FAULT, "Doorbell handshake failed\n"); 1033 return (ENXIO); 1034 } 1035 1036 /* Step 5 */ 1037 /* Clock out the message data synchronously in 32-bit dwords*/ 1038 data32 = (uint32_t *)req; 1039 for (i = 0; i < count; i++) { 1040 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET, htole32(data32[i])); 1041 if (mpr_wait_db_ack(sc, 5, sleep_flags) != 0) { 1042 mpr_dprint(sc, MPR_FAULT, 1043 "Timeout while writing doorbell\n"); 1044 return (ENXIO); 1045 } 1046 } 1047 1048 /* Step 6 */ 1049 /* Clock in the reply in 16-bit words. The total length of the 1050 * message is always in the 4th byte, so clock out the first 2 words 1051 * manually, then loop the rest. 1052 */ 1053 data16 = (uint16_t *)reply; 1054 if (mpr_wait_db_int(sc) != 0) { 1055 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell 0\n"); 1056 return (ENXIO); 1057 } 1058 data16[0] = 1059 mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_DATA_MASK; 1060 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1061 if (mpr_wait_db_int(sc) != 0) { 1062 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell 1\n"); 1063 return (ENXIO); 1064 } 1065 data16[1] = 1066 mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_DATA_MASK; 1067 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1068 1069 /* Number of 32bit words in the message */ 1070 ioc_sz = reply->MsgLength; 1071 1072 /* 1073 * Figure out how many 16bit words to clock in without overrunning. 1074 * The precision loss with dividing reply_sz can safely be 1075 * ignored because the messages can only be multiples of 32bits. 1076 */ 1077 residual = 0; 1078 count = MIN((reply_sz / 4), ioc_sz) * 2; 1079 if (count < ioc_sz * 2) { 1080 residual = ioc_sz * 2 - count; 1081 mpr_dprint(sc, MPR_ERROR, "Driver error, throwing away %d " 1082 "residual message words\n", residual); 1083 } 1084 1085 for (i = 2; i < count; i++) { 1086 if (mpr_wait_db_int(sc) != 0) { 1087 mpr_dprint(sc, MPR_FAULT, 1088 "Timeout reading doorbell %d\n", i); 1089 return (ENXIO); 1090 } 1091 data16[i] = mpr_regread(sc, MPI2_DOORBELL_OFFSET) & 1092 MPI2_DOORBELL_DATA_MASK; 1093 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1094 } 1095 1096 /* 1097 * Pull out residual words that won't fit into the provided buffer. 1098 * This keeps the chip from hanging due to a driver programming 1099 * error. 1100 */ 1101 while (residual--) { 1102 if (mpr_wait_db_int(sc) != 0) { 1103 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell\n"); 1104 return (ENXIO); 1105 } 1106 (void)mpr_regread(sc, MPI2_DOORBELL_OFFSET); 1107 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1108 } 1109 1110 /* Step 7 */ 1111 if (mpr_wait_db_int(sc) != 0) { 1112 mpr_dprint(sc, MPR_FAULT, "Timeout waiting to exit doorbell\n"); 1113 return (ENXIO); 1114 } 1115 if (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED) 1116 mpr_dprint(sc, MPR_FAULT, "Warning, doorbell still active\n"); 1117 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1118 1119 return (0); 1120 } 1121 1122 static void 1123 mpr_enqueue_request(struct mpr_softc *sc, struct mpr_command *cm) 1124 { 1125 request_descriptor rd; 1126 1127 MPR_FUNCTRACE(sc); 1128 mpr_dprint(sc, MPR_TRACE, "SMID %u cm %p ccb %p\n", 1129 cm->cm_desc.Default.SMID, cm, cm->cm_ccb); 1130 1131 if (sc->mpr_flags & MPR_FLAGS_ATTACH_DONE && !(sc->mpr_flags & 1132 MPR_FLAGS_SHUTDOWN)) 1133 mtx_assert(&sc->mpr_mtx, MA_OWNED); 1134 1135 if (++sc->io_cmds_active > sc->io_cmds_highwater) 1136 sc->io_cmds_highwater++; 1137 1138 KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, ("command not busy\n")); 1139 cm->cm_state = MPR_CM_STATE_INQUEUE; 1140 1141 if (sc->atomic_desc_capable) { 1142 rd.u.low = cm->cm_desc.Words.Low; 1143 mpr_regwrite(sc, MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET, 1144 rd.u.low); 1145 } else { 1146 rd.u.low = cm->cm_desc.Words.Low; 1147 rd.u.high = cm->cm_desc.Words.High; 1148 rd.word = htole64(rd.word); 1149 mpr_regwrite(sc, MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET, 1150 rd.u.low); 1151 mpr_regwrite(sc, MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET, 1152 rd.u.high); 1153 } 1154 } 1155 1156 /* 1157 * Just the FACTS, ma'am. 1158 */ 1159 static int 1160 mpr_get_iocfacts(struct mpr_softc *sc, MPI2_IOC_FACTS_REPLY *facts) 1161 { 1162 MPI2_DEFAULT_REPLY *reply; 1163 MPI2_IOC_FACTS_REQUEST request; 1164 int error, req_sz, reply_sz; 1165 1166 MPR_FUNCTRACE(sc); 1167 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 1168 1169 req_sz = sizeof(MPI2_IOC_FACTS_REQUEST); 1170 reply_sz = sizeof(MPI2_IOC_FACTS_REPLY); 1171 reply = (MPI2_DEFAULT_REPLY *)facts; 1172 1173 bzero(&request, req_sz); 1174 request.Function = MPI2_FUNCTION_IOC_FACTS; 1175 error = mpr_request_sync(sc, &request, reply, req_sz, reply_sz, 5); 1176 1177 mpr_dprint(sc, MPR_INIT, "%s exit, error= %d\n", __func__, error); 1178 return (error); 1179 } 1180 1181 static int 1182 mpr_send_iocinit(struct mpr_softc *sc) 1183 { 1184 MPI2_IOC_INIT_REQUEST init; 1185 MPI2_DEFAULT_REPLY reply; 1186 int req_sz, reply_sz, error; 1187 struct timeval now; 1188 uint64_t time_in_msec; 1189 1190 MPR_FUNCTRACE(sc); 1191 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 1192 1193 /* Do a quick sanity check on proper initialization */ 1194 if ((sc->pqdepth == 0) || (sc->fqdepth == 0) || (sc->reqframesz == 0) 1195 || (sc->replyframesz == 0)) { 1196 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 1197 "Driver not fully initialized for IOCInit\n"); 1198 return (EINVAL); 1199 } 1200 1201 req_sz = sizeof(MPI2_IOC_INIT_REQUEST); 1202 reply_sz = sizeof(MPI2_IOC_INIT_REPLY); 1203 bzero(&init, req_sz); 1204 bzero(&reply, reply_sz); 1205 1206 /* 1207 * Fill in the init block. Note that most addresses are 1208 * deliberately in the lower 32bits of memory. This is a micro- 1209 * optimzation for PCI/PCIX, though it's not clear if it helps PCIe. 1210 */ 1211 init.Function = MPI2_FUNCTION_IOC_INIT; 1212 init.WhoInit = MPI2_WHOINIT_HOST_DRIVER; 1213 init.MsgVersion = htole16(MPI2_VERSION); 1214 init.HeaderVersion = htole16(MPI2_HEADER_VERSION); 1215 init.SystemRequestFrameSize = htole16((uint16_t)(sc->reqframesz / 4)); 1216 init.ReplyDescriptorPostQueueDepth = htole16(sc->pqdepth); 1217 init.ReplyFreeQueueDepth = htole16(sc->fqdepth); 1218 init.SenseBufferAddressHigh = 0; 1219 init.SystemReplyAddressHigh = 0; 1220 init.SystemRequestFrameBaseAddress.High = 0; 1221 init.SystemRequestFrameBaseAddress.Low = 1222 htole32((uint32_t)sc->req_busaddr); 1223 init.ReplyDescriptorPostQueueAddress.High = 0; 1224 init.ReplyDescriptorPostQueueAddress.Low = 1225 htole32((uint32_t)sc->post_busaddr); 1226 init.ReplyFreeQueueAddress.High = 0; 1227 init.ReplyFreeQueueAddress.Low = htole32((uint32_t)sc->free_busaddr); 1228 getmicrotime(&now); 1229 time_in_msec = (now.tv_sec * 1000 + now.tv_usec/1000); 1230 init.TimeStamp.High = htole32((time_in_msec >> 32) & 0xFFFFFFFF); 1231 init.TimeStamp.Low = htole32(time_in_msec & 0xFFFFFFFF); 1232 init.HostPageSize = HOST_PAGE_SIZE_4K; 1233 1234 error = mpr_request_sync(sc, &init, &reply, req_sz, reply_sz, 5); 1235 if ((reply.IOCStatus & MPI2_IOCSTATUS_MASK) != MPI2_IOCSTATUS_SUCCESS) 1236 error = ENXIO; 1237 1238 mpr_dprint(sc, MPR_INIT, "IOCInit status= 0x%x\n", reply.IOCStatus); 1239 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 1240 return (error); 1241 } 1242 1243 void 1244 mpr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1245 { 1246 bus_addr_t *addr; 1247 1248 addr = arg; 1249 *addr = segs[0].ds_addr; 1250 } 1251 1252 void 1253 mpr_memaddr_wait_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1254 { 1255 struct mpr_busdma_context *ctx; 1256 int need_unload, need_free; 1257 1258 ctx = (struct mpr_busdma_context *)arg; 1259 need_unload = 0; 1260 need_free = 0; 1261 1262 mpr_lock(ctx->softc); 1263 ctx->error = error; 1264 ctx->completed = 1; 1265 if ((error == 0) && (ctx->abandoned == 0)) { 1266 *ctx->addr = segs[0].ds_addr; 1267 } else { 1268 if (nsegs != 0) 1269 need_unload = 1; 1270 if (ctx->abandoned != 0) 1271 need_free = 1; 1272 } 1273 if (need_free == 0) 1274 wakeup(ctx); 1275 1276 mpr_unlock(ctx->softc); 1277 1278 if (need_unload != 0) { 1279 bus_dmamap_unload(ctx->buffer_dmat, 1280 ctx->buffer_dmamap); 1281 *ctx->addr = 0; 1282 } 1283 1284 if (need_free != 0) 1285 free(ctx, M_MPR); 1286 } 1287 1288 static int 1289 mpr_alloc_queues(struct mpr_softc *sc) 1290 { 1291 struct mpr_queue *q; 1292 int nq, i; 1293 1294 nq = sc->msi_msgs; 1295 mpr_dprint(sc, MPR_INIT|MPR_XINFO, "Allocating %d I/O queues\n", nq); 1296 1297 sc->queues = malloc(sizeof(struct mpr_queue) * nq, M_MPR, 1298 M_NOWAIT|M_ZERO); 1299 if (sc->queues == NULL) 1300 return (ENOMEM); 1301 1302 for (i = 0; i < nq; i++) { 1303 q = &sc->queues[i]; 1304 mpr_dprint(sc, MPR_INIT, "Configuring queue %d %p\n", i, q); 1305 q->sc = sc; 1306 q->qnum = i; 1307 } 1308 return (0); 1309 } 1310 1311 static int 1312 mpr_alloc_hw_queues(struct mpr_softc *sc) 1313 { 1314 bus_dma_tag_template_t t; 1315 bus_addr_t queues_busaddr; 1316 uint8_t *queues; 1317 int qsize, fqsize, pqsize; 1318 1319 /* 1320 * The reply free queue contains 4 byte entries in multiples of 16 and 1321 * aligned on a 16 byte boundary. There must always be an unused entry. 1322 * This queue supplies fresh reply frames for the firmware to use. 1323 * 1324 * The reply descriptor post queue contains 8 byte entries in 1325 * multiples of 16 and aligned on a 16 byte boundary. This queue 1326 * contains filled-in reply frames sent from the firmware to the host. 1327 * 1328 * These two queues are allocated together for simplicity. 1329 */ 1330 sc->fqdepth = roundup2(sc->num_replies + 1, 16); 1331 sc->pqdepth = roundup2(sc->num_replies + 1, 16); 1332 fqsize= sc->fqdepth * 4; 1333 pqsize = sc->pqdepth * 8; 1334 qsize = fqsize + pqsize; 1335 1336 bus_dma_template_init(&t, sc->mpr_parent_dmat); 1337 t.alignment = 16; 1338 t.lowaddr = BUS_SPACE_MAXADDR_32BIT; 1339 t.maxsize = t.maxsegsize = qsize; 1340 t.nsegments = 1; 1341 if (bus_dma_template_tag(&t, &sc->queues_dmat)) { 1342 mpr_dprint(sc, MPR_ERROR, "Cannot allocate queues DMA tag\n"); 1343 return (ENOMEM); 1344 } 1345 if (bus_dmamem_alloc(sc->queues_dmat, (void **)&queues, BUS_DMA_NOWAIT, 1346 &sc->queues_map)) { 1347 mpr_dprint(sc, MPR_ERROR, "Cannot allocate queues memory\n"); 1348 return (ENOMEM); 1349 } 1350 bzero(queues, qsize); 1351 bus_dmamap_load(sc->queues_dmat, sc->queues_map, queues, qsize, 1352 mpr_memaddr_cb, &queues_busaddr, 0); 1353 1354 sc->free_queue = (uint32_t *)queues; 1355 sc->free_busaddr = queues_busaddr; 1356 sc->post_queue = (MPI2_REPLY_DESCRIPTORS_UNION *)(queues + fqsize); 1357 sc->post_busaddr = queues_busaddr + fqsize; 1358 mpr_dprint(sc, MPR_INIT, "free queue busaddr= %#016jx size= %d\n", 1359 (uintmax_t)sc->free_busaddr, fqsize); 1360 mpr_dprint(sc, MPR_INIT, "reply queue busaddr= %#016jx size= %d\n", 1361 (uintmax_t)sc->post_busaddr, pqsize); 1362 1363 return (0); 1364 } 1365 1366 static int 1367 mpr_alloc_replies(struct mpr_softc *sc) 1368 { 1369 bus_dma_tag_template_t t; 1370 int rsize, num_replies; 1371 1372 /* Store the reply frame size in bytes rather than as 32bit words */ 1373 sc->replyframesz = sc->facts->ReplyFrameSize * 4; 1374 1375 /* 1376 * sc->num_replies should be one less than sc->fqdepth. We need to 1377 * allocate space for sc->fqdepth replies, but only sc->num_replies 1378 * replies can be used at once. 1379 */ 1380 num_replies = max(sc->fqdepth, sc->num_replies); 1381 1382 rsize = sc->replyframesz * num_replies; 1383 bus_dma_template_init(&t, sc->mpr_parent_dmat); 1384 t.alignment = 4; 1385 t.lowaddr = BUS_SPACE_MAXADDR_32BIT; 1386 t.maxsize = t.maxsegsize = rsize; 1387 t.nsegments = 1; 1388 if (bus_dma_template_tag(&t, &sc->reply_dmat)) { 1389 mpr_dprint(sc, MPR_ERROR, "Cannot allocate replies DMA tag\n"); 1390 return (ENOMEM); 1391 } 1392 if (bus_dmamem_alloc(sc->reply_dmat, (void **)&sc->reply_frames, 1393 BUS_DMA_NOWAIT, &sc->reply_map)) { 1394 mpr_dprint(sc, MPR_ERROR, "Cannot allocate replies memory\n"); 1395 return (ENOMEM); 1396 } 1397 bzero(sc->reply_frames, rsize); 1398 bus_dmamap_load(sc->reply_dmat, sc->reply_map, sc->reply_frames, rsize, 1399 mpr_memaddr_cb, &sc->reply_busaddr, 0); 1400 mpr_dprint(sc, MPR_INIT, "reply frames busaddr= %#016jx size= %d\n", 1401 (uintmax_t)sc->reply_busaddr, rsize); 1402 1403 return (0); 1404 } 1405 1406 static void 1407 mpr_load_chains_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1408 { 1409 struct mpr_softc *sc = arg; 1410 struct mpr_chain *chain; 1411 bus_size_t bo; 1412 int i, o, s; 1413 1414 if (error != 0) 1415 return; 1416 1417 for (i = 0, o = 0, s = 0; s < nsegs; s++) { 1418 for (bo = 0; bo + sc->chain_frame_size <= segs[s].ds_len; 1419 bo += sc->chain_frame_size) { 1420 chain = &sc->chains[i++]; 1421 chain->chain =(MPI2_SGE_IO_UNION *)(sc->chain_frames+o); 1422 chain->chain_busaddr = segs[s].ds_addr + bo; 1423 o += sc->chain_frame_size; 1424 mpr_free_chain(sc, chain); 1425 } 1426 if (bo != segs[s].ds_len) 1427 o += segs[s].ds_len - bo; 1428 } 1429 sc->chain_free_lowwater = i; 1430 } 1431 1432 static int 1433 mpr_alloc_requests(struct mpr_softc *sc) 1434 { 1435 bus_dma_tag_template_t t; 1436 struct mpr_command *cm; 1437 int i, rsize, nsegs; 1438 1439 rsize = sc->reqframesz * sc->num_reqs; 1440 bus_dma_template_init(&t, sc->mpr_parent_dmat); 1441 t.alignment = 16; 1442 t.lowaddr = BUS_SPACE_MAXADDR_32BIT; 1443 t.maxsize = t.maxsegsize = rsize; 1444 t.nsegments = 1; 1445 if (bus_dma_template_tag(&t, &sc->req_dmat)) { 1446 mpr_dprint(sc, MPR_ERROR, "Cannot allocate request DMA tag\n"); 1447 return (ENOMEM); 1448 } 1449 if (bus_dmamem_alloc(sc->req_dmat, (void **)&sc->req_frames, 1450 BUS_DMA_NOWAIT, &sc->req_map)) { 1451 mpr_dprint(sc, MPR_ERROR, "Cannot allocate request memory\n"); 1452 return (ENOMEM); 1453 } 1454 bzero(sc->req_frames, rsize); 1455 bus_dmamap_load(sc->req_dmat, sc->req_map, sc->req_frames, rsize, 1456 mpr_memaddr_cb, &sc->req_busaddr, 0); 1457 mpr_dprint(sc, MPR_INIT, "request frames busaddr= %#016jx size= %d\n", 1458 (uintmax_t)sc->req_busaddr, rsize); 1459 1460 sc->chains = malloc(sizeof(struct mpr_chain) * sc->num_chains, M_MPR, 1461 M_NOWAIT | M_ZERO); 1462 if (!sc->chains) { 1463 mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain memory\n"); 1464 return (ENOMEM); 1465 } 1466 rsize = sc->chain_frame_size * sc->num_chains; 1467 bus_dma_template_init(&t, sc->mpr_parent_dmat); 1468 t.alignment = 16; 1469 t.maxsize = t.maxsegsize = rsize; 1470 t.nsegments = howmany(rsize, PAGE_SIZE); 1471 if (bus_dma_template_tag(&t, &sc->chain_dmat)) { 1472 mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain DMA tag\n"); 1473 return (ENOMEM); 1474 } 1475 if (bus_dmamem_alloc(sc->chain_dmat, (void **)&sc->chain_frames, 1476 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->chain_map)) { 1477 mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain memory\n"); 1478 return (ENOMEM); 1479 } 1480 if (bus_dmamap_load(sc->chain_dmat, sc->chain_map, sc->chain_frames, 1481 rsize, mpr_load_chains_cb, sc, BUS_DMA_NOWAIT)) { 1482 mpr_dprint(sc, MPR_ERROR, "Cannot load chain memory\n"); 1483 bus_dmamem_free(sc->chain_dmat, sc->chain_frames, 1484 sc->chain_map); 1485 return (ENOMEM); 1486 } 1487 1488 rsize = MPR_SENSE_LEN * sc->num_reqs; 1489 bus_dma_template_clone(&t, sc->req_dmat); 1490 t.maxsize = t.maxsegsize = rsize; 1491 if (bus_dma_template_tag(&t, &sc->sense_dmat)) { 1492 mpr_dprint(sc, MPR_ERROR, "Cannot allocate sense DMA tag\n"); 1493 return (ENOMEM); 1494 } 1495 if (bus_dmamem_alloc(sc->sense_dmat, (void **)&sc->sense_frames, 1496 BUS_DMA_NOWAIT, &sc->sense_map)) { 1497 mpr_dprint(sc, MPR_ERROR, "Cannot allocate sense memory\n"); 1498 return (ENOMEM); 1499 } 1500 bzero(sc->sense_frames, rsize); 1501 bus_dmamap_load(sc->sense_dmat, sc->sense_map, sc->sense_frames, rsize, 1502 mpr_memaddr_cb, &sc->sense_busaddr, 0); 1503 mpr_dprint(sc, MPR_INIT, "sense frames busaddr= %#016jx size= %d\n", 1504 (uintmax_t)sc->sense_busaddr, rsize); 1505 1506 /* 1507 * Allocate NVMe PRP Pages for NVMe SGL support only if the FW supports 1508 * these devices. 1509 */ 1510 if ((sc->facts->MsgVersion >= MPI2_VERSION_02_06) && 1511 (sc->facts->ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES)) { 1512 if (mpr_alloc_nvme_prp_pages(sc) == ENOMEM) 1513 return (ENOMEM); 1514 } 1515 1516 nsegs = (sc->maxio / PAGE_SIZE) + 1; 1517 bus_dma_template_init(&t, sc->mpr_parent_dmat); 1518 t.nsegments = nsegs; 1519 t.flags = BUS_DMA_ALLOCNOW; 1520 t.lockfunc = busdma_lock_mutex; 1521 t.lockfuncarg = &sc->mpr_mtx; 1522 if (bus_dma_template_tag(&t, &sc->buffer_dmat)) { 1523 mpr_dprint(sc, MPR_ERROR, "Cannot allocate buffer DMA tag\n"); 1524 return (ENOMEM); 1525 } 1526 1527 /* 1528 * SMID 0 cannot be used as a free command per the firmware spec. 1529 * Just drop that command instead of risking accounting bugs. 1530 */ 1531 sc->commands = malloc(sizeof(struct mpr_command) * sc->num_reqs, 1532 M_MPR, M_WAITOK | M_ZERO); 1533 if (!sc->commands) { 1534 mpr_dprint(sc, MPR_ERROR, "Cannot allocate command memory\n"); 1535 return (ENOMEM); 1536 } 1537 for (i = 1; i < sc->num_reqs; i++) { 1538 cm = &sc->commands[i]; 1539 cm->cm_req = sc->req_frames + i * sc->reqframesz; 1540 cm->cm_req_busaddr = sc->req_busaddr + i * sc->reqframesz; 1541 cm->cm_sense = &sc->sense_frames[i]; 1542 cm->cm_sense_busaddr = sc->sense_busaddr + i * MPR_SENSE_LEN; 1543 cm->cm_desc.Default.SMID = i; 1544 cm->cm_sc = sc; 1545 cm->cm_state = MPR_CM_STATE_BUSY; 1546 TAILQ_INIT(&cm->cm_chain_list); 1547 TAILQ_INIT(&cm->cm_prp_page_list); 1548 callout_init_mtx(&cm->cm_callout, &sc->mpr_mtx, 0); 1549 1550 /* XXX Is a failure here a critical problem? */ 1551 if (bus_dmamap_create(sc->buffer_dmat, 0, &cm->cm_dmamap) 1552 == 0) { 1553 if (i <= sc->num_prireqs) 1554 mpr_free_high_priority_command(sc, cm); 1555 else 1556 mpr_free_command(sc, cm); 1557 } else { 1558 panic("failed to allocate command %d\n", i); 1559 sc->num_reqs = i; 1560 break; 1561 } 1562 } 1563 1564 return (0); 1565 } 1566 1567 /* 1568 * Allocate contiguous buffers for PCIe NVMe devices for building native PRPs, 1569 * which are scatter/gather lists for NVMe devices. 1570 * 1571 * This buffer must be contiguous due to the nature of how NVMe PRPs are built 1572 * and translated by FW. 1573 * 1574 * returns ENOMEM if memory could not be allocated, otherwise returns 0. 1575 */ 1576 static int 1577 mpr_alloc_nvme_prp_pages(struct mpr_softc *sc) 1578 { 1579 bus_dma_tag_template_t t; 1580 struct mpr_prp_page *prp_page; 1581 int PRPs_per_page, PRPs_required, pages_required; 1582 int rsize, i; 1583 1584 /* 1585 * Assuming a MAX_IO_SIZE of 1MB and a PAGE_SIZE of 4k, the max number 1586 * of PRPs (NVMe's Scatter/Gather Element) needed per I/O is: 1587 * MAX_IO_SIZE / PAGE_SIZE = 256 1588 * 1589 * 1 PRP entry in main frame for PRP list pointer still leaves 255 PRPs 1590 * required for the remainder of the 1MB I/O. 512 PRPs can fit into one 1591 * page (4096 / 8 = 512), so only one page is required for each I/O. 1592 * 1593 * Each of these buffers will need to be contiguous. For simplicity, 1594 * only one buffer is allocated here, which has all of the space 1595 * required for the NVMe Queue Depth. If there are problems allocating 1596 * this one buffer, this function will need to change to allocate 1597 * individual, contiguous NVME_QDEPTH buffers. 1598 * 1599 * The real calculation will use the real max io size. Above is just an 1600 * example. 1601 * 1602 */ 1603 PRPs_required = sc->maxio / PAGE_SIZE; 1604 PRPs_per_page = (PAGE_SIZE / PRP_ENTRY_SIZE) - 1; 1605 pages_required = (PRPs_required / PRPs_per_page) + 1; 1606 1607 sc->prp_buffer_size = PAGE_SIZE * pages_required; 1608 rsize = sc->prp_buffer_size * NVME_QDEPTH; 1609 bus_dma_template_init(&t, sc->mpr_parent_dmat); 1610 t.alignment = 4; 1611 t.lowaddr = BUS_SPACE_MAXADDR_32BIT; 1612 t.maxsize = t.maxsegsize = rsize; 1613 t.nsegments = 1; 1614 if (bus_dma_template_tag(&t, &sc->prp_page_dmat)) { 1615 mpr_dprint(sc, MPR_ERROR, "Cannot allocate NVMe PRP DMA " 1616 "tag\n"); 1617 return (ENOMEM); 1618 } 1619 if (bus_dmamem_alloc(sc->prp_page_dmat, (void **)&sc->prp_pages, 1620 BUS_DMA_NOWAIT, &sc->prp_page_map)) { 1621 mpr_dprint(sc, MPR_ERROR, "Cannot allocate NVMe PRP memory\n"); 1622 return (ENOMEM); 1623 } 1624 bzero(sc->prp_pages, rsize); 1625 bus_dmamap_load(sc->prp_page_dmat, sc->prp_page_map, sc->prp_pages, 1626 rsize, mpr_memaddr_cb, &sc->prp_page_busaddr, 0); 1627 1628 sc->prps = malloc(sizeof(struct mpr_prp_page) * NVME_QDEPTH, M_MPR, 1629 M_WAITOK | M_ZERO); 1630 for (i = 0; i < NVME_QDEPTH; i++) { 1631 prp_page = &sc->prps[i]; 1632 prp_page->prp_page = (uint64_t *)(sc->prp_pages + 1633 i * sc->prp_buffer_size); 1634 prp_page->prp_page_busaddr = (uint64_t)(sc->prp_page_busaddr + 1635 i * sc->prp_buffer_size); 1636 mpr_free_prp_page(sc, prp_page); 1637 sc->prp_pages_free_lowwater++; 1638 } 1639 1640 return (0); 1641 } 1642 1643 static int 1644 mpr_init_queues(struct mpr_softc *sc) 1645 { 1646 int i; 1647 1648 memset((uint8_t *)sc->post_queue, 0xff, sc->pqdepth * 8); 1649 1650 /* 1651 * According to the spec, we need to use one less reply than we 1652 * have space for on the queue. So sc->num_replies (the number we 1653 * use) should be less than sc->fqdepth (allocated size). 1654 */ 1655 if (sc->num_replies >= sc->fqdepth) 1656 return (EINVAL); 1657 1658 /* 1659 * Initialize all of the free queue entries. 1660 */ 1661 for (i = 0; i < sc->fqdepth; i++) { 1662 sc->free_queue[i] = sc->reply_busaddr + (i * sc->replyframesz); 1663 } 1664 sc->replyfreeindex = sc->num_replies; 1665 1666 return (0); 1667 } 1668 1669 /* Get the driver parameter tunables. Lowest priority are the driver defaults. 1670 * Next are the global settings, if they exist. Highest are the per-unit 1671 * settings, if they exist. 1672 */ 1673 void 1674 mpr_get_tunables(struct mpr_softc *sc) 1675 { 1676 char tmpstr[80], mpr_debug[80]; 1677 1678 /* XXX default to some debugging for now */ 1679 sc->mpr_debug = MPR_INFO | MPR_FAULT; 1680 sc->disable_msix = 0; 1681 sc->disable_msi = 0; 1682 sc->max_msix = MPR_MSIX_MAX; 1683 sc->max_chains = MPR_CHAIN_FRAMES; 1684 sc->max_io_pages = MPR_MAXIO_PAGES; 1685 sc->enable_ssu = MPR_SSU_ENABLE_SSD_DISABLE_HDD; 1686 sc->spinup_wait_time = DEFAULT_SPINUP_WAIT; 1687 sc->use_phynum = 1; 1688 sc->max_reqframes = MPR_REQ_FRAMES; 1689 sc->max_prireqframes = MPR_PRI_REQ_FRAMES; 1690 sc->max_replyframes = MPR_REPLY_FRAMES; 1691 sc->max_evtframes = MPR_EVT_REPLY_FRAMES; 1692 1693 /* 1694 * Grab the global variables. 1695 */ 1696 bzero(mpr_debug, 80); 1697 if (TUNABLE_STR_FETCH("hw.mpr.debug_level", mpr_debug, 80) != 0) 1698 mpr_parse_debug(sc, mpr_debug); 1699 TUNABLE_INT_FETCH("hw.mpr.disable_msix", &sc->disable_msix); 1700 TUNABLE_INT_FETCH("hw.mpr.disable_msi", &sc->disable_msi); 1701 TUNABLE_INT_FETCH("hw.mpr.max_msix", &sc->max_msix); 1702 TUNABLE_INT_FETCH("hw.mpr.max_chains", &sc->max_chains); 1703 TUNABLE_INT_FETCH("hw.mpr.max_io_pages", &sc->max_io_pages); 1704 TUNABLE_INT_FETCH("hw.mpr.enable_ssu", &sc->enable_ssu); 1705 TUNABLE_INT_FETCH("hw.mpr.spinup_wait_time", &sc->spinup_wait_time); 1706 TUNABLE_INT_FETCH("hw.mpr.use_phy_num", &sc->use_phynum); 1707 TUNABLE_INT_FETCH("hw.mpr.max_reqframes", &sc->max_reqframes); 1708 TUNABLE_INT_FETCH("hw.mpr.max_prireqframes", &sc->max_prireqframes); 1709 TUNABLE_INT_FETCH("hw.mpr.max_replyframes", &sc->max_replyframes); 1710 TUNABLE_INT_FETCH("hw.mpr.max_evtframes", &sc->max_evtframes); 1711 1712 /* Grab the unit-instance variables */ 1713 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.debug_level", 1714 device_get_unit(sc->mpr_dev)); 1715 bzero(mpr_debug, 80); 1716 if (TUNABLE_STR_FETCH(tmpstr, mpr_debug, 80) != 0) 1717 mpr_parse_debug(sc, mpr_debug); 1718 1719 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.disable_msix", 1720 device_get_unit(sc->mpr_dev)); 1721 TUNABLE_INT_FETCH(tmpstr, &sc->disable_msix); 1722 1723 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.disable_msi", 1724 device_get_unit(sc->mpr_dev)); 1725 TUNABLE_INT_FETCH(tmpstr, &sc->disable_msi); 1726 1727 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_msix", 1728 device_get_unit(sc->mpr_dev)); 1729 TUNABLE_INT_FETCH(tmpstr, &sc->max_msix); 1730 1731 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_chains", 1732 device_get_unit(sc->mpr_dev)); 1733 TUNABLE_INT_FETCH(tmpstr, &sc->max_chains); 1734 1735 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_io_pages", 1736 device_get_unit(sc->mpr_dev)); 1737 TUNABLE_INT_FETCH(tmpstr, &sc->max_io_pages); 1738 1739 bzero(sc->exclude_ids, sizeof(sc->exclude_ids)); 1740 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.exclude_ids", 1741 device_get_unit(sc->mpr_dev)); 1742 TUNABLE_STR_FETCH(tmpstr, sc->exclude_ids, sizeof(sc->exclude_ids)); 1743 1744 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.enable_ssu", 1745 device_get_unit(sc->mpr_dev)); 1746 TUNABLE_INT_FETCH(tmpstr, &sc->enable_ssu); 1747 1748 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.spinup_wait_time", 1749 device_get_unit(sc->mpr_dev)); 1750 TUNABLE_INT_FETCH(tmpstr, &sc->spinup_wait_time); 1751 1752 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.use_phy_num", 1753 device_get_unit(sc->mpr_dev)); 1754 TUNABLE_INT_FETCH(tmpstr, &sc->use_phynum); 1755 1756 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_reqframes", 1757 device_get_unit(sc->mpr_dev)); 1758 TUNABLE_INT_FETCH(tmpstr, &sc->max_reqframes); 1759 1760 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_prireqframes", 1761 device_get_unit(sc->mpr_dev)); 1762 TUNABLE_INT_FETCH(tmpstr, &sc->max_prireqframes); 1763 1764 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_replyframes", 1765 device_get_unit(sc->mpr_dev)); 1766 TUNABLE_INT_FETCH(tmpstr, &sc->max_replyframes); 1767 1768 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_evtframes", 1769 device_get_unit(sc->mpr_dev)); 1770 TUNABLE_INT_FETCH(tmpstr, &sc->max_evtframes); 1771 } 1772 1773 static void 1774 mpr_setup_sysctl(struct mpr_softc *sc) 1775 { 1776 struct sysctl_ctx_list *sysctl_ctx = NULL; 1777 struct sysctl_oid *sysctl_tree = NULL; 1778 char tmpstr[80], tmpstr2[80]; 1779 1780 /* 1781 * Setup the sysctl variable so the user can change the debug level 1782 * on the fly. 1783 */ 1784 snprintf(tmpstr, sizeof(tmpstr), "MPR controller %d", 1785 device_get_unit(sc->mpr_dev)); 1786 snprintf(tmpstr2, sizeof(tmpstr2), "%d", device_get_unit(sc->mpr_dev)); 1787 1788 sysctl_ctx = device_get_sysctl_ctx(sc->mpr_dev); 1789 if (sysctl_ctx != NULL) 1790 sysctl_tree = device_get_sysctl_tree(sc->mpr_dev); 1791 1792 if (sysctl_tree == NULL) { 1793 sysctl_ctx_init(&sc->sysctl_ctx); 1794 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 1795 SYSCTL_STATIC_CHILDREN(_hw_mpr), OID_AUTO, tmpstr2, 1796 CTLFLAG_RD, 0, tmpstr); 1797 if (sc->sysctl_tree == NULL) 1798 return; 1799 sysctl_ctx = &sc->sysctl_ctx; 1800 sysctl_tree = sc->sysctl_tree; 1801 } 1802 1803 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1804 OID_AUTO, "debug_level", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 1805 sc, 0, mpr_debug_sysctl, "A", "mpr debug level"); 1806 1807 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1808 OID_AUTO, "disable_msix", CTLFLAG_RD, &sc->disable_msix, 0, 1809 "Disable the use of MSI-X interrupts"); 1810 1811 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1812 OID_AUTO, "max_msix", CTLFLAG_RD, &sc->max_msix, 0, 1813 "User-defined maximum number of MSIX queues"); 1814 1815 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1816 OID_AUTO, "msix_msgs", CTLFLAG_RD, &sc->msi_msgs, 0, 1817 "Negotiated number of MSIX queues"); 1818 1819 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1820 OID_AUTO, "max_reqframes", CTLFLAG_RD, &sc->max_reqframes, 0, 1821 "Total number of allocated request frames"); 1822 1823 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1824 OID_AUTO, "max_prireqframes", CTLFLAG_RD, &sc->max_prireqframes, 0, 1825 "Total number of allocated high priority request frames"); 1826 1827 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1828 OID_AUTO, "max_replyframes", CTLFLAG_RD, &sc->max_replyframes, 0, 1829 "Total number of allocated reply frames"); 1830 1831 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1832 OID_AUTO, "max_evtframes", CTLFLAG_RD, &sc->max_evtframes, 0, 1833 "Total number of event frames allocated"); 1834 1835 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1836 OID_AUTO, "firmware_version", CTLFLAG_RW, sc->fw_version, 1837 strlen(sc->fw_version), "firmware version"); 1838 1839 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1840 OID_AUTO, "driver_version", CTLFLAG_RW, MPR_DRIVER_VERSION, 1841 strlen(MPR_DRIVER_VERSION), "driver version"); 1842 1843 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1844 OID_AUTO, "io_cmds_active", CTLFLAG_RD, 1845 &sc->io_cmds_active, 0, "number of currently active commands"); 1846 1847 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1848 OID_AUTO, "io_cmds_highwater", CTLFLAG_RD, 1849 &sc->io_cmds_highwater, 0, "maximum active commands seen"); 1850 1851 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1852 OID_AUTO, "chain_free", CTLFLAG_RD, 1853 &sc->chain_free, 0, "number of free chain elements"); 1854 1855 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1856 OID_AUTO, "chain_free_lowwater", CTLFLAG_RD, 1857 &sc->chain_free_lowwater, 0,"lowest number of free chain elements"); 1858 1859 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1860 OID_AUTO, "max_chains", CTLFLAG_RD, 1861 &sc->max_chains, 0,"maximum chain frames that will be allocated"); 1862 1863 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1864 OID_AUTO, "max_io_pages", CTLFLAG_RD, 1865 &sc->max_io_pages, 0,"maximum pages to allow per I/O (if <1 use " 1866 "IOCFacts)"); 1867 1868 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1869 OID_AUTO, "enable_ssu", CTLFLAG_RW, &sc->enable_ssu, 0, 1870 "enable SSU to SATA SSD/HDD at shutdown"); 1871 1872 SYSCTL_ADD_UQUAD(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1873 OID_AUTO, "chain_alloc_fail", CTLFLAG_RD, 1874 &sc->chain_alloc_fail, "chain allocation failures"); 1875 1876 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1877 OID_AUTO, "spinup_wait_time", CTLFLAG_RD, 1878 &sc->spinup_wait_time, DEFAULT_SPINUP_WAIT, "seconds to wait for " 1879 "spinup after SATA ID error"); 1880 1881 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1882 OID_AUTO, "dump_reqs", CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_SKIP, sc, 0, 1883 mpr_dump_reqs, "I", "Dump Active Requests"); 1884 1885 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1886 OID_AUTO, "use_phy_num", CTLFLAG_RD, &sc->use_phynum, 0, 1887 "Use the phy number for enumeration"); 1888 1889 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1890 OID_AUTO, "prp_pages_free", CTLFLAG_RD, 1891 &sc->prp_pages_free, 0, "number of free PRP pages"); 1892 1893 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1894 OID_AUTO, "prp_pages_free_lowwater", CTLFLAG_RD, 1895 &sc->prp_pages_free_lowwater, 0,"lowest number of free PRP pages"); 1896 1897 SYSCTL_ADD_UQUAD(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1898 OID_AUTO, "prp_page_alloc_fail", CTLFLAG_RD, 1899 &sc->prp_page_alloc_fail, "PRP page allocation failures"); 1900 } 1901 1902 static struct mpr_debug_string { 1903 char *name; 1904 int flag; 1905 } mpr_debug_strings[] = { 1906 {"info", MPR_INFO}, 1907 {"fault", MPR_FAULT}, 1908 {"event", MPR_EVENT}, 1909 {"log", MPR_LOG}, 1910 {"recovery", MPR_RECOVERY}, 1911 {"error", MPR_ERROR}, 1912 {"init", MPR_INIT}, 1913 {"xinfo", MPR_XINFO}, 1914 {"user", MPR_USER}, 1915 {"mapping", MPR_MAPPING}, 1916 {"trace", MPR_TRACE} 1917 }; 1918 1919 enum mpr_debug_level_combiner { 1920 COMB_NONE, 1921 COMB_ADD, 1922 COMB_SUB 1923 }; 1924 1925 static int 1926 mpr_debug_sysctl(SYSCTL_HANDLER_ARGS) 1927 { 1928 struct mpr_softc *sc; 1929 struct mpr_debug_string *string; 1930 struct sbuf *sbuf; 1931 char *buffer; 1932 size_t sz; 1933 int i, len, debug, error; 1934 1935 sc = (struct mpr_softc *)arg1; 1936 1937 error = sysctl_wire_old_buffer(req, 0); 1938 if (error != 0) 1939 return (error); 1940 1941 sbuf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 1942 debug = sc->mpr_debug; 1943 1944 sbuf_printf(sbuf, "%#x", debug); 1945 1946 sz = sizeof(mpr_debug_strings) / sizeof(mpr_debug_strings[0]); 1947 for (i = 0; i < sz; i++) { 1948 string = &mpr_debug_strings[i]; 1949 if (debug & string->flag) 1950 sbuf_printf(sbuf, ",%s", string->name); 1951 } 1952 1953 error = sbuf_finish(sbuf); 1954 sbuf_delete(sbuf); 1955 1956 if (error || req->newptr == NULL) 1957 return (error); 1958 1959 len = req->newlen - req->newidx; 1960 if (len == 0) 1961 return (0); 1962 1963 buffer = malloc(len, M_MPR, M_ZERO|M_WAITOK); 1964 error = SYSCTL_IN(req, buffer, len); 1965 1966 mpr_parse_debug(sc, buffer); 1967 1968 free(buffer, M_MPR); 1969 return (error); 1970 } 1971 1972 static void 1973 mpr_parse_debug(struct mpr_softc *sc, char *list) 1974 { 1975 struct mpr_debug_string *string; 1976 enum mpr_debug_level_combiner op; 1977 char *token, *endtoken; 1978 size_t sz; 1979 int flags, i; 1980 1981 if (list == NULL || *list == '\0') 1982 return; 1983 1984 if (*list == '+') { 1985 op = COMB_ADD; 1986 list++; 1987 } else if (*list == '-') { 1988 op = COMB_SUB; 1989 list++; 1990 } else 1991 op = COMB_NONE; 1992 if (*list == '\0') 1993 return; 1994 1995 flags = 0; 1996 sz = sizeof(mpr_debug_strings) / sizeof(mpr_debug_strings[0]); 1997 while ((token = strsep(&list, ":,")) != NULL) { 1998 1999 /* Handle integer flags */ 2000 flags |= strtol(token, &endtoken, 0); 2001 if (token != endtoken) 2002 continue; 2003 2004 /* Handle text flags */ 2005 for (i = 0; i < sz; i++) { 2006 string = &mpr_debug_strings[i]; 2007 if (strcasecmp(token, string->name) == 0) { 2008 flags |= string->flag; 2009 break; 2010 } 2011 } 2012 } 2013 2014 switch (op) { 2015 case COMB_NONE: 2016 sc->mpr_debug = flags; 2017 break; 2018 case COMB_ADD: 2019 sc->mpr_debug |= flags; 2020 break; 2021 case COMB_SUB: 2022 sc->mpr_debug &= (~flags); 2023 break; 2024 } 2025 return; 2026 } 2027 2028 struct mpr_dumpreq_hdr { 2029 uint32_t smid; 2030 uint32_t state; 2031 uint32_t numframes; 2032 uint32_t deschi; 2033 uint32_t desclo; 2034 }; 2035 2036 static int 2037 mpr_dump_reqs(SYSCTL_HANDLER_ARGS) 2038 { 2039 struct mpr_softc *sc; 2040 struct mpr_chain *chain, *chain1; 2041 struct mpr_command *cm; 2042 struct mpr_dumpreq_hdr hdr; 2043 struct sbuf *sb; 2044 uint32_t smid, state; 2045 int i, numreqs, error = 0; 2046 2047 sc = (struct mpr_softc *)arg1; 2048 2049 if ((error = priv_check(curthread, PRIV_DRIVER)) != 0) { 2050 printf("priv check error %d\n", error); 2051 return (error); 2052 } 2053 2054 state = MPR_CM_STATE_INQUEUE; 2055 smid = 1; 2056 numreqs = sc->num_reqs; 2057 2058 if (req->newptr != NULL) 2059 return (EINVAL); 2060 2061 if (smid == 0 || smid > sc->num_reqs) 2062 return (EINVAL); 2063 if (numreqs <= 0 || (numreqs + smid > sc->num_reqs)) 2064 numreqs = sc->num_reqs; 2065 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 2066 2067 /* Best effort, no locking */ 2068 for (i = smid; i < numreqs; i++) { 2069 cm = &sc->commands[i]; 2070 if (cm->cm_state != state) 2071 continue; 2072 hdr.smid = i; 2073 hdr.state = cm->cm_state; 2074 hdr.numframes = 1; 2075 hdr.deschi = cm->cm_desc.Words.High; 2076 hdr.desclo = cm->cm_desc.Words.Low; 2077 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, 2078 chain1) 2079 hdr.numframes++; 2080 sbuf_bcat(sb, &hdr, sizeof(hdr)); 2081 sbuf_bcat(sb, cm->cm_req, 128); 2082 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, 2083 chain1) 2084 sbuf_bcat(sb, chain->chain, 128); 2085 } 2086 2087 error = sbuf_finish(sb); 2088 sbuf_delete(sb); 2089 return (error); 2090 } 2091 2092 int 2093 mpr_attach(struct mpr_softc *sc) 2094 { 2095 int error; 2096 2097 MPR_FUNCTRACE(sc); 2098 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 2099 2100 mtx_init(&sc->mpr_mtx, "MPR lock", NULL, MTX_DEF); 2101 callout_init_mtx(&sc->periodic, &sc->mpr_mtx, 0); 2102 callout_init_mtx(&sc->device_check_callout, &sc->mpr_mtx, 0); 2103 TAILQ_INIT(&sc->event_list); 2104 timevalclear(&sc->lastfail); 2105 2106 if ((error = mpr_transition_ready(sc)) != 0) { 2107 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 2108 "Failed to transition ready\n"); 2109 return (error); 2110 } 2111 2112 sc->facts = malloc(sizeof(MPI2_IOC_FACTS_REPLY), M_MPR, 2113 M_ZERO|M_NOWAIT); 2114 if (!sc->facts) { 2115 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 2116 "Cannot allocate memory, exit\n"); 2117 return (ENOMEM); 2118 } 2119 2120 /* 2121 * Get IOC Facts and allocate all structures based on this information. 2122 * A Diag Reset will also call mpr_iocfacts_allocate and re-read the IOC 2123 * Facts. If relevant values have changed in IOC Facts, this function 2124 * will free all of the memory based on IOC Facts and reallocate that 2125 * memory. If this fails, any allocated memory should already be freed. 2126 */ 2127 if ((error = mpr_iocfacts_allocate(sc, TRUE)) != 0) { 2128 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC Facts allocation " 2129 "failed with error %d\n", error); 2130 return (error); 2131 } 2132 2133 /* Start the periodic watchdog check on the IOC Doorbell */ 2134 mpr_periodic(sc); 2135 2136 /* 2137 * The portenable will kick off discovery events that will drive the 2138 * rest of the initialization process. The CAM/SAS module will 2139 * hold up the boot sequence until discovery is complete. 2140 */ 2141 sc->mpr_ich.ich_func = mpr_startup; 2142 sc->mpr_ich.ich_arg = sc; 2143 if (config_intrhook_establish(&sc->mpr_ich) != 0) { 2144 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 2145 "Cannot establish MPR config hook\n"); 2146 error = EINVAL; 2147 } 2148 2149 /* 2150 * Allow IR to shutdown gracefully when shutdown occurs. 2151 */ 2152 sc->shutdown_eh = EVENTHANDLER_REGISTER(shutdown_final, 2153 mprsas_ir_shutdown, sc, SHUTDOWN_PRI_DEFAULT); 2154 2155 if (sc->shutdown_eh == NULL) 2156 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 2157 "shutdown event registration failed\n"); 2158 2159 mpr_setup_sysctl(sc); 2160 2161 sc->mpr_flags |= MPR_FLAGS_ATTACH_DONE; 2162 mpr_dprint(sc, MPR_INIT, "%s exit error= %d\n", __func__, error); 2163 2164 return (error); 2165 } 2166 2167 /* Run through any late-start handlers. */ 2168 static void 2169 mpr_startup(void *arg) 2170 { 2171 struct mpr_softc *sc; 2172 2173 sc = (struct mpr_softc *)arg; 2174 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 2175 2176 mpr_lock(sc); 2177 mpr_unmask_intr(sc); 2178 2179 /* initialize device mapping tables */ 2180 mpr_base_static_config_pages(sc); 2181 mpr_mapping_initialize(sc); 2182 mprsas_startup(sc); 2183 mpr_unlock(sc); 2184 2185 mpr_dprint(sc, MPR_INIT, "disestablish config intrhook\n"); 2186 config_intrhook_disestablish(&sc->mpr_ich); 2187 sc->mpr_ich.ich_arg = NULL; 2188 2189 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 2190 } 2191 2192 /* Periodic watchdog. Is called with the driver lock already held. */ 2193 static void 2194 mpr_periodic(void *arg) 2195 { 2196 struct mpr_softc *sc; 2197 uint32_t db; 2198 2199 sc = (struct mpr_softc *)arg; 2200 if (sc->mpr_flags & MPR_FLAGS_SHUTDOWN) 2201 return; 2202 2203 db = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 2204 if ((db & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 2205 if ((db & MPI2_DOORBELL_FAULT_CODE_MASK) == 2206 IFAULT_IOP_OVER_TEMP_THRESHOLD_EXCEEDED) { 2207 panic("TEMPERATURE FAULT: STOPPING."); 2208 } 2209 mpr_dprint(sc, MPR_FAULT, "IOC Fault 0x%08x, Resetting\n", db); 2210 mpr_reinit(sc); 2211 } 2212 2213 callout_reset(&sc->periodic, MPR_PERIODIC_DELAY * hz, mpr_periodic, sc); 2214 } 2215 2216 static void 2217 mpr_log_evt_handler(struct mpr_softc *sc, uintptr_t data, 2218 MPI2_EVENT_NOTIFICATION_REPLY *event) 2219 { 2220 MPI2_EVENT_DATA_LOG_ENTRY_ADDED *entry; 2221 2222 MPR_DPRINT_EVENT(sc, generic, event); 2223 2224 switch (event->Event) { 2225 case MPI2_EVENT_LOG_DATA: 2226 mpr_dprint(sc, MPR_EVENT, "MPI2_EVENT_LOG_DATA:\n"); 2227 if (sc->mpr_debug & MPR_EVENT) 2228 hexdump(event->EventData, event->EventDataLength, NULL, 2229 0); 2230 break; 2231 case MPI2_EVENT_LOG_ENTRY_ADDED: 2232 entry = (MPI2_EVENT_DATA_LOG_ENTRY_ADDED *)event->EventData; 2233 mpr_dprint(sc, MPR_EVENT, "MPI2_EVENT_LOG_ENTRY_ADDED event " 2234 "0x%x Sequence %d:\n", entry->LogEntryQualifier, 2235 entry->LogSequence); 2236 break; 2237 default: 2238 break; 2239 } 2240 return; 2241 } 2242 2243 static int 2244 mpr_attach_log(struct mpr_softc *sc) 2245 { 2246 uint8_t events[16]; 2247 2248 bzero(events, 16); 2249 setbit(events, MPI2_EVENT_LOG_DATA); 2250 setbit(events, MPI2_EVENT_LOG_ENTRY_ADDED); 2251 2252 mpr_register_events(sc, events, mpr_log_evt_handler, NULL, 2253 &sc->mpr_log_eh); 2254 2255 return (0); 2256 } 2257 2258 static int 2259 mpr_detach_log(struct mpr_softc *sc) 2260 { 2261 2262 if (sc->mpr_log_eh != NULL) 2263 mpr_deregister_events(sc, sc->mpr_log_eh); 2264 return (0); 2265 } 2266 2267 /* 2268 * Free all of the driver resources and detach submodules. Should be called 2269 * without the lock held. 2270 */ 2271 int 2272 mpr_free(struct mpr_softc *sc) 2273 { 2274 int error; 2275 2276 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 2277 /* Turn off the watchdog */ 2278 mpr_lock(sc); 2279 sc->mpr_flags |= MPR_FLAGS_SHUTDOWN; 2280 mpr_unlock(sc); 2281 /* Lock must not be held for this */ 2282 callout_drain(&sc->periodic); 2283 callout_drain(&sc->device_check_callout); 2284 2285 if (((error = mpr_detach_log(sc)) != 0) || 2286 ((error = mpr_detach_sas(sc)) != 0)) { 2287 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "failed to detach " 2288 "subsystems, error= %d, exit\n", error); 2289 return (error); 2290 } 2291 2292 mpr_detach_user(sc); 2293 2294 /* Put the IOC back in the READY state. */ 2295 mpr_lock(sc); 2296 if ((error = mpr_transition_ready(sc)) != 0) { 2297 mpr_unlock(sc); 2298 return (error); 2299 } 2300 mpr_unlock(sc); 2301 2302 if (sc->facts != NULL) 2303 free(sc->facts, M_MPR); 2304 2305 /* 2306 * Free all buffers that are based on IOC Facts. A Diag Reset may need 2307 * to free these buffers too. 2308 */ 2309 mpr_iocfacts_free(sc); 2310 2311 if (sc->sysctl_tree != NULL) 2312 sysctl_ctx_free(&sc->sysctl_ctx); 2313 2314 /* Deregister the shutdown function */ 2315 if (sc->shutdown_eh != NULL) 2316 EVENTHANDLER_DEREGISTER(shutdown_final, sc->shutdown_eh); 2317 2318 mtx_destroy(&sc->mpr_mtx); 2319 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 2320 2321 return (0); 2322 } 2323 2324 static __inline void 2325 mpr_complete_command(struct mpr_softc *sc, struct mpr_command *cm) 2326 { 2327 MPR_FUNCTRACE(sc); 2328 2329 if (cm == NULL) { 2330 mpr_dprint(sc, MPR_ERROR, "Completing NULL command\n"); 2331 return; 2332 } 2333 2334 cm->cm_state = MPR_CM_STATE_BUSY; 2335 if (cm->cm_flags & MPR_CM_FLAGS_POLLED) 2336 cm->cm_flags |= MPR_CM_FLAGS_COMPLETE; 2337 2338 if (cm->cm_complete != NULL) { 2339 mpr_dprint(sc, MPR_TRACE, 2340 "%s cm %p calling cm_complete %p data %p reply %p\n", 2341 __func__, cm, cm->cm_complete, cm->cm_complete_data, 2342 cm->cm_reply); 2343 cm->cm_complete(sc, cm); 2344 } 2345 2346 if (cm->cm_flags & MPR_CM_FLAGS_WAKEUP) { 2347 mpr_dprint(sc, MPR_TRACE, "waking up %p\n", cm); 2348 wakeup(cm); 2349 } 2350 2351 if (sc->io_cmds_active != 0) { 2352 sc->io_cmds_active--; 2353 } else { 2354 mpr_dprint(sc, MPR_ERROR, "Warning: io_cmds_active is " 2355 "out of sync - resynching to 0\n"); 2356 } 2357 } 2358 2359 static void 2360 mpr_sas_log_info(struct mpr_softc *sc , u32 log_info) 2361 { 2362 union loginfo_type { 2363 u32 loginfo; 2364 struct { 2365 u32 subcode:16; 2366 u32 code:8; 2367 u32 originator:4; 2368 u32 bus_type:4; 2369 } dw; 2370 }; 2371 union loginfo_type sas_loginfo; 2372 char *originator_str = NULL; 2373 2374 sas_loginfo.loginfo = log_info; 2375 if (sas_loginfo.dw.bus_type != 3 /*SAS*/) 2376 return; 2377 2378 /* each nexus loss loginfo */ 2379 if (log_info == 0x31170000) 2380 return; 2381 2382 /* eat the loginfos associated with task aborts */ 2383 if ((log_info == 30050000) || (log_info == 0x31140000) || 2384 (log_info == 0x31130000)) 2385 return; 2386 2387 switch (sas_loginfo.dw.originator) { 2388 case 0: 2389 originator_str = "IOP"; 2390 break; 2391 case 1: 2392 originator_str = "PL"; 2393 break; 2394 case 2: 2395 originator_str = "IR"; 2396 break; 2397 } 2398 2399 mpr_dprint(sc, MPR_LOG, "log_info(0x%08x): originator(%s), " 2400 "code(0x%02x), sub_code(0x%04x)\n", log_info, originator_str, 2401 sas_loginfo.dw.code, sas_loginfo.dw.subcode); 2402 } 2403 2404 static void 2405 mpr_display_reply_info(struct mpr_softc *sc, uint8_t *reply) 2406 { 2407 MPI2DefaultReply_t *mpi_reply; 2408 u16 sc_status; 2409 2410 mpi_reply = (MPI2DefaultReply_t*)reply; 2411 sc_status = le16toh(mpi_reply->IOCStatus); 2412 if (sc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) 2413 mpr_sas_log_info(sc, le32toh(mpi_reply->IOCLogInfo)); 2414 } 2415 2416 void 2417 mpr_intr(void *data) 2418 { 2419 struct mpr_softc *sc; 2420 uint32_t status; 2421 2422 sc = (struct mpr_softc *)data; 2423 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2424 2425 /* 2426 * Check interrupt status register to flush the bus. This is 2427 * needed for both INTx interrupts and driver-driven polling 2428 */ 2429 status = mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET); 2430 if ((status & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) == 0) 2431 return; 2432 2433 mpr_lock(sc); 2434 mpr_intr_locked(data); 2435 mpr_unlock(sc); 2436 return; 2437 } 2438 2439 /* 2440 * In theory, MSI/MSIX interrupts shouldn't need to read any registers on the 2441 * chip. Hopefully this theory is correct. 2442 */ 2443 void 2444 mpr_intr_msi(void *data) 2445 { 2446 struct mpr_softc *sc; 2447 2448 sc = (struct mpr_softc *)data; 2449 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2450 mpr_lock(sc); 2451 mpr_intr_locked(data); 2452 mpr_unlock(sc); 2453 return; 2454 } 2455 2456 /* 2457 * The locking is overly broad and simplistic, but easy to deal with for now. 2458 */ 2459 void 2460 mpr_intr_locked(void *data) 2461 { 2462 MPI2_REPLY_DESCRIPTORS_UNION *desc; 2463 MPI2_DIAG_RELEASE_REPLY *rel_rep; 2464 mpr_fw_diagnostic_buffer_t *pBuffer; 2465 struct mpr_softc *sc; 2466 uint64_t tdesc; 2467 struct mpr_command *cm = NULL; 2468 uint8_t flags; 2469 u_int pq; 2470 2471 sc = (struct mpr_softc *)data; 2472 2473 pq = sc->replypostindex; 2474 mpr_dprint(sc, MPR_TRACE, 2475 "%s sc %p starting with replypostindex %u\n", 2476 __func__, sc, sc->replypostindex); 2477 2478 for ( ;; ) { 2479 cm = NULL; 2480 desc = &sc->post_queue[sc->replypostindex]; 2481 2482 /* 2483 * Copy and clear out the descriptor so that any reentry will 2484 * immediately know that this descriptor has already been 2485 * looked at. There is unfortunate casting magic because the 2486 * MPI API doesn't have a cardinal 64bit type. 2487 */ 2488 tdesc = 0xffffffffffffffff; 2489 tdesc = atomic_swap_64((uint64_t *)desc, tdesc); 2490 desc = (MPI2_REPLY_DESCRIPTORS_UNION *)&tdesc; 2491 2492 flags = desc->Default.ReplyFlags & 2493 MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 2494 if ((flags == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) || 2495 (le32toh(desc->Words.High) == 0xffffffff)) 2496 break; 2497 2498 /* increment the replypostindex now, so that event handlers 2499 * and cm completion handlers which decide to do a diag 2500 * reset can zero it without it getting incremented again 2501 * afterwards, and we break out of this loop on the next 2502 * iteration since the reply post queue has been cleared to 2503 * 0xFF and all descriptors look unused (which they are). 2504 */ 2505 if (++sc->replypostindex >= sc->pqdepth) 2506 sc->replypostindex = 0; 2507 2508 switch (flags) { 2509 case MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS: 2510 case MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS: 2511 case MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS: 2512 cm = &sc->commands[le16toh(desc->SCSIIOSuccess.SMID)]; 2513 KASSERT(cm->cm_state == MPR_CM_STATE_INQUEUE, 2514 ("command not inqueue\n")); 2515 cm->cm_state = MPR_CM_STATE_BUSY; 2516 cm->cm_reply = NULL; 2517 break; 2518 case MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY: 2519 { 2520 uint32_t baddr; 2521 uint8_t *reply; 2522 2523 /* 2524 * Re-compose the reply address from the address 2525 * sent back from the chip. The ReplyFrameAddress 2526 * is the lower 32 bits of the physical address of 2527 * particular reply frame. Convert that address to 2528 * host format, and then use that to provide the 2529 * offset against the virtual address base 2530 * (sc->reply_frames). 2531 */ 2532 baddr = le32toh(desc->AddressReply.ReplyFrameAddress); 2533 reply = sc->reply_frames + 2534 (baddr - ((uint32_t)sc->reply_busaddr)); 2535 /* 2536 * Make sure the reply we got back is in a valid 2537 * range. If not, go ahead and panic here, since 2538 * we'll probably panic as soon as we deference the 2539 * reply pointer anyway. 2540 */ 2541 if ((reply < sc->reply_frames) 2542 || (reply > (sc->reply_frames + 2543 (sc->fqdepth * sc->replyframesz)))) { 2544 printf("%s: WARNING: reply %p out of range!\n", 2545 __func__, reply); 2546 printf("%s: reply_frames %p, fqdepth %d, " 2547 "frame size %d\n", __func__, 2548 sc->reply_frames, sc->fqdepth, 2549 sc->replyframesz); 2550 printf("%s: baddr %#x,\n", __func__, baddr); 2551 /* LSI-TODO. See Linux Code for Graceful exit */ 2552 panic("Reply address out of range"); 2553 } 2554 if (le16toh(desc->AddressReply.SMID) == 0) { 2555 if (((MPI2_DEFAULT_REPLY *)reply)->Function == 2556 MPI2_FUNCTION_DIAG_BUFFER_POST) { 2557 /* 2558 * If SMID is 0 for Diag Buffer Post, 2559 * this implies that the reply is due to 2560 * a release function with a status that 2561 * the buffer has been released. Set 2562 * the buffer flags accordingly. 2563 */ 2564 rel_rep = 2565 (MPI2_DIAG_RELEASE_REPLY *)reply; 2566 if ((le16toh(rel_rep->IOCStatus) & 2567 MPI2_IOCSTATUS_MASK) == 2568 MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) 2569 { 2570 pBuffer = 2571 &sc->fw_diag_buffer_list[ 2572 rel_rep->BufferType]; 2573 pBuffer->valid_data = TRUE; 2574 pBuffer->owned_by_firmware = 2575 FALSE; 2576 pBuffer->immediate = FALSE; 2577 } 2578 } else 2579 mpr_dispatch_event(sc, baddr, 2580 (MPI2_EVENT_NOTIFICATION_REPLY *) 2581 reply); 2582 } else { 2583 cm = &sc->commands[ 2584 le16toh(desc->AddressReply.SMID)]; 2585 if (cm->cm_state == MPR_CM_STATE_INQUEUE) { 2586 cm->cm_reply = reply; 2587 cm->cm_reply_data = 2588 le32toh(desc->AddressReply. 2589 ReplyFrameAddress); 2590 } else { 2591 mpr_dprint(sc, MPR_RECOVERY, 2592 "Bad state for ADDRESS_REPLY status," 2593 " ignoring state %d cm %p\n", 2594 cm->cm_state, cm); 2595 } 2596 } 2597 break; 2598 } 2599 case MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS: 2600 case MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER: 2601 case MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS: 2602 default: 2603 /* Unhandled */ 2604 mpr_dprint(sc, MPR_ERROR, "Unhandled reply 0x%x\n", 2605 desc->Default.ReplyFlags); 2606 cm = NULL; 2607 break; 2608 } 2609 2610 if (cm != NULL) { 2611 // Print Error reply frame 2612 if (cm->cm_reply) 2613 mpr_display_reply_info(sc,cm->cm_reply); 2614 mpr_complete_command(sc, cm); 2615 } 2616 } 2617 2618 if (pq != sc->replypostindex) { 2619 mpr_dprint(sc, MPR_TRACE, "%s sc %p writing postindex %d\n", 2620 __func__, sc, sc->replypostindex); 2621 mpr_regwrite(sc, MPI2_REPLY_POST_HOST_INDEX_OFFSET, 2622 sc->replypostindex); 2623 } 2624 2625 return; 2626 } 2627 2628 static void 2629 mpr_dispatch_event(struct mpr_softc *sc, uintptr_t data, 2630 MPI2_EVENT_NOTIFICATION_REPLY *reply) 2631 { 2632 struct mpr_event_handle *eh; 2633 int event, handled = 0; 2634 2635 event = le16toh(reply->Event); 2636 TAILQ_FOREACH(eh, &sc->event_list, eh_list) { 2637 if (isset(eh->mask, event)) { 2638 eh->callback(sc, data, reply); 2639 handled++; 2640 } 2641 } 2642 2643 if (handled == 0) 2644 mpr_dprint(sc, MPR_EVENT, "Unhandled event 0x%x\n", 2645 le16toh(event)); 2646 2647 /* 2648 * This is the only place that the event/reply should be freed. 2649 * Anything wanting to hold onto the event data should have 2650 * already copied it into their own storage. 2651 */ 2652 mpr_free_reply(sc, data); 2653 } 2654 2655 static void 2656 mpr_reregister_events_complete(struct mpr_softc *sc, struct mpr_command *cm) 2657 { 2658 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2659 2660 if (cm->cm_reply) 2661 MPR_DPRINT_EVENT(sc, generic, 2662 (MPI2_EVENT_NOTIFICATION_REPLY *)cm->cm_reply); 2663 2664 mpr_free_command(sc, cm); 2665 2666 /* next, send a port enable */ 2667 mprsas_startup(sc); 2668 } 2669 2670 /* 2671 * For both register_events and update_events, the caller supplies a bitmap 2672 * of events that it _wants_. These functions then turn that into a bitmask 2673 * suitable for the controller. 2674 */ 2675 int 2676 mpr_register_events(struct mpr_softc *sc, uint8_t *mask, 2677 mpr_evt_callback_t *cb, void *data, struct mpr_event_handle **handle) 2678 { 2679 struct mpr_event_handle *eh; 2680 int error = 0; 2681 2682 eh = malloc(sizeof(struct mpr_event_handle), M_MPR, M_WAITOK|M_ZERO); 2683 if (!eh) { 2684 mpr_dprint(sc, MPR_EVENT|MPR_ERROR, 2685 "Cannot allocate event memory\n"); 2686 return (ENOMEM); 2687 } 2688 eh->callback = cb; 2689 eh->data = data; 2690 TAILQ_INSERT_TAIL(&sc->event_list, eh, eh_list); 2691 if (mask != NULL) 2692 error = mpr_update_events(sc, eh, mask); 2693 *handle = eh; 2694 2695 return (error); 2696 } 2697 2698 int 2699 mpr_update_events(struct mpr_softc *sc, struct mpr_event_handle *handle, 2700 uint8_t *mask) 2701 { 2702 MPI2_EVENT_NOTIFICATION_REQUEST *evtreq; 2703 MPI2_EVENT_NOTIFICATION_REPLY *reply = NULL; 2704 struct mpr_command *cm = NULL; 2705 struct mpr_event_handle *eh; 2706 int error, i; 2707 2708 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2709 2710 if ((mask != NULL) && (handle != NULL)) 2711 bcopy(mask, &handle->mask[0], 16); 2712 memset(sc->event_mask, 0xff, 16); 2713 2714 TAILQ_FOREACH(eh, &sc->event_list, eh_list) { 2715 for (i = 0; i < 16; i++) 2716 sc->event_mask[i] &= ~eh->mask[i]; 2717 } 2718 2719 if ((cm = mpr_alloc_command(sc)) == NULL) 2720 return (EBUSY); 2721 evtreq = (MPI2_EVENT_NOTIFICATION_REQUEST *)cm->cm_req; 2722 evtreq->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 2723 evtreq->MsgFlags = 0; 2724 evtreq->SASBroadcastPrimitiveMasks = 0; 2725 #ifdef MPR_DEBUG_ALL_EVENTS 2726 { 2727 u_char fullmask[16]; 2728 memset(fullmask, 0x00, 16); 2729 bcopy(fullmask, (uint8_t *)&evtreq->EventMasks, 16); 2730 } 2731 #else 2732 bcopy(sc->event_mask, (uint8_t *)&evtreq->EventMasks, 16); 2733 #endif 2734 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 2735 cm->cm_data = NULL; 2736 2737 error = mpr_request_polled(sc, &cm); 2738 if (cm != NULL) 2739 reply = (MPI2_EVENT_NOTIFICATION_REPLY *)cm->cm_reply; 2740 if ((reply == NULL) || 2741 (reply->IOCStatus & MPI2_IOCSTATUS_MASK) != MPI2_IOCSTATUS_SUCCESS) 2742 error = ENXIO; 2743 2744 if (reply) 2745 MPR_DPRINT_EVENT(sc, generic, reply); 2746 2747 mpr_dprint(sc, MPR_TRACE, "%s finished error %d\n", __func__, error); 2748 2749 if (cm != NULL) 2750 mpr_free_command(sc, cm); 2751 return (error); 2752 } 2753 2754 static int 2755 mpr_reregister_events(struct mpr_softc *sc) 2756 { 2757 MPI2_EVENT_NOTIFICATION_REQUEST *evtreq; 2758 struct mpr_command *cm; 2759 struct mpr_event_handle *eh; 2760 int error, i; 2761 2762 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2763 2764 /* first, reregister events */ 2765 2766 memset(sc->event_mask, 0xff, 16); 2767 2768 TAILQ_FOREACH(eh, &sc->event_list, eh_list) { 2769 for (i = 0; i < 16; i++) 2770 sc->event_mask[i] &= ~eh->mask[i]; 2771 } 2772 2773 if ((cm = mpr_alloc_command(sc)) == NULL) 2774 return (EBUSY); 2775 evtreq = (MPI2_EVENT_NOTIFICATION_REQUEST *)cm->cm_req; 2776 evtreq->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 2777 evtreq->MsgFlags = 0; 2778 evtreq->SASBroadcastPrimitiveMasks = 0; 2779 #ifdef MPR_DEBUG_ALL_EVENTS 2780 { 2781 u_char fullmask[16]; 2782 memset(fullmask, 0x00, 16); 2783 bcopy(fullmask, (uint8_t *)&evtreq->EventMasks, 16); 2784 } 2785 #else 2786 bcopy(sc->event_mask, (uint8_t *)&evtreq->EventMasks, 16); 2787 #endif 2788 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 2789 cm->cm_data = NULL; 2790 cm->cm_complete = mpr_reregister_events_complete; 2791 2792 error = mpr_map_command(sc, cm); 2793 2794 mpr_dprint(sc, MPR_TRACE, "%s finished with error %d\n", __func__, 2795 error); 2796 return (error); 2797 } 2798 2799 int 2800 mpr_deregister_events(struct mpr_softc *sc, struct mpr_event_handle *handle) 2801 { 2802 2803 TAILQ_REMOVE(&sc->event_list, handle, eh_list); 2804 free(handle, M_MPR); 2805 return (mpr_update_events(sc, NULL, NULL)); 2806 } 2807 2808 /** 2809 * mpr_build_nvme_prp - This function is called for NVMe end devices to build a 2810 * native SGL (NVMe PRP). The native SGL is built starting in the first PRP entry 2811 * of the NVMe message (PRP1). If the data buffer is small enough to be described 2812 * entirely using PRP1, then PRP2 is not used. If needed, PRP2 is used to 2813 * describe a larger data buffer. If the data buffer is too large to describe 2814 * using the two PRP entriess inside the NVMe message, then PRP1 describes the 2815 * first data memory segment, and PRP2 contains a pointer to a PRP list located 2816 * elsewhere in memory to describe the remaining data memory segments. The PRP 2817 * list will be contiguous. 2818 2819 * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP 2820 * consists of a list of PRP entries to describe a number of noncontigous 2821 * physical memory segments as a single memory buffer, just as a SGL does. Note 2822 * however, that this function is only used by the IOCTL call, so the memory 2823 * given will be guaranteed to be contiguous. There is no need to translate 2824 * non-contiguous SGL into a PRP in this case. All PRPs will describe contiguous 2825 * space that is one page size each. 2826 * 2827 * Each NVMe message contains two PRP entries. The first (PRP1) either contains 2828 * a PRP list pointer or a PRP element, depending upon the command. PRP2 contains 2829 * the second PRP element if the memory being described fits within 2 PRP 2830 * entries, or a PRP list pointer if the PRP spans more than two entries. 2831 * 2832 * A PRP list pointer contains the address of a PRP list, structured as a linear 2833 * array of PRP entries. Each PRP entry in this list describes a segment of 2834 * physical memory. 2835 * 2836 * Each 64-bit PRP entry comprises an address and an offset field. The address 2837 * always points to the beginning of a PAGE_SIZE physical memory page, and the 2838 * offset describes where within that page the memory segment begins. Only the 2839 * first element in a PRP list may contain a non-zero offest, implying that all 2840 * memory segments following the first begin at the start of a PAGE_SIZE page. 2841 * 2842 * Each PRP element normally describes a chunck of PAGE_SIZE physical memory, 2843 * with exceptions for the first and last elements in the list. If the memory 2844 * being described by the list begins at a non-zero offset within the first page, 2845 * then the first PRP element will contain a non-zero offset indicating where the 2846 * region begins within the page. The last memory segment may end before the end 2847 * of the PAGE_SIZE segment, depending upon the overall size of the memory being 2848 * described by the PRP list. 2849 * 2850 * Since PRP entries lack any indication of size, the overall data buffer length 2851 * is used to determine where the end of the data memory buffer is located, and 2852 * how many PRP entries are required to describe it. 2853 * 2854 * Returns nothing. 2855 */ 2856 void 2857 mpr_build_nvme_prp(struct mpr_softc *sc, struct mpr_command *cm, 2858 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, void *data, 2859 uint32_t data_in_sz, uint32_t data_out_sz) 2860 { 2861 int prp_size = PRP_ENTRY_SIZE; 2862 uint64_t *prp_entry, *prp1_entry, *prp2_entry; 2863 uint64_t *prp_entry_phys, *prp_page, *prp_page_phys; 2864 uint32_t offset, entry_len, page_mask_result, page_mask; 2865 bus_addr_t paddr; 2866 size_t length; 2867 struct mpr_prp_page *prp_page_info = NULL; 2868 2869 /* 2870 * Not all commands require a data transfer. If no data, just return 2871 * without constructing any PRP. 2872 */ 2873 if (!data_in_sz && !data_out_sz) 2874 return; 2875 2876 /* 2877 * Set pointers to PRP1 and PRP2, which are in the NVMe command. PRP1 is 2878 * located at a 24 byte offset from the start of the NVMe command. Then 2879 * set the current PRP entry pointer to PRP1. 2880 */ 2881 prp1_entry = (uint64_t *)(nvme_encap_request->NVMe_Command + 2882 NVME_CMD_PRP1_OFFSET); 2883 prp2_entry = (uint64_t *)(nvme_encap_request->NVMe_Command + 2884 NVME_CMD_PRP2_OFFSET); 2885 prp_entry = prp1_entry; 2886 2887 /* 2888 * For the PRP entries, use the specially allocated buffer of 2889 * contiguous memory. PRP Page allocation failures should not happen 2890 * because there should be enough PRP page buffers to account for the 2891 * possible NVMe QDepth. 2892 */ 2893 prp_page_info = mpr_alloc_prp_page(sc); 2894 KASSERT(prp_page_info != NULL, ("%s: There are no PRP Pages left to be " 2895 "used for building a native NVMe SGL.\n", __func__)); 2896 prp_page = (uint64_t *)prp_page_info->prp_page; 2897 prp_page_phys = (uint64_t *)(uintptr_t)prp_page_info->prp_page_busaddr; 2898 2899 /* 2900 * Insert the allocated PRP page into the command's PRP page list. This 2901 * will be freed when the command is freed. 2902 */ 2903 TAILQ_INSERT_TAIL(&cm->cm_prp_page_list, prp_page_info, prp_page_link); 2904 2905 /* 2906 * Check if we are within 1 entry of a page boundary we don't want our 2907 * first entry to be a PRP List entry. 2908 */ 2909 page_mask = PAGE_SIZE - 1; 2910 page_mask_result = (uintptr_t)((uint8_t *)prp_page + prp_size) & 2911 page_mask; 2912 if (!page_mask_result) 2913 { 2914 /* Bump up to next page boundary. */ 2915 prp_page = (uint64_t *)((uint8_t *)prp_page + prp_size); 2916 prp_page_phys = (uint64_t *)((uint8_t *)prp_page_phys + 2917 prp_size); 2918 } 2919 2920 /* 2921 * Set PRP physical pointer, which initially points to the current PRP 2922 * DMA memory page. 2923 */ 2924 prp_entry_phys = prp_page_phys; 2925 2926 /* Get physical address and length of the data buffer. */ 2927 paddr = (bus_addr_t)(uintptr_t)data; 2928 if (data_in_sz) 2929 length = data_in_sz; 2930 else 2931 length = data_out_sz; 2932 2933 /* Loop while the length is not zero. */ 2934 while (length) 2935 { 2936 /* 2937 * Check if we need to put a list pointer here if we are at page 2938 * boundary - prp_size (8 bytes). 2939 */ 2940 page_mask_result = (uintptr_t)((uint8_t *)prp_entry_phys + 2941 prp_size) & page_mask; 2942 if (!page_mask_result) 2943 { 2944 /* 2945 * This is the last entry in a PRP List, so we need to 2946 * put a PRP list pointer here. What this does is: 2947 * - bump the current memory pointer to the next 2948 * address, which will be the next full page. 2949 * - set the PRP Entry to point to that page. This is 2950 * now the PRP List pointer. 2951 * - bump the PRP Entry pointer the start of the next 2952 * page. Since all of this PRP memory is contiguous, 2953 * no need to get a new page - it's just the next 2954 * address. 2955 */ 2956 prp_entry_phys++; 2957 *prp_entry = 2958 htole64((uint64_t)(uintptr_t)prp_entry_phys); 2959 prp_entry++; 2960 } 2961 2962 /* Need to handle if entry will be part of a page. */ 2963 offset = (uint32_t)paddr & page_mask; 2964 entry_len = PAGE_SIZE - offset; 2965 2966 if (prp_entry == prp1_entry) 2967 { 2968 /* 2969 * Must fill in the first PRP pointer (PRP1) before 2970 * moving on. 2971 */ 2972 *prp1_entry = htole64((uint64_t)paddr); 2973 2974 /* 2975 * Now point to the second PRP entry within the 2976 * command (PRP2). 2977 */ 2978 prp_entry = prp2_entry; 2979 } 2980 else if (prp_entry == prp2_entry) 2981 { 2982 /* 2983 * Should the PRP2 entry be a PRP List pointer or just a 2984 * regular PRP pointer? If there is more than one more 2985 * page of data, must use a PRP List pointer. 2986 */ 2987 if (length > PAGE_SIZE) 2988 { 2989 /* 2990 * PRP2 will contain a PRP List pointer because 2991 * more PRP's are needed with this command. The 2992 * list will start at the beginning of the 2993 * contiguous buffer. 2994 */ 2995 *prp2_entry = 2996 htole64( 2997 (uint64_t)(uintptr_t)prp_entry_phys); 2998 2999 /* 3000 * The next PRP Entry will be the start of the 3001 * first PRP List. 3002 */ 3003 prp_entry = prp_page; 3004 } 3005 else 3006 { 3007 /* 3008 * After this, the PRP Entries are complete. 3009 * This command uses 2 PRP's and no PRP list. 3010 */ 3011 *prp2_entry = htole64((uint64_t)paddr); 3012 } 3013 } 3014 else 3015 { 3016 /* 3017 * Put entry in list and bump the addresses. 3018 * 3019 * After PRP1 and PRP2 are filled in, this will fill in 3020 * all remaining PRP entries in a PRP List, one per each 3021 * time through the loop. 3022 */ 3023 *prp_entry = htole64((uint64_t)paddr); 3024 prp_entry++; 3025 prp_entry_phys++; 3026 } 3027 3028 /* 3029 * Bump the phys address of the command's data buffer by the 3030 * entry_len. 3031 */ 3032 paddr += entry_len; 3033 3034 /* Decrement length accounting for last partial page. */ 3035 if (entry_len > length) 3036 length = 0; 3037 else 3038 length -= entry_len; 3039 } 3040 } 3041 3042 /* 3043 * mpr_check_pcie_native_sgl - This function is called for PCIe end devices to 3044 * determine if the driver needs to build a native SGL. If so, that native SGL 3045 * is built in the contiguous buffers allocated especially for PCIe SGL 3046 * creation. If the driver will not build a native SGL, return TRUE and a 3047 * normal IEEE SGL will be built. Currently this routine supports NVMe devices 3048 * only. 3049 * 3050 * Returns FALSE (0) if native SGL was built, TRUE (1) if no SGL was built. 3051 */ 3052 static int 3053 mpr_check_pcie_native_sgl(struct mpr_softc *sc, struct mpr_command *cm, 3054 bus_dma_segment_t *segs, int segs_left) 3055 { 3056 uint32_t i, sge_dwords, length, offset, entry_len; 3057 uint32_t num_entries, buff_len = 0, sges_in_segment; 3058 uint32_t page_mask, page_mask_result, *curr_buff; 3059 uint32_t *ptr_sgl, *ptr_first_sgl, first_page_offset; 3060 uint32_t first_page_data_size, end_residual; 3061 uint64_t *msg_phys; 3062 bus_addr_t paddr; 3063 int build_native_sgl = 0, first_prp_entry; 3064 int prp_size = PRP_ENTRY_SIZE; 3065 Mpi25IeeeSgeChain64_t *main_chain_element = NULL; 3066 struct mpr_prp_page *prp_page_info = NULL; 3067 3068 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 3069 3070 /* 3071 * Add up the sizes of each segment length to get the total transfer 3072 * size, which will be checked against the Maximum Data Transfer Size. 3073 * If the data transfer length exceeds the MDTS for this device, just 3074 * return 1 so a normal IEEE SGL will be built. F/W will break the I/O 3075 * up into multiple I/O's. [nvme_mdts = 0 means unlimited] 3076 */ 3077 for (i = 0; i < segs_left; i++) 3078 buff_len += htole32(segs[i].ds_len); 3079 if ((cm->cm_targ->MDTS > 0) && (buff_len > cm->cm_targ->MDTS)) 3080 return 1; 3081 3082 /* Create page_mask (to get offset within page) */ 3083 page_mask = PAGE_SIZE - 1; 3084 3085 /* 3086 * Check if the number of elements exceeds the max number that can be 3087 * put in the main message frame (H/W can only translate an SGL that 3088 * is contained entirely in the main message frame). 3089 */ 3090 sges_in_segment = (sc->reqframesz - 3091 offsetof(Mpi25SCSIIORequest_t, SGL)) / sizeof(MPI25_SGE_IO_UNION); 3092 if (segs_left > sges_in_segment) 3093 build_native_sgl = 1; 3094 else 3095 { 3096 /* 3097 * NVMe uses one PRP for each physical page (or part of physical 3098 * page). 3099 * if 4 pages or less then IEEE is OK 3100 * if > 5 pages then we need to build a native SGL 3101 * if > 4 and <= 5 pages, then check the physical address of 3102 * the first SG entry, then if this first size in the page 3103 * is >= the residual beyond 4 pages then use IEEE, 3104 * otherwise use native SGL 3105 */ 3106 if (buff_len > (PAGE_SIZE * 5)) 3107 build_native_sgl = 1; 3108 else if ((buff_len > (PAGE_SIZE * 4)) && 3109 (buff_len <= (PAGE_SIZE * 5)) ) 3110 { 3111 msg_phys = (uint64_t *)(uintptr_t)segs[0].ds_addr; 3112 first_page_offset = 3113 ((uint32_t)(uint64_t)(uintptr_t)msg_phys & 3114 page_mask); 3115 first_page_data_size = PAGE_SIZE - first_page_offset; 3116 end_residual = buff_len % PAGE_SIZE; 3117 3118 /* 3119 * If offset into first page pushes the end of the data 3120 * beyond end of the 5th page, we need the extra PRP 3121 * list. 3122 */ 3123 if (first_page_data_size < end_residual) 3124 build_native_sgl = 1; 3125 3126 /* 3127 * Check if first SG entry size is < residual beyond 4 3128 * pages. 3129 */ 3130 if (htole32(segs[0].ds_len) < 3131 (buff_len - (PAGE_SIZE * 4))) 3132 build_native_sgl = 1; 3133 } 3134 } 3135 3136 /* check if native SGL is needed */ 3137 if (!build_native_sgl) 3138 return 1; 3139 3140 /* 3141 * Native SGL is needed. 3142 * Put a chain element in main message frame that points to the first 3143 * chain buffer. 3144 * 3145 * NOTE: The ChainOffset field must be 0 when using a chain pointer to 3146 * a native SGL. 3147 */ 3148 3149 /* Set main message chain element pointer */ 3150 main_chain_element = (pMpi25IeeeSgeChain64_t)cm->cm_sge; 3151 3152 /* 3153 * For NVMe the chain element needs to be the 2nd SGL entry in the main 3154 * message. 3155 */ 3156 main_chain_element = (Mpi25IeeeSgeChain64_t *) 3157 ((uint8_t *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64)); 3158 3159 /* 3160 * For the PRP entries, use the specially allocated buffer of 3161 * contiguous memory. PRP Page allocation failures should not happen 3162 * because there should be enough PRP page buffers to account for the 3163 * possible NVMe QDepth. 3164 */ 3165 prp_page_info = mpr_alloc_prp_page(sc); 3166 KASSERT(prp_page_info != NULL, ("%s: There are no PRP Pages left to be " 3167 "used for building a native NVMe SGL.\n", __func__)); 3168 curr_buff = (uint32_t *)prp_page_info->prp_page; 3169 msg_phys = (uint64_t *)(uintptr_t)prp_page_info->prp_page_busaddr; 3170 3171 /* 3172 * Insert the allocated PRP page into the command's PRP page list. This 3173 * will be freed when the command is freed. 3174 */ 3175 TAILQ_INSERT_TAIL(&cm->cm_prp_page_list, prp_page_info, prp_page_link); 3176 3177 /* 3178 * Check if we are within 1 entry of a page boundary we don't want our 3179 * first entry to be a PRP List entry. 3180 */ 3181 page_mask_result = (uintptr_t)((uint8_t *)curr_buff + prp_size) & 3182 page_mask; 3183 if (!page_mask_result) { 3184 /* Bump up to next page boundary. */ 3185 curr_buff = (uint32_t *)((uint8_t *)curr_buff + prp_size); 3186 msg_phys = (uint64_t *)((uint8_t *)msg_phys + prp_size); 3187 } 3188 3189 /* Fill in the chain element and make it an NVMe segment type. */ 3190 main_chain_element->Address.High = 3191 htole32((uint32_t)((uint64_t)(uintptr_t)msg_phys >> 32)); 3192 main_chain_element->Address.Low = 3193 htole32((uint32_t)(uintptr_t)msg_phys); 3194 main_chain_element->NextChainOffset = 0; 3195 main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 3196 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 3197 MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP; 3198 3199 /* Set SGL pointer to start of contiguous PCIe buffer. */ 3200 ptr_sgl = curr_buff; 3201 sge_dwords = 2; 3202 num_entries = 0; 3203 3204 /* 3205 * NVMe has a very convoluted PRP format. One PRP is required for each 3206 * page or partial page. We need to split up OS SG entries if they are 3207 * longer than one page or cross a page boundary. We also have to insert 3208 * a PRP list pointer entry as the last entry in each physical page of 3209 * the PRP list. 3210 * 3211 * NOTE: The first PRP "entry" is actually placed in the first SGL entry 3212 * in the main message in IEEE 64 format. The 2nd entry in the main 3213 * message is the chain element, and the rest of the PRP entries are 3214 * built in the contiguous PCIe buffer. 3215 */ 3216 first_prp_entry = 1; 3217 ptr_first_sgl = (uint32_t *)cm->cm_sge; 3218 3219 for (i = 0; i < segs_left; i++) { 3220 /* Get physical address and length of this SG entry. */ 3221 paddr = segs[i].ds_addr; 3222 length = segs[i].ds_len; 3223 3224 /* 3225 * Check whether a given SGE buffer lies on a non-PAGED 3226 * boundary if this is not the first page. If so, this is not 3227 * expected so have FW build the SGL. 3228 */ 3229 if ((i != 0) && (((uint32_t)paddr & page_mask) != 0)) { 3230 mpr_dprint(sc, MPR_ERROR, "Unaligned SGE while " 3231 "building NVMe PRPs, low address is 0x%x\n", 3232 (uint32_t)paddr); 3233 return 1; 3234 } 3235 3236 /* Apart from last SGE, if any other SGE boundary is not page 3237 * aligned then it means that hole exists. Existence of hole 3238 * leads to data corruption. So fallback to IEEE SGEs. 3239 */ 3240 if (i != (segs_left - 1)) { 3241 if (((uint32_t)paddr + length) & page_mask) { 3242 mpr_dprint(sc, MPR_ERROR, "Unaligned SGE " 3243 "boundary while building NVMe PRPs, low " 3244 "address: 0x%x and length: %u\n", 3245 (uint32_t)paddr, length); 3246 return 1; 3247 } 3248 } 3249 3250 /* Loop while the length is not zero. */ 3251 while (length) { 3252 /* 3253 * Check if we need to put a list pointer here if we are 3254 * at page boundary - prp_size. 3255 */ 3256 page_mask_result = (uintptr_t)((uint8_t *)ptr_sgl + 3257 prp_size) & page_mask; 3258 if (!page_mask_result) { 3259 /* 3260 * Need to put a PRP list pointer here. 3261 */ 3262 msg_phys = (uint64_t *)((uint8_t *)msg_phys + 3263 prp_size); 3264 *ptr_sgl = htole32((uintptr_t)msg_phys); 3265 *(ptr_sgl+1) = htole32((uint64_t)(uintptr_t) 3266 msg_phys >> 32); 3267 ptr_sgl += sge_dwords; 3268 num_entries++; 3269 } 3270 3271 /* Need to handle if entry will be part of a page. */ 3272 offset = (uint32_t)paddr & page_mask; 3273 entry_len = PAGE_SIZE - offset; 3274 if (first_prp_entry) { 3275 /* 3276 * Put IEEE entry in first SGE in main message. 3277 * (Simple element, System addr, not end of 3278 * list.) 3279 */ 3280 *ptr_first_sgl = htole32((uint32_t)paddr); 3281 *(ptr_first_sgl + 1) = 3282 htole32((uint32_t)((uint64_t)paddr >> 32)); 3283 *(ptr_first_sgl + 2) = htole32(entry_len); 3284 *(ptr_first_sgl + 3) = 0; 3285 3286 /* No longer the first PRP entry. */ 3287 first_prp_entry = 0; 3288 } else { 3289 /* Put entry in list. */ 3290 *ptr_sgl = htole32((uint32_t)paddr); 3291 *(ptr_sgl + 1) = 3292 htole32((uint32_t)((uint64_t)paddr >> 32)); 3293 3294 /* Bump ptr_sgl, msg_phys, and num_entries. */ 3295 ptr_sgl += sge_dwords; 3296 msg_phys = (uint64_t *)((uint8_t *)msg_phys + 3297 prp_size); 3298 num_entries++; 3299 } 3300 3301 /* Bump the phys address by the entry_len. */ 3302 paddr += entry_len; 3303 3304 /* Decrement length accounting for last partial page. */ 3305 if (entry_len > length) 3306 length = 0; 3307 else 3308 length -= entry_len; 3309 } 3310 } 3311 3312 /* Set chain element Length. */ 3313 main_chain_element->Length = htole32(num_entries * prp_size); 3314 3315 /* Return 0, indicating we built a native SGL. */ 3316 return 0; 3317 } 3318 3319 /* 3320 * Add a chain element as the next SGE for the specified command. 3321 * Reset cm_sge and cm_sgesize to indicate all the available space. Chains are 3322 * only required for IEEE commands. Therefore there is no code for commands 3323 * that have the MPR_CM_FLAGS_SGE_SIMPLE flag set (and those commands 3324 * shouldn't be requesting chains). 3325 */ 3326 static int 3327 mpr_add_chain(struct mpr_command *cm, int segsleft) 3328 { 3329 struct mpr_softc *sc = cm->cm_sc; 3330 MPI2_REQUEST_HEADER *req; 3331 MPI25_IEEE_SGE_CHAIN64 *ieee_sgc; 3332 struct mpr_chain *chain; 3333 int sgc_size, current_segs, rem_segs, segs_per_frame; 3334 uint8_t next_chain_offset = 0; 3335 3336 /* 3337 * Fail if a command is requesting a chain for SIMPLE SGE's. For SAS3 3338 * only IEEE commands should be requesting chains. Return some error 3339 * code other than 0. 3340 */ 3341 if (cm->cm_flags & MPR_CM_FLAGS_SGE_SIMPLE) { 3342 mpr_dprint(sc, MPR_ERROR, "A chain element cannot be added to " 3343 "an MPI SGL.\n"); 3344 return(ENOBUFS); 3345 } 3346 3347 sgc_size = sizeof(MPI25_IEEE_SGE_CHAIN64); 3348 if (cm->cm_sglsize < sgc_size) 3349 panic("MPR: Need SGE Error Code\n"); 3350 3351 chain = mpr_alloc_chain(cm->cm_sc); 3352 if (chain == NULL) 3353 return (ENOBUFS); 3354 3355 /* 3356 * Note: a double-linked list is used to make it easier to walk for 3357 * debugging. 3358 */ 3359 TAILQ_INSERT_TAIL(&cm->cm_chain_list, chain, chain_link); 3360 3361 /* 3362 * Need to know if the number of frames left is more than 1 or not. If 3363 * more than 1 frame is required, NextChainOffset will need to be set, 3364 * which will just be the last segment of the frame. 3365 */ 3366 rem_segs = 0; 3367 if (cm->cm_sglsize < (sgc_size * segsleft)) { 3368 /* 3369 * rem_segs is the number of segements remaining after the 3370 * segments that will go into the current frame. Since it is 3371 * known that at least one more frame is required, account for 3372 * the chain element. To know if more than one more frame is 3373 * required, just check if there will be a remainder after using 3374 * the current frame (with this chain) and the next frame. If 3375 * so the NextChainOffset must be the last element of the next 3376 * frame. 3377 */ 3378 current_segs = (cm->cm_sglsize / sgc_size) - 1; 3379 rem_segs = segsleft - current_segs; 3380 segs_per_frame = sc->chain_frame_size / sgc_size; 3381 if (rem_segs > segs_per_frame) { 3382 next_chain_offset = segs_per_frame - 1; 3383 } 3384 } 3385 ieee_sgc = &((MPI25_SGE_IO_UNION *)cm->cm_sge)->IeeeChain; 3386 ieee_sgc->Length = next_chain_offset ? 3387 htole32((uint32_t)sc->chain_frame_size) : 3388 htole32((uint32_t)rem_segs * (uint32_t)sgc_size); 3389 ieee_sgc->NextChainOffset = next_chain_offset; 3390 ieee_sgc->Flags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 3391 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 3392 ieee_sgc->Address.Low = htole32(chain->chain_busaddr); 3393 ieee_sgc->Address.High = htole32(chain->chain_busaddr >> 32); 3394 cm->cm_sge = &((MPI25_SGE_IO_UNION *)chain->chain)->IeeeSimple; 3395 req = (MPI2_REQUEST_HEADER *)cm->cm_req; 3396 req->ChainOffset = (sc->chain_frame_size - sgc_size) >> 4; 3397 3398 cm->cm_sglsize = sc->chain_frame_size; 3399 return (0); 3400 } 3401 3402 /* 3403 * Add one scatter-gather element to the scatter-gather list for a command. 3404 * Maintain cm_sglsize and cm_sge as the remaining size and pointer to the 3405 * next SGE to fill in, respectively. In Gen3, the MPI SGL does not have a 3406 * chain, so don't consider any chain additions. 3407 */ 3408 int 3409 mpr_push_sge(struct mpr_command *cm, MPI2_SGE_SIMPLE64 *sge, size_t len, 3410 int segsleft) 3411 { 3412 uint32_t saved_buf_len, saved_address_low, saved_address_high; 3413 u32 sge_flags; 3414 3415 /* 3416 * case 1: >=1 more segment, no room for anything (error) 3417 * case 2: 1 more segment and enough room for it 3418 */ 3419 3420 if (cm->cm_sglsize < (segsleft * sizeof(MPI2_SGE_SIMPLE64))) { 3421 mpr_dprint(cm->cm_sc, MPR_ERROR, 3422 "%s: warning: Not enough room for MPI SGL in frame.\n", 3423 __func__); 3424 return(ENOBUFS); 3425 } 3426 3427 KASSERT(segsleft == 1, 3428 ("segsleft cannot be more than 1 for an MPI SGL; segsleft = %d\n", 3429 segsleft)); 3430 3431 /* 3432 * There is one more segment left to add for the MPI SGL and there is 3433 * enough room in the frame to add it. This is the normal case because 3434 * MPI SGL's don't have chains, otherwise something is wrong. 3435 * 3436 * If this is a bi-directional request, need to account for that 3437 * here. Save the pre-filled sge values. These will be used 3438 * either for the 2nd SGL or for a single direction SGL. If 3439 * cm_out_len is non-zero, this is a bi-directional request, so 3440 * fill in the OUT SGL first, then the IN SGL, otherwise just 3441 * fill in the IN SGL. Note that at this time, when filling in 3442 * 2 SGL's for a bi-directional request, they both use the same 3443 * DMA buffer (same cm command). 3444 */ 3445 saved_buf_len = sge->FlagsLength & 0x00FFFFFF; 3446 saved_address_low = sge->Address.Low; 3447 saved_address_high = sge->Address.High; 3448 if (cm->cm_out_len) { 3449 sge->FlagsLength = cm->cm_out_len | 3450 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 3451 MPI2_SGE_FLAGS_END_OF_BUFFER | 3452 MPI2_SGE_FLAGS_HOST_TO_IOC | 3453 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 3454 MPI2_SGE_FLAGS_SHIFT); 3455 cm->cm_sglsize -= len; 3456 /* Endian Safe code */ 3457 sge_flags = sge->FlagsLength; 3458 sge->FlagsLength = htole32(sge_flags); 3459 sge->Address.High = htole32(sge->Address.High); 3460 sge->Address.Low = htole32(sge->Address.Low); 3461 bcopy(sge, cm->cm_sge, len); 3462 cm->cm_sge = (MPI2_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + len); 3463 } 3464 sge->FlagsLength = saved_buf_len | 3465 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 3466 MPI2_SGE_FLAGS_END_OF_BUFFER | 3467 MPI2_SGE_FLAGS_LAST_ELEMENT | 3468 MPI2_SGE_FLAGS_END_OF_LIST | 3469 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 3470 MPI2_SGE_FLAGS_SHIFT); 3471 if (cm->cm_flags & MPR_CM_FLAGS_DATAIN) { 3472 sge->FlagsLength |= 3473 ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) << 3474 MPI2_SGE_FLAGS_SHIFT); 3475 } else { 3476 sge->FlagsLength |= 3477 ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) << 3478 MPI2_SGE_FLAGS_SHIFT); 3479 } 3480 sge->Address.Low = saved_address_low; 3481 sge->Address.High = saved_address_high; 3482 3483 cm->cm_sglsize -= len; 3484 /* Endian Safe code */ 3485 sge_flags = sge->FlagsLength; 3486 sge->FlagsLength = htole32(sge_flags); 3487 sge->Address.High = htole32(sge->Address.High); 3488 sge->Address.Low = htole32(sge->Address.Low); 3489 bcopy(sge, cm->cm_sge, len); 3490 cm->cm_sge = (MPI2_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + len); 3491 return (0); 3492 } 3493 3494 /* 3495 * Add one IEEE scatter-gather element (chain or simple) to the IEEE scatter- 3496 * gather list for a command. Maintain cm_sglsize and cm_sge as the 3497 * remaining size and pointer to the next SGE to fill in, respectively. 3498 */ 3499 int 3500 mpr_push_ieee_sge(struct mpr_command *cm, void *sgep, int segsleft) 3501 { 3502 MPI2_IEEE_SGE_SIMPLE64 *sge = sgep; 3503 int error, ieee_sge_size = sizeof(MPI25_SGE_IO_UNION); 3504 uint32_t saved_buf_len, saved_address_low, saved_address_high; 3505 uint32_t sge_length; 3506 3507 /* 3508 * case 1: No room for chain or segment (error). 3509 * case 2: Two or more segments left but only room for chain. 3510 * case 3: Last segment and room for it, so set flags. 3511 */ 3512 3513 /* 3514 * There should be room for at least one element, or there is a big 3515 * problem. 3516 */ 3517 if (cm->cm_sglsize < ieee_sge_size) 3518 panic("MPR: Need SGE Error Code\n"); 3519 3520 if ((segsleft >= 2) && (cm->cm_sglsize < (ieee_sge_size * 2))) { 3521 if ((error = mpr_add_chain(cm, segsleft)) != 0) 3522 return (error); 3523 } 3524 3525 if (segsleft == 1) { 3526 /* 3527 * If this is a bi-directional request, need to account for that 3528 * here. Save the pre-filled sge values. These will be used 3529 * either for the 2nd SGL or for a single direction SGL. If 3530 * cm_out_len is non-zero, this is a bi-directional request, so 3531 * fill in the OUT SGL first, then the IN SGL, otherwise just 3532 * fill in the IN SGL. Note that at this time, when filling in 3533 * 2 SGL's for a bi-directional request, they both use the same 3534 * DMA buffer (same cm command). 3535 */ 3536 saved_buf_len = sge->Length; 3537 saved_address_low = sge->Address.Low; 3538 saved_address_high = sge->Address.High; 3539 if (cm->cm_out_len) { 3540 sge->Length = cm->cm_out_len; 3541 sge->Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 3542 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 3543 cm->cm_sglsize -= ieee_sge_size; 3544 /* Endian Safe code */ 3545 sge_length = sge->Length; 3546 sge->Length = htole32(sge_length); 3547 sge->Address.High = htole32(sge->Address.High); 3548 sge->Address.Low = htole32(sge->Address.Low); 3549 bcopy(sgep, cm->cm_sge, ieee_sge_size); 3550 cm->cm_sge = 3551 (MPI25_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + 3552 ieee_sge_size); 3553 } 3554 sge->Length = saved_buf_len; 3555 sge->Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 3556 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 3557 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 3558 sge->Address.Low = saved_address_low; 3559 sge->Address.High = saved_address_high; 3560 } 3561 3562 cm->cm_sglsize -= ieee_sge_size; 3563 /* Endian Safe code */ 3564 sge_length = sge->Length; 3565 sge->Length = htole32(sge_length); 3566 sge->Address.High = htole32(sge->Address.High); 3567 sge->Address.Low = htole32(sge->Address.Low); 3568 bcopy(sgep, cm->cm_sge, ieee_sge_size); 3569 cm->cm_sge = (MPI25_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + 3570 ieee_sge_size); 3571 return (0); 3572 } 3573 3574 /* 3575 * Add one dma segment to the scatter-gather list for a command. 3576 */ 3577 int 3578 mpr_add_dmaseg(struct mpr_command *cm, vm_paddr_t pa, size_t len, u_int flags, 3579 int segsleft) 3580 { 3581 MPI2_SGE_SIMPLE64 sge; 3582 MPI2_IEEE_SGE_SIMPLE64 ieee_sge; 3583 3584 if (!(cm->cm_flags & MPR_CM_FLAGS_SGE_SIMPLE)) { 3585 ieee_sge.Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 3586 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 3587 ieee_sge.Length = len; 3588 mpr_from_u64(pa, &ieee_sge.Address); 3589 3590 return (mpr_push_ieee_sge(cm, &ieee_sge, segsleft)); 3591 } else { 3592 /* 3593 * This driver always uses 64-bit address elements for 3594 * simplicity. 3595 */ 3596 flags |= MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 3597 MPI2_SGE_FLAGS_64_BIT_ADDRESSING; 3598 /* Set Endian safe macro in mpr_push_sge */ 3599 sge.FlagsLength = len | (flags << MPI2_SGE_FLAGS_SHIFT); 3600 mpr_from_u64(pa, &sge.Address); 3601 3602 return (mpr_push_sge(cm, &sge, sizeof sge, segsleft)); 3603 } 3604 } 3605 3606 static void 3607 mpr_data_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3608 { 3609 struct mpr_softc *sc; 3610 struct mpr_command *cm; 3611 u_int i, dir, sflags; 3612 3613 cm = (struct mpr_command *)arg; 3614 sc = cm->cm_sc; 3615 3616 /* 3617 * In this case, just print out a warning and let the chip tell the 3618 * user they did the wrong thing. 3619 */ 3620 if ((cm->cm_max_segs != 0) && (nsegs > cm->cm_max_segs)) { 3621 mpr_dprint(sc, MPR_ERROR, "%s: warning: busdma returned %d " 3622 "segments, more than the %d allowed\n", __func__, nsegs, 3623 cm->cm_max_segs); 3624 } 3625 3626 /* 3627 * Set up DMA direction flags. Bi-directional requests are also handled 3628 * here. In that case, both direction flags will be set. 3629 */ 3630 sflags = 0; 3631 if (cm->cm_flags & MPR_CM_FLAGS_SMP_PASS) { 3632 /* 3633 * We have to add a special case for SMP passthrough, there 3634 * is no easy way to generically handle it. The first 3635 * S/G element is used for the command (therefore the 3636 * direction bit needs to be set). The second one is used 3637 * for the reply. We'll leave it to the caller to make 3638 * sure we only have two buffers. 3639 */ 3640 /* 3641 * Even though the busdma man page says it doesn't make 3642 * sense to have both direction flags, it does in this case. 3643 * We have one s/g element being accessed in each direction. 3644 */ 3645 dir = BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD; 3646 3647 /* 3648 * Set the direction flag on the first buffer in the SMP 3649 * passthrough request. We'll clear it for the second one. 3650 */ 3651 sflags |= MPI2_SGE_FLAGS_DIRECTION | 3652 MPI2_SGE_FLAGS_END_OF_BUFFER; 3653 } else if (cm->cm_flags & MPR_CM_FLAGS_DATAOUT) { 3654 sflags |= MPI2_SGE_FLAGS_HOST_TO_IOC; 3655 dir = BUS_DMASYNC_PREWRITE; 3656 } else 3657 dir = BUS_DMASYNC_PREREAD; 3658 3659 /* Check if a native SG list is needed for an NVMe PCIe device. */ 3660 if (cm->cm_targ && cm->cm_targ->is_nvme && 3661 mpr_check_pcie_native_sgl(sc, cm, segs, nsegs) == 0) { 3662 /* A native SG list was built, skip to end. */ 3663 goto out; 3664 } 3665 3666 for (i = 0; i < nsegs; i++) { 3667 if ((cm->cm_flags & MPR_CM_FLAGS_SMP_PASS) && (i != 0)) { 3668 sflags &= ~MPI2_SGE_FLAGS_DIRECTION; 3669 } 3670 error = mpr_add_dmaseg(cm, segs[i].ds_addr, segs[i].ds_len, 3671 sflags, nsegs - i); 3672 if (error != 0) { 3673 /* Resource shortage, roll back! */ 3674 if (ratecheck(&sc->lastfail, &mpr_chainfail_interval)) 3675 mpr_dprint(sc, MPR_INFO, "Out of chain frames, " 3676 "consider increasing hw.mpr.max_chains.\n"); 3677 cm->cm_flags |= MPR_CM_FLAGS_CHAIN_FAILED; 3678 mpr_complete_command(sc, cm); 3679 return; 3680 } 3681 } 3682 3683 out: 3684 bus_dmamap_sync(sc->buffer_dmat, cm->cm_dmamap, dir); 3685 mpr_enqueue_request(sc, cm); 3686 3687 return; 3688 } 3689 3690 static void 3691 mpr_data_cb2(void *arg, bus_dma_segment_t *segs, int nsegs, bus_size_t mapsize, 3692 int error) 3693 { 3694 mpr_data_cb(arg, segs, nsegs, error); 3695 } 3696 3697 /* 3698 * This is the routine to enqueue commands ansynchronously. 3699 * Note that the only error path here is from bus_dmamap_load(), which can 3700 * return EINPROGRESS if it is waiting for resources. Other than this, it's 3701 * assumed that if you have a command in-hand, then you have enough credits 3702 * to use it. 3703 */ 3704 int 3705 mpr_map_command(struct mpr_softc *sc, struct mpr_command *cm) 3706 { 3707 int error = 0; 3708 3709 if (cm->cm_flags & MPR_CM_FLAGS_USE_UIO) { 3710 error = bus_dmamap_load_uio(sc->buffer_dmat, cm->cm_dmamap, 3711 &cm->cm_uio, mpr_data_cb2, cm, 0); 3712 } else if (cm->cm_flags & MPR_CM_FLAGS_USE_CCB) { 3713 error = bus_dmamap_load_ccb(sc->buffer_dmat, cm->cm_dmamap, 3714 cm->cm_data, mpr_data_cb, cm, 0); 3715 } else if ((cm->cm_data != NULL) && (cm->cm_length != 0)) { 3716 error = bus_dmamap_load(sc->buffer_dmat, cm->cm_dmamap, 3717 cm->cm_data, cm->cm_length, mpr_data_cb, cm, 0); 3718 } else { 3719 /* Add a zero-length element as needed */ 3720 if (cm->cm_sge != NULL) 3721 mpr_add_dmaseg(cm, 0, 0, 0, 1); 3722 mpr_enqueue_request(sc, cm); 3723 } 3724 3725 return (error); 3726 } 3727 3728 /* 3729 * This is the routine to enqueue commands synchronously. An error of 3730 * EINPROGRESS from mpr_map_command() is ignored since the command will 3731 * be executed and enqueued automatically. Other errors come from msleep(). 3732 */ 3733 int 3734 mpr_wait_command(struct mpr_softc *sc, struct mpr_command **cmp, int timeout, 3735 int sleep_flag) 3736 { 3737 int error, rc; 3738 struct timeval cur_time, start_time; 3739 struct mpr_command *cm = *cmp; 3740 3741 if (sc->mpr_flags & MPR_FLAGS_DIAGRESET) 3742 return EBUSY; 3743 3744 cm->cm_complete = NULL; 3745 cm->cm_flags |= (MPR_CM_FLAGS_WAKEUP + MPR_CM_FLAGS_POLLED); 3746 error = mpr_map_command(sc, cm); 3747 if ((error != 0) && (error != EINPROGRESS)) 3748 return (error); 3749 3750 // Check for context and wait for 50 mSec at a time until time has 3751 // expired or the command has finished. If msleep can't be used, need 3752 // to poll. 3753 #if __FreeBSD_version >= 1000029 3754 if (curthread->td_no_sleeping) 3755 #else //__FreeBSD_version < 1000029 3756 if (curthread->td_pflags & TDP_NOSLEEPING) 3757 #endif //__FreeBSD_version >= 1000029 3758 sleep_flag = NO_SLEEP; 3759 getmicrouptime(&start_time); 3760 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) { 3761 error = msleep(cm, &sc->mpr_mtx, 0, "mprwait", timeout*hz); 3762 if (error == EWOULDBLOCK) { 3763 /* 3764 * Record the actual elapsed time in the case of a 3765 * timeout for the message below. 3766 */ 3767 getmicrouptime(&cur_time); 3768 timevalsub(&cur_time, &start_time); 3769 } 3770 } else { 3771 while ((cm->cm_flags & MPR_CM_FLAGS_COMPLETE) == 0) { 3772 mpr_intr_locked(sc); 3773 if (sleep_flag == CAN_SLEEP) 3774 pause("mprwait", hz/20); 3775 else 3776 DELAY(50000); 3777 3778 getmicrouptime(&cur_time); 3779 timevalsub(&cur_time, &start_time); 3780 if (cur_time.tv_sec > timeout) { 3781 error = EWOULDBLOCK; 3782 break; 3783 } 3784 } 3785 } 3786 3787 if (error == EWOULDBLOCK) { 3788 if (cm->cm_timeout_handler == NULL) { 3789 mpr_dprint(sc, MPR_FAULT, "Calling Reinit from %s, timeout=%d," 3790 " elapsed=%jd\n", __func__, timeout, 3791 (intmax_t)cur_time.tv_sec); 3792 rc = mpr_reinit(sc); 3793 mpr_dprint(sc, MPR_FAULT, "Reinit %s\n", (rc == 0) ? "success" : 3794 "failed"); 3795 } else 3796 cm->cm_timeout_handler(sc, cm); 3797 if (sc->mpr_flags & MPR_FLAGS_REALLOCATED) { 3798 /* 3799 * Tell the caller that we freed the command in a 3800 * reinit. 3801 */ 3802 *cmp = NULL; 3803 } 3804 error = ETIMEDOUT; 3805 } 3806 return (error); 3807 } 3808 3809 /* 3810 * This is the routine to enqueue a command synchonously and poll for 3811 * completion. Its use should be rare. 3812 */ 3813 int 3814 mpr_request_polled(struct mpr_softc *sc, struct mpr_command **cmp) 3815 { 3816 int error, rc; 3817 struct timeval cur_time, start_time; 3818 struct mpr_command *cm = *cmp; 3819 3820 error = 0; 3821 3822 cm->cm_flags |= MPR_CM_FLAGS_POLLED; 3823 cm->cm_complete = NULL; 3824 mpr_map_command(sc, cm); 3825 3826 getmicrouptime(&start_time); 3827 while ((cm->cm_flags & MPR_CM_FLAGS_COMPLETE) == 0) { 3828 mpr_intr_locked(sc); 3829 3830 if (mtx_owned(&sc->mpr_mtx)) 3831 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, 3832 "mprpoll", hz/20); 3833 else 3834 pause("mprpoll", hz/20); 3835 3836 /* 3837 * Check for real-time timeout and fail if more than 60 seconds. 3838 */ 3839 getmicrouptime(&cur_time); 3840 timevalsub(&cur_time, &start_time); 3841 if (cur_time.tv_sec > 60) { 3842 mpr_dprint(sc, MPR_FAULT, "polling failed\n"); 3843 error = ETIMEDOUT; 3844 break; 3845 } 3846 } 3847 cm->cm_state = MPR_CM_STATE_BUSY; 3848 if (error) { 3849 mpr_dprint(sc, MPR_FAULT, "Calling Reinit from %s\n", __func__); 3850 rc = mpr_reinit(sc); 3851 mpr_dprint(sc, MPR_FAULT, "Reinit %s\n", (rc == 0) ? "success" : 3852 "failed"); 3853 3854 if (sc->mpr_flags & MPR_FLAGS_REALLOCATED) { 3855 /* 3856 * Tell the caller that we freed the command in a 3857 * reinit. 3858 */ 3859 *cmp = NULL; 3860 } 3861 } 3862 return (error); 3863 } 3864 3865 /* 3866 * The MPT driver had a verbose interface for config pages. In this driver, 3867 * reduce it to much simpler terms, similar to the Linux driver. 3868 */ 3869 int 3870 mpr_read_config_page(struct mpr_softc *sc, struct mpr_config_params *params) 3871 { 3872 MPI2_CONFIG_REQUEST *req; 3873 struct mpr_command *cm; 3874 int error; 3875 3876 if (sc->mpr_flags & MPR_FLAGS_BUSY) { 3877 return (EBUSY); 3878 } 3879 3880 cm = mpr_alloc_command(sc); 3881 if (cm == NULL) { 3882 return (EBUSY); 3883 } 3884 3885 req = (MPI2_CONFIG_REQUEST *)cm->cm_req; 3886 req->Function = MPI2_FUNCTION_CONFIG; 3887 req->Action = params->action; 3888 req->SGLFlags = 0; 3889 req->ChainOffset = 0; 3890 req->PageAddress = params->page_address; 3891 if (params->hdr.Struct.PageType == MPI2_CONFIG_PAGETYPE_EXTENDED) { 3892 MPI2_CONFIG_EXTENDED_PAGE_HEADER *hdr; 3893 3894 hdr = ¶ms->hdr.Ext; 3895 req->ExtPageType = hdr->ExtPageType; 3896 req->ExtPageLength = hdr->ExtPageLength; 3897 req->Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; 3898 req->Header.PageLength = 0; /* Must be set to zero */ 3899 req->Header.PageNumber = hdr->PageNumber; 3900 req->Header.PageVersion = hdr->PageVersion; 3901 } else { 3902 MPI2_CONFIG_PAGE_HEADER *hdr; 3903 3904 hdr = ¶ms->hdr.Struct; 3905 req->Header.PageType = hdr->PageType; 3906 req->Header.PageNumber = hdr->PageNumber; 3907 req->Header.PageLength = hdr->PageLength; 3908 req->Header.PageVersion = hdr->PageVersion; 3909 } 3910 3911 cm->cm_data = params->buffer; 3912 cm->cm_length = params->length; 3913 if (cm->cm_data != NULL) { 3914 cm->cm_sge = &req->PageBufferSGE; 3915 cm->cm_sglsize = sizeof(MPI2_SGE_IO_UNION); 3916 cm->cm_flags = MPR_CM_FLAGS_SGE_SIMPLE | MPR_CM_FLAGS_DATAIN; 3917 } else 3918 cm->cm_sge = NULL; 3919 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 3920 3921 cm->cm_complete_data = params; 3922 if (params->callback != NULL) { 3923 cm->cm_complete = mpr_config_complete; 3924 return (mpr_map_command(sc, cm)); 3925 } else { 3926 error = mpr_wait_command(sc, &cm, 0, CAN_SLEEP); 3927 if (error) { 3928 mpr_dprint(sc, MPR_FAULT, 3929 "Error %d reading config page\n", error); 3930 if (cm != NULL) 3931 mpr_free_command(sc, cm); 3932 return (error); 3933 } 3934 mpr_config_complete(sc, cm); 3935 } 3936 3937 return (0); 3938 } 3939 3940 int 3941 mpr_write_config_page(struct mpr_softc *sc, struct mpr_config_params *params) 3942 { 3943 return (EINVAL); 3944 } 3945 3946 static void 3947 mpr_config_complete(struct mpr_softc *sc, struct mpr_command *cm) 3948 { 3949 MPI2_CONFIG_REPLY *reply; 3950 struct mpr_config_params *params; 3951 3952 MPR_FUNCTRACE(sc); 3953 params = cm->cm_complete_data; 3954 3955 if (cm->cm_data != NULL) { 3956 bus_dmamap_sync(sc->buffer_dmat, cm->cm_dmamap, 3957 BUS_DMASYNC_POSTREAD); 3958 bus_dmamap_unload(sc->buffer_dmat, cm->cm_dmamap); 3959 } 3960 3961 /* 3962 * XXX KDM need to do more error recovery? This results in the 3963 * device in question not getting probed. 3964 */ 3965 if ((cm->cm_flags & MPR_CM_FLAGS_ERROR_MASK) != 0) { 3966 params->status = MPI2_IOCSTATUS_BUSY; 3967 goto done; 3968 } 3969 3970 reply = (MPI2_CONFIG_REPLY *)cm->cm_reply; 3971 if (reply == NULL) { 3972 params->status = MPI2_IOCSTATUS_BUSY; 3973 goto done; 3974 } 3975 params->status = reply->IOCStatus; 3976 if (params->hdr.Struct.PageType == MPI2_CONFIG_PAGETYPE_EXTENDED) { 3977 params->hdr.Ext.ExtPageType = reply->ExtPageType; 3978 params->hdr.Ext.ExtPageLength = reply->ExtPageLength; 3979 params->hdr.Ext.PageType = reply->Header.PageType; 3980 params->hdr.Ext.PageNumber = reply->Header.PageNumber; 3981 params->hdr.Ext.PageVersion = reply->Header.PageVersion; 3982 } else { 3983 params->hdr.Struct.PageType = reply->Header.PageType; 3984 params->hdr.Struct.PageNumber = reply->Header.PageNumber; 3985 params->hdr.Struct.PageLength = reply->Header.PageLength; 3986 params->hdr.Struct.PageVersion = reply->Header.PageVersion; 3987 } 3988 3989 done: 3990 mpr_free_command(sc, cm); 3991 if (params->callback != NULL) 3992 params->callback(sc, params); 3993 3994 return; 3995 } 3996