1 /* 2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy 3 * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy 4 * Support: freebsdraid@avagotech.com 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 2. Redistributions 12 * in binary form must reproduce the above copyright notice, this list of 13 * conditions and the following disclaimer in the documentation and/or other 14 * materials provided with the distribution. 3. Neither the name of the 15 * <ORGANIZATION> nor the names of its contributors may be used to endorse or 16 * promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * The views and conclusions contained in the software and documentation are 32 * those of the authors and should not be interpreted as representing 33 * official policies,either expressed or implied, of the FreeBSD Project. 34 * 35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621 36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD 37 * 38 */ 39 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD$"); 42 43 #ifndef MRSAS_H 44 #define MRSAS_H 45 46 #include <sys/param.h> /* defines used in kernel.h */ 47 #include <sys/module.h> 48 #include <sys/systm.h> 49 #include <sys/proc.h> 50 #include <sys/errno.h> 51 #include <sys/kernel.h> /* types used in module initialization */ 52 #include <sys/conf.h> /* cdevsw struct */ 53 #include <sys/uio.h> /* uio struct */ 54 #include <sys/malloc.h> 55 #include <sys/bus.h> /* structs, prototypes for pci bus 56 * stuff */ 57 #include <sys/rman.h> 58 #include <sys/types.h> 59 #include <sys/lock.h> 60 #include <sys/sema.h> 61 #include <sys/sysctl.h> 62 #include <sys/stat.h> 63 #include <sys/taskqueue.h> 64 #include <sys/poll.h> 65 #include <sys/selinfo.h> 66 67 #include <machine/bus.h> 68 #include <machine/resource.h> 69 #include <machine/atomic.h> 70 71 #include <dev/pci/pcivar.h> /* For pci_get macros! */ 72 #include <dev/pci/pcireg.h> 73 74 75 #define IOCTL_SEMA_DESCRIPTION "mrsas semaphore for MFI pool" 76 77 /* 78 * Device IDs and PCI 79 */ 80 #define MRSAS_TBOLT 0x005b 81 #define MRSAS_INVADER 0x005d 82 #define MRSAS_FURY 0x005f 83 #define MRSAS_INTRUDER 0x00ce 84 #define MRSAS_INTRUDER_24 0x00cf 85 #define MRSAS_CUTLASS_52 0x0052 86 #define MRSAS_CUTLASS_53 0x0053 87 /* Gen3.5 Conroller */ 88 #define MRSAS_VENTURA 0x0014 89 #define MRSAS_CRUSADER 0x0015 90 #define MRSAS_HARPOON 0x0016 91 #define MRSAS_TOMCAT 0x0017 92 #define MRSAS_VENTURA_4PORT 0x001B 93 #define MRSAS_CRUSADER_4PORT 0x001C 94 #define MRSAS_AERO_10E0 0x10E0 95 #define MRSAS_AERO_10E1 0x10E1 96 #define MRSAS_AERO_10E2 0x10E2 97 #define MRSAS_AERO_10E3 0x10E3 98 #define MRSAS_AERO_10E4 0x10E4 99 #define MRSAS_AERO_10E5 0x10E5 100 #define MRSAS_AERO_10E6 0x10E6 101 #define MRSAS_AERO_10E7 0x10E7 102 103 104 /* 105 * Firmware State Defines 106 */ 107 #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF 108 #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000 109 #define MRSAS_FW_STATE_CHNG_INTERRUPT 1 110 111 /* 112 * Message Frame Defines 113 */ 114 #define MRSAS_SENSE_LEN 96 115 #define MRSAS_FUSION_MAX_RESET_TRIES 3 116 117 /* 118 * Miscellaneous Defines 119 */ 120 #define BYTE_ALIGNMENT 1 121 #define MRSAS_MAX_NAME_LENGTH 32 122 #define MRSAS_VERSION "07.709.04.00-fbsd" 123 #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF 124 #define MRSAS_DEFAULT_TIMEOUT 0x14 /* Temporarily set */ 125 #define DONE 0 126 #define MRSAS_PAGE_SIZE 4096 127 #define MRSAS_RESET_NOTICE_INTERVAL 5 128 #define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */ 129 #define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */ 130 #define THRESHOLD_REPLY_COUNT 50 131 #define MAX_MSIX_COUNT 128 132 133 #define MAX_STREAMS_TRACKED 8 134 #define MR_STREAM_BITMAP 0x76543210 135 #define BITS_PER_INDEX_STREAM 4 /* number of bits per index in U32 TrackStream */ 136 #define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1) 137 #define ZERO_LAST_STREAM 0x0fffffff 138 139 /* 140 * Boolean types 141 */ 142 #if (__FreeBSD_version < 901000) 143 typedef enum _boolean { 144 false, true 145 } boolean; 146 147 #endif 148 enum err { 149 SUCCESS, FAIL 150 }; 151 152 MALLOC_DECLARE(M_MRSAS); 153 SYSCTL_DECL(_hw_mrsas); 154 155 #define MRSAS_INFO (1 << 0) 156 #define MRSAS_TRACE (1 << 1) 157 #define MRSAS_FAULT (1 << 2) 158 #define MRSAS_OCR (1 << 3) 159 #define MRSAS_TOUT MRSAS_OCR 160 #define MRSAS_AEN (1 << 4) 161 #define MRSAS_PRL11 (1 << 5) 162 163 #define mrsas_dprint(sc, level, msg, args...) \ 164 do { \ 165 if (sc->mrsas_debug & level) \ 166 device_printf(sc->mrsas_dev, msg, ##args); \ 167 } while (0) 168 169 170 /**************************************************************************** 171 * Raid Context structure which describes MegaRAID specific IO Paramenters 172 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 173 ****************************************************************************/ 174 175 typedef struct _RAID_CONTEXT { 176 u_int8_t Type:4; 177 u_int8_t nseg:4; 178 u_int8_t resvd0; 179 u_int16_t timeoutValue; 180 u_int8_t regLockFlags; 181 u_int8_t resvd1; 182 u_int16_t VirtualDiskTgtId; 183 u_int64_t regLockRowLBA; 184 u_int32_t regLockLength; 185 u_int16_t nextLMId; 186 u_int8_t exStatus; 187 u_int8_t status; 188 u_int8_t RAIDFlags; 189 u_int8_t numSGE; 190 u_int16_t configSeqNum; 191 u_int8_t spanArm; 192 u_int8_t priority; /* 0x1D MR_PRIORITY_RANGE */ 193 u_int8_t numSGEExt; /* 0x1E 1M IO support */ 194 u_int8_t resvd2; /* 0x1F */ 195 } RAID_CONTEXT; 196 197 /* 198 * Raid Context structure which describes ventura MegaRAID specific IO Paramenters 199 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 200 */ 201 typedef struct _RAID_CONTEXT_G35 { 202 u_int16_t Type:4; 203 u_int16_t nseg:4; 204 u_int16_t resvd0:8; 205 u_int16_t timeoutValue; 206 union { 207 struct { 208 u_int16_t reserved:1; 209 u_int16_t sld:1; 210 u_int16_t c2f:1; 211 u_int16_t fwn:1; 212 u_int16_t sqn:1; 213 u_int16_t sbs:1; 214 u_int16_t rw:1; 215 u_int16_t log:1; 216 u_int16_t cpuSel:4; 217 u_int16_t setDivert:4; 218 } bits; 219 u_int16_t s; 220 } routingFlags; 221 u_int16_t VirtualDiskTgtId; 222 u_int64_t regLockRowLBA; 223 u_int32_t regLockLength; 224 union { 225 u_int16_t nextLMId; 226 u_int16_t peerSMID; 227 } smid; 228 u_int8_t exStatus; 229 u_int8_t status; 230 u_int8_t RAIDFlags; 231 u_int8_t spanArm; 232 u_int16_t configSeqNum; 233 u_int16_t numSGE:12; 234 u_int16_t reserved:3; 235 u_int16_t streamDetected:1; 236 u_int8_t resvd2[2]; 237 } RAID_CONTEXT_G35; 238 239 typedef union _RAID_CONTEXT_UNION { 240 RAID_CONTEXT raid_context; 241 RAID_CONTEXT_G35 raid_context_g35; 242 } RAID_CONTEXT_UNION, *PRAID_CONTEXT_UNION; 243 244 245 /************************************************************************* 246 * MPI2 Defines 247 ************************************************************************/ 248 249 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 250 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 251 #define MPI2_VERSION_MAJOR (0x02) 252 #define MPI2_VERSION_MINOR (0x00) 253 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 254 #define MPI2_VERSION_MAJOR_SHIFT (8) 255 #define MPI2_VERSION_MINOR_MASK (0x00FF) 256 #define MPI2_VERSION_MINOR_SHIFT (0) 257 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 258 MPI2_VERSION_MINOR) 259 #define MPI2_HEADER_VERSION_UNIT (0x10) 260 #define MPI2_HEADER_VERSION_DEV (0x00) 261 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 262 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 263 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 264 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 265 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 266 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 267 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 268 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 269 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 270 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 271 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 272 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 273 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 274 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) 275 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03) 276 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06) 277 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 278 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 279 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 280 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 281 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 282 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 283 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 284 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 285 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 286 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 287 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 288 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 289 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 290 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 291 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 292 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 293 294 #ifndef MPI2_POINTER 295 #define MPI2_POINTER * 296 #endif 297 298 299 /*************************************** 300 * MPI2 Structures 301 ***************************************/ 302 303 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 304 u_int64_t Address; 305 u_int32_t Length; 306 u_int16_t Reserved1; 307 u_int8_t NextChainOffset; 308 u_int8_t Flags; 309 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 310 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 311 312 typedef struct _MPI2_SGE_SIMPLE_UNION { 313 u_int32_t FlagsLength; 314 union { 315 u_int32_t Address32; 316 u_int64_t Address64; 317 } u; 318 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 319 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 320 321 typedef struct { 322 u_int8_t CDB[20]; /* 0x00 */ 323 u_int32_t PrimaryReferenceTag; /* 0x14 */ 324 u_int16_t PrimaryApplicationTag;/* 0x18 */ 325 u_int16_t PrimaryApplicationTagMask; /* 0x1A */ 326 u_int32_t TransferLength; /* 0x1C */ 327 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 328 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 329 330 typedef struct _MPI2_SGE_CHAIN_UNION { 331 u_int16_t Length; 332 u_int8_t NextChainOffset; 333 u_int8_t Flags; 334 union { 335 u_int32_t Address32; 336 u_int64_t Address64; 337 } u; 338 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 339 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 340 341 typedef struct _MPI2_IEEE_SGE_SIMPLE32 { 342 u_int32_t Address; 343 u_int32_t FlagsLength; 344 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 345 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 346 typedef struct _MPI2_IEEE_SGE_SIMPLE64 { 347 u_int64_t Address; 348 u_int32_t Length; 349 u_int16_t Reserved1; 350 u_int8_t Reserved2; 351 u_int8_t Flags; 352 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 353 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 354 355 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 356 MPI2_IEEE_SGE_SIMPLE32 Simple32; 357 MPI2_IEEE_SGE_SIMPLE64 Simple64; 358 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 359 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 360 361 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 362 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 363 364 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 365 MPI2_IEEE_SGE_CHAIN32 Chain32; 366 MPI2_IEEE_SGE_CHAIN64 Chain64; 367 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 368 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 369 370 typedef union _MPI2_SGE_IO_UNION { 371 MPI2_SGE_SIMPLE_UNION MpiSimple; 372 MPI2_SGE_CHAIN_UNION MpiChain; 373 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 374 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 375 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 376 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 377 378 typedef union { 379 u_int8_t CDB32[32]; 380 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 381 MPI2_SGE_SIMPLE_UNION SGE; 382 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 383 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 384 385 /**************************************************************************** 386 * * SCSI Task Management messages 387 * ****************************************************************************/ 388 389 /*SCSI Task Management Request Message */ 390 typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST { 391 u_int16_t DevHandle; /*0x00 */ 392 u_int8_t ChainOffset; /*0x02 */ 393 u_int8_t Function; /*0x03 */ 394 u_int8_t Reserved1; /*0x04 */ 395 u_int8_t TaskType; /*0x05 */ 396 u_int8_t Reserved2; /*0x06 */ 397 u_int8_t MsgFlags; /*0x07 */ 398 u_int8_t VP_ID; /*0x08 */ 399 u_int8_t VF_ID; /*0x09 */ 400 u_int16_t Reserved3; /*0x0A */ 401 u_int8_t LUN[8]; /*0x0C */ 402 u_int32_t Reserved4[7]; /*0x14 */ 403 u_int16_t TaskMID; /*0x30 */ 404 u_int16_t Reserved5; /*0x32 */ 405 } MPI2_SCSI_TASK_MANAGE_REQUEST; 406 407 /*SCSI Task Management Reply Message */ 408 typedef struct _MPI2_SCSI_TASK_MANAGE_REPLY { 409 u_int16_t DevHandle; /*0x00 */ 410 u_int8_t MsgLength; /*0x02 */ 411 u_int8_t Function; /*0x03 */ 412 u_int8_t ResponseCode; /*0x04 */ 413 u_int8_t TaskType; /*0x05 */ 414 u_int8_t Reserved1; /*0x06 */ 415 u_int8_t MsgFlags; /*0x07 */ 416 u_int8_t VP_ID; /*0x08 */ 417 u_int8_t VF_ID; /*0x09 */ 418 u_int16_t Reserved2; /*0x0A */ 419 u_int16_t Reserved3; /*0x0C */ 420 u_int16_t IOCStatus; /*0x0E */ 421 u_int32_t IOCLogInfo; /*0x10 */ 422 u_int32_t TerminationCount; /*0x14 */ 423 u_int32_t ResponseInfo; /*0x18 */ 424 } MPI2_SCSI_TASK_MANAGE_REPLY; 425 426 typedef struct _MR_TM_REQUEST { 427 char request[128]; 428 } MR_TM_REQUEST; 429 430 typedef struct _MR_TM_REPLY { 431 char reply[128]; 432 } MR_TM_REPLY; 433 434 /* SCSI Task Management Request Message */ 435 typedef struct _MR_TASK_MANAGE_REQUEST { 436 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */ 437 MR_TM_REQUEST TmRequest; 438 union { 439 struct { 440 u_int32_t isTMForLD:1; 441 u_int32_t isTMForPD:1; 442 u_int32_t reserved1:30; 443 u_int32_t reserved2; 444 } tmReqFlags; 445 MR_TM_REPLY TMReply; 446 } uTmReqReply; 447 } MR_TASK_MANAGE_REQUEST; 448 449 /* TaskType values */ 450 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) 451 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) 452 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) 453 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) 454 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) 455 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) 456 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08) 457 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09) 458 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A) 459 460 /* ResponseCode values */ 461 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00) 462 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02) 463 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04) 464 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05) 465 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08) 466 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09) 467 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A) 468 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80) 469 470 /* 471 * RAID SCSI IO Request Message Total SGE count will be one less than 472 * _MPI2_SCSI_IO_REQUEST 473 */ 474 typedef struct _MPI2_RAID_SCSI_IO_REQUEST { 475 u_int16_t DevHandle; /* 0x00 */ 476 u_int8_t ChainOffset; /* 0x02 */ 477 u_int8_t Function; /* 0x03 */ 478 u_int16_t Reserved1; /* 0x04 */ 479 u_int8_t Reserved2; /* 0x06 */ 480 u_int8_t MsgFlags; /* 0x07 */ 481 u_int8_t VP_ID; /* 0x08 */ 482 u_int8_t VF_ID; /* 0x09 */ 483 u_int16_t Reserved3; /* 0x0A */ 484 u_int32_t SenseBufferLowAddress;/* 0x0C */ 485 u_int16_t SGLFlags; /* 0x10 */ 486 u_int8_t SenseBufferLength; /* 0x12 */ 487 u_int8_t Reserved4; /* 0x13 */ 488 u_int8_t SGLOffset0; /* 0x14 */ 489 u_int8_t SGLOffset1; /* 0x15 */ 490 u_int8_t SGLOffset2; /* 0x16 */ 491 u_int8_t SGLOffset3; /* 0x17 */ 492 u_int32_t SkipCount; /* 0x18 */ 493 u_int32_t DataLength; /* 0x1C */ 494 u_int32_t BidirectionalDataLength; /* 0x20 */ 495 u_int16_t IoFlags; /* 0x24 */ 496 u_int16_t EEDPFlags; /* 0x26 */ 497 u_int32_t EEDPBlockSize; /* 0x28 */ 498 u_int32_t SecondaryReferenceTag;/* 0x2C */ 499 u_int16_t SecondaryApplicationTag; /* 0x30 */ 500 u_int16_t ApplicationTagTranslationMask; /* 0x32 */ 501 u_int8_t LUN[8]; /* 0x34 */ 502 u_int32_t Control; /* 0x3C */ 503 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 504 RAID_CONTEXT_UNION RaidContext; /* 0x60 */ 505 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 506 } MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST, 507 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t; 508 509 /* 510 * MPT RAID MFA IO Descriptor. 511 */ 512 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR { 513 u_int32_t RequestFlags:8; 514 u_int32_t MessageAddress1:24; /* bits 31:8 */ 515 u_int32_t MessageAddress2; /* bits 61:32 */ 516 } MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR; 517 518 /* Default Request Descriptor */ 519 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 520 u_int8_t RequestFlags; /* 0x00 */ 521 u_int8_t MSIxIndex; /* 0x01 */ 522 u_int16_t SMID; /* 0x02 */ 523 u_int16_t LMID; /* 0x04 */ 524 u_int16_t DescriptorTypeDependent; /* 0x06 */ 525 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 526 527 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 528 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 529 530 /* High Priority Request Descriptor */ 531 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 532 u_int8_t RequestFlags; /* 0x00 */ 533 u_int8_t MSIxIndex; /* 0x01 */ 534 u_int16_t SMID; /* 0x02 */ 535 u_int16_t LMID; /* 0x04 */ 536 u_int16_t Reserved1; /* 0x06 */ 537 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 538 539 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 540 Mpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 541 542 /* SCSI IO Request Descriptor */ 543 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 544 u_int8_t RequestFlags; /* 0x00 */ 545 u_int8_t MSIxIndex; /* 0x01 */ 546 u_int16_t SMID; /* 0x02 */ 547 u_int16_t LMID; /* 0x04 */ 548 u_int16_t DevHandle; /* 0x06 */ 549 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 550 551 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 552 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 553 554 /* SCSI Target Request Descriptor */ 555 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 556 u_int8_t RequestFlags; /* 0x00 */ 557 u_int8_t MSIxIndex; /* 0x01 */ 558 u_int16_t SMID; /* 0x02 */ 559 u_int16_t LMID; /* 0x04 */ 560 u_int16_t IoIndex; /* 0x06 */ 561 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 562 563 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 564 Mpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 565 566 /* RAID Accelerator Request Descriptor */ 567 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 568 u_int8_t RequestFlags; /* 0x00 */ 569 u_int8_t MSIxIndex; /* 0x01 */ 570 u_int16_t SMID; /* 0x02 */ 571 u_int16_t LMID; /* 0x04 */ 572 u_int16_t Reserved; /* 0x06 */ 573 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 574 575 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 576 Mpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 577 578 /* union of Request Descriptors */ 579 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION { 580 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 581 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 582 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 583 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 584 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 585 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 586 union { 587 struct { 588 u_int32_t low; 589 u_int32_t high; 590 } u; 591 u_int64_t Words; 592 } addr; 593 } MRSAS_REQUEST_DESCRIPTOR_UNION; 594 595 /* Default Reply Descriptor */ 596 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 597 u_int8_t ReplyFlags; /* 0x00 */ 598 u_int8_t MSIxIndex; /* 0x01 */ 599 u_int16_t DescriptorTypeDependent1; /* 0x02 */ 600 u_int32_t DescriptorTypeDependent2; /* 0x04 */ 601 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 602 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 603 604 /* Address Reply Descriptor */ 605 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 606 u_int8_t ReplyFlags; /* 0x00 */ 607 u_int8_t MSIxIndex; /* 0x01 */ 608 u_int16_t SMID; /* 0x02 */ 609 u_int32_t ReplyFrameAddress; /* 0x04 */ 610 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 611 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 612 613 /* SCSI IO Success Reply Descriptor */ 614 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 615 u_int8_t ReplyFlags; /* 0x00 */ 616 u_int8_t MSIxIndex; /* 0x01 */ 617 u_int16_t SMID; /* 0x02 */ 618 u_int16_t TaskTag; /* 0x04 */ 619 u_int16_t Reserved1; /* 0x06 */ 620 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 621 622 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 623 Mpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 624 625 /* TargetAssist Success Reply Descriptor */ 626 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 627 u_int8_t ReplyFlags; /* 0x00 */ 628 u_int8_t MSIxIndex; /* 0x01 */ 629 u_int16_t SMID; /* 0x02 */ 630 u_int8_t SequenceNumber; /* 0x04 */ 631 u_int8_t Reserved1; /* 0x05 */ 632 u_int16_t IoIndex; /* 0x06 */ 633 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 634 635 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 636 Mpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 637 638 /* Target Command Buffer Reply Descriptor */ 639 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 640 u_int8_t ReplyFlags; /* 0x00 */ 641 u_int8_t MSIxIndex; /* 0x01 */ 642 u_int8_t VP_ID; /* 0x02 */ 643 u_int8_t Flags; /* 0x03 */ 644 u_int16_t InitiatorDevHandle; /* 0x04 */ 645 u_int16_t IoIndex; /* 0x06 */ 646 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 647 648 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 649 Mpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 650 651 /* RAID Accelerator Success Reply Descriptor */ 652 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 653 u_int8_t ReplyFlags; /* 0x00 */ 654 u_int8_t MSIxIndex; /* 0x01 */ 655 u_int16_t SMID; /* 0x02 */ 656 u_int32_t Reserved; /* 0x04 */ 657 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 658 659 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 660 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 661 662 /* union of Reply Descriptors */ 663 typedef union _MPI2_REPLY_DESCRIPTORS_UNION { 664 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 665 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 666 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 667 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 668 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 669 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 670 u_int64_t Words; 671 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 672 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 673 674 typedef union { 675 volatile unsigned int val; 676 unsigned int val_rdonly; 677 } mrsas_atomic_t; 678 679 #define mrsas_atomic_read(v) atomic_load_acq_int(&(v)->val) 680 #define mrsas_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 681 #define mrsas_atomic_dec(v) atomic_subtract_int(&(v)->val, 1) 682 #define mrsas_atomic_inc(v) atomic_add_int(&(v)->val, 1) 683 684 static inline int 685 mrsas_atomic_inc_return(mrsas_atomic_t *v) 686 { 687 return 1 + atomic_fetchadd_int(&(v)->val, 1); 688 } 689 690 /* IOCInit Request message */ 691 typedef struct _MPI2_IOC_INIT_REQUEST { 692 u_int8_t WhoInit; /* 0x00 */ 693 u_int8_t Reserved1; /* 0x01 */ 694 u_int8_t ChainOffset; /* 0x02 */ 695 u_int8_t Function; /* 0x03 */ 696 u_int16_t Reserved2; /* 0x04 */ 697 u_int8_t Reserved3; /* 0x06 */ 698 u_int8_t MsgFlags; /* 0x07 */ 699 u_int8_t VP_ID; /* 0x08 */ 700 u_int8_t VF_ID; /* 0x09 */ 701 u_int16_t Reserved4; /* 0x0A */ 702 u_int16_t MsgVersion; /* 0x0C */ 703 u_int16_t HeaderVersion; /* 0x0E */ 704 u_int32_t Reserved5; /* 0x10 */ 705 u_int16_t Reserved6; /* 0x14 */ 706 u_int8_t HostPageSize; /* 0x16 */ 707 u_int8_t HostMSIxVectors; /* 0x17 */ 708 u_int16_t Reserved8; /* 0x18 */ 709 u_int16_t SystemRequestFrameSize; /* 0x1A */ 710 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 711 u_int16_t ReplyFreeQueueDepth; /* 0x1E */ 712 u_int32_t SenseBufferAddressHigh; /* 0x20 */ 713 u_int32_t SystemReplyAddressHigh; /* 0x24 */ 714 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */ 715 u_int64_t ReplyDescriptorPostQueueAddress; /* 0x30 */ 716 u_int64_t ReplyFreeQueueAddress;/* 0x38 */ 717 u_int64_t TimeStamp; /* 0x40 */ 718 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 719 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 720 721 /* 722 * MR private defines 723 */ 724 #define MR_PD_INVALID 0xFFFF 725 #define MR_DEVHANDLE_INVALID 0xFFFF 726 #define MAX_SPAN_DEPTH 8 727 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 728 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 729 #define MAX_ROW_SIZE 32 730 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 731 #define MAX_LOGICAL_DRIVES 64 732 #define MAX_LOGICAL_DRIVES_EXT 256 733 #define MAX_LOGICAL_DRIVES_DYN 512 734 735 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 736 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 737 738 #define MAX_ARRAYS 128 739 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 740 741 #define MAX_ARRAYS_EXT 256 742 #define MAX_API_ARRAYS_EXT MAX_ARRAYS_EXT 743 #define MAX_API_ARRAYS_DYN 512 744 745 #define MAX_PHYSICAL_DEVICES 256 746 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 747 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512 748 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 749 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102 750 #define MR_DCMD_PD_MFI_TASK_MGMT 0x0200e100 751 752 #define MR_DCMD_PD_GET_INFO 0x02020000 753 #define MRSAS_MAX_PD_CHANNELS 1 754 #define MRSAS_MAX_LD_CHANNELS 1 755 #define MRSAS_MAX_DEV_PER_CHANNEL 256 756 #define MRSAS_DEFAULT_INIT_ID -1 757 #define MRSAS_MAX_LUN 8 758 #define MRSAS_DEFAULT_CMD_PER_LUN 256 759 #define MRSAS_MAX_PD (MRSAS_MAX_PD_CHANNELS * \ 760 MRSAS_MAX_DEV_PER_CHANNEL) 761 #define MRSAS_MAX_LD_IDS (MRSAS_MAX_LD_CHANNELS * \ 762 MRSAS_MAX_DEV_PER_CHANNEL) 763 764 765 #define VD_EXT_DEBUG 0 766 #define TM_DEBUG 1 767 768 /******************************************************************* 769 * RAID map related structures 770 ********************************************************************/ 771 #pragma pack(1) 772 typedef struct _MR_DEV_HANDLE_INFO { 773 u_int16_t curDevHdl; 774 u_int8_t validHandles; 775 u_int8_t interfaceType; 776 u_int16_t devHandle[2]; 777 } MR_DEV_HANDLE_INFO; 778 779 #pragma pack() 780 781 typedef struct _MR_ARRAY_INFO { 782 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE]; 783 } MR_ARRAY_INFO; 784 785 typedef struct _MR_QUAD_ELEMENT { 786 u_int64_t logStart; 787 u_int64_t logEnd; 788 u_int64_t offsetInSpan; 789 u_int32_t diff; 790 u_int32_t reserved1; 791 } MR_QUAD_ELEMENT; 792 793 typedef struct _MR_SPAN_INFO { 794 u_int32_t noElements; 795 u_int32_t reserved1; 796 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 797 } MR_SPAN_INFO; 798 799 typedef struct _MR_LD_SPAN_ { 800 u_int64_t startBlk; 801 u_int64_t numBlks; 802 u_int16_t arrayRef; 803 u_int8_t spanRowSize; 804 u_int8_t spanRowDataSize; 805 u_int8_t reserved[4]; 806 } MR_LD_SPAN; 807 808 typedef struct _MR_SPAN_BLOCK_INFO { 809 u_int64_t num_rows; 810 MR_LD_SPAN span; 811 MR_SPAN_INFO block_span_info; 812 } MR_SPAN_BLOCK_INFO; 813 814 typedef struct _MR_LD_RAID { 815 struct { 816 u_int32_t fpCapable:1; 817 u_int32_t raCapable:1; 818 u_int32_t reserved5:2; 819 u_int32_t ldPiMode:4; 820 u_int32_t pdPiMode:4; 821 u_int32_t encryptionType:8; 822 u_int32_t fpWriteCapable:1; 823 u_int32_t fpReadCapable:1; 824 u_int32_t fpWriteAcrossStripe:1; 825 u_int32_t fpReadAcrossStripe:1; 826 u_int32_t fpNonRWCapable:1; 827 u_int32_t tmCapable:1; 828 u_int32_t fpCacheBypassCapable:1; 829 u_int32_t reserved4:5; 830 } capability; 831 u_int32_t reserved6; 832 u_int64_t size; 833 834 u_int8_t spanDepth; 835 u_int8_t level; 836 u_int8_t stripeShift; 837 u_int8_t rowSize; 838 839 u_int8_t rowDataSize; 840 u_int8_t writeMode; 841 u_int8_t PRL; 842 u_int8_t SRL; 843 844 u_int16_t targetId; 845 u_int8_t ldState; 846 u_int8_t regTypeReqOnWrite; 847 u_int8_t modFactor; 848 u_int8_t regTypeReqOnRead; 849 u_int16_t seqNum; 850 851 struct { 852 u_int32_t ldSyncRequired:1; 853 u_int32_t regTypeReqOnReadLsValid:1; 854 u_int32_t reserved:30; 855 } flags; 856 857 u_int8_t LUN[8]; 858 u_int8_t fpIoTimeoutForLd; 859 u_int8_t reserved2[3]; 860 u_int32_t logicalBlockLength; 861 struct { 862 u_int32_t LdPiExp:4; 863 u_int32_t LdLogicalBlockExp:4; 864 u_int32_t reserved1:24; 865 } exponent; 866 u_int8_t reserved3[0x80 - 0x38]; 867 } MR_LD_RAID; 868 869 typedef struct _MR_LD_SPAN_MAP { 870 MR_LD_RAID ldRaid; 871 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 872 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 873 } MR_LD_SPAN_MAP; 874 875 typedef struct _MR_FW_RAID_MAP { 876 u_int32_t totalSize; 877 union { 878 struct { 879 u_int32_t maxLd; 880 u_int32_t maxSpanDepth; 881 u_int32_t maxRowSize; 882 u_int32_t maxPdCount; 883 u_int32_t maxArrays; 884 } validationInfo; 885 u_int32_t version[5]; 886 u_int32_t reserved1[5]; 887 } raid_desc; 888 u_int32_t ldCount; 889 u_int32_t Reserved1; 890 891 /* 892 * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For 893 * example: if tgt Id is 4 and FW LD is 2, and there is only one LD, 894 * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF, 895 * 0x0,.....]. This is to help reduce the entire strcture size if 896 * there are few LDs or driver is looking info for 1 LD only. 897 */ 898 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS]; 899 u_int8_t fpPdIoTimeoutSec; 900 u_int8_t reserved2[7]; 901 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 902 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 903 MR_LD_SPAN_MAP ldSpanMap[1]; 904 } MR_FW_RAID_MAP; 905 906 907 typedef struct _MR_FW_RAID_MAP_EXT { 908 /* Not used in new map */ 909 u_int32_t reserved; 910 911 union { 912 struct { 913 u_int32_t maxLd; 914 u_int32_t maxSpanDepth; 915 u_int32_t maxRowSize; 916 u_int32_t maxPdCount; 917 u_int32_t maxArrays; 918 } validationInfo; 919 u_int32_t version[5]; 920 u_int32_t reserved1[5]; 921 } fw_raid_desc; 922 923 u_int8_t fpPdIoTimeoutSec; 924 u_int8_t reserved2[7]; 925 926 u_int16_t ldCount; 927 u_int16_t arCount; 928 u_int16_t spanCount; 929 u_int16_t reserve3; 930 931 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 932 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 933 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 934 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 935 } MR_FW_RAID_MAP_EXT; 936 937 938 typedef struct _MR_DRV_RAID_MAP { 939 /* 940 * Total size of this structure, including this field. This feild 941 * will be manupulated by driver for ext raid map, else pick the 942 * value from firmware raid map. 943 */ 944 u_int32_t totalSize; 945 946 union { 947 struct { 948 u_int32_t maxLd; 949 u_int32_t maxSpanDepth; 950 u_int32_t maxRowSize; 951 u_int32_t maxPdCount; 952 u_int32_t maxArrays; 953 } validationInfo; 954 u_int32_t version[5]; 955 u_int32_t reserved1[5]; 956 } drv_raid_desc; 957 958 /* timeout value used by driver in FP IOs */ 959 u_int8_t fpPdIoTimeoutSec; 960 u_int8_t reserved2[7]; 961 962 u_int16_t ldCount; 963 u_int16_t arCount; 964 u_int16_t spanCount; 965 u_int16_t reserve3; 966 967 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN]; 968 u_int16_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN]; 969 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN]; 970 MR_LD_SPAN_MAP ldSpanMap[1]; 971 972 } MR_DRV_RAID_MAP; 973 974 /* 975 * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is 976 * created to sync with old raid. And it is mainly for code re-use purpose. 977 */ 978 979 #pragma pack(1) 980 typedef struct _MR_DRV_RAID_MAP_ALL { 981 982 MR_DRV_RAID_MAP raidMap; 983 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1]; 984 } MR_DRV_RAID_MAP_ALL; 985 986 #pragma pack() 987 988 typedef struct _LD_LOAD_BALANCE_INFO { 989 u_int8_t loadBalanceFlag; 990 u_int8_t reserved1; 991 mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES]; 992 u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES]; 993 } LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO; 994 995 /* SPAN_SET is info caclulated from span info from Raid map per ld */ 996 typedef struct _LD_SPAN_SET { 997 u_int64_t log_start_lba; 998 u_int64_t log_end_lba; 999 u_int64_t span_row_start; 1000 u_int64_t span_row_end; 1001 u_int64_t data_strip_start; 1002 u_int64_t data_strip_end; 1003 u_int64_t data_row_start; 1004 u_int64_t data_row_end; 1005 u_int8_t strip_offset[MAX_SPAN_DEPTH]; 1006 u_int32_t span_row_data_width; 1007 u_int32_t diff; 1008 u_int32_t reserved[2]; 1009 } LD_SPAN_SET, *PLD_SPAN_SET; 1010 1011 typedef struct LOG_BLOCK_SPAN_INFO { 1012 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 1013 } LD_SPAN_INFO, *PLD_SPAN_INFO; 1014 1015 #pragma pack(1) 1016 typedef struct _MR_FW_RAID_MAP_ALL { 1017 MR_FW_RAID_MAP raidMap; 1018 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 1019 } MR_FW_RAID_MAP_ALL; 1020 1021 #pragma pack() 1022 1023 struct IO_REQUEST_INFO { 1024 u_int64_t ldStartBlock; 1025 u_int32_t numBlocks; 1026 u_int16_t ldTgtId; 1027 u_int8_t isRead; 1028 u_int16_t devHandle; 1029 u_int8_t pdInterface; 1030 u_int64_t pdBlock; 1031 u_int8_t fpOkForIo; 1032 u_int8_t IoforUnevenSpan; 1033 u_int8_t start_span; 1034 u_int8_t reserved; 1035 u_int64_t start_row; 1036 /* span[7:5], arm[4:0] */ 1037 u_int8_t span_arm; 1038 u_int8_t pd_after_lb; 1039 boolean_t raCapable; 1040 u_int16_t r1_alt_dev_handle; 1041 }; 1042 1043 /* 1044 * define MR_PD_CFG_SEQ structure for system PDs 1045 */ 1046 struct MR_PD_CFG_SEQ { 1047 u_int16_t seqNum; 1048 u_int16_t devHandle; 1049 struct { 1050 u_int8_t tmCapable:1; 1051 u_int8_t reserved:7; 1052 } capability; 1053 u_int8_t reserved; 1054 u_int16_t pdTargetId; 1055 } __packed; 1056 1057 struct MR_PD_CFG_SEQ_NUM_SYNC { 1058 u_int32_t size; 1059 u_int32_t count; 1060 struct MR_PD_CFG_SEQ seq[1]; 1061 } __packed; 1062 1063 typedef struct _STREAM_DETECT { 1064 u_int64_t nextSeqLBA; 1065 struct megasas_cmd_fusion *first_cmd_fusion; 1066 struct megasas_cmd_fusion *last_cmd_fusion; 1067 u_int32_t countCmdsInStream; 1068 u_int16_t numSGEsInGroup; 1069 u_int8_t isRead; 1070 u_int8_t groupDepth; 1071 boolean_t groupFlush; 1072 u_int8_t reserved[7]; 1073 } STREAM_DETECT, *PTR_STREAM_DETECT; 1074 1075 typedef struct _LD_STREAM_DETECT { 1076 boolean_t writeBack; 1077 boolean_t FPWriteEnabled; 1078 boolean_t membersSSDs; 1079 boolean_t fpCacheBypassCapable; 1080 u_int32_t mruBitMap; 1081 volatile long iosToFware; 1082 volatile long writeBytesOutstanding; 1083 STREAM_DETECT streamTrack[MAX_STREAMS_TRACKED]; 1084 } LD_STREAM_DETECT, *PTR_LD_STREAM_DETECT; 1085 1086 1087 typedef struct _MR_LD_TARGET_SYNC { 1088 u_int8_t targetId; 1089 u_int8_t reserved; 1090 u_int16_t seqNum; 1091 } MR_LD_TARGET_SYNC; 1092 1093 1094 /* 1095 * RAID Map descriptor Types. 1096 * Each element should uniquely idetify one data structure in the RAID map 1097 */ 1098 typedef enum _MR_RAID_MAP_DESC_TYPE { 1099 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0, /* MR_DEV_HANDLE_INFO data */ 1100 RAID_MAP_DESC_TYPE_TGTID_INFO = 1, /* target to Ld num Index map */ 1101 RAID_MAP_DESC_TYPE_ARRAY_INFO = 2, /* MR_ARRAY_INFO data */ 1102 RAID_MAP_DESC_TYPE_SPAN_INFO = 3, /* MR_LD_SPAN_MAP data */ 1103 RAID_MAP_DESC_TYPE_COUNT, 1104 } MR_RAID_MAP_DESC_TYPE; 1105 1106 /* 1107 * This table defines the offset, size and num elements of each descriptor 1108 * type in the RAID Map buffer 1109 */ 1110 typedef struct _MR_RAID_MAP_DESC_TABLE { 1111 /* Raid map descriptor type */ 1112 u_int32_t raidMapDescType; 1113 /* Offset into the RAID map buffer where descriptor data is saved */ 1114 u_int32_t raidMapDescOffset; 1115 /* total size of the descriptor buffer */ 1116 u_int32_t raidMapDescBufferSize; 1117 /* Number of elements contained in the descriptor buffer */ 1118 u_int32_t raidMapDescElements; 1119 } MR_RAID_MAP_DESC_TABLE; 1120 1121 /* 1122 * Dynamic Raid Map Structure. 1123 */ 1124 typedef struct _MR_FW_RAID_MAP_DYNAMIC { 1125 u_int32_t raidMapSize; 1126 u_int32_t descTableOffset; 1127 u_int32_t descTableSize; 1128 u_int32_t descTableNumElements; 1129 u_int64_t PCIThresholdBandwidth; 1130 u_int32_t reserved2[3]; 1131 1132 u_int8_t fpPdIoTimeoutSec; 1133 u_int8_t reserved3[3]; 1134 u_int32_t rmwFPSeqNum; 1135 u_int16_t ldCount; 1136 u_int16_t arCount; 1137 u_int16_t spanCount; 1138 u_int16_t reserved4[3]; 1139 1140 /* 1141 * The below structure of pointers is only to be used by the driver. 1142 * This is added in the API to reduce the amount of code changes needed in 1143 * the driver to support dynamic RAID map. 1144 * Firmware should not update these pointers while preparing the raid map 1145 */ 1146 union { 1147 struct { 1148 MR_DEV_HANDLE_INFO *devHndlInfo; 1149 u_int16_t *ldTgtIdToLd; 1150 MR_ARRAY_INFO *arMapInfo; 1151 MR_LD_SPAN_MAP *ldSpanMap; 1152 } ptrStruct; 1153 u_int64_t ptrStructureSize[RAID_MAP_DESC_TYPE_COUNT]; 1154 } RaidMapDescPtrs; 1155 1156 /* 1157 * RAID Map descriptor table defines the layout of data in the RAID Map. 1158 * The size of the descriptor table itself could change. 1159 */ 1160 1161 /* Variable Size descriptor Table. */ 1162 MR_RAID_MAP_DESC_TABLE raidMapDescTable[RAID_MAP_DESC_TYPE_COUNT]; 1163 /* Variable Size buffer containing all data */ 1164 u_int32_t raidMapDescData[1]; 1165 1166 } MR_FW_RAID_MAP_DYNAMIC; 1167 1168 1169 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1170 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1171 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1172 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1173 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1174 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1175 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1176 1177 /* Few NVME flags defines*/ 1178 #define MPI2_SGE_FLAGS_SHIFT (0x02) 1179 #define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0) 1180 #define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00) 1181 #define IEEE_SGE_FLAGS_FORMAT_PQI (0x01) 1182 #define IEEE_SGE_FLAGS_FORMAT_NVME (0x02) 1183 #define IEEE_SGE_FLAGS_FORMAT_AHCI (0x03) 1184 1185 1186 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1187 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1188 #define MPI26_IEEE_SGE_FLAGS_NSF_PQI (0x04) 1189 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1190 #define MPI26_IEEE_SGE_FLAGS_NSF_AHCI_PRDT (0x0C) 1191 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1192 1193 union desc_value { 1194 u_int64_t word; 1195 struct { 1196 u_int32_t low; 1197 u_int32_t high; 1198 } u; 1199 }; 1200 1201 /******************************************************************* 1202 * Temporary command 1203 ********************************************************************/ 1204 struct mrsas_tmp_dcmd { 1205 bus_dma_tag_t tmp_dcmd_tag; 1206 bus_dmamap_t tmp_dcmd_dmamap; 1207 void *tmp_dcmd_mem; 1208 bus_addr_t tmp_dcmd_phys_addr; 1209 }; 1210 1211 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16 1212 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF 1213 #define MR_MIN_MAP_SIZE 0x10000 1214 1215 1216 /******************************************************************* 1217 * Register set, included legacy controllers 1068 and 1078, 1218 * structure extended for 1078 registers 1219 *******************************************************************/ 1220 #pragma pack(1) 1221 typedef struct _mrsas_register_set { 1222 u_int32_t doorbell; /* 0000h */ 1223 u_int32_t fusion_seq_offset; /* 0004h */ 1224 u_int32_t fusion_host_diag; /* 0008h */ 1225 u_int32_t reserved_01; /* 000Ch */ 1226 1227 u_int32_t inbound_msg_0; /* 0010h */ 1228 u_int32_t inbound_msg_1; /* 0014h */ 1229 u_int32_t outbound_msg_0; /* 0018h */ 1230 u_int32_t outbound_msg_1; /* 001Ch */ 1231 1232 u_int32_t inbound_doorbell; /* 0020h */ 1233 u_int32_t inbound_intr_status; /* 0024h */ 1234 u_int32_t inbound_intr_mask; /* 0028h */ 1235 1236 u_int32_t outbound_doorbell; /* 002Ch */ 1237 u_int32_t outbound_intr_status; /* 0030h */ 1238 u_int32_t outbound_intr_mask; /* 0034h */ 1239 1240 u_int32_t reserved_1[2]; /* 0038h */ 1241 1242 u_int32_t inbound_queue_port; /* 0040h */ 1243 u_int32_t outbound_queue_port; /* 0044h */ 1244 1245 u_int32_t reserved_2[9]; /* 0048h */ 1246 u_int32_t reply_post_host_index;/* 006Ch */ 1247 u_int32_t reserved_2_2[12]; /* 0070h */ 1248 1249 u_int32_t outbound_doorbell_clear; /* 00A0h */ 1250 1251 u_int32_t reserved_3[3]; /* 00A4h */ 1252 1253 u_int32_t outbound_scratch_pad; /* 00B0h */ 1254 u_int32_t outbound_scratch_pad_2; /* 00B4h */ 1255 u_int32_t outbound_scratch_pad_3; /* 00B8h */ 1256 u_int32_t outbound_scratch_pad_4; /* 00BCh */ 1257 1258 u_int32_t inbound_low_queue_port; /* 00C0h */ 1259 1260 u_int32_t inbound_high_queue_port; /* 00C4h */ 1261 1262 u_int32_t inbound_single_queue_port; /* 00C8h */ 1263 u_int32_t res_6[11]; /* CCh */ 1264 u_int32_t host_diag; 1265 u_int32_t seq_offset; 1266 u_int32_t index_registers[807]; /* 00CCh */ 1267 } mrsas_reg_set; 1268 1269 #pragma pack() 1270 1271 /******************************************************************* 1272 * Firmware Interface Defines 1273 ******************************************************************* 1274 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 1275 * for protocol between the software and firmware. Commands are 1276 * issued using "message frames". 1277 ******************************************************************/ 1278 /* 1279 * FW posts its state in upper 4 bits of outbound_msg_0 register 1280 */ 1281 #define MFI_STATE_MASK 0xF0000000 1282 #define MFI_STATE_UNDEFINED 0x00000000 1283 #define MFI_STATE_BB_INIT 0x10000000 1284 #define MFI_STATE_FW_INIT 0x40000000 1285 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 1286 #define MFI_STATE_FW_INIT_2 0x70000000 1287 #define MFI_STATE_DEVICE_SCAN 0x80000000 1288 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 1289 #define MFI_STATE_FLUSH_CACHE 0xA0000000 1290 #define MFI_STATE_READY 0xB0000000 1291 #define MFI_STATE_OPERATIONAL 0xC0000000 1292 #define MFI_STATE_FAULT 0xF0000000 1293 #define MFI_RESET_REQUIRED 0x00000001 1294 #define MFI_RESET_ADAPTER 0x00000002 1295 #define MEGAMFI_FRAME_SIZE 64 1296 #define MRSAS_MFI_FRAME_SIZE 1024 1297 #define MRSAS_MFI_SENSE_SIZE 128 1298 1299 /* 1300 * During FW init, clear pending cmds & reset state using inbound_msg_0 1301 * 1302 * ABORT : Abort all pending cmds READY : Move from OPERATIONAL to 1303 * READY state; discard queue info MFIMODE : Discard (possible) low MFA 1304 * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from 1305 * BIOS or Driver HOTPLUG : Resume from Hotplug MFI_STOP_ADP : Send 1306 * signal to FW to stop processing 1307 */ 1308 1309 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) 1310 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) 1311 #define DIAG_WRITE_ENABLE (0x00000080) 1312 #define DIAG_RESET_ADAPTER (0x00000004) 1313 1314 #define MFI_ADP_RESET 0x00000040 1315 #define MFI_INIT_ABORT 0x00000001 1316 #define MFI_INIT_READY 0x00000002 1317 #define MFI_INIT_MFIMODE 0x00000004 1318 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 1319 #define MFI_INIT_HOTPLUG 0x00000010 1320 #define MFI_STOP_ADP 0x00000020 1321 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 1322 MFI_INIT_MFIMODE| \ 1323 MFI_INIT_ABORT 1324 1325 /* 1326 * MFI frame flags 1327 */ 1328 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 1329 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 1330 #define MFI_FRAME_SGL32 0x0000 1331 #define MFI_FRAME_SGL64 0x0002 1332 #define MFI_FRAME_SENSE32 0x0000 1333 #define MFI_FRAME_SENSE64 0x0004 1334 #define MFI_FRAME_DIR_NONE 0x0000 1335 #define MFI_FRAME_DIR_WRITE 0x0008 1336 #define MFI_FRAME_DIR_READ 0x0010 1337 #define MFI_FRAME_DIR_BOTH 0x0018 1338 #define MFI_FRAME_IEEE 0x0020 1339 1340 /* 1341 * Definition for cmd_status 1342 */ 1343 #define MFI_CMD_STATUS_POLL_MODE 0xFF 1344 1345 /* 1346 * MFI command opcodes 1347 */ 1348 #define MFI_CMD_INIT 0x00 1349 #define MFI_CMD_LD_READ 0x01 1350 #define MFI_CMD_LD_WRITE 0x02 1351 #define MFI_CMD_LD_SCSI_IO 0x03 1352 #define MFI_CMD_PD_SCSI_IO 0x04 1353 #define MFI_CMD_DCMD 0x05 1354 #define MFI_CMD_ABORT 0x06 1355 #define MFI_CMD_SMP 0x07 1356 #define MFI_CMD_STP 0x08 1357 #define MFI_CMD_INVALID 0xff 1358 1359 #define MR_DCMD_CTRL_GET_INFO 0x01010000 1360 #define MR_DCMD_LD_GET_LIST 0x03010000 1361 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 1362 #define MR_FLUSH_CTRL_CACHE 0x01 1363 #define MR_FLUSH_DISK_CACHE 0x02 1364 1365 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 1366 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 1367 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 1368 1369 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 1370 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 1371 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 1372 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 1373 1374 #define MR_DCMD_CLUSTER 0x08000000 1375 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 1376 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 1377 #define MR_DCMD_PD_LIST_QUERY 0x02010100 1378 1379 #define MR_DCMD_CTRL_MISC_CPX 0x0100e200 1380 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201 1381 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202 1382 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203 1383 #define MAX_MR_ROW_SIZE 32 1384 #define MR_CPX_DIR_WRITE 1 1385 #define MR_CPX_DIR_READ 0 1386 #define MR_CPX_VERSION 1 1387 1388 #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 1389 1390 #define MR_EVT_CFG_CLEARED 0x0004 1391 1392 #define MR_EVT_LD_STATE_CHANGE 0x0051 1393 #define MR_EVT_PD_INSERTED 0x005b 1394 #define MR_EVT_PD_REMOVED 0x0070 1395 #define MR_EVT_LD_CREATED 0x008a 1396 #define MR_EVT_LD_DELETED 0x008b 1397 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1398 #define MR_EVT_LD_OFFLINE 0x00fc 1399 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1400 #define MR_EVT_CTRL_PERF_COLLECTION 0x017e 1401 1402 /* 1403 * MFI command completion codes 1404 */ 1405 enum MFI_STAT { 1406 MFI_STAT_OK = 0x00, 1407 MFI_STAT_INVALID_CMD = 0x01, 1408 MFI_STAT_INVALID_DCMD = 0x02, 1409 MFI_STAT_INVALID_PARAMETER = 0x03, 1410 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 1411 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 1412 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 1413 MFI_STAT_APP_IN_USE = 0x07, 1414 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 1415 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 1416 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 1417 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 1418 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 1419 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 1420 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 1421 MFI_STAT_FLASH_BUSY = 0x0f, 1422 MFI_STAT_FLASH_ERROR = 0x10, 1423 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 1424 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 1425 MFI_STAT_FLASH_NOT_OPEN = 0x13, 1426 MFI_STAT_FLASH_NOT_STARTED = 0x14, 1427 MFI_STAT_FLUSH_FAILED = 0x15, 1428 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 1429 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 1430 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 1431 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 1432 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 1433 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 1434 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 1435 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 1436 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 1437 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 1438 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 1439 MFI_STAT_MFC_HW_ERROR = 0x21, 1440 MFI_STAT_NO_HW_PRESENT = 0x22, 1441 MFI_STAT_NOT_FOUND = 0x23, 1442 MFI_STAT_NOT_IN_ENCL = 0x24, 1443 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 1444 MFI_STAT_PD_TYPE_WRONG = 0x26, 1445 MFI_STAT_PR_DISABLED = 0x27, 1446 MFI_STAT_ROW_INDEX_INVALID = 0x28, 1447 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 1448 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 1449 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 1450 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 1451 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 1452 MFI_STAT_SCSI_IO_FAILED = 0x2e, 1453 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 1454 MFI_STAT_SHUTDOWN_FAILED = 0x30, 1455 MFI_STAT_TIME_NOT_SET = 0x31, 1456 MFI_STAT_WRONG_STATE = 0x32, 1457 MFI_STAT_LD_OFFLINE = 0x33, 1458 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 1459 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 1460 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 1461 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 1462 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 1463 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 1464 1465 MFI_STAT_INVALID_STATUS = 0xFF 1466 }; 1467 1468 /* 1469 * Number of mailbox bytes in DCMD message frame 1470 */ 1471 #define MFI_MBOX_SIZE 12 1472 1473 enum MR_EVT_CLASS { 1474 1475 MR_EVT_CLASS_DEBUG = -2, 1476 MR_EVT_CLASS_PROGRESS = -1, 1477 MR_EVT_CLASS_INFO = 0, 1478 MR_EVT_CLASS_WARNING = 1, 1479 MR_EVT_CLASS_CRITICAL = 2, 1480 MR_EVT_CLASS_FATAL = 3, 1481 MR_EVT_CLASS_DEAD = 4, 1482 1483 }; 1484 1485 enum MR_EVT_LOCALE { 1486 1487 MR_EVT_LOCALE_LD = 0x0001, 1488 MR_EVT_LOCALE_PD = 0x0002, 1489 MR_EVT_LOCALE_ENCL = 0x0004, 1490 MR_EVT_LOCALE_BBU = 0x0008, 1491 MR_EVT_LOCALE_SAS = 0x0010, 1492 MR_EVT_LOCALE_CTRL = 0x0020, 1493 MR_EVT_LOCALE_CONFIG = 0x0040, 1494 MR_EVT_LOCALE_CLUSTER = 0x0080, 1495 MR_EVT_LOCALE_ALL = 0xffff, 1496 1497 }; 1498 1499 enum MR_EVT_ARGS { 1500 1501 MR_EVT_ARGS_NONE, 1502 MR_EVT_ARGS_CDB_SENSE, 1503 MR_EVT_ARGS_LD, 1504 MR_EVT_ARGS_LD_COUNT, 1505 MR_EVT_ARGS_LD_LBA, 1506 MR_EVT_ARGS_LD_OWNER, 1507 MR_EVT_ARGS_LD_LBA_PD_LBA, 1508 MR_EVT_ARGS_LD_PROG, 1509 MR_EVT_ARGS_LD_STATE, 1510 MR_EVT_ARGS_LD_STRIP, 1511 MR_EVT_ARGS_PD, 1512 MR_EVT_ARGS_PD_ERR, 1513 MR_EVT_ARGS_PD_LBA, 1514 MR_EVT_ARGS_PD_LBA_LD, 1515 MR_EVT_ARGS_PD_PROG, 1516 MR_EVT_ARGS_PD_STATE, 1517 MR_EVT_ARGS_PCI, 1518 MR_EVT_ARGS_RATE, 1519 MR_EVT_ARGS_STR, 1520 MR_EVT_ARGS_TIME, 1521 MR_EVT_ARGS_ECC, 1522 MR_EVT_ARGS_LD_PROP, 1523 MR_EVT_ARGS_PD_SPARE, 1524 MR_EVT_ARGS_PD_INDEX, 1525 MR_EVT_ARGS_DIAG_PASS, 1526 MR_EVT_ARGS_DIAG_FAIL, 1527 MR_EVT_ARGS_PD_LBA_LBA, 1528 MR_EVT_ARGS_PORT_PHY, 1529 MR_EVT_ARGS_PD_MISSING, 1530 MR_EVT_ARGS_PD_ADDRESS, 1531 MR_EVT_ARGS_BITMAP, 1532 MR_EVT_ARGS_CONNECTOR, 1533 MR_EVT_ARGS_PD_PD, 1534 MR_EVT_ARGS_PD_FRU, 1535 MR_EVT_ARGS_PD_PATHINFO, 1536 MR_EVT_ARGS_PD_POWER_STATE, 1537 MR_EVT_ARGS_GENERIC, 1538 }; 1539 1540 /* 1541 * Thunderbolt (and later) Defines 1542 */ 1543 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024 1544 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 1545 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 1546 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 1547 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 1548 #define MRSAS_LOAD_BALANCE_FLAG 0x1 1549 #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1 1550 #define HOST_DIAG_WRITE_ENABLE 0x80 1551 #define HOST_DIAG_RESET_ADAPTER 0x4 1552 #define MRSAS_TBOLT_MAX_RESET_TRIES 3 1553 #define MRSAS_MAX_MFI_CMDS 16 1554 #define MRSAS_MAX_IOCTL_CMDS 3 1555 1556 /* 1557 * Invader Defines 1558 */ 1559 #define MPI2_TYPE_CUDA 0x2 1560 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 1561 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 1562 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 1563 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 1564 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 1565 #define MR_RL_WRITE_THROUGH_MODE 0x00 1566 #define MR_RL_WRITE_BACK_MODE 0x01 1567 1568 /* 1569 * T10 PI defines 1570 */ 1571 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 1572 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 1573 #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9 1574 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB 1575 #define MRSAS_SCSI_ADDL_CDB_LEN 0x18 1576 #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20 1577 #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60 1578 #define MRSAS_SCSIBLOCKSIZE 512 1579 1580 /* 1581 * Raid context flags 1582 */ 1583 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 1584 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 1585 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 1586 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 1587 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 1588 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2, 1589 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3, 1590 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4, 1591 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6, 1592 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7 1593 } MR_RAID_FLAGS_IO_SUB_TYPE; 1594 /* 1595 * Request descriptor types 1596 */ 1597 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1598 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1 1599 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 1600 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 1601 #define MRSAS_FP_CMD_LEN 16 1602 #define MRSAS_FUSION_IN_RESET 0 1603 1604 #define RAID_CTX_SPANARM_ARM_SHIFT (0) 1605 #define RAID_CTX_SPANARM_ARM_MASK (0x1f) 1606 #define RAID_CTX_SPANARM_SPAN_SHIFT (5) 1607 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 1608 1609 /* 1610 * Define region lock types 1611 */ 1612 typedef enum _REGION_TYPE { 1613 REGION_TYPE_UNUSED = 0, 1614 REGION_TYPE_SHARED_READ = 1, 1615 REGION_TYPE_SHARED_WRITE = 2, 1616 REGION_TYPE_EXCLUSIVE = 3, 1617 } REGION_TYPE; 1618 1619 1620 /* 1621 * SCSI-CAM Related Defines 1622 */ 1623 #define MRSAS_SCSI_MAX_LUNS 0 1624 #define MRSAS_SCSI_INITIATOR_ID 255 1625 #define MRSAS_SCSI_MAX_CMDS 8 1626 #define MRSAS_SCSI_MAX_CDB_LEN 16 1627 #define MRSAS_SCSI_SENSE_BUFFERSIZE 96 1628 #define MRSAS_INTERNAL_CMDS 32 1629 #define MRSAS_FUSION_INT_CMDS 8 1630 1631 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000 1632 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0 1633 #define MEGASAS_256K_IO 128 1634 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4) 1635 1636 /* Request types */ 1637 #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0 1638 #define MRSAS_REQ_TYPE_AEN_FETCH 0x1 1639 #define MRSAS_REQ_TYPE_PASSTHRU 0x2 1640 #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3 1641 #define MRSAS_REQ_TYPE_SCSI_IO 0x4 1642 1643 /* Request states */ 1644 #define MRSAS_REQ_STATE_FREE 0 1645 #define MRSAS_REQ_STATE_BUSY 1 1646 #define MRSAS_REQ_STATE_TRAN 2 1647 #define MRSAS_REQ_STATE_COMPLETE 3 1648 1649 typedef enum _MR_SCSI_CMD_TYPE { 1650 READ_WRITE_LDIO = 0, 1651 NON_READ_WRITE_LDIO = 1, 1652 READ_WRITE_SYSPDIO = 2, 1653 NON_READ_WRITE_SYSPDIO = 3, 1654 } MR_SCSI_CMD_TYPE; 1655 1656 enum mrsas_req_flags { 1657 MRSAS_DIR_UNKNOWN = 0x1, 1658 MRSAS_DIR_IN = 0x2, 1659 MRSAS_DIR_OUT = 0x4, 1660 MRSAS_DIR_NONE = 0x8, 1661 }; 1662 1663 /* 1664 * Adapter Reset States 1665 */ 1666 enum { 1667 MRSAS_HBA_OPERATIONAL = 0, 1668 MRSAS_ADPRESET_SM_INFAULT = 1, 1669 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1670 MRSAS_ADPRESET_SM_OPERATIONAL = 3, 1671 MRSAS_HW_CRITICAL_ERROR = 4, 1672 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1673 }; 1674 1675 /* 1676 * MPT Command Structure 1677 */ 1678 struct mrsas_mpt_cmd { 1679 MRSAS_RAID_SCSI_IO_REQUEST *io_request; 1680 bus_addr_t io_request_phys_addr; 1681 MPI2_SGE_IO_UNION *chain_frame; 1682 bus_addr_t chain_frame_phys_addr; 1683 u_int32_t sge_count; 1684 u_int8_t *sense; 1685 bus_addr_t sense_phys_addr; 1686 u_int8_t retry_for_fw_reset; 1687 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1688 u_int32_t sync_cmd_idx; 1689 u_int32_t index; 1690 u_int8_t flags; 1691 u_int8_t pd_r1_lb; 1692 u_int8_t load_balance; 1693 bus_size_t length; 1694 u_int32_t error_code; 1695 bus_dmamap_t data_dmamap; 1696 void *data; 1697 union ccb *ccb_ptr; 1698 struct callout cm_callout; 1699 struct mrsas_softc *sc; 1700 boolean_t tmCapable; 1701 u_int16_t r1_alt_dev_handle; 1702 boolean_t cmd_completed; 1703 struct mrsas_mpt_cmd *peer_cmd; 1704 bool callout_owner; 1705 TAILQ_ENTRY(mrsas_mpt_cmd) next; 1706 u_int8_t pdInterface; 1707 }; 1708 1709 /* 1710 * MFI Command Structure 1711 */ 1712 struct mrsas_mfi_cmd { 1713 union mrsas_frame *frame; 1714 bus_dmamap_t frame_dmamap; 1715 void *frame_mem; 1716 bus_addr_t frame_phys_addr; 1717 u_int8_t *sense; 1718 bus_dmamap_t sense_dmamap; 1719 void *sense_mem; 1720 bus_addr_t sense_phys_addr; 1721 u_int32_t index; 1722 u_int8_t sync_cmd; 1723 u_int8_t cmd_status; 1724 u_int8_t abort_aen; 1725 u_int8_t retry_for_fw_reset; 1726 struct mrsas_softc *sc; 1727 union ccb *ccb_ptr; 1728 union { 1729 struct { 1730 u_int16_t smid; 1731 u_int16_t resvd; 1732 } context; 1733 u_int32_t frame_count; 1734 } cmd_id; 1735 TAILQ_ENTRY(mrsas_mfi_cmd) next; 1736 }; 1737 1738 1739 /* 1740 * define constants for device list query options 1741 */ 1742 enum MR_PD_QUERY_TYPE { 1743 MR_PD_QUERY_TYPE_ALL = 0, 1744 MR_PD_QUERY_TYPE_STATE = 1, 1745 MR_PD_QUERY_TYPE_POWER_STATE = 2, 1746 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 1747 MR_PD_QUERY_TYPE_SPEED = 4, 1748 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 1749 }; 1750 1751 #define MR_EVT_CFG_CLEARED 0x0004 1752 #define MR_EVT_LD_STATE_CHANGE 0x0051 1753 #define MR_EVT_PD_INSERTED 0x005b 1754 #define MR_EVT_PD_REMOVED 0x0070 1755 #define MR_EVT_LD_CREATED 0x008a 1756 #define MR_EVT_LD_DELETED 0x008b 1757 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1758 #define MR_EVT_LD_OFFLINE 0x00fc 1759 #define MR_EVT_CTRL_PROP_CHANGED 0x012f 1760 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1761 1762 enum MR_PD_STATE { 1763 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1764 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 1765 MR_PD_STATE_HOT_SPARE = 0x02, 1766 MR_PD_STATE_OFFLINE = 0x10, 1767 MR_PD_STATE_FAILED = 0x11, 1768 MR_PD_STATE_REBUILD = 0x14, 1769 MR_PD_STATE_ONLINE = 0x18, 1770 MR_PD_STATE_COPYBACK = 0x20, 1771 MR_PD_STATE_SYSTEM = 0x40, 1772 }; 1773 1774 /* 1775 * defines the physical drive address structure 1776 */ 1777 #pragma pack(1) 1778 struct MR_PD_ADDRESS { 1779 u_int16_t deviceId; 1780 u_int16_t enclDeviceId; 1781 1782 union { 1783 struct { 1784 u_int8_t enclIndex; 1785 u_int8_t slotNumber; 1786 } mrPdAddress; 1787 struct { 1788 u_int8_t enclPosition; 1789 u_int8_t enclConnectorIndex; 1790 } mrEnclAddress; 1791 } u1; 1792 u_int8_t scsiDevType; 1793 union { 1794 u_int8_t connectedPortBitmap; 1795 u_int8_t connectedPortNumbers; 1796 } u2; 1797 u_int64_t sasAddr[2]; 1798 }; 1799 1800 #pragma pack() 1801 1802 /* 1803 * defines the physical drive list structure 1804 */ 1805 #pragma pack(1) 1806 struct MR_PD_LIST { 1807 u_int32_t size; 1808 u_int32_t count; 1809 struct MR_PD_ADDRESS addr[1]; 1810 }; 1811 1812 #pragma pack() 1813 1814 #pragma pack(1) 1815 struct mrsas_pd_list { 1816 u_int16_t tid; 1817 u_int8_t driveType; 1818 u_int8_t driveState; 1819 }; 1820 1821 #pragma pack() 1822 1823 /* 1824 * defines the logical drive reference structure 1825 */ 1826 typedef union _MR_LD_REF { 1827 struct { 1828 u_int8_t targetId; 1829 u_int8_t reserved; 1830 u_int16_t seqNum; 1831 } ld_context; 1832 u_int32_t ref; 1833 } MR_LD_REF; 1834 1835 1836 /* 1837 * defines the logical drive list structure 1838 */ 1839 #pragma pack(1) 1840 struct MR_LD_LIST { 1841 u_int32_t ldCount; 1842 u_int32_t reserved; 1843 struct { 1844 MR_LD_REF ref; 1845 u_int8_t state; 1846 u_int8_t reserved[3]; 1847 u_int64_t size; 1848 } ldList[MAX_LOGICAL_DRIVES_EXT]; 1849 }; 1850 1851 #pragma pack() 1852 1853 /* 1854 * SAS controller properties 1855 */ 1856 #pragma pack(1) 1857 struct mrsas_ctrl_prop { 1858 u_int16_t seq_num; 1859 u_int16_t pred_fail_poll_interval; 1860 u_int16_t intr_throttle_count; 1861 u_int16_t intr_throttle_timeouts; 1862 u_int8_t rebuild_rate; 1863 u_int8_t patrol_read_rate; 1864 u_int8_t bgi_rate; 1865 u_int8_t cc_rate; 1866 u_int8_t recon_rate; 1867 u_int8_t cache_flush_interval; 1868 u_int8_t spinup_drv_count; 1869 u_int8_t spinup_delay; 1870 u_int8_t cluster_enable; 1871 u_int8_t coercion_mode; 1872 u_int8_t alarm_enable; 1873 u_int8_t disable_auto_rebuild; 1874 u_int8_t disable_battery_warn; 1875 u_int8_t ecc_bucket_size; 1876 u_int16_t ecc_bucket_leak_rate; 1877 u_int8_t restore_hotspare_on_insertion; 1878 u_int8_t expose_encl_devices; 1879 u_int8_t maintainPdFailHistory; 1880 u_int8_t disallowHostRequestReordering; 1881 u_int8_t abortCCOnError; 1882 u_int8_t loadBalanceMode; 1883 u_int8_t disableAutoDetectBackplane; 1884 u_int8_t snapVDSpace; 1885 /* 1886 * Add properties that can be controlled by a bit in the following 1887 * structure. 1888 */ 1889 struct { 1890 u_int32_t copyBackDisabled:1; 1891 u_int32_t SMARTerEnabled:1; 1892 u_int32_t prCorrectUnconfiguredAreas:1; 1893 u_int32_t useFdeOnly:1; 1894 u_int32_t disableNCQ:1; 1895 u_int32_t SSDSMARTerEnabled:1; 1896 u_int32_t SSDPatrolReadEnabled:1; 1897 u_int32_t enableSpinDownUnconfigured:1; 1898 u_int32_t autoEnhancedImport:1; 1899 u_int32_t enableSecretKeyControl:1; 1900 u_int32_t disableOnlineCtrlReset:1; 1901 u_int32_t allowBootWithPinnedCache:1; 1902 u_int32_t disableSpinDownHS:1; 1903 u_int32_t enableJBOD:1; 1904 u_int32_t disableCacheBypass:1; 1905 u_int32_t useDiskActivityForLocate:1; 1906 u_int32_t enablePI:1; 1907 u_int32_t preventPIImport:1; 1908 u_int32_t useGlobalSparesForEmergency:1; 1909 u_int32_t useUnconfGoodForEmergency:1; 1910 u_int32_t useEmergencySparesforSMARTer:1; 1911 u_int32_t forceSGPIOForQuadOnly:1; 1912 u_int32_t enableConfigAutoBalance:1; 1913 u_int32_t enableVirtualCache:1; 1914 u_int32_t enableAutoLockRecovery:1; 1915 u_int32_t disableImmediateIO:1; 1916 u_int32_t disableT10RebuildAssist:1; 1917 u_int32_t ignore64ldRestriction:1; 1918 u_int32_t enableSwZone:1; 1919 u_int32_t limitMaxRateSATA3G:1; 1920 u_int32_t reserved:2; 1921 } OnOffProperties; 1922 u_int8_t autoSnapVDSpace; 1923 u_int8_t viewSpace; 1924 u_int16_t spinDownTime; 1925 u_int8_t reserved[24]; 1926 1927 }; 1928 1929 #pragma pack() 1930 1931 1932 /* 1933 * SAS controller information 1934 */ 1935 struct mrsas_ctrl_info { 1936 /* 1937 * PCI device information 1938 */ 1939 struct { 1940 u_int16_t vendor_id; 1941 u_int16_t device_id; 1942 u_int16_t sub_vendor_id; 1943 u_int16_t sub_device_id; 1944 u_int8_t reserved[24]; 1945 } __packed pci; 1946 /* 1947 * Host interface information 1948 */ 1949 struct { 1950 u_int8_t PCIX:1; 1951 u_int8_t PCIE:1; 1952 u_int8_t iSCSI:1; 1953 u_int8_t SAS_3G:1; 1954 u_int8_t reserved_0:4; 1955 u_int8_t reserved_1[6]; 1956 u_int8_t port_count; 1957 u_int64_t port_addr[8]; 1958 } __packed host_interface; 1959 /* 1960 * Device (backend) interface information 1961 */ 1962 struct { 1963 u_int8_t SPI:1; 1964 u_int8_t SAS_3G:1; 1965 u_int8_t SATA_1_5G:1; 1966 u_int8_t SATA_3G:1; 1967 u_int8_t reserved_0:4; 1968 u_int8_t reserved_1[6]; 1969 u_int8_t port_count; 1970 u_int64_t port_addr[8]; 1971 } __packed device_interface; 1972 1973 u_int32_t image_check_word; 1974 u_int32_t image_component_count; 1975 1976 struct { 1977 char name[8]; 1978 char version[32]; 1979 char build_date[16]; 1980 char built_time[16]; 1981 } __packed image_component[8]; 1982 1983 u_int32_t pending_image_component_count; 1984 1985 struct { 1986 char name[8]; 1987 char version[32]; 1988 char build_date[16]; 1989 char build_time[16]; 1990 } __packed pending_image_component[8]; 1991 1992 u_int8_t max_arms; 1993 u_int8_t max_spans; 1994 u_int8_t max_arrays; 1995 u_int8_t max_lds; 1996 char product_name[80]; 1997 char serial_no[32]; 1998 1999 /* 2000 * Other physical/controller/operation information. Indicates the 2001 * presence of the hardware 2002 */ 2003 struct { 2004 u_int32_t bbu:1; 2005 u_int32_t alarm:1; 2006 u_int32_t nvram:1; 2007 u_int32_t uart:1; 2008 u_int32_t reserved:28; 2009 } __packed hw_present; 2010 2011 u_int32_t current_fw_time; 2012 2013 /* 2014 * Maximum data transfer sizes 2015 */ 2016 u_int16_t max_concurrent_cmds; 2017 u_int16_t max_sge_count; 2018 u_int32_t max_request_size; 2019 2020 /* 2021 * Logical and physical device counts 2022 */ 2023 u_int16_t ld_present_count; 2024 u_int16_t ld_degraded_count; 2025 u_int16_t ld_offline_count; 2026 2027 u_int16_t pd_present_count; 2028 u_int16_t pd_disk_present_count; 2029 u_int16_t pd_disk_pred_failure_count; 2030 u_int16_t pd_disk_failed_count; 2031 2032 /* 2033 * Memory size information 2034 */ 2035 u_int16_t nvram_size; 2036 u_int16_t memory_size; 2037 u_int16_t flash_size; 2038 2039 /* 2040 * Error counters 2041 */ 2042 u_int16_t mem_correctable_error_count; 2043 u_int16_t mem_uncorrectable_error_count; 2044 2045 /* 2046 * Cluster information 2047 */ 2048 u_int8_t cluster_permitted; 2049 u_int8_t cluster_active; 2050 2051 /* 2052 * Additional max data transfer sizes 2053 */ 2054 u_int16_t max_strips_per_io; 2055 2056 /* 2057 * Controller capabilities structures 2058 */ 2059 struct { 2060 u_int32_t raid_level_0:1; 2061 u_int32_t raid_level_1:1; 2062 u_int32_t raid_level_5:1; 2063 u_int32_t raid_level_1E:1; 2064 u_int32_t raid_level_6:1; 2065 u_int32_t reserved:27; 2066 } __packed raid_levels; 2067 2068 struct { 2069 u_int32_t rbld_rate:1; 2070 u_int32_t cc_rate:1; 2071 u_int32_t bgi_rate:1; 2072 u_int32_t recon_rate:1; 2073 u_int32_t patrol_rate:1; 2074 u_int32_t alarm_control:1; 2075 u_int32_t cluster_supported:1; 2076 u_int32_t bbu:1; 2077 u_int32_t spanning_allowed:1; 2078 u_int32_t dedicated_hotspares:1; 2079 u_int32_t revertible_hotspares:1; 2080 u_int32_t foreign_config_import:1; 2081 u_int32_t self_diagnostic:1; 2082 u_int32_t mixed_redundancy_arr:1; 2083 u_int32_t global_hot_spares:1; 2084 u_int32_t reserved:17; 2085 } __packed adapter_operations; 2086 2087 struct { 2088 u_int32_t read_policy:1; 2089 u_int32_t write_policy:1; 2090 u_int32_t io_policy:1; 2091 u_int32_t access_policy:1; 2092 u_int32_t disk_cache_policy:1; 2093 u_int32_t reserved:27; 2094 } __packed ld_operations; 2095 2096 struct { 2097 u_int8_t min; 2098 u_int8_t max; 2099 u_int8_t reserved[2]; 2100 } __packed stripe_sz_ops; 2101 2102 struct { 2103 u_int32_t force_online:1; 2104 u_int32_t force_offline:1; 2105 u_int32_t force_rebuild:1; 2106 u_int32_t reserved:29; 2107 } __packed pd_operations; 2108 2109 struct { 2110 u_int32_t ctrl_supports_sas:1; 2111 u_int32_t ctrl_supports_sata:1; 2112 u_int32_t allow_mix_in_encl:1; 2113 u_int32_t allow_mix_in_ld:1; 2114 u_int32_t allow_sata_in_cluster:1; 2115 u_int32_t reserved:27; 2116 } __packed pd_mix_support; 2117 2118 /* 2119 * Define ECC single-bit-error bucket information 2120 */ 2121 u_int8_t ecc_bucket_count; 2122 u_int8_t reserved_2[11]; 2123 2124 /* 2125 * Include the controller properties (changeable items) 2126 */ 2127 struct mrsas_ctrl_prop properties; 2128 2129 /* 2130 * Define FW pkg version (set in envt v'bles on OEM basis) 2131 */ 2132 char package_version[0x60]; 2133 2134 u_int64_t deviceInterfacePortAddr2[8]; 2135 u_int8_t reserved3[128]; 2136 2137 struct { 2138 u_int16_t minPdRaidLevel_0:4; 2139 u_int16_t maxPdRaidLevel_0:12; 2140 2141 u_int16_t minPdRaidLevel_1:4; 2142 u_int16_t maxPdRaidLevel_1:12; 2143 2144 u_int16_t minPdRaidLevel_5:4; 2145 u_int16_t maxPdRaidLevel_5:12; 2146 2147 u_int16_t minPdRaidLevel_1E:4; 2148 u_int16_t maxPdRaidLevel_1E:12; 2149 2150 u_int16_t minPdRaidLevel_6:4; 2151 u_int16_t maxPdRaidLevel_6:12; 2152 2153 u_int16_t minPdRaidLevel_10:4; 2154 u_int16_t maxPdRaidLevel_10:12; 2155 2156 u_int16_t minPdRaidLevel_50:4; 2157 u_int16_t maxPdRaidLevel_50:12; 2158 2159 u_int16_t minPdRaidLevel_60:4; 2160 u_int16_t maxPdRaidLevel_60:12; 2161 2162 u_int16_t minPdRaidLevel_1E_RLQ0:4; 2163 u_int16_t maxPdRaidLevel_1E_RLQ0:12; 2164 2165 u_int16_t minPdRaidLevel_1E0_RLQ0:4; 2166 u_int16_t maxPdRaidLevel_1E0_RLQ0:12; 2167 2168 u_int16_t reserved[6]; 2169 } pdsForRaidLevels; 2170 2171 u_int16_t maxPds; /* 0x780 */ 2172 u_int16_t maxDedHSPs; /* 0x782 */ 2173 u_int16_t maxGlobalHSPs; /* 0x784 */ 2174 u_int16_t ddfSize; /* 0x786 */ 2175 u_int8_t maxLdsPerArray; /* 0x788 */ 2176 u_int8_t partitionsInDDF; /* 0x789 */ 2177 u_int8_t lockKeyBinding; /* 0x78a */ 2178 u_int8_t maxPITsPerLd; /* 0x78b */ 2179 u_int8_t maxViewsPerLd; /* 0x78c */ 2180 u_int8_t maxTargetId; /* 0x78d */ 2181 u_int16_t maxBvlVdSize; /* 0x78e */ 2182 2183 u_int16_t maxConfigurableSSCSize; /* 0x790 */ 2184 u_int16_t currentSSCsize; /* 0x792 */ 2185 2186 char expanderFwVersion[12]; /* 0x794 */ 2187 2188 u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */ 2189 2190 u_int16_t cacheMemorySize; /* 0x7A2 */ 2191 2192 struct { /* 0x7A4 */ 2193 u_int32_t supportPIcontroller:1; 2194 u_int32_t supportLdPIType1:1; 2195 u_int32_t supportLdPIType2:1; 2196 u_int32_t supportLdPIType3:1; 2197 u_int32_t supportLdBBMInfo:1; 2198 u_int32_t supportShieldState:1; 2199 u_int32_t blockSSDWriteCacheChange:1; 2200 u_int32_t supportSuspendResumeBGops:1; 2201 u_int32_t supportEmergencySpares:1; 2202 u_int32_t supportSetLinkSpeed:1; 2203 u_int32_t supportBootTimePFKChange:1; 2204 u_int32_t supportJBOD:1; 2205 u_int32_t disableOnlinePFKChange:1; 2206 u_int32_t supportPerfTuning:1; 2207 u_int32_t supportSSDPatrolRead:1; 2208 u_int32_t realTimeScheduler:1; 2209 2210 u_int32_t supportResetNow:1; 2211 u_int32_t supportEmulatedDrives:1; 2212 u_int32_t headlessMode:1; 2213 u_int32_t dedicatedHotSparesLimited:1; 2214 2215 2216 u_int32_t supportUnevenSpans:1; 2217 u_int32_t reserved:11; 2218 } adapterOperations2; 2219 2220 u_int8_t driverVersion[32]; /* 0x7A8 */ 2221 u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */ 2222 u_int8_t temperatureROC; /* 0x7C9 */ 2223 u_int8_t temperatureCtrl; /* 0x7CA */ 2224 u_int8_t reserved4; /* 0x7CB */ 2225 u_int16_t maxConfigurablePds; /* 0x7CC */ 2226 2227 2228 u_int8_t reserved5[2]; /* 0x7CD reserved */ 2229 2230 struct { 2231 u_int32_t peerIsPresent:1; 2232 u_int32_t peerIsIncompatible:1; 2233 2234 u_int32_t hwIncompatible:1; 2235 u_int32_t fwVersionMismatch:1; 2236 u_int32_t ctrlPropIncompatible:1; 2237 u_int32_t premiumFeatureMismatch:1; 2238 u_int32_t reserved:26; 2239 } cluster; 2240 2241 char clusterId[16]; /* 0x7D4 */ 2242 2243 char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ 2244 2245 struct { /* 0x7E8 */ 2246 u_int32_t supportPersonalityChange:2; 2247 u_int32_t supportThermalPollInterval:1; 2248 u_int32_t supportDisableImmediateIO:1; 2249 u_int32_t supportT10RebuildAssist:1; 2250 u_int32_t supportMaxExtLDs:1; 2251 u_int32_t supportCrashDump:1; 2252 u_int32_t supportSwZone:1; 2253 u_int32_t supportDebugQueue:1; 2254 u_int32_t supportNVCacheErase:1; 2255 u_int32_t supportForceTo512e:1; 2256 u_int32_t supportHOQRebuild:1; 2257 u_int32_t supportAllowedOpsforDrvRemoval:1; 2258 u_int32_t supportDrvActivityLEDSetting:1; 2259 u_int32_t supportNVDRAM:1; 2260 u_int32_t supportForceFlash:1; 2261 u_int32_t supportDisableSESMonitoring:1; 2262 u_int32_t supportCacheBypassModes:1; 2263 u_int32_t supportSecurityonJBOD:1; 2264 u_int32_t discardCacheDuringLDDelete:1; 2265 u_int32_t supportTTYLogCompression:1; 2266 u_int32_t supportCPLDUpdate:1; 2267 u_int32_t supportDiskCacheSettingForSysPDs:1; 2268 u_int32_t supportExtendedSSCSize:1; 2269 u_int32_t useSeqNumJbodFP:1; 2270 u_int32_t reserved:7; 2271 } adapterOperations3; 2272 2273 u_int8_t pad_cpld[16]; 2274 2275 struct { 2276 u_int16_t ctrlInfoExtSupported:1; 2277 u_int16_t supportIbuttonLess:1; 2278 u_int16_t supportedEncAlgo:1; 2279 u_int16_t supportEncryptedMfc:1; 2280 u_int16_t imageUploadSupported:1; 2281 u_int16_t supportSESCtrlInMultipathCfg:1; 2282 u_int16_t supportPdMapTargetId:1; 2283 u_int16_t FWSwapsBBUVPDInfo:1; 2284 u_int16_t reserved:8; 2285 } adapterOperations4; 2286 2287 u_int8_t pad[0x800 - 0x7FE]; /* 0x7FE */ 2288 } __packed; 2289 2290 /* 2291 * When SCSI mid-layer calls driver's reset routine, driver waits for 2292 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 2293 * that the driver cannot _actually_ abort or reset pending commands. While 2294 * it is waiting for the commands to complete, it prints a diagnostic message 2295 * every MRSAS_RESET_NOTICE_INTERVAL seconds 2296 */ 2297 #define MRSAS_RESET_WAIT_TIME 180 2298 #define MRSAS_INTERNAL_CMD_WAIT_TIME 180 2299 #define MRSAS_RESET_NOTICE_INTERVAL 5 2300 #define MRSAS_IOCTL_CMD 0 2301 #define MRSAS_DEFAULT_CMD_TIMEOUT 90 2302 #define MRSAS_THROTTLE_QUEUE_DEPTH 16 2303 2304 /* 2305 * MSI-x regsiters offset defines 2306 */ 2307 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) 2308 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 2309 #define MR_MAX_REPLY_QUEUES_OFFSET (0x0000001F) 2310 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET (0x003FC000) 2311 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 2312 #define MR_MAX_MSIX_REG_ARRAY 16 2313 2314 /* 2315 * SYNC CACHE offset define 2316 */ 2317 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000 2318 2319 #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET (1 << 24) 2320 2321 /* 2322 * FW reports the maximum of number of commands that it can accept (maximum 2323 * commands that can be outstanding) at any time. The driver must report a 2324 * lower number to the mid layer because it can issue a few internal commands 2325 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 2326 * is shown below 2327 */ 2328 #define MRSAS_INT_CMDS 32 2329 #define MRSAS_SKINNY_INT_CMDS 5 2330 #define MRSAS_MAX_MSIX_QUEUES 128 2331 2332 /* 2333 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs 2334 * based on the size of bus_addr_t 2335 */ 2336 #define IS_DMA64 (sizeof(bus_addr_t) == 8) 2337 2338 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 2339 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 2340 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 2341 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 2342 2343 #define MFI_OB_INTR_STATUS_MASK 0x00000002 2344 #define MFI_POLL_TIMEOUT_SECS 60 2345 2346 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 2347 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 2348 #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001 2349 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 2350 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 2351 #define MFI_1068_PCSR_OFFSET 0x84 2352 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 2353 #define MFI_1068_FW_READY 0xDDDD0000 2354 2355 typedef union _MFI_CAPABILITIES { 2356 struct { 2357 u_int32_t support_fp_remote_lun:1; 2358 u_int32_t support_additional_msix:1; 2359 u_int32_t support_fastpath_wb:1; 2360 u_int32_t support_max_255lds:1; 2361 u_int32_t support_ndrive_r1_lb:1; 2362 u_int32_t support_core_affinity:1; 2363 u_int32_t security_protocol_cmds_fw:1; 2364 u_int32_t support_ext_queue_depth:1; 2365 u_int32_t support_ext_io_size:1; 2366 u_int32_t reserved:23; 2367 } mfi_capabilities; 2368 u_int32_t reg; 2369 } MFI_CAPABILITIES; 2370 2371 #pragma pack(1) 2372 struct mrsas_sge32 { 2373 u_int32_t phys_addr; 2374 u_int32_t length; 2375 }; 2376 2377 #pragma pack() 2378 2379 #pragma pack(1) 2380 struct mrsas_sge64 { 2381 u_int64_t phys_addr; 2382 u_int32_t length; 2383 }; 2384 2385 #pragma pack() 2386 2387 #pragma pack() 2388 union mrsas_sgl { 2389 struct mrsas_sge32 sge32[1]; 2390 struct mrsas_sge64 sge64[1]; 2391 }; 2392 2393 #pragma pack() 2394 2395 #pragma pack(1) 2396 struct mrsas_header { 2397 u_int8_t cmd; /* 00e */ 2398 u_int8_t sense_len; /* 01h */ 2399 u_int8_t cmd_status; /* 02h */ 2400 u_int8_t scsi_status; /* 03h */ 2401 2402 u_int8_t target_id; /* 04h */ 2403 u_int8_t lun; /* 05h */ 2404 u_int8_t cdb_len; /* 06h */ 2405 u_int8_t sge_count; /* 07h */ 2406 2407 u_int32_t context; /* 08h */ 2408 u_int32_t pad_0; /* 0Ch */ 2409 2410 u_int16_t flags; /* 10h */ 2411 u_int16_t timeout; /* 12h */ 2412 u_int32_t data_xferlen; /* 14h */ 2413 }; 2414 2415 #pragma pack() 2416 2417 #pragma pack(1) 2418 struct mrsas_init_frame { 2419 u_int8_t cmd; /* 00h */ 2420 u_int8_t reserved_0; /* 01h */ 2421 u_int8_t cmd_status; /* 02h */ 2422 2423 u_int8_t reserved_1; /* 03h */ 2424 MFI_CAPABILITIES driver_operations; /* 04h */ 2425 u_int32_t context; /* 08h */ 2426 u_int32_t pad_0; /* 0Ch */ 2427 2428 u_int16_t flags; /* 10h */ 2429 u_int16_t reserved_3; /* 12h */ 2430 u_int32_t data_xfer_len; /* 14h */ 2431 2432 u_int32_t queue_info_new_phys_addr_lo; /* 18h */ 2433 u_int32_t queue_info_new_phys_addr_hi; /* 1Ch */ 2434 u_int32_t queue_info_old_phys_addr_lo; /* 20h */ 2435 u_int32_t queue_info_old_phys_addr_hi; /* 24h */ 2436 u_int32_t driver_ver_lo; /* 28h */ 2437 u_int32_t driver_ver_hi; /* 2Ch */ 2438 u_int32_t reserved_4[4]; /* 30h */ 2439 }; 2440 2441 #pragma pack() 2442 2443 #pragma pack(1) 2444 struct mrsas_io_frame { 2445 u_int8_t cmd; /* 00h */ 2446 u_int8_t sense_len; /* 01h */ 2447 u_int8_t cmd_status; /* 02h */ 2448 u_int8_t scsi_status; /* 03h */ 2449 2450 u_int8_t target_id; /* 04h */ 2451 u_int8_t access_byte; /* 05h */ 2452 u_int8_t reserved_0; /* 06h */ 2453 u_int8_t sge_count; /* 07h */ 2454 2455 u_int32_t context; /* 08h */ 2456 u_int32_t pad_0; /* 0Ch */ 2457 2458 u_int16_t flags; /* 10h */ 2459 u_int16_t timeout; /* 12h */ 2460 u_int32_t lba_count; /* 14h */ 2461 2462 u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2463 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2464 2465 u_int32_t start_lba_lo; /* 20h */ 2466 u_int32_t start_lba_hi; /* 24h */ 2467 2468 union mrsas_sgl sgl; /* 28h */ 2469 }; 2470 2471 #pragma pack() 2472 2473 #pragma pack(1) 2474 struct mrsas_pthru_frame { 2475 u_int8_t cmd; /* 00h */ 2476 u_int8_t sense_len; /* 01h */ 2477 u_int8_t cmd_status; /* 02h */ 2478 u_int8_t scsi_status; /* 03h */ 2479 2480 u_int8_t target_id; /* 04h */ 2481 u_int8_t lun; /* 05h */ 2482 u_int8_t cdb_len; /* 06h */ 2483 u_int8_t sge_count; /* 07h */ 2484 2485 u_int32_t context; /* 08h */ 2486 u_int32_t pad_0; /* 0Ch */ 2487 2488 u_int16_t flags; /* 10h */ 2489 u_int16_t timeout; /* 12h */ 2490 u_int32_t data_xfer_len; /* 14h */ 2491 2492 u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2493 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2494 2495 u_int8_t cdb[16]; /* 20h */ 2496 union mrsas_sgl sgl; /* 30h */ 2497 }; 2498 2499 #pragma pack() 2500 2501 #pragma pack(1) 2502 struct mrsas_dcmd_frame { 2503 u_int8_t cmd; /* 00h */ 2504 u_int8_t reserved_0; /* 01h */ 2505 u_int8_t cmd_status; /* 02h */ 2506 u_int8_t reserved_1[4]; /* 03h */ 2507 u_int8_t sge_count; /* 07h */ 2508 2509 u_int32_t context; /* 08h */ 2510 u_int32_t pad_0; /* 0Ch */ 2511 2512 u_int16_t flags; /* 10h */ 2513 u_int16_t timeout; /* 12h */ 2514 2515 u_int32_t data_xfer_len; /* 14h */ 2516 u_int32_t opcode; /* 18h */ 2517 2518 union { /* 1Ch */ 2519 u_int8_t b[12]; 2520 u_int16_t s[6]; 2521 u_int32_t w[3]; 2522 } mbox; 2523 2524 union mrsas_sgl sgl; /* 28h */ 2525 }; 2526 2527 #pragma pack() 2528 2529 #pragma pack(1) 2530 struct mrsas_abort_frame { 2531 u_int8_t cmd; /* 00h */ 2532 u_int8_t reserved_0; /* 01h */ 2533 u_int8_t cmd_status; /* 02h */ 2534 2535 u_int8_t reserved_1; /* 03h */ 2536 MFI_CAPABILITIES driver_operations; /* 04h */ 2537 u_int32_t context; /* 08h */ 2538 u_int32_t pad_0; /* 0Ch */ 2539 2540 u_int16_t flags; /* 10h */ 2541 u_int16_t reserved_3; /* 12h */ 2542 u_int32_t reserved_4; /* 14h */ 2543 2544 u_int32_t abort_context; /* 18h */ 2545 u_int32_t pad_1; /* 1Ch */ 2546 2547 u_int32_t abort_mfi_phys_addr_lo; /* 20h */ 2548 u_int32_t abort_mfi_phys_addr_hi; /* 24h */ 2549 2550 u_int32_t reserved_5[6]; /* 28h */ 2551 }; 2552 2553 #pragma pack() 2554 2555 #pragma pack(1) 2556 struct mrsas_smp_frame { 2557 u_int8_t cmd; /* 00h */ 2558 u_int8_t reserved_1; /* 01h */ 2559 u_int8_t cmd_status; /* 02h */ 2560 u_int8_t connection_status; /* 03h */ 2561 2562 u_int8_t reserved_2[3]; /* 04h */ 2563 u_int8_t sge_count; /* 07h */ 2564 2565 u_int32_t context; /* 08h */ 2566 u_int32_t pad_0; /* 0Ch */ 2567 2568 u_int16_t flags; /* 10h */ 2569 u_int16_t timeout; /* 12h */ 2570 2571 u_int32_t data_xfer_len; /* 14h */ 2572 u_int64_t sas_addr; /* 18h */ 2573 2574 union { 2575 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */ 2576 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */ 2577 } sgl; 2578 }; 2579 2580 #pragma pack() 2581 2582 2583 #pragma pack(1) 2584 struct mrsas_stp_frame { 2585 u_int8_t cmd; /* 00h */ 2586 u_int8_t reserved_1; /* 01h */ 2587 u_int8_t cmd_status; /* 02h */ 2588 u_int8_t reserved_2; /* 03h */ 2589 2590 u_int8_t target_id; /* 04h */ 2591 u_int8_t reserved_3[2]; /* 05h */ 2592 u_int8_t sge_count; /* 07h */ 2593 2594 u_int32_t context; /* 08h */ 2595 u_int32_t pad_0; /* 0Ch */ 2596 2597 u_int16_t flags; /* 10h */ 2598 u_int16_t timeout; /* 12h */ 2599 2600 u_int32_t data_xfer_len; /* 14h */ 2601 2602 u_int16_t fis[10]; /* 18h */ 2603 u_int32_t stp_flags; 2604 2605 union { 2606 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */ 2607 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */ 2608 } sgl; 2609 }; 2610 2611 #pragma pack() 2612 2613 union mrsas_frame { 2614 struct mrsas_header hdr; 2615 struct mrsas_init_frame init; 2616 struct mrsas_io_frame io; 2617 struct mrsas_pthru_frame pthru; 2618 struct mrsas_dcmd_frame dcmd; 2619 struct mrsas_abort_frame abort; 2620 struct mrsas_smp_frame smp; 2621 struct mrsas_stp_frame stp; 2622 u_int8_t raw_bytes[64]; 2623 }; 2624 2625 #pragma pack(1) 2626 union mrsas_evt_class_locale { 2627 2628 struct { 2629 u_int16_t locale; 2630 u_int8_t reserved; 2631 int8_t class; 2632 } __packed members; 2633 2634 u_int32_t word; 2635 2636 } __packed; 2637 2638 #pragma pack() 2639 2640 2641 #pragma pack(1) 2642 struct mrsas_evt_log_info { 2643 u_int32_t newest_seq_num; 2644 u_int32_t oldest_seq_num; 2645 u_int32_t clear_seq_num; 2646 u_int32_t shutdown_seq_num; 2647 u_int32_t boot_seq_num; 2648 2649 } __packed; 2650 2651 #pragma pack() 2652 2653 struct mrsas_progress { 2654 2655 u_int16_t progress; 2656 u_int16_t elapsed_seconds; 2657 2658 } __packed; 2659 2660 struct mrsas_evtarg_ld { 2661 2662 u_int16_t target_id; 2663 u_int8_t ld_index; 2664 u_int8_t reserved; 2665 2666 } __packed; 2667 2668 struct mrsas_evtarg_pd { 2669 u_int16_t device_id; 2670 u_int8_t encl_index; 2671 u_int8_t slot_number; 2672 2673 } __packed; 2674 2675 struct mrsas_evt_detail { 2676 2677 u_int32_t seq_num; 2678 u_int32_t time_stamp; 2679 u_int32_t code; 2680 union mrsas_evt_class_locale cl; 2681 u_int8_t arg_type; 2682 u_int8_t reserved1[15]; 2683 2684 union { 2685 struct { 2686 struct mrsas_evtarg_pd pd; 2687 u_int8_t cdb_length; 2688 u_int8_t sense_length; 2689 u_int8_t reserved[2]; 2690 u_int8_t cdb[16]; 2691 u_int8_t sense[64]; 2692 } __packed cdbSense; 2693 2694 struct mrsas_evtarg_ld ld; 2695 2696 struct { 2697 struct mrsas_evtarg_ld ld; 2698 u_int64_t count; 2699 } __packed ld_count; 2700 2701 struct { 2702 u_int64_t lba; 2703 struct mrsas_evtarg_ld ld; 2704 } __packed ld_lba; 2705 2706 struct { 2707 struct mrsas_evtarg_ld ld; 2708 u_int32_t prevOwner; 2709 u_int32_t newOwner; 2710 } __packed ld_owner; 2711 2712 struct { 2713 u_int64_t ld_lba; 2714 u_int64_t pd_lba; 2715 struct mrsas_evtarg_ld ld; 2716 struct mrsas_evtarg_pd pd; 2717 } __packed ld_lba_pd_lba; 2718 2719 struct { 2720 struct mrsas_evtarg_ld ld; 2721 struct mrsas_progress prog; 2722 } __packed ld_prog; 2723 2724 struct { 2725 struct mrsas_evtarg_ld ld; 2726 u_int32_t prev_state; 2727 u_int32_t new_state; 2728 } __packed ld_state; 2729 2730 struct { 2731 u_int64_t strip; 2732 struct mrsas_evtarg_ld ld; 2733 } __packed ld_strip; 2734 2735 struct mrsas_evtarg_pd pd; 2736 2737 struct { 2738 struct mrsas_evtarg_pd pd; 2739 u_int32_t err; 2740 } __packed pd_err; 2741 2742 struct { 2743 u_int64_t lba; 2744 struct mrsas_evtarg_pd pd; 2745 } __packed pd_lba; 2746 2747 struct { 2748 u_int64_t lba; 2749 struct mrsas_evtarg_pd pd; 2750 struct mrsas_evtarg_ld ld; 2751 } __packed pd_lba_ld; 2752 2753 struct { 2754 struct mrsas_evtarg_pd pd; 2755 struct mrsas_progress prog; 2756 } __packed pd_prog; 2757 2758 struct { 2759 struct mrsas_evtarg_pd pd; 2760 u_int32_t prevState; 2761 u_int32_t newState; 2762 } __packed pd_state; 2763 2764 struct { 2765 u_int16_t vendorId; 2766 u_int16_t deviceId; 2767 u_int16_t subVendorId; 2768 u_int16_t subDeviceId; 2769 } __packed pci; 2770 2771 u_int32_t rate; 2772 char str[96]; 2773 2774 struct { 2775 u_int32_t rtc; 2776 u_int32_t elapsedSeconds; 2777 } __packed time; 2778 2779 struct { 2780 u_int32_t ecar; 2781 u_int32_t elog; 2782 char str[64]; 2783 } __packed ecc; 2784 2785 u_int8_t b[96]; 2786 u_int16_t s[48]; 2787 u_int32_t w[24]; 2788 u_int64_t d[12]; 2789 } args; 2790 2791 char description[128]; 2792 2793 } __packed; 2794 2795 struct mrsas_irq_context { 2796 struct mrsas_softc *sc; 2797 uint32_t MSIxIndex; 2798 }; 2799 2800 enum MEGASAS_OCR_REASON { 2801 FW_FAULT_OCR = 0, 2802 MFI_DCMD_TIMEOUT_OCR = 1, 2803 }; 2804 2805 /* Controller management info added to support Linux Emulator */ 2806 #define MAX_MGMT_ADAPTERS 1024 2807 2808 struct mrsas_mgmt_info { 2809 u_int16_t count; 2810 struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS]; 2811 int max_index; 2812 }; 2813 2814 #define PCI_TYPE0_ADDRESSES 6 2815 #define PCI_TYPE1_ADDRESSES 2 2816 #define PCI_TYPE2_ADDRESSES 5 2817 2818 typedef struct _MRSAS_DRV_PCI_COMMON_HEADER { 2819 u_int16_t vendorID; 2820 //(ro) 2821 u_int16_t deviceID; 2822 //(ro) 2823 u_int16_t command; 2824 //Device control 2825 u_int16_t status; 2826 u_int8_t revisionID; 2827 //(ro) 2828 u_int8_t progIf; 2829 //(ro) 2830 u_int8_t subClass; 2831 //(ro) 2832 u_int8_t baseClass; 2833 //(ro) 2834 u_int8_t cacheLineSize; 2835 //(ro +) 2836 u_int8_t latencyTimer; 2837 //(ro +) 2838 u_int8_t headerType; 2839 //(ro) 2840 u_int8_t bist; 2841 //Built in self test 2842 2843 union { 2844 struct _MRSAS_DRV_PCI_HEADER_TYPE_0 { 2845 u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 2846 u_int32_t cis; 2847 u_int16_t subVendorID; 2848 u_int16_t subSystemID; 2849 u_int32_t romBaseAddress; 2850 u_int8_t capabilitiesPtr; 2851 u_int8_t reserved1[3]; 2852 u_int32_t reserved2; 2853 u_int8_t interruptLine; 2854 u_int8_t interruptPin; 2855 //(ro) 2856 u_int8_t minimumGrant; 2857 //(ro) 2858 u_int8_t maximumLatency; 2859 //(ro) 2860 } type0; 2861 2862 /* 2863 * PCI to PCI Bridge 2864 */ 2865 2866 struct _MRSAS_DRV_PCI_HEADER_TYPE_1 { 2867 u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 2868 u_int8_t primaryBus; 2869 u_int8_t secondaryBus; 2870 u_int8_t subordinateBus; 2871 u_int8_t secondaryLatency; 2872 u_int8_t ioBase; 2873 u_int8_t ioLimit; 2874 u_int16_t secondaryStatus; 2875 u_int16_t memoryBase; 2876 u_int16_t memoryLimit; 2877 u_int16_t prefetchBase; 2878 u_int16_t prefetchLimit; 2879 u_int32_t prefetchBaseUpper32; 2880 u_int32_t prefetchLimitUpper32; 2881 u_int16_t ioBaseUpper16; 2882 u_int16_t ioLimitUpper16; 2883 u_int8_t capabilitiesPtr; 2884 u_int8_t reserved1[3]; 2885 u_int32_t romBaseAddress; 2886 u_int8_t interruptLine; 2887 u_int8_t interruptPin; 2888 u_int16_t bridgeControl; 2889 } type1; 2890 2891 /* 2892 * PCI to CARDBUS Bridge 2893 */ 2894 2895 struct _MRSAS_DRV_PCI_HEADER_TYPE_2 { 2896 u_int32_t socketRegistersBaseAddress; 2897 u_int8_t capabilitiesPtr; 2898 u_int8_t reserved; 2899 u_int16_t secondaryStatus; 2900 u_int8_t primaryBus; 2901 u_int8_t secondaryBus; 2902 u_int8_t subordinateBus; 2903 u_int8_t secondaryLatency; 2904 struct { 2905 u_int32_t base; 2906 u_int32_t limit; 2907 } range [PCI_TYPE2_ADDRESSES - 1]; 2908 u_int8_t interruptLine; 2909 u_int8_t interruptPin; 2910 u_int16_t bridgeControl; 2911 } type2; 2912 } u; 2913 2914 } MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER; 2915 2916 #define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes 2917 2918 typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY { 2919 union { 2920 struct { 2921 u_int32_t linkSpeed:4; 2922 u_int32_t linkWidth:6; 2923 u_int32_t aspmSupport:2; 2924 u_int32_t losExitLatency:3; 2925 u_int32_t l1ExitLatency:3; 2926 u_int32_t rsvdp:6; 2927 u_int32_t portNumber:8; 2928 } bits; 2929 2930 u_int32_t asUlong; 2931 } u; 2932 } MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY; 2933 2934 #define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY) 2935 2936 typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY { 2937 union { 2938 struct { 2939 u_int16_t linkSpeed:4; 2940 u_int16_t negotiatedLinkWidth:6; 2941 u_int16_t linkTrainingError:1; 2942 u_int16_t linkTraning:1; 2943 u_int16_t slotClockConfig:1; 2944 u_int16_t rsvdZ:3; 2945 } bits; 2946 2947 u_int16_t asUshort; 2948 } u; 2949 u_int16_t reserved; 2950 } MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY; 2951 2952 #define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY) 2953 2954 2955 typedef struct _MRSAS_DRV_PCI_CAPABILITIES { 2956 MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability; 2957 MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability; 2958 } MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES; 2959 2960 #define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES) 2961 2962 /* PCI information */ 2963 typedef struct _MRSAS_DRV_PCI_INFORMATION { 2964 u_int32_t busNumber; 2965 u_int8_t deviceNumber; 2966 u_int8_t functionNumber; 2967 u_int8_t interruptVector; 2968 u_int8_t reserved1; 2969 MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo; 2970 MRSAS_DRV_PCI_CAPABILITIES capability; 2971 u_int32_t domainID; 2972 u_int8_t reserved2[28]; 2973 } MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION; 2974 2975 typedef enum _MR_PD_TYPE { 2976 UNKNOWN_DRIVE = 0, 2977 PARALLEL_SCSI = 1, 2978 SAS_PD = 2, 2979 SATA_PD = 3, 2980 FC_PD = 4, 2981 NVME_PD = 5, 2982 } MR_PD_TYPE; 2983 2984 typedef union _MR_PD_REF { 2985 struct { 2986 u_int16_t deviceId; 2987 u_int16_t seqNum; 2988 } mrPdRef; 2989 u_int32_t ref; 2990 } MR_PD_REF; 2991 2992 /* 2993 * define the DDF Type bit structure 2994 */ 2995 union MR_PD_DDF_TYPE { 2996 struct { 2997 union { 2998 struct { 2999 u_int16_t forcedPDGUID:1; 3000 u_int16_t inVD:1; 3001 u_int16_t isGlobalSpare:1; 3002 u_int16_t isSpare:1; 3003 u_int16_t isForeign:1; 3004 u_int16_t reserved:7; 3005 u_int16_t intf:4; 3006 } pdType; 3007 u_int16_t type; 3008 }; 3009 u_int16_t reserved; 3010 } ddf; 3011 struct { 3012 u_int32_t reserved; 3013 } nonDisk; 3014 u_int32_t type; 3015 } __packed; 3016 3017 /* 3018 * defines the progress structure 3019 */ 3020 union MR_PROGRESS { 3021 struct { 3022 u_int16_t progress; 3023 union { 3024 u_int16_t elapsedSecs; 3025 u_int16_t elapsedSecsForLastPercent; 3026 }; 3027 } mrProgress; 3028 u_int32_t w; 3029 } __packed; 3030 3031 /* 3032 * defines the physical drive progress structure 3033 */ 3034 struct MR_PD_PROGRESS { 3035 struct { 3036 u_int32_t rbld:1; 3037 u_int32_t patrol:1; 3038 u_int32_t clear:1; 3039 u_int32_t copyBack:1; 3040 u_int32_t erase:1; 3041 u_int32_t locate:1; 3042 u_int32_t reserved:26; 3043 } active; 3044 union MR_PROGRESS rbld; 3045 union MR_PROGRESS patrol; 3046 union { 3047 union MR_PROGRESS clear; 3048 union MR_PROGRESS erase; 3049 }; 3050 3051 struct { 3052 u_int32_t rbld:1; 3053 u_int32_t patrol:1; 3054 u_int32_t clear:1; 3055 u_int32_t copyBack:1; 3056 u_int32_t erase:1; 3057 u_int32_t reserved:27; 3058 } pause; 3059 3060 union MR_PROGRESS reserved[3]; 3061 } __packed; 3062 3063 3064 struct mrsas_pd_info { 3065 MR_PD_REF ref; 3066 u_int8_t inquiryData[96]; 3067 u_int8_t vpdPage83[64]; 3068 3069 u_int8_t notSupported; 3070 u_int8_t scsiDevType; 3071 3072 union { 3073 u_int8_t connectedPortBitmap; 3074 u_int8_t connectedPortNumbers; 3075 }; 3076 3077 u_int8_t deviceSpeed; 3078 u_int32_t mediaErrCount; 3079 u_int32_t otherErrCount; 3080 u_int32_t predFailCount; 3081 u_int32_t lastPredFailEventSeqNum; 3082 3083 u_int16_t fwState; 3084 u_int8_t disabledForRemoval; 3085 u_int8_t linkSpeed; 3086 union MR_PD_DDF_TYPE state; 3087 3088 struct { 3089 u_int8_t count; 3090 u_int8_t isPathBroken:4; 3091 u_int8_t reserved3:3; 3092 u_int8_t widePortCapable:1; 3093 3094 u_int8_t connectorIndex[2]; 3095 u_int8_t reserved[4]; 3096 u_int64_t sasAddr[2]; 3097 u_int8_t reserved2[16]; 3098 } pathInfo; 3099 3100 u_int64_t rawSize; 3101 u_int64_t nonCoercedSize; 3102 u_int64_t coercedSize; 3103 u_int16_t enclDeviceId; 3104 u_int8_t enclIndex; 3105 3106 union { 3107 u_int8_t slotNumber; 3108 u_int8_t enclConnectorIndex; 3109 }; 3110 3111 struct MR_PD_PROGRESS progInfo; 3112 u_int8_t badBlockTableFull; 3113 u_int8_t unusableInCurrentConfig; 3114 u_int8_t vpdPage83Ext[64]; 3115 u_int8_t powerState; 3116 u_int8_t enclPosition; 3117 u_int32_t allowedOps; 3118 u_int16_t copyBackPartnerId; 3119 u_int16_t enclPartnerDeviceId; 3120 struct { 3121 u_int16_t fdeCapable:1; 3122 u_int16_t fdeEnabled:1; 3123 u_int16_t secured:1; 3124 u_int16_t locked:1; 3125 u_int16_t foreign:1; 3126 u_int16_t needsEKM:1; 3127 u_int16_t reserved:10; 3128 } security; 3129 u_int8_t mediaType; 3130 u_int8_t notCertified; 3131 u_int8_t bridgeVendor[8]; 3132 u_int8_t bridgeProductIdentification[16]; 3133 u_int8_t bridgeProductRevisionLevel[4]; 3134 u_int8_t satBridgeExists; 3135 3136 u_int8_t interfaceType; 3137 u_int8_t temperature; 3138 u_int8_t emulatedBlockSize; 3139 u_int16_t userDataBlockSize; 3140 u_int16_t reserved2; 3141 3142 struct { 3143 u_int32_t piType:3; 3144 u_int32_t piFormatted:1; 3145 u_int32_t piEligible:1; 3146 u_int32_t NCQ:1; 3147 u_int32_t WCE:1; 3148 u_int32_t commissionedSpare:1; 3149 u_int32_t emergencySpare:1; 3150 u_int32_t ineligibleForSSCD:1; 3151 u_int32_t ineligibleForLd:1; 3152 u_int32_t useSSEraseType:1; 3153 u_int32_t wceUnchanged:1; 3154 u_int32_t supportScsiUnmap:1; 3155 u_int32_t reserved:18; 3156 } properties; 3157 3158 u_int64_t shieldDiagCompletionTime; 3159 u_int8_t shieldCounter; 3160 3161 u_int8_t linkSpeedOther; 3162 u_int8_t reserved4[2]; 3163 3164 struct { 3165 u_int32_t bbmErrCountSupported:1; 3166 u_int32_t bbmErrCount:31; 3167 } bbmErr; 3168 3169 u_int8_t reserved1[512-428]; 3170 } __packed; 3171 3172 struct mrsas_target { 3173 u_int16_t target_id; 3174 u_int32_t queue_depth; 3175 u_int8_t interface_type; 3176 u_int32_t max_io_size_kb; 3177 } __packed; 3178 3179 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF 3180 #define MR_DEFAULT_NVME_PAGE_SIZE 4096 3181 #define MR_DEFAULT_NVME_PAGE_SHIFT 12 3182 3183 /******************************************************************* 3184 * per-instance data 3185 ********************************************************************/ 3186 struct mrsas_softc { 3187 device_t mrsas_dev; 3188 struct cdev *mrsas_cdev; 3189 struct intr_config_hook mrsas_ich; 3190 struct cdev *mrsas_linux_emulator_cdev; 3191 uint16_t device_id; 3192 struct resource *reg_res; 3193 int reg_res_id; 3194 bus_space_tag_t bus_tag; 3195 bus_space_handle_t bus_handle; 3196 bus_dma_tag_t mrsas_parent_tag; 3197 bus_dma_tag_t verbuf_tag; 3198 bus_dmamap_t verbuf_dmamap; 3199 void *verbuf_mem; 3200 bus_addr_t verbuf_phys_addr; 3201 bus_dma_tag_t sense_tag; 3202 bus_dmamap_t sense_dmamap; 3203 void *sense_mem; 3204 bus_addr_t sense_phys_addr; 3205 bus_dma_tag_t io_request_tag; 3206 bus_dmamap_t io_request_dmamap; 3207 void *io_request_mem; 3208 bus_addr_t io_request_phys_addr; 3209 bus_dma_tag_t chain_frame_tag; 3210 bus_dmamap_t chain_frame_dmamap; 3211 void *chain_frame_mem; 3212 bus_addr_t chain_frame_phys_addr; 3213 bus_dma_tag_t reply_desc_tag; 3214 bus_dmamap_t reply_desc_dmamap; 3215 void *reply_desc_mem; 3216 bus_addr_t reply_desc_phys_addr; 3217 bus_dma_tag_t ioc_init_tag; 3218 bus_dmamap_t ioc_init_dmamap; 3219 void *ioc_init_mem; 3220 bus_addr_t ioc_init_phys_mem; 3221 bus_dma_tag_t data_tag; 3222 struct cam_sim *sim_0; 3223 struct cam_sim *sim_1; 3224 struct cam_path *path_0; 3225 struct cam_path *path_1; 3226 struct mtx sim_lock; 3227 struct mtx pci_lock; 3228 struct mtx io_lock; 3229 struct mtx ioctl_lock; 3230 struct mtx mpt_cmd_pool_lock; 3231 struct mtx mfi_cmd_pool_lock; 3232 struct mtx raidmap_lock; 3233 struct mtx aen_lock; 3234 struct mtx stream_lock; 3235 struct selinfo mrsas_select; 3236 uint32_t mrsas_aen_triggered; 3237 uint32_t mrsas_poll_waiting; 3238 3239 struct sema ioctl_count_sema; 3240 uint32_t max_fw_cmds; 3241 uint16_t max_scsi_cmds; 3242 uint32_t max_num_sge; 3243 struct resource *mrsas_irq[MAX_MSIX_COUNT]; 3244 void *intr_handle[MAX_MSIX_COUNT]; 3245 int irq_id[MAX_MSIX_COUNT]; 3246 struct mrsas_irq_context irq_context[MAX_MSIX_COUNT]; 3247 int msix_vectors; 3248 int msix_enable; 3249 uint32_t msix_reg_offset[16]; 3250 uint8_t mask_interrupts; 3251 uint16_t max_chain_frame_sz; 3252 struct mrsas_mpt_cmd **mpt_cmd_list; 3253 struct mrsas_mfi_cmd **mfi_cmd_list; 3254 TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head; 3255 TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head; 3256 bus_addr_t req_frames_desc_phys; 3257 u_int8_t *req_frames_desc; 3258 u_int8_t *req_desc; 3259 bus_addr_t io_request_frames_phys; 3260 u_int8_t *io_request_frames; 3261 bus_addr_t reply_frames_desc_phys; 3262 u_int16_t last_reply_idx[MAX_MSIX_COUNT]; 3263 u_int32_t reply_q_depth; 3264 u_int32_t request_alloc_sz; 3265 u_int32_t reply_alloc_sz; 3266 u_int32_t io_frames_alloc_sz; 3267 u_int32_t chain_frames_alloc_sz; 3268 u_int16_t max_sge_in_main_msg; 3269 u_int16_t max_sge_in_chain; 3270 u_int8_t chain_offset_io_request; 3271 u_int8_t chain_offset_mfi_pthru; 3272 u_int32_t map_sz; 3273 u_int64_t map_id; 3274 u_int64_t pd_seq_map_id; 3275 struct mrsas_mfi_cmd *map_update_cmd; 3276 struct mrsas_mfi_cmd *jbod_seq_cmd; 3277 struct mrsas_mfi_cmd *aen_cmd; 3278 u_int8_t fast_path_io; 3279 void *chan; 3280 void *ocr_chan; 3281 u_int8_t adprecovery; 3282 u_int8_t remove_in_progress; 3283 u_int8_t ocr_thread_active; 3284 u_int8_t do_timedout_reset; 3285 u_int32_t reset_in_progress; 3286 u_int32_t reset_count; 3287 u_int32_t block_sync_cache; 3288 u_int32_t drv_stream_detection; 3289 u_int8_t fw_sync_cache_support; 3290 mrsas_atomic_t target_reset_outstanding; 3291 #define MRSAS_MAX_TM_TARGETS (MRSAS_MAX_PD + MRSAS_MAX_LD_IDS) 3292 struct mrsas_mpt_cmd *target_reset_pool[MRSAS_MAX_TM_TARGETS]; 3293 3294 bus_dma_tag_t jbodmap_tag[2]; 3295 bus_dmamap_t jbodmap_dmamap[2]; 3296 void *jbodmap_mem[2]; 3297 bus_addr_t jbodmap_phys_addr[2]; 3298 3299 bus_dma_tag_t raidmap_tag[2]; 3300 bus_dmamap_t raidmap_dmamap[2]; 3301 void *raidmap_mem[2]; 3302 bus_addr_t raidmap_phys_addr[2]; 3303 bus_dma_tag_t mficmd_frame_tag; 3304 bus_dma_tag_t mficmd_sense_tag; 3305 bus_addr_t evt_detail_phys_addr; 3306 bus_dma_tag_t evt_detail_tag; 3307 bus_dmamap_t evt_detail_dmamap; 3308 struct mrsas_evt_detail *evt_detail_mem; 3309 bus_addr_t pd_info_phys_addr; 3310 bus_dma_tag_t pd_info_tag; 3311 bus_dmamap_t pd_info_dmamap; 3312 struct mrsas_pd_info *pd_info_mem; 3313 struct mrsas_ctrl_info *ctrl_info; 3314 bus_dma_tag_t ctlr_info_tag; 3315 bus_dmamap_t ctlr_info_dmamap; 3316 void *ctlr_info_mem; 3317 bus_addr_t ctlr_info_phys_addr; 3318 u_int32_t max_sectors_per_req; 3319 u_int32_t disableOnlineCtrlReset; 3320 mrsas_atomic_t fw_outstanding; 3321 mrsas_atomic_t prp_count; 3322 mrsas_atomic_t sge_holes; 3323 3324 u_int32_t mrsas_debug; 3325 u_int32_t mrsas_io_timeout; 3326 u_int32_t mrsas_fw_fault_check_delay; 3327 u_int32_t io_cmds_highwater; 3328 u_int8_t UnevenSpanSupport; 3329 struct sysctl_ctx_list sysctl_ctx; 3330 struct sysctl_oid *sysctl_tree; 3331 struct proc *ocr_thread; 3332 u_int32_t last_seq_num; 3333 bus_dma_tag_t el_info_tag; 3334 bus_dmamap_t el_info_dmamap; 3335 void *el_info_mem; 3336 bus_addr_t el_info_phys_addr; 3337 struct mrsas_pd_list pd_list[MRSAS_MAX_PD]; 3338 struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD]; 3339 struct mrsas_target target_list[MRSAS_MAX_TM_TARGETS]; 3340 u_int8_t ld_ids[MRSAS_MAX_LD_IDS]; 3341 struct taskqueue *ev_tq; 3342 struct task ev_task; 3343 u_int32_t CurLdCount; 3344 u_int64_t reset_flags; 3345 int lb_pending_cmds; 3346 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT]; 3347 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT]; 3348 3349 u_int8_t mrsas_gen3_ctrl; 3350 u_int8_t secure_jbod_support; 3351 u_int8_t use_seqnum_jbod_fp; 3352 /* FW suport for more than 256 PD/JBOD */ 3353 u_int32_t support_morethan256jbod; 3354 u_int8_t max256vdSupport; 3355 u_int16_t fw_supported_vd_count; 3356 u_int16_t fw_supported_pd_count; 3357 3358 u_int16_t drv_supported_vd_count; 3359 u_int16_t drv_supported_pd_count; 3360 3361 u_int32_t max_map_sz; 3362 u_int32_t current_map_sz; 3363 u_int32_t old_map_sz; 3364 u_int32_t new_map_sz; 3365 u_int32_t drv_map_sz; 3366 3367 u_int32_t nvme_page_size; 3368 boolean_t is_ventura; 3369 boolean_t is_aero; 3370 boolean_t msix_combined; 3371 boolean_t atomic_desc_support; 3372 u_int16_t maxRaidMapSize; 3373 3374 /* Non dma-able memory. Driver local copy. */ 3375 MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; 3376 PTR_LD_STREAM_DETECT *streamDetectByLD; 3377 }; 3378 3379 /* Compatibility shims for different OS versions */ 3380 #if __FreeBSD_version >= 800001 3381 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 3382 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 3383 #define mrsas_kproc_exit(arg) kproc_exit(arg) 3384 #else 3385 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 3386 kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 3387 #define mrsas_kproc_exit(arg) kthread_exit(arg) 3388 #endif 3389 3390 static __inline void 3391 mrsas_clear_bit(int b, volatile void *p) 3392 { 3393 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 3394 } 3395 3396 static __inline void 3397 mrsas_set_bit(int b, volatile void *p) 3398 { 3399 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 3400 } 3401 3402 static __inline int 3403 mrsas_test_bit(int b, volatile void *p) 3404 { 3405 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 3406 } 3407 3408 #endif /* MRSAS_H */ 3409