1 /* 2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy 3 * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy 4 * Support: freebsdraid@avagotech.com 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 2. Redistributions 12 * in binary form must reproduce the above copyright notice, this list of 13 * conditions and the following disclaimer in the documentation and/or other 14 * materials provided with the distribution. 3. Neither the name of the 15 * <ORGANIZATION> nor the names of its contributors may be used to endorse or 16 * promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * The views and conclusions contained in the software and documentation are 32 * those of the authors and should not be interpreted as representing 33 * official policies,either expressed or implied, of the FreeBSD Project. 34 * 35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621 36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD 37 * 38 */ 39 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD$"); 42 43 #ifndef MRSAS_H 44 #define MRSAS_H 45 46 #include <sys/param.h> /* defines used in kernel.h */ 47 #include <sys/module.h> 48 #include <sys/systm.h> 49 #include <sys/proc.h> 50 #include <sys/errno.h> 51 #include <sys/kernel.h> /* types used in module initialization */ 52 #include <sys/conf.h> /* cdevsw struct */ 53 #include <sys/uio.h> /* uio struct */ 54 #include <sys/malloc.h> 55 #include <sys/bus.h> /* structs, prototypes for pci bus 56 * stuff */ 57 #include <sys/rman.h> 58 #include <sys/types.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/sema.h> 62 #include <sys/sysctl.h> 63 #include <sys/stat.h> 64 #include <sys/taskqueue.h> 65 #include <sys/poll.h> 66 #include <sys/selinfo.h> 67 68 #include <machine/bus.h> 69 #include <machine/resource.h> 70 #include <machine/atomic.h> 71 72 #include <dev/pci/pcivar.h> /* For pci_get macros! */ 73 #include <dev/pci/pcireg.h> 74 75 #define IOCTL_SEMA_DESCRIPTION "mrsas semaphore for MFI pool" 76 77 /* 78 * Device IDs and PCI 79 */ 80 #define MRSAS_TBOLT 0x005b 81 #define MRSAS_INVADER 0x005d 82 #define MRSAS_FURY 0x005f 83 #define MRSAS_INTRUDER 0x00ce 84 #define MRSAS_INTRUDER_24 0x00cf 85 #define MRSAS_CUTLASS_52 0x0052 86 #define MRSAS_CUTLASS_53 0x0053 87 /* Gen3.5 Conroller */ 88 #define MRSAS_VENTURA 0x0014 89 #define MRSAS_CRUSADER 0x0015 90 #define MRSAS_HARPOON 0x0016 91 #define MRSAS_TOMCAT 0x0017 92 #define MRSAS_VENTURA_4PORT 0x001B 93 #define MRSAS_CRUSADER_4PORT 0x001C 94 #define MRSAS_AERO_10E0 0x10E0 95 #define MRSAS_AERO_10E1 0x10E1 96 #define MRSAS_AERO_10E2 0x10E2 97 #define MRSAS_AERO_10E3 0x10E3 98 #define MRSAS_AERO_10E4 0x10E4 99 #define MRSAS_AERO_10E5 0x10E5 100 #define MRSAS_AERO_10E6 0x10E6 101 #define MRSAS_AERO_10E7 0x10E7 102 103 /* 104 * Firmware State Defines 105 */ 106 #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF 107 #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000 108 #define MRSAS_FW_STATE_CHNG_INTERRUPT 1 109 110 /* 111 * Message Frame Defines 112 */ 113 #define MRSAS_SENSE_LEN 96 114 #define MRSAS_FUSION_MAX_RESET_TRIES 3 115 116 /* 117 * Miscellaneous Defines 118 */ 119 #define BYTE_ALIGNMENT 1 120 #define MRSAS_MAX_NAME_LENGTH 32 121 #define MRSAS_VERSION "07.709.04.00-fbsd" 122 #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF 123 #define MRSAS_DEFAULT_TIMEOUT 0x14 /* Temporarily set */ 124 #define DONE 0 125 #define MRSAS_PAGE_SIZE 4096 126 #define MRSAS_RESET_NOTICE_INTERVAL 5 127 #define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */ 128 #define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */ 129 #define THRESHOLD_REPLY_COUNT 50 130 #define MAX_MSIX_COUNT 128 131 132 #define MAX_STREAMS_TRACKED 8 133 #define MR_STREAM_BITMAP 0x76543210 134 #define BITS_PER_INDEX_STREAM 4 /* number of bits per index in U32 TrackStream */ 135 #define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1) 136 #define ZERO_LAST_STREAM 0x0fffffff 137 138 /* 139 * Boolean types 140 */ 141 enum err { 142 SUCCESS, FAIL 143 }; 144 145 MALLOC_DECLARE(M_MRSAS); 146 SYSCTL_DECL(_hw_mrsas); 147 148 #define MRSAS_INFO (1 << 0) 149 #define MRSAS_TRACE (1 << 1) 150 #define MRSAS_FAULT (1 << 2) 151 #define MRSAS_OCR (1 << 3) 152 #define MRSAS_TOUT MRSAS_OCR 153 #define MRSAS_AEN (1 << 4) 154 #define MRSAS_PRL11 (1 << 5) 155 156 #define mrsas_dprint(sc, level, msg, args...) \ 157 do { \ 158 if (sc->mrsas_debug & level) \ 159 device_printf(sc->mrsas_dev, msg, ##args); \ 160 } while (0) 161 162 #define le32_to_cpus(x) do { *((u_int32_t *)(x)) = le32toh((*(u_int32_t *)x)); } while (0) 163 #define le16_to_cpus(x) do { *((u_int16_t *)(x)) = le16toh((*(u_int16_t *)x)); } while (0) 164 165 /**************************************************************************** 166 * Raid Context structure which describes MegaRAID specific IO Paramenters 167 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 168 ****************************************************************************/ 169 170 typedef struct _RAID_CONTEXT { 171 #if _BYTE_ORDER == _LITTLE_ENDIAN 172 u_int8_t Type:4; 173 u_int8_t nseg:4; 174 #else 175 u_int8_t nseg:4; 176 u_int8_t Type:4; 177 #endif 178 u_int8_t resvd0; 179 u_int16_t timeoutValue; 180 u_int8_t regLockFlags; 181 u_int8_t resvd1; 182 u_int16_t VirtualDiskTgtId; 183 u_int64_t regLockRowLBA; 184 u_int32_t regLockLength; 185 u_int16_t nextLMId; 186 u_int8_t exStatus; 187 u_int8_t status; 188 u_int8_t RAIDFlags; 189 u_int8_t numSGE; 190 u_int16_t configSeqNum; 191 u_int8_t spanArm; 192 u_int8_t priority; /* 0x1D MR_PRIORITY_RANGE */ 193 u_int8_t numSGEExt; /* 0x1E 1M IO support */ 194 u_int8_t resvd2; /* 0x1F */ 195 } RAID_CONTEXT; 196 197 /* 198 * Raid Context structure which describes ventura MegaRAID specific IO Paramenters 199 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 200 */ 201 typedef struct _RAID_CONTEXT_G35 { 202 #if _BYTE_ORDER == _LITTLE_ENDIAN 203 u_int16_t Type:4; 204 u_int16_t nseg:4; 205 u_int16_t resvd0:8; 206 #else 207 u_int16_t resvd0:8; 208 u_int16_t nseg:4; 209 u_int16_t Type:4; 210 #endif 211 u_int16_t timeoutValue; 212 union { 213 struct { 214 #if _BYTE_ORDER == _LITTLE_ENDIAN 215 u_int16_t reserved:1; 216 u_int16_t sld:1; 217 u_int16_t c2f:1; 218 u_int16_t fwn:1; 219 u_int16_t sqn:1; 220 u_int16_t sbs:1; 221 u_int16_t rw:1; 222 u_int16_t log:1; 223 u_int16_t cpuSel:4; 224 u_int16_t setDivert:4; 225 #else 226 u_int16_t setDivert:4; 227 u_int16_t cpuSel:4; 228 u_int16_t log:1; 229 u_int16_t rw:1; 230 u_int16_t sbs:1; 231 u_int16_t sqn:1; 232 u_int16_t fwn:1; 233 u_int16_t c2f:1; 234 u_int16_t sld:1; 235 u_int16_t reserved:1; 236 #endif 237 } bits; 238 u_int16_t s; 239 } routingFlags; 240 u_int16_t VirtualDiskTgtId; 241 u_int64_t regLockRowLBA; 242 u_int32_t regLockLength; 243 union { 244 u_int16_t nextLMId; 245 u_int16_t peerSMID; 246 } smid; 247 u_int8_t exStatus; 248 u_int8_t status; 249 u_int8_t RAIDFlags; 250 u_int8_t spanArm; 251 u_int16_t configSeqNum; 252 #if _BYTE_ORDER == _LITTLE_ENDIAN 253 u_int16_t numSGE:12; 254 u_int16_t reserved:3; 255 u_int16_t streamDetected:1; 256 #else 257 u_int16_t streamDetected:1; 258 u_int16_t reserved:3; 259 u_int16_t numSGE:12; 260 #endif 261 u_int8_t resvd2[2]; 262 } RAID_CONTEXT_G35; 263 264 typedef union _RAID_CONTEXT_UNION { 265 RAID_CONTEXT raid_context; 266 RAID_CONTEXT_G35 raid_context_g35; 267 } RAID_CONTEXT_UNION, *PRAID_CONTEXT_UNION; 268 269 /************************************************************************* 270 * MPI2 Defines 271 ************************************************************************/ 272 273 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 274 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 275 #define MPI2_VERSION_MAJOR (0x02) 276 #define MPI2_VERSION_MINOR (0x00) 277 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 278 #define MPI2_VERSION_MAJOR_SHIFT (8) 279 #define MPI2_VERSION_MINOR_MASK (0x00FF) 280 #define MPI2_VERSION_MINOR_SHIFT (0) 281 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 282 MPI2_VERSION_MINOR) 283 #define MPI2_HEADER_VERSION_UNIT (0x10) 284 #define MPI2_HEADER_VERSION_DEV (0x00) 285 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 286 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 287 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 288 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 289 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 290 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 291 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 292 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 293 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 294 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 295 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 296 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 297 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 298 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) 299 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03) 300 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06) 301 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 302 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 303 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 304 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 305 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 306 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 307 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 308 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 309 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 310 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 311 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 312 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 313 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 314 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 315 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 316 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 317 318 #ifndef MPI2_POINTER 319 #define MPI2_POINTER * 320 #endif 321 322 /*************************************** 323 * MPI2 Structures 324 ***************************************/ 325 326 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 327 u_int64_t Address; 328 u_int32_t Length; 329 u_int16_t Reserved1; 330 u_int8_t NextChainOffset; 331 u_int8_t Flags; 332 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 333 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 334 335 typedef struct _MPI2_SGE_SIMPLE_UNION { 336 u_int32_t FlagsLength; 337 union { 338 u_int32_t Address32; 339 u_int64_t Address64; 340 } u; 341 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 342 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 343 344 typedef struct { 345 u_int8_t CDB[20]; /* 0x00 */ 346 u_int32_t PrimaryReferenceTag; /* 0x14 */ 347 u_int16_t PrimaryApplicationTag;/* 0x18 */ 348 u_int16_t PrimaryApplicationTagMask; /* 0x1A */ 349 u_int32_t TransferLength; /* 0x1C */ 350 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 351 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 352 353 typedef struct _MPI2_SGE_CHAIN_UNION { 354 u_int16_t Length; 355 u_int8_t NextChainOffset; 356 u_int8_t Flags; 357 union { 358 u_int32_t Address32; 359 u_int64_t Address64; 360 } u; 361 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 362 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 363 364 typedef struct _MPI2_IEEE_SGE_SIMPLE32 { 365 u_int32_t Address; 366 u_int32_t FlagsLength; 367 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 368 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 369 typedef struct _MPI2_IEEE_SGE_SIMPLE64 { 370 u_int64_t Address; 371 u_int32_t Length; 372 u_int16_t Reserved1; 373 u_int8_t Reserved2; 374 u_int8_t Flags; 375 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 376 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 377 378 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 379 MPI2_IEEE_SGE_SIMPLE32 Simple32; 380 MPI2_IEEE_SGE_SIMPLE64 Simple64; 381 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 382 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 383 384 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 385 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 386 387 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 388 MPI2_IEEE_SGE_CHAIN32 Chain32; 389 MPI2_IEEE_SGE_CHAIN64 Chain64; 390 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 391 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 392 393 typedef union _MPI2_SGE_IO_UNION { 394 MPI2_SGE_SIMPLE_UNION MpiSimple; 395 MPI2_SGE_CHAIN_UNION MpiChain; 396 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 397 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 398 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 399 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 400 401 typedef union { 402 u_int8_t CDB32[32]; 403 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 404 MPI2_SGE_SIMPLE_UNION SGE; 405 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 406 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 407 408 /**************************************************************************** 409 * * SCSI Task Management messages 410 * ****************************************************************************/ 411 412 /*SCSI Task Management Request Message */ 413 typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST { 414 u_int16_t DevHandle; /*0x00 */ 415 u_int8_t ChainOffset; /*0x02 */ 416 u_int8_t Function; /*0x03 */ 417 u_int8_t Reserved1; /*0x04 */ 418 u_int8_t TaskType; /*0x05 */ 419 u_int8_t Reserved2; /*0x06 */ 420 u_int8_t MsgFlags; /*0x07 */ 421 u_int8_t VP_ID; /*0x08 */ 422 u_int8_t VF_ID; /*0x09 */ 423 u_int16_t Reserved3; /*0x0A */ 424 u_int8_t LUN[8]; /*0x0C */ 425 u_int32_t Reserved4[7]; /*0x14 */ 426 u_int16_t TaskMID; /*0x30 */ 427 u_int16_t Reserved5; /*0x32 */ 428 } MPI2_SCSI_TASK_MANAGE_REQUEST; 429 430 /*SCSI Task Management Reply Message */ 431 typedef struct _MPI2_SCSI_TASK_MANAGE_REPLY { 432 u_int16_t DevHandle; /*0x00 */ 433 u_int8_t MsgLength; /*0x02 */ 434 u_int8_t Function; /*0x03 */ 435 u_int8_t ResponseCode; /*0x04 */ 436 u_int8_t TaskType; /*0x05 */ 437 u_int8_t Reserved1; /*0x06 */ 438 u_int8_t MsgFlags; /*0x07 */ 439 u_int8_t VP_ID; /*0x08 */ 440 u_int8_t VF_ID; /*0x09 */ 441 u_int16_t Reserved2; /*0x0A */ 442 u_int16_t Reserved3; /*0x0C */ 443 u_int16_t IOCStatus; /*0x0E */ 444 u_int32_t IOCLogInfo; /*0x10 */ 445 u_int32_t TerminationCount; /*0x14 */ 446 u_int32_t ResponseInfo; /*0x18 */ 447 } MPI2_SCSI_TASK_MANAGE_REPLY; 448 449 typedef struct _MR_TM_REQUEST { 450 char request[128]; 451 } MR_TM_REQUEST; 452 453 typedef struct _MR_TM_REPLY { 454 char reply[128]; 455 } MR_TM_REPLY; 456 457 /* SCSI Task Management Request Message */ 458 typedef struct _MR_TASK_MANAGE_REQUEST { 459 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */ 460 MR_TM_REQUEST TmRequest; 461 union { 462 struct { 463 #if _BYTE_ORDER == _LITTLE_ENDIAN 464 u_int32_t isTMForLD:1; 465 u_int32_t isTMForPD:1; 466 u_int32_t reserved1:30; 467 #else 468 u_int32_t reserved1:30; 469 u_int32_t isTMForPD:1; 470 u_int32_t isTMForLD:1; 471 #endif 472 u_int32_t reserved2; 473 } tmReqFlags; 474 MR_TM_REPLY TMReply; 475 } uTmReqReply; 476 } MR_TASK_MANAGE_REQUEST; 477 478 /* TaskType values */ 479 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) 480 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) 481 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) 482 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) 483 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) 484 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) 485 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08) 486 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09) 487 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A) 488 489 /* ResponseCode values */ 490 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00) 491 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02) 492 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04) 493 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05) 494 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08) 495 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09) 496 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A) 497 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80) 498 499 /* 500 * RAID SCSI IO Request Message Total SGE count will be one less than 501 * _MPI2_SCSI_IO_REQUEST 502 */ 503 typedef struct _MPI2_RAID_SCSI_IO_REQUEST { 504 u_int16_t DevHandle; /* 0x00 */ 505 u_int8_t ChainOffset; /* 0x02 */ 506 u_int8_t Function; /* 0x03 */ 507 u_int16_t Reserved1; /* 0x04 */ 508 u_int8_t Reserved2; /* 0x06 */ 509 u_int8_t MsgFlags; /* 0x07 */ 510 u_int8_t VP_ID; /* 0x08 */ 511 u_int8_t VF_ID; /* 0x09 */ 512 u_int16_t Reserved3; /* 0x0A */ 513 u_int32_t SenseBufferLowAddress;/* 0x0C */ 514 u_int16_t SGLFlags; /* 0x10 */ 515 u_int8_t SenseBufferLength; /* 0x12 */ 516 u_int8_t Reserved4; /* 0x13 */ 517 u_int8_t SGLOffset0; /* 0x14 */ 518 u_int8_t SGLOffset1; /* 0x15 */ 519 u_int8_t SGLOffset2; /* 0x16 */ 520 u_int8_t SGLOffset3; /* 0x17 */ 521 u_int32_t SkipCount; /* 0x18 */ 522 u_int32_t DataLength; /* 0x1C */ 523 u_int32_t BidirectionalDataLength; /* 0x20 */ 524 u_int16_t IoFlags; /* 0x24 */ 525 u_int16_t EEDPFlags; /* 0x26 */ 526 u_int32_t EEDPBlockSize; /* 0x28 */ 527 u_int32_t SecondaryReferenceTag;/* 0x2C */ 528 u_int16_t SecondaryApplicationTag; /* 0x30 */ 529 u_int16_t ApplicationTagTranslationMask; /* 0x32 */ 530 u_int8_t LUN[8]; /* 0x34 */ 531 u_int32_t Control; /* 0x3C */ 532 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 533 RAID_CONTEXT_UNION RaidContext; /* 0x60 */ 534 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 535 } MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST, 536 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t; 537 538 /* 539 * MPT RAID MFA IO Descriptor. 540 */ 541 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR { 542 u_int32_t RequestFlags:8; 543 u_int32_t MessageAddress1:24; /* bits 31:8 */ 544 u_int32_t MessageAddress2; /* bits 61:32 */ 545 } MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR; 546 547 /* Default Request Descriptor */ 548 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 549 u_int8_t RequestFlags; /* 0x00 */ 550 u_int8_t MSIxIndex; /* 0x01 */ 551 u_int16_t SMID; /* 0x02 */ 552 u_int16_t LMID; /* 0x04 */ 553 u_int16_t DescriptorTypeDependent; /* 0x06 */ 554 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 555 556 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 557 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 558 559 /* High Priority Request Descriptor */ 560 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 561 u_int8_t RequestFlags; /* 0x00 */ 562 u_int8_t MSIxIndex; /* 0x01 */ 563 u_int16_t SMID; /* 0x02 */ 564 u_int16_t LMID; /* 0x04 */ 565 u_int16_t Reserved1; /* 0x06 */ 566 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 567 568 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 569 Mpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 570 571 /* SCSI IO Request Descriptor */ 572 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 573 u_int8_t RequestFlags; /* 0x00 */ 574 u_int8_t MSIxIndex; /* 0x01 */ 575 u_int16_t SMID; /* 0x02 */ 576 u_int16_t LMID; /* 0x04 */ 577 u_int16_t DevHandle; /* 0x06 */ 578 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 579 580 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 581 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 582 583 /* SCSI Target Request Descriptor */ 584 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 585 u_int8_t RequestFlags; /* 0x00 */ 586 u_int8_t MSIxIndex; /* 0x01 */ 587 u_int16_t SMID; /* 0x02 */ 588 u_int16_t LMID; /* 0x04 */ 589 u_int16_t IoIndex; /* 0x06 */ 590 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 591 592 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 593 Mpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 594 595 /* RAID Accelerator Request Descriptor */ 596 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 597 u_int8_t RequestFlags; /* 0x00 */ 598 u_int8_t MSIxIndex; /* 0x01 */ 599 u_int16_t SMID; /* 0x02 */ 600 u_int16_t LMID; /* 0x04 */ 601 u_int16_t Reserved; /* 0x06 */ 602 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 603 604 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 605 Mpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 606 607 /* union of Request Descriptors */ 608 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION { 609 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 610 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 611 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 612 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 613 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 614 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 615 union { 616 struct { 617 u_int32_t low; 618 u_int32_t high; 619 } u; 620 u_int64_t Words; 621 } addr; 622 } MRSAS_REQUEST_DESCRIPTOR_UNION; 623 624 /* Default Reply Descriptor */ 625 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 626 u_int8_t ReplyFlags; /* 0x00 */ 627 u_int8_t MSIxIndex; /* 0x01 */ 628 u_int16_t DescriptorTypeDependent1; /* 0x02 */ 629 u_int32_t DescriptorTypeDependent2; /* 0x04 */ 630 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 631 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 632 633 /* Address Reply Descriptor */ 634 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 635 u_int8_t ReplyFlags; /* 0x00 */ 636 u_int8_t MSIxIndex; /* 0x01 */ 637 u_int16_t SMID; /* 0x02 */ 638 u_int32_t ReplyFrameAddress; /* 0x04 */ 639 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 640 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 641 642 /* SCSI IO Success Reply Descriptor */ 643 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 644 u_int8_t ReplyFlags; /* 0x00 */ 645 u_int8_t MSIxIndex; /* 0x01 */ 646 u_int16_t SMID; /* 0x02 */ 647 u_int16_t TaskTag; /* 0x04 */ 648 u_int16_t Reserved1; /* 0x06 */ 649 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 650 651 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 652 Mpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 653 654 /* TargetAssist Success Reply Descriptor */ 655 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 656 u_int8_t ReplyFlags; /* 0x00 */ 657 u_int8_t MSIxIndex; /* 0x01 */ 658 u_int16_t SMID; /* 0x02 */ 659 u_int8_t SequenceNumber; /* 0x04 */ 660 u_int8_t Reserved1; /* 0x05 */ 661 u_int16_t IoIndex; /* 0x06 */ 662 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 663 664 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 665 Mpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 666 667 /* Target Command Buffer Reply Descriptor */ 668 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 669 u_int8_t ReplyFlags; /* 0x00 */ 670 u_int8_t MSIxIndex; /* 0x01 */ 671 u_int8_t VP_ID; /* 0x02 */ 672 u_int8_t Flags; /* 0x03 */ 673 u_int16_t InitiatorDevHandle; /* 0x04 */ 674 u_int16_t IoIndex; /* 0x06 */ 675 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 676 677 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 678 Mpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 679 680 /* RAID Accelerator Success Reply Descriptor */ 681 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 682 u_int8_t ReplyFlags; /* 0x00 */ 683 u_int8_t MSIxIndex; /* 0x01 */ 684 u_int16_t SMID; /* 0x02 */ 685 u_int32_t Reserved; /* 0x04 */ 686 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 687 688 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 689 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 690 691 /* union of Reply Descriptors */ 692 typedef union _MPI2_REPLY_DESCRIPTORS_UNION { 693 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 694 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 695 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 696 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 697 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 698 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 699 u_int64_t Words; 700 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 701 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 702 703 typedef union { 704 volatile unsigned int val; 705 unsigned int val_rdonly; 706 } mrsas_atomic_t; 707 708 #define mrsas_atomic_read(v) atomic_load_acq_int(&(v)->val) 709 #define mrsas_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 710 #define mrsas_atomic_dec(v) atomic_subtract_int(&(v)->val, 1) 711 #define mrsas_atomic_inc(v) atomic_add_int(&(v)->val, 1) 712 713 static inline int 714 mrsas_atomic_inc_return(mrsas_atomic_t *v) 715 { 716 return 1 + atomic_fetchadd_int(&(v)->val, 1); 717 } 718 719 /* IOCInit Request message */ 720 typedef struct _MPI2_IOC_INIT_REQUEST { 721 u_int8_t WhoInit; /* 0x00 */ 722 u_int8_t Reserved1; /* 0x01 */ 723 u_int8_t ChainOffset; /* 0x02 */ 724 u_int8_t Function; /* 0x03 */ 725 u_int16_t Reserved2; /* 0x04 */ 726 u_int8_t Reserved3; /* 0x06 */ 727 u_int8_t MsgFlags; /* 0x07 */ 728 u_int8_t VP_ID; /* 0x08 */ 729 u_int8_t VF_ID; /* 0x09 */ 730 u_int16_t Reserved4; /* 0x0A */ 731 u_int16_t MsgVersion; /* 0x0C */ 732 u_int16_t HeaderVersion; /* 0x0E */ 733 u_int32_t Reserved5; /* 0x10 */ 734 u_int16_t Reserved6; /* 0x14 */ 735 u_int8_t HostPageSize; /* 0x16 */ 736 u_int8_t HostMSIxVectors; /* 0x17 */ 737 u_int16_t Reserved8; /* 0x18 */ 738 u_int16_t SystemRequestFrameSize; /* 0x1A */ 739 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 740 u_int16_t ReplyFreeQueueDepth; /* 0x1E */ 741 u_int32_t SenseBufferAddressHigh; /* 0x20 */ 742 u_int32_t SystemReplyAddressHigh; /* 0x24 */ 743 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */ 744 u_int64_t ReplyDescriptorPostQueueAddress; /* 0x30 */ 745 u_int64_t ReplyFreeQueueAddress;/* 0x38 */ 746 u_int64_t TimeStamp; /* 0x40 */ 747 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 748 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 749 750 /* 751 * MR private defines 752 */ 753 #define MR_PD_INVALID 0xFFFF 754 #define MR_DEVHANDLE_INVALID 0xFFFF 755 #define MAX_SPAN_DEPTH 8 756 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 757 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 758 #define MAX_ROW_SIZE 32 759 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 760 #define MAX_LOGICAL_DRIVES 64 761 #define MAX_LOGICAL_DRIVES_EXT 256 762 #define MAX_LOGICAL_DRIVES_DYN 512 763 764 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 765 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 766 767 #define MAX_ARRAYS 128 768 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 769 770 #define MAX_ARRAYS_EXT 256 771 #define MAX_API_ARRAYS_EXT MAX_ARRAYS_EXT 772 #define MAX_API_ARRAYS_DYN 512 773 774 #define MAX_PHYSICAL_DEVICES 256 775 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 776 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512 777 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 778 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102 779 #define MR_DCMD_PD_MFI_TASK_MGMT 0x0200e100 780 781 #define MR_DCMD_PD_GET_INFO 0x02020000 782 #define MRSAS_MAX_PD_CHANNELS 1 783 #define MRSAS_MAX_LD_CHANNELS 1 784 #define MRSAS_MAX_DEV_PER_CHANNEL 256 785 #define MRSAS_DEFAULT_INIT_ID -1 786 #define MRSAS_MAX_LUN 8 787 #define MRSAS_DEFAULT_CMD_PER_LUN 256 788 #define MRSAS_MAX_PD (MRSAS_MAX_PD_CHANNELS * \ 789 MRSAS_MAX_DEV_PER_CHANNEL) 790 #define MRSAS_MAX_LD_IDS (MRSAS_MAX_LD_CHANNELS * \ 791 MRSAS_MAX_DEV_PER_CHANNEL) 792 793 #define VD_EXT_DEBUG 0 794 #define TM_DEBUG 1 795 796 /******************************************************************* 797 * RAID map related structures 798 ********************************************************************/ 799 #pragma pack(1) 800 typedef struct _MR_DEV_HANDLE_INFO { 801 u_int16_t curDevHdl; 802 u_int8_t validHandles; 803 u_int8_t interfaceType; 804 u_int16_t devHandle[2]; 805 } MR_DEV_HANDLE_INFO; 806 807 #pragma pack() 808 809 typedef struct _MR_ARRAY_INFO { 810 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE]; 811 } MR_ARRAY_INFO; 812 813 typedef struct _MR_QUAD_ELEMENT { 814 u_int64_t logStart; 815 u_int64_t logEnd; 816 u_int64_t offsetInSpan; 817 u_int32_t diff; 818 u_int32_t reserved1; 819 } MR_QUAD_ELEMENT; 820 821 typedef struct _MR_SPAN_INFO { 822 u_int32_t noElements; 823 u_int32_t reserved1; 824 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 825 } MR_SPAN_INFO; 826 827 typedef struct _MR_LD_SPAN_ { 828 u_int64_t startBlk; 829 u_int64_t numBlks; 830 u_int16_t arrayRef; 831 u_int8_t spanRowSize; 832 u_int8_t spanRowDataSize; 833 u_int8_t reserved[4]; 834 } MR_LD_SPAN; 835 836 typedef struct _MR_SPAN_BLOCK_INFO { 837 u_int64_t num_rows; 838 MR_LD_SPAN span; 839 MR_SPAN_INFO block_span_info; 840 } MR_SPAN_BLOCK_INFO; 841 842 typedef struct _MR_LD_RAID { 843 struct { 844 #if _BYTE_ORDER == _LITTLE_ENDIAN 845 u_int32_t fpCapable:1; 846 u_int32_t raCapable:1; 847 u_int32_t reserved5:2; 848 u_int32_t ldPiMode:4; 849 u_int32_t pdPiMode:4; 850 u_int32_t encryptionType:8; 851 u_int32_t fpWriteCapable:1; 852 u_int32_t fpReadCapable:1; 853 u_int32_t fpWriteAcrossStripe:1; 854 u_int32_t fpReadAcrossStripe:1; 855 u_int32_t fpNonRWCapable:1; 856 u_int32_t tmCapable:1; 857 u_int32_t fpCacheBypassCapable:1; 858 u_int32_t reserved4:5; 859 #else 860 u_int32_t reserved4:5; 861 u_int32_t fpCacheBypassCapable:1; 862 u_int32_t tmCapable:1; 863 u_int32_t fpNonRWCapable:1; 864 u_int32_t fpReadAcrossStripe:1; 865 u_int32_t fpWriteAcrossStripe:1; 866 u_int32_t fpReadCapable:1; 867 u_int32_t fpWriteCapable:1; 868 u_int32_t encryptionType:8; 869 u_int32_t pdPiMode:4; 870 u_int32_t ldPiMode:4; 871 u_int32_t reserved5:2; 872 u_int32_t raCapable:1; 873 u_int32_t fpCapable:1; 874 #endif 875 } capability; 876 u_int32_t reserved6; 877 u_int64_t size; 878 879 u_int8_t spanDepth; 880 u_int8_t level; 881 u_int8_t stripeShift; 882 u_int8_t rowSize; 883 884 u_int8_t rowDataSize; 885 u_int8_t writeMode; 886 u_int8_t PRL; 887 u_int8_t SRL; 888 889 u_int16_t targetId; 890 u_int8_t ldState; 891 u_int8_t regTypeReqOnWrite; 892 u_int8_t modFactor; 893 u_int8_t regTypeReqOnRead; 894 u_int16_t seqNum; 895 896 struct { 897 #if _BYTE_ORDER == _LITTLE_ENDIAN 898 u_int32_t reserved:30; 899 u_int32_t regTypeReqOnReadLsValid:1; 900 u_int32_t ldSyncRequired:1; 901 #else 902 u_int32_t ldSyncRequired:1; 903 u_int32_t regTypeReqOnReadLsValid:1; 904 u_int32_t reserved:30; 905 #endif 906 } flags; 907 908 u_int8_t LUN[8]; 909 u_int8_t fpIoTimeoutForLd; 910 u_int8_t reserved2[3]; 911 u_int32_t logicalBlockLength; 912 struct { 913 #if _BYTE_ORDER == _LITTLE_ENDIAN 914 u_int32_t reserved1:24; 915 u_int32_t LdLogicalBlockExp:4; 916 u_int32_t LdPiExp:4; 917 #else 918 u_int32_t LdPiExp:4; 919 u_int32_t LdLogicalBlockExp:4; 920 u_int32_t reserved1:24; 921 #endif 922 } exponent; 923 u_int8_t reserved3[0x80 - 0x38]; 924 } MR_LD_RAID; 925 926 typedef struct _MR_LD_SPAN_MAP { 927 MR_LD_RAID ldRaid; 928 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 929 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 930 } MR_LD_SPAN_MAP; 931 932 typedef struct _MR_FW_RAID_MAP { 933 u_int32_t totalSize; 934 union { 935 struct { 936 u_int32_t maxLd; 937 u_int32_t maxSpanDepth; 938 u_int32_t maxRowSize; 939 u_int32_t maxPdCount; 940 u_int32_t maxArrays; 941 } validationInfo; 942 u_int32_t version[5]; 943 u_int32_t reserved1[5]; 944 } raid_desc; 945 u_int32_t ldCount; 946 u_int32_t Reserved1; 947 948 /* 949 * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For 950 * example: if tgt Id is 4 and FW LD is 2, and there is only one LD, 951 * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF, 952 * 0x0,.....]. This is to help reduce the entire strcture size if 953 * there are few LDs or driver is looking info for 1 LD only. 954 */ 955 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS]; 956 u_int8_t fpPdIoTimeoutSec; 957 u_int8_t reserved2[7]; 958 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 959 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 960 MR_LD_SPAN_MAP ldSpanMap[1]; 961 } MR_FW_RAID_MAP; 962 963 typedef struct _MR_FW_RAID_MAP_EXT { 964 /* Not used in new map */ 965 u_int32_t reserved; 966 967 union { 968 struct { 969 u_int32_t maxLd; 970 u_int32_t maxSpanDepth; 971 u_int32_t maxRowSize; 972 u_int32_t maxPdCount; 973 u_int32_t maxArrays; 974 } validationInfo; 975 u_int32_t version[5]; 976 u_int32_t reserved1[5]; 977 } fw_raid_desc; 978 979 u_int8_t fpPdIoTimeoutSec; 980 u_int8_t reserved2[7]; 981 982 u_int16_t ldCount; 983 u_int16_t arCount; 984 u_int16_t spanCount; 985 u_int16_t reserve3; 986 987 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 988 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 989 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 990 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 991 } MR_FW_RAID_MAP_EXT; 992 993 typedef struct _MR_DRV_RAID_MAP { 994 /* 995 * Total size of this structure, including this field. This feild 996 * will be manupulated by driver for ext raid map, else pick the 997 * value from firmware raid map. 998 */ 999 u_int32_t totalSize; 1000 1001 union { 1002 struct { 1003 u_int32_t maxLd; 1004 u_int32_t maxSpanDepth; 1005 u_int32_t maxRowSize; 1006 u_int32_t maxPdCount; 1007 u_int32_t maxArrays; 1008 } validationInfo; 1009 u_int32_t version[5]; 1010 u_int32_t reserved1[5]; 1011 } drv_raid_desc; 1012 1013 /* timeout value used by driver in FP IOs */ 1014 u_int8_t fpPdIoTimeoutSec; 1015 u_int8_t reserved2[7]; 1016 1017 u_int16_t ldCount; 1018 u_int16_t arCount; 1019 u_int16_t spanCount; 1020 u_int16_t reserve3; 1021 1022 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN]; 1023 u_int16_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN]; 1024 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN]; 1025 MR_LD_SPAN_MAP ldSpanMap[1]; 1026 1027 } MR_DRV_RAID_MAP; 1028 1029 /* 1030 * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is 1031 * created to sync with old raid. And it is mainly for code re-use purpose. 1032 */ 1033 1034 #pragma pack(1) 1035 typedef struct _MR_DRV_RAID_MAP_ALL { 1036 MR_DRV_RAID_MAP raidMap; 1037 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1]; 1038 } MR_DRV_RAID_MAP_ALL; 1039 1040 #pragma pack() 1041 1042 typedef struct _LD_LOAD_BALANCE_INFO { 1043 u_int8_t loadBalanceFlag; 1044 u_int8_t reserved1; 1045 mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES]; 1046 u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES]; 1047 } LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO; 1048 1049 /* SPAN_SET is info caclulated from span info from Raid map per ld */ 1050 typedef struct _LD_SPAN_SET { 1051 u_int64_t log_start_lba; 1052 u_int64_t log_end_lba; 1053 u_int64_t span_row_start; 1054 u_int64_t span_row_end; 1055 u_int64_t data_strip_start; 1056 u_int64_t data_strip_end; 1057 u_int64_t data_row_start; 1058 u_int64_t data_row_end; 1059 u_int8_t strip_offset[MAX_SPAN_DEPTH]; 1060 u_int32_t span_row_data_width; 1061 u_int32_t diff; 1062 u_int32_t reserved[2]; 1063 } LD_SPAN_SET, *PLD_SPAN_SET; 1064 1065 typedef struct LOG_BLOCK_SPAN_INFO { 1066 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 1067 } LD_SPAN_INFO, *PLD_SPAN_INFO; 1068 1069 #pragma pack(1) 1070 typedef struct _MR_FW_RAID_MAP_ALL { 1071 MR_FW_RAID_MAP raidMap; 1072 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 1073 } MR_FW_RAID_MAP_ALL; 1074 1075 #pragma pack() 1076 1077 struct IO_REQUEST_INFO { 1078 u_int64_t ldStartBlock; 1079 u_int32_t numBlocks; 1080 u_int16_t ldTgtId; 1081 u_int8_t isRead; 1082 u_int16_t devHandle; 1083 u_int8_t pdInterface; 1084 u_int64_t pdBlock; 1085 u_int8_t fpOkForIo; 1086 u_int8_t IoforUnevenSpan; 1087 u_int8_t start_span; 1088 u_int8_t reserved; 1089 u_int64_t start_row; 1090 /* span[7:5], arm[4:0] */ 1091 u_int8_t span_arm; 1092 u_int8_t pd_after_lb; 1093 boolean_t raCapable; 1094 u_int16_t r1_alt_dev_handle; 1095 }; 1096 1097 /* 1098 * define MR_PD_CFG_SEQ structure for system PDs 1099 */ 1100 struct MR_PD_CFG_SEQ { 1101 u_int16_t seqNum; 1102 u_int16_t devHandle; 1103 struct { 1104 #if _BYTE_ORDER == _LITTLE_ENDIAN 1105 u_int8_t tmCapable:1; 1106 u_int8_t reserved:7; 1107 #else 1108 u_int8_t reserved:7; 1109 u_int8_t tmCapable:1; 1110 #endif 1111 } capability; 1112 u_int8_t reserved; 1113 u_int16_t pdTargetId; 1114 } __packed; 1115 1116 struct MR_PD_CFG_SEQ_NUM_SYNC { 1117 u_int32_t size; 1118 u_int32_t count; 1119 struct MR_PD_CFG_SEQ seq[1]; 1120 } __packed; 1121 1122 typedef struct _STREAM_DETECT { 1123 u_int64_t nextSeqLBA; 1124 struct megasas_cmd_fusion *first_cmd_fusion; 1125 struct megasas_cmd_fusion *last_cmd_fusion; 1126 u_int32_t countCmdsInStream; 1127 u_int16_t numSGEsInGroup; 1128 u_int8_t isRead; 1129 u_int8_t groupDepth; 1130 boolean_t groupFlush; 1131 u_int8_t reserved[7]; 1132 } STREAM_DETECT, *PTR_STREAM_DETECT; 1133 1134 typedef struct _LD_STREAM_DETECT { 1135 boolean_t writeBack; 1136 boolean_t FPWriteEnabled; 1137 boolean_t membersSSDs; 1138 boolean_t fpCacheBypassCapable; 1139 u_int32_t mruBitMap; 1140 volatile long iosToFware; 1141 volatile long writeBytesOutstanding; 1142 STREAM_DETECT streamTrack[MAX_STREAMS_TRACKED]; 1143 } LD_STREAM_DETECT, *PTR_LD_STREAM_DETECT; 1144 1145 typedef struct _MR_LD_TARGET_SYNC { 1146 u_int8_t targetId; 1147 u_int8_t reserved; 1148 u_int16_t seqNum; 1149 } MR_LD_TARGET_SYNC; 1150 1151 /* 1152 * RAID Map descriptor Types. 1153 * Each element should uniquely idetify one data structure in the RAID map 1154 */ 1155 typedef enum _MR_RAID_MAP_DESC_TYPE { 1156 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0, /* MR_DEV_HANDLE_INFO data */ 1157 RAID_MAP_DESC_TYPE_TGTID_INFO = 1, /* target to Ld num Index map */ 1158 RAID_MAP_DESC_TYPE_ARRAY_INFO = 2, /* MR_ARRAY_INFO data */ 1159 RAID_MAP_DESC_TYPE_SPAN_INFO = 3, /* MR_LD_SPAN_MAP data */ 1160 RAID_MAP_DESC_TYPE_COUNT, 1161 } MR_RAID_MAP_DESC_TYPE; 1162 1163 /* 1164 * This table defines the offset, size and num elements of each descriptor 1165 * type in the RAID Map buffer 1166 */ 1167 typedef struct _MR_RAID_MAP_DESC_TABLE { 1168 /* Raid map descriptor type */ 1169 u_int32_t raidMapDescType; 1170 /* Offset into the RAID map buffer where descriptor data is saved */ 1171 u_int32_t raidMapDescOffset; 1172 /* total size of the descriptor buffer */ 1173 u_int32_t raidMapDescBufferSize; 1174 /* Number of elements contained in the descriptor buffer */ 1175 u_int32_t raidMapDescElements; 1176 } MR_RAID_MAP_DESC_TABLE; 1177 1178 /* 1179 * Dynamic Raid Map Structure. 1180 */ 1181 typedef struct _MR_FW_RAID_MAP_DYNAMIC { 1182 u_int32_t raidMapSize; 1183 u_int32_t descTableOffset; 1184 u_int32_t descTableSize; 1185 u_int32_t descTableNumElements; 1186 u_int64_t PCIThresholdBandwidth; 1187 u_int32_t reserved2[3]; 1188 1189 u_int8_t fpPdIoTimeoutSec; 1190 u_int8_t reserved3[3]; 1191 u_int32_t rmwFPSeqNum; 1192 u_int16_t ldCount; 1193 u_int16_t arCount; 1194 u_int16_t spanCount; 1195 u_int16_t reserved4[3]; 1196 1197 /* 1198 * The below structure of pointers is only to be used by the driver. 1199 * This is added in the API to reduce the amount of code changes needed in 1200 * the driver to support dynamic RAID map. 1201 * Firmware should not update these pointers while preparing the raid map 1202 */ 1203 union { 1204 struct { 1205 MR_DEV_HANDLE_INFO *devHndlInfo; 1206 u_int16_t *ldTgtIdToLd; 1207 MR_ARRAY_INFO *arMapInfo; 1208 MR_LD_SPAN_MAP *ldSpanMap; 1209 } ptrStruct; 1210 u_int64_t ptrStructureSize[RAID_MAP_DESC_TYPE_COUNT]; 1211 } RaidMapDescPtrs; 1212 1213 /* 1214 * RAID Map descriptor table defines the layout of data in the RAID Map. 1215 * The size of the descriptor table itself could change. 1216 */ 1217 1218 /* Variable Size descriptor Table. */ 1219 MR_RAID_MAP_DESC_TABLE raidMapDescTable[RAID_MAP_DESC_TYPE_COUNT]; 1220 /* Variable Size buffer containing all data */ 1221 u_int32_t raidMapDescData[1]; 1222 1223 } MR_FW_RAID_MAP_DYNAMIC; 1224 1225 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1226 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1227 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1228 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1229 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1230 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1231 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1232 1233 /* Few NVME flags defines*/ 1234 #define MPI2_SGE_FLAGS_SHIFT (0x02) 1235 #define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0) 1236 #define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00) 1237 #define IEEE_SGE_FLAGS_FORMAT_PQI (0x01) 1238 #define IEEE_SGE_FLAGS_FORMAT_NVME (0x02) 1239 #define IEEE_SGE_FLAGS_FORMAT_AHCI (0x03) 1240 1241 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1242 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1243 #define MPI26_IEEE_SGE_FLAGS_NSF_PQI (0x04) 1244 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1245 #define MPI26_IEEE_SGE_FLAGS_NSF_AHCI_PRDT (0x0C) 1246 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1247 1248 union desc_value { 1249 u_int64_t word; 1250 struct { 1251 u_int32_t low; 1252 u_int32_t high; 1253 } u; 1254 }; 1255 1256 /******************************************************************* 1257 * Temporary command 1258 ********************************************************************/ 1259 struct mrsas_tmp_dcmd { 1260 bus_dma_tag_t tmp_dcmd_tag; 1261 bus_dmamap_t tmp_dcmd_dmamap; 1262 void *tmp_dcmd_mem; 1263 bus_addr_t tmp_dcmd_phys_addr; 1264 }; 1265 1266 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16 1267 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF 1268 #define MR_MIN_MAP_SIZE 0x10000 1269 1270 /******************************************************************* 1271 * Register set, included legacy controllers 1068 and 1078, 1272 * structure extended for 1078 registers 1273 *******************************************************************/ 1274 #pragma pack(1) 1275 typedef struct _mrsas_register_set { 1276 u_int32_t doorbell; /* 0000h */ 1277 u_int32_t fusion_seq_offset; /* 0004h */ 1278 u_int32_t fusion_host_diag; /* 0008h */ 1279 u_int32_t reserved_01; /* 000Ch */ 1280 1281 u_int32_t inbound_msg_0; /* 0010h */ 1282 u_int32_t inbound_msg_1; /* 0014h */ 1283 u_int32_t outbound_msg_0; /* 0018h */ 1284 u_int32_t outbound_msg_1; /* 001Ch */ 1285 1286 u_int32_t inbound_doorbell; /* 0020h */ 1287 u_int32_t inbound_intr_status; /* 0024h */ 1288 u_int32_t inbound_intr_mask; /* 0028h */ 1289 1290 u_int32_t outbound_doorbell; /* 002Ch */ 1291 u_int32_t outbound_intr_status; /* 0030h */ 1292 u_int32_t outbound_intr_mask; /* 0034h */ 1293 1294 u_int32_t reserved_1[2]; /* 0038h */ 1295 1296 u_int32_t inbound_queue_port; /* 0040h */ 1297 u_int32_t outbound_queue_port; /* 0044h */ 1298 1299 u_int32_t reserved_2[9]; /* 0048h */ 1300 u_int32_t reply_post_host_index;/* 006Ch */ 1301 u_int32_t reserved_2_2[12]; /* 0070h */ 1302 1303 u_int32_t outbound_doorbell_clear; /* 00A0h */ 1304 1305 u_int32_t reserved_3[3]; /* 00A4h */ 1306 1307 u_int32_t outbound_scratch_pad; /* 00B0h */ 1308 u_int32_t outbound_scratch_pad_2; /* 00B4h */ 1309 u_int32_t outbound_scratch_pad_3; /* 00B8h */ 1310 u_int32_t outbound_scratch_pad_4; /* 00BCh */ 1311 1312 u_int32_t inbound_low_queue_port; /* 00C0h */ 1313 1314 u_int32_t inbound_high_queue_port; /* 00C4h */ 1315 1316 u_int32_t inbound_single_queue_port; /* 00C8h */ 1317 u_int32_t res_6[11]; /* CCh */ 1318 u_int32_t host_diag; 1319 u_int32_t seq_offset; 1320 u_int32_t index_registers[807]; /* 00CCh */ 1321 } mrsas_reg_set; 1322 1323 #pragma pack() 1324 1325 /******************************************************************* 1326 * Firmware Interface Defines 1327 ******************************************************************* 1328 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 1329 * for protocol between the software and firmware. Commands are 1330 * issued using "message frames". 1331 ******************************************************************/ 1332 /* 1333 * FW posts its state in upper 4 bits of outbound_msg_0 register 1334 */ 1335 #define MFI_STATE_MASK 0xF0000000 1336 #define MFI_STATE_UNDEFINED 0x00000000 1337 #define MFI_STATE_BB_INIT 0x10000000 1338 #define MFI_STATE_FW_INIT 0x40000000 1339 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 1340 #define MFI_STATE_FW_INIT_2 0x70000000 1341 #define MFI_STATE_DEVICE_SCAN 0x80000000 1342 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 1343 #define MFI_STATE_FLUSH_CACHE 0xA0000000 1344 #define MFI_STATE_READY 0xB0000000 1345 #define MFI_STATE_OPERATIONAL 0xC0000000 1346 #define MFI_STATE_FAULT 0xF0000000 1347 #define MFI_RESET_REQUIRED 0x00000001 1348 #define MFI_RESET_ADAPTER 0x00000002 1349 #define MEGAMFI_FRAME_SIZE 64 1350 #define MRSAS_MFI_FRAME_SIZE 1024 1351 #define MRSAS_MFI_SENSE_SIZE 128 1352 1353 /* 1354 * During FW init, clear pending cmds & reset state using inbound_msg_0 1355 * 1356 * ABORT : Abort all pending cmds READY : Move from OPERATIONAL to 1357 * READY state; discard queue info MFIMODE : Discard (possible) low MFA 1358 * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from 1359 * BIOS or Driver HOTPLUG : Resume from Hotplug MFI_STOP_ADP : Send 1360 * signal to FW to stop processing 1361 */ 1362 1363 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) 1364 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) 1365 #define DIAG_WRITE_ENABLE (0x00000080) 1366 #define DIAG_RESET_ADAPTER (0x00000004) 1367 1368 #define MFI_ADP_RESET 0x00000040 1369 #define MFI_INIT_ABORT 0x00000001 1370 #define MFI_INIT_READY 0x00000002 1371 #define MFI_INIT_MFIMODE 0x00000004 1372 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 1373 #define MFI_INIT_HOTPLUG 0x00000010 1374 #define MFI_STOP_ADP 0x00000020 1375 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 1376 MFI_INIT_MFIMODE| \ 1377 MFI_INIT_ABORT 1378 1379 /* 1380 * MFI frame flags 1381 */ 1382 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 1383 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 1384 #define MFI_FRAME_SGL32 0x0000 1385 #define MFI_FRAME_SGL64 0x0002 1386 #define MFI_FRAME_SENSE32 0x0000 1387 #define MFI_FRAME_SENSE64 0x0004 1388 #define MFI_FRAME_DIR_NONE 0x0000 1389 #define MFI_FRAME_DIR_WRITE 0x0008 1390 #define MFI_FRAME_DIR_READ 0x0010 1391 #define MFI_FRAME_DIR_BOTH 0x0018 1392 #define MFI_FRAME_IEEE 0x0020 1393 1394 /* 1395 * Definition for cmd_status 1396 */ 1397 #define MFI_CMD_STATUS_POLL_MODE 0xFF 1398 1399 /* 1400 * MFI command opcodes 1401 */ 1402 #define MFI_CMD_INIT 0x00 1403 #define MFI_CMD_LD_READ 0x01 1404 #define MFI_CMD_LD_WRITE 0x02 1405 #define MFI_CMD_LD_SCSI_IO 0x03 1406 #define MFI_CMD_PD_SCSI_IO 0x04 1407 #define MFI_CMD_DCMD 0x05 1408 #define MFI_CMD_ABORT 0x06 1409 #define MFI_CMD_SMP 0x07 1410 #define MFI_CMD_STP 0x08 1411 #define MFI_CMD_INVALID 0xff 1412 1413 #define MR_DCMD_CTRL_GET_INFO 0x01010000 1414 #define MR_DCMD_LD_GET_LIST 0x03010000 1415 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 1416 #define MR_FLUSH_CTRL_CACHE 0x01 1417 #define MR_FLUSH_DISK_CACHE 0x02 1418 1419 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 1420 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 1421 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 1422 1423 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 1424 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 1425 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 1426 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 1427 1428 #define MR_DCMD_CLUSTER 0x08000000 1429 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 1430 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 1431 #define MR_DCMD_PD_LIST_QUERY 0x02010100 1432 1433 #define MR_DCMD_CTRL_MISC_CPX 0x0100e200 1434 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201 1435 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202 1436 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203 1437 #define MAX_MR_ROW_SIZE 32 1438 #define MR_CPX_DIR_WRITE 1 1439 #define MR_CPX_DIR_READ 0 1440 #define MR_CPX_VERSION 1 1441 1442 #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 1443 1444 #define MR_EVT_CFG_CLEARED 0x0004 1445 1446 #define MR_EVT_LD_STATE_CHANGE 0x0051 1447 #define MR_EVT_PD_INSERTED 0x005b 1448 #define MR_EVT_PD_REMOVED 0x0070 1449 #define MR_EVT_LD_CREATED 0x008a 1450 #define MR_EVT_LD_DELETED 0x008b 1451 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1452 #define MR_EVT_LD_OFFLINE 0x00fc 1453 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1454 #define MR_EVT_CTRL_PERF_COLLECTION 0x017e 1455 1456 /* 1457 * MFI command completion codes 1458 */ 1459 enum MFI_STAT { 1460 MFI_STAT_OK = 0x00, 1461 MFI_STAT_INVALID_CMD = 0x01, 1462 MFI_STAT_INVALID_DCMD = 0x02, 1463 MFI_STAT_INVALID_PARAMETER = 0x03, 1464 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 1465 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 1466 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 1467 MFI_STAT_APP_IN_USE = 0x07, 1468 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 1469 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 1470 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 1471 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 1472 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 1473 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 1474 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 1475 MFI_STAT_FLASH_BUSY = 0x0f, 1476 MFI_STAT_FLASH_ERROR = 0x10, 1477 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 1478 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 1479 MFI_STAT_FLASH_NOT_OPEN = 0x13, 1480 MFI_STAT_FLASH_NOT_STARTED = 0x14, 1481 MFI_STAT_FLUSH_FAILED = 0x15, 1482 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 1483 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 1484 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 1485 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 1486 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 1487 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 1488 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 1489 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 1490 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 1491 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 1492 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 1493 MFI_STAT_MFC_HW_ERROR = 0x21, 1494 MFI_STAT_NO_HW_PRESENT = 0x22, 1495 MFI_STAT_NOT_FOUND = 0x23, 1496 MFI_STAT_NOT_IN_ENCL = 0x24, 1497 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 1498 MFI_STAT_PD_TYPE_WRONG = 0x26, 1499 MFI_STAT_PR_DISABLED = 0x27, 1500 MFI_STAT_ROW_INDEX_INVALID = 0x28, 1501 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 1502 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 1503 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 1504 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 1505 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 1506 MFI_STAT_SCSI_IO_FAILED = 0x2e, 1507 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 1508 MFI_STAT_SHUTDOWN_FAILED = 0x30, 1509 MFI_STAT_TIME_NOT_SET = 0x31, 1510 MFI_STAT_WRONG_STATE = 0x32, 1511 MFI_STAT_LD_OFFLINE = 0x33, 1512 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 1513 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 1514 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 1515 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 1516 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 1517 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 1518 1519 MFI_STAT_INVALID_STATUS = 0xFF 1520 }; 1521 1522 /* 1523 * Number of mailbox bytes in DCMD message frame 1524 */ 1525 #define MFI_MBOX_SIZE 12 1526 1527 enum MR_EVT_CLASS { 1528 MR_EVT_CLASS_DEBUG = -2, 1529 MR_EVT_CLASS_PROGRESS = -1, 1530 MR_EVT_CLASS_INFO = 0, 1531 MR_EVT_CLASS_WARNING = 1, 1532 MR_EVT_CLASS_CRITICAL = 2, 1533 MR_EVT_CLASS_FATAL = 3, 1534 MR_EVT_CLASS_DEAD = 4, 1535 1536 }; 1537 1538 enum MR_EVT_LOCALE { 1539 MR_EVT_LOCALE_LD = 0x0001, 1540 MR_EVT_LOCALE_PD = 0x0002, 1541 MR_EVT_LOCALE_ENCL = 0x0004, 1542 MR_EVT_LOCALE_BBU = 0x0008, 1543 MR_EVT_LOCALE_SAS = 0x0010, 1544 MR_EVT_LOCALE_CTRL = 0x0020, 1545 MR_EVT_LOCALE_CONFIG = 0x0040, 1546 MR_EVT_LOCALE_CLUSTER = 0x0080, 1547 MR_EVT_LOCALE_ALL = 0xffff, 1548 1549 }; 1550 1551 enum MR_EVT_ARGS { 1552 MR_EVT_ARGS_NONE, 1553 MR_EVT_ARGS_CDB_SENSE, 1554 MR_EVT_ARGS_LD, 1555 MR_EVT_ARGS_LD_COUNT, 1556 MR_EVT_ARGS_LD_LBA, 1557 MR_EVT_ARGS_LD_OWNER, 1558 MR_EVT_ARGS_LD_LBA_PD_LBA, 1559 MR_EVT_ARGS_LD_PROG, 1560 MR_EVT_ARGS_LD_STATE, 1561 MR_EVT_ARGS_LD_STRIP, 1562 MR_EVT_ARGS_PD, 1563 MR_EVT_ARGS_PD_ERR, 1564 MR_EVT_ARGS_PD_LBA, 1565 MR_EVT_ARGS_PD_LBA_LD, 1566 MR_EVT_ARGS_PD_PROG, 1567 MR_EVT_ARGS_PD_STATE, 1568 MR_EVT_ARGS_PCI, 1569 MR_EVT_ARGS_RATE, 1570 MR_EVT_ARGS_STR, 1571 MR_EVT_ARGS_TIME, 1572 MR_EVT_ARGS_ECC, 1573 MR_EVT_ARGS_LD_PROP, 1574 MR_EVT_ARGS_PD_SPARE, 1575 MR_EVT_ARGS_PD_INDEX, 1576 MR_EVT_ARGS_DIAG_PASS, 1577 MR_EVT_ARGS_DIAG_FAIL, 1578 MR_EVT_ARGS_PD_LBA_LBA, 1579 MR_EVT_ARGS_PORT_PHY, 1580 MR_EVT_ARGS_PD_MISSING, 1581 MR_EVT_ARGS_PD_ADDRESS, 1582 MR_EVT_ARGS_BITMAP, 1583 MR_EVT_ARGS_CONNECTOR, 1584 MR_EVT_ARGS_PD_PD, 1585 MR_EVT_ARGS_PD_FRU, 1586 MR_EVT_ARGS_PD_PATHINFO, 1587 MR_EVT_ARGS_PD_POWER_STATE, 1588 MR_EVT_ARGS_GENERIC, 1589 }; 1590 1591 /* 1592 * Thunderbolt (and later) Defines 1593 */ 1594 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024 1595 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 1596 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 1597 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 1598 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 1599 #define MRSAS_LOAD_BALANCE_FLAG 0x1 1600 #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1 1601 #define HOST_DIAG_WRITE_ENABLE 0x80 1602 #define HOST_DIAG_RESET_ADAPTER 0x4 1603 #define MRSAS_TBOLT_MAX_RESET_TRIES 3 1604 #define MRSAS_MAX_MFI_CMDS 16 1605 #define MRSAS_MAX_IOCTL_CMDS 3 1606 1607 /* 1608 * Invader Defines 1609 */ 1610 #define MPI2_TYPE_CUDA 0x2 1611 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 1612 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 1613 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 1614 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 1615 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 1616 #define MR_RL_WRITE_THROUGH_MODE 0x00 1617 #define MR_RL_WRITE_BACK_MODE 0x01 1618 1619 /* 1620 * T10 PI defines 1621 */ 1622 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 1623 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 1624 #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9 1625 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB 1626 #define MRSAS_SCSI_ADDL_CDB_LEN 0x18 1627 #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20 1628 #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60 1629 #define MRSAS_SCSIBLOCKSIZE 512 1630 1631 /* 1632 * Raid context flags 1633 */ 1634 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 1635 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 1636 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 1637 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 1638 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 1639 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2, 1640 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3, 1641 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4, 1642 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6, 1643 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7 1644 } MR_RAID_FLAGS_IO_SUB_TYPE; 1645 /* 1646 * Request descriptor types 1647 */ 1648 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1649 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1 1650 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 1651 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 1652 #define MRSAS_FP_CMD_LEN 16 1653 #define MRSAS_FUSION_IN_RESET 0 1654 1655 #define RAID_CTX_SPANARM_ARM_SHIFT (0) 1656 #define RAID_CTX_SPANARM_ARM_MASK (0x1f) 1657 #define RAID_CTX_SPANARM_SPAN_SHIFT (5) 1658 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 1659 1660 /* 1661 * Define region lock types 1662 */ 1663 typedef enum _REGION_TYPE { 1664 REGION_TYPE_UNUSED = 0, 1665 REGION_TYPE_SHARED_READ = 1, 1666 REGION_TYPE_SHARED_WRITE = 2, 1667 REGION_TYPE_EXCLUSIVE = 3, 1668 } REGION_TYPE; 1669 1670 /* 1671 * SCSI-CAM Related Defines 1672 */ 1673 #define MRSAS_SCSI_MAX_LUNS 0 1674 #define MRSAS_SCSI_INITIATOR_ID 255 1675 #define MRSAS_SCSI_MAX_CMDS 8 1676 #define MRSAS_SCSI_MAX_CDB_LEN 16 1677 #define MRSAS_SCSI_SENSE_BUFFERSIZE 96 1678 #define MRSAS_INTERNAL_CMDS 32 1679 #define MRSAS_FUSION_INT_CMDS 8 1680 1681 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000 1682 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0 1683 #define MEGASAS_256K_IO 128 1684 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4) 1685 1686 /* Request types */ 1687 #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0 1688 #define MRSAS_REQ_TYPE_AEN_FETCH 0x1 1689 #define MRSAS_REQ_TYPE_PASSTHRU 0x2 1690 #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3 1691 #define MRSAS_REQ_TYPE_SCSI_IO 0x4 1692 1693 /* Request states */ 1694 #define MRSAS_REQ_STATE_FREE 0 1695 #define MRSAS_REQ_STATE_BUSY 1 1696 #define MRSAS_REQ_STATE_TRAN 2 1697 #define MRSAS_REQ_STATE_COMPLETE 3 1698 1699 typedef enum _MR_SCSI_CMD_TYPE { 1700 READ_WRITE_LDIO = 0, 1701 NON_READ_WRITE_LDIO = 1, 1702 READ_WRITE_SYSPDIO = 2, 1703 NON_READ_WRITE_SYSPDIO = 3, 1704 } MR_SCSI_CMD_TYPE; 1705 1706 enum mrsas_req_flags { 1707 MRSAS_DIR_UNKNOWN = 0x1, 1708 MRSAS_DIR_IN = 0x2, 1709 MRSAS_DIR_OUT = 0x4, 1710 MRSAS_DIR_NONE = 0x8, 1711 }; 1712 1713 /* 1714 * Adapter Reset States 1715 */ 1716 enum { 1717 MRSAS_HBA_OPERATIONAL = 0, 1718 MRSAS_ADPRESET_SM_INFAULT = 1, 1719 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1720 MRSAS_ADPRESET_SM_OPERATIONAL = 3, 1721 MRSAS_HW_CRITICAL_ERROR = 4, 1722 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1723 }; 1724 1725 /* 1726 * MPT Command Structure 1727 */ 1728 struct mrsas_mpt_cmd { 1729 MRSAS_RAID_SCSI_IO_REQUEST *io_request; 1730 bus_addr_t io_request_phys_addr; 1731 MPI2_SGE_IO_UNION *chain_frame; 1732 bus_addr_t chain_frame_phys_addr; 1733 u_int32_t sge_count; 1734 u_int8_t *sense; 1735 bus_addr_t sense_phys_addr; 1736 u_int8_t retry_for_fw_reset; 1737 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1738 u_int32_t sync_cmd_idx; 1739 u_int32_t index; 1740 u_int8_t flags; 1741 u_int8_t pd_r1_lb; 1742 u_int8_t load_balance; 1743 bus_size_t length; 1744 u_int32_t error_code; 1745 bus_dmamap_t data_dmamap; 1746 void *data; 1747 union ccb *ccb_ptr; 1748 struct callout cm_callout; 1749 struct mrsas_softc *sc; 1750 boolean_t tmCapable; 1751 u_int16_t r1_alt_dev_handle; 1752 boolean_t cmd_completed; 1753 struct mrsas_mpt_cmd *peer_cmd; 1754 bool callout_owner; 1755 TAILQ_ENTRY(mrsas_mpt_cmd) next; 1756 u_int8_t pdInterface; 1757 }; 1758 1759 /* 1760 * MFI Command Structure 1761 */ 1762 struct mrsas_mfi_cmd { 1763 union mrsas_frame *frame; 1764 bus_dmamap_t frame_dmamap; 1765 void *frame_mem; 1766 bus_addr_t frame_phys_addr; 1767 u_int8_t *sense; 1768 bus_dmamap_t sense_dmamap; 1769 void *sense_mem; 1770 bus_addr_t sense_phys_addr; 1771 u_int32_t index; 1772 u_int8_t sync_cmd; 1773 u_int8_t cmd_status; 1774 u_int8_t abort_aen; 1775 u_int8_t retry_for_fw_reset; 1776 struct mrsas_softc *sc; 1777 union ccb *ccb_ptr; 1778 union { 1779 struct { 1780 u_int16_t smid; 1781 u_int16_t resvd; 1782 } context; 1783 u_int32_t frame_count; 1784 } cmd_id; 1785 TAILQ_ENTRY(mrsas_mfi_cmd) next; 1786 }; 1787 1788 /* 1789 * define constants for device list query options 1790 */ 1791 enum MR_PD_QUERY_TYPE { 1792 MR_PD_QUERY_TYPE_ALL = 0, 1793 MR_PD_QUERY_TYPE_STATE = 1, 1794 MR_PD_QUERY_TYPE_POWER_STATE = 2, 1795 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 1796 MR_PD_QUERY_TYPE_SPEED = 4, 1797 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 1798 }; 1799 1800 #define MR_EVT_CFG_CLEARED 0x0004 1801 #define MR_EVT_LD_STATE_CHANGE 0x0051 1802 #define MR_EVT_PD_INSERTED 0x005b 1803 #define MR_EVT_PD_REMOVED 0x0070 1804 #define MR_EVT_LD_CREATED 0x008a 1805 #define MR_EVT_LD_DELETED 0x008b 1806 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1807 #define MR_EVT_LD_OFFLINE 0x00fc 1808 #define MR_EVT_CTRL_PROP_CHANGED 0x012f 1809 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1810 1811 enum MR_PD_STATE { 1812 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1813 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 1814 MR_PD_STATE_HOT_SPARE = 0x02, 1815 MR_PD_STATE_OFFLINE = 0x10, 1816 MR_PD_STATE_FAILED = 0x11, 1817 MR_PD_STATE_REBUILD = 0x14, 1818 MR_PD_STATE_ONLINE = 0x18, 1819 MR_PD_STATE_COPYBACK = 0x20, 1820 MR_PD_STATE_SYSTEM = 0x40, 1821 }; 1822 1823 /* 1824 * defines the physical drive address structure 1825 */ 1826 #pragma pack(1) 1827 struct MR_PD_ADDRESS { 1828 u_int16_t deviceId; 1829 u_int16_t enclDeviceId; 1830 1831 union { 1832 struct { 1833 u_int8_t enclIndex; 1834 u_int8_t slotNumber; 1835 } mrPdAddress; 1836 struct { 1837 u_int8_t enclPosition; 1838 u_int8_t enclConnectorIndex; 1839 } mrEnclAddress; 1840 } u1; 1841 u_int8_t scsiDevType; 1842 union { 1843 u_int8_t connectedPortBitmap; 1844 u_int8_t connectedPortNumbers; 1845 } u2; 1846 u_int64_t sasAddr[2]; 1847 }; 1848 1849 #pragma pack() 1850 1851 /* 1852 * defines the physical drive list structure 1853 */ 1854 #pragma pack(1) 1855 struct MR_PD_LIST { 1856 u_int32_t size; 1857 u_int32_t count; 1858 struct MR_PD_ADDRESS addr[1]; 1859 }; 1860 1861 #pragma pack() 1862 1863 #pragma pack(1) 1864 struct mrsas_pd_list { 1865 u_int16_t tid; 1866 u_int8_t driveType; 1867 u_int8_t driveState; 1868 }; 1869 1870 #pragma pack() 1871 1872 /* 1873 * defines the logical drive reference structure 1874 */ 1875 typedef union _MR_LD_REF { 1876 struct { 1877 u_int8_t targetId; 1878 u_int8_t reserved; 1879 u_int16_t seqNum; 1880 } ld_context; 1881 u_int32_t ref; 1882 } MR_LD_REF; 1883 1884 /* 1885 * defines the logical drive list structure 1886 */ 1887 #pragma pack(1) 1888 struct MR_LD_LIST { 1889 u_int32_t ldCount; 1890 u_int32_t reserved; 1891 struct { 1892 MR_LD_REF ref; 1893 u_int8_t state; 1894 u_int8_t reserved[3]; 1895 u_int64_t size; 1896 } ldList[MAX_LOGICAL_DRIVES_EXT]; 1897 }; 1898 1899 #pragma pack() 1900 1901 /* 1902 * SAS controller properties 1903 */ 1904 #pragma pack(1) 1905 struct mrsas_ctrl_prop { 1906 u_int16_t seq_num; 1907 u_int16_t pred_fail_poll_interval; 1908 u_int16_t intr_throttle_count; 1909 u_int16_t intr_throttle_timeouts; 1910 u_int8_t rebuild_rate; 1911 u_int8_t patrol_read_rate; 1912 u_int8_t bgi_rate; 1913 u_int8_t cc_rate; 1914 u_int8_t recon_rate; 1915 u_int8_t cache_flush_interval; 1916 u_int8_t spinup_drv_count; 1917 u_int8_t spinup_delay; 1918 u_int8_t cluster_enable; 1919 u_int8_t coercion_mode; 1920 u_int8_t alarm_enable; 1921 u_int8_t disable_auto_rebuild; 1922 u_int8_t disable_battery_warn; 1923 u_int8_t ecc_bucket_size; 1924 u_int16_t ecc_bucket_leak_rate; 1925 u_int8_t restore_hotspare_on_insertion; 1926 u_int8_t expose_encl_devices; 1927 u_int8_t maintainPdFailHistory; 1928 u_int8_t disallowHostRequestReordering; 1929 u_int8_t abortCCOnError; 1930 u_int8_t loadBalanceMode; 1931 u_int8_t disableAutoDetectBackplane; 1932 u_int8_t snapVDSpace; 1933 /* 1934 * Add properties that can be controlled by a bit in the following 1935 * structure. 1936 */ 1937 struct { 1938 #if _BYTE_ORDER == _LITTLE_ENDIAN 1939 u_int32_t copyBackDisabled:1; 1940 u_int32_t SMARTerEnabled:1; 1941 u_int32_t prCorrectUnconfiguredAreas:1; 1942 u_int32_t useFdeOnly:1; 1943 u_int32_t disableNCQ:1; 1944 u_int32_t SSDSMARTerEnabled:1; 1945 u_int32_t SSDPatrolReadEnabled:1; 1946 u_int32_t enableSpinDownUnconfigured:1; 1947 u_int32_t autoEnhancedImport:1; 1948 u_int32_t enableSecretKeyControl:1; 1949 u_int32_t disableOnlineCtrlReset:1; 1950 u_int32_t allowBootWithPinnedCache:1; 1951 u_int32_t disableSpinDownHS:1; 1952 u_int32_t enableJBOD:1; 1953 u_int32_t disableCacheBypass:1; 1954 u_int32_t useDiskActivityForLocate:1; 1955 u_int32_t enablePI:1; 1956 u_int32_t preventPIImport:1; 1957 u_int32_t useGlobalSparesForEmergency:1; 1958 u_int32_t useUnconfGoodForEmergency:1; 1959 u_int32_t useEmergencySparesforSMARTer:1; 1960 u_int32_t forceSGPIOForQuadOnly:1; 1961 u_int32_t enableConfigAutoBalance:1; 1962 u_int32_t enableVirtualCache:1; 1963 u_int32_t enableAutoLockRecovery:1; 1964 u_int32_t disableImmediateIO:1; 1965 u_int32_t disableT10RebuildAssist:1; 1966 u_int32_t ignore64ldRestriction:1; 1967 u_int32_t enableSwZone:1; 1968 u_int32_t limitMaxRateSATA3G:1; 1969 u_int32_t reserved:2; 1970 #else 1971 u_int32_t reserved:2; 1972 u_int32_t limitMaxRateSATA3G:1; 1973 u_int32_t enableSwZone:1; 1974 u_int32_t ignore64ldRestriction:1; 1975 u_int32_t disableT10RebuildAssist:1; 1976 u_int32_t disableImmediateIO:1; 1977 u_int32_t enableAutoLockRecovery:1; 1978 u_int32_t enableVirtualCache:1; 1979 u_int32_t enableConfigAutoBalance:1; 1980 u_int32_t forceSGPIOForQuadOnly:1; 1981 u_int32_t useEmergencySparesforSMARTer:1; 1982 u_int32_t useUnconfGoodForEmergency:1; 1983 u_int32_t useGlobalSparesForEmergency:1; 1984 u_int32_t preventPIImport:1; 1985 u_int32_t enablePI:1; 1986 u_int32_t useDiskActivityForLocate:1; 1987 u_int32_t disableCacheBypass:1; 1988 u_int32_t enableJBOD:1; 1989 u_int32_t disableSpinDownHS:1; 1990 u_int32_t allowBootWithPinnedCache:1; 1991 u_int32_t disableOnlineCtrlReset:1; 1992 u_int32_t enableSecretKeyControl:1; 1993 u_int32_t autoEnhancedImport:1; 1994 u_int32_t enableSpinDownUnconfigured:1; 1995 u_int32_t SSDPatrolReadEnabled:1; 1996 u_int32_t SSDSMARTerEnabled:1; 1997 u_int32_t disableNCQ:1; 1998 u_int32_t useFdeOnly:1; 1999 u_int32_t prCorrectUnconfiguredAreas:1; 2000 u_int32_t SMARTerEnabled:1; 2001 u_int32_t copyBackDisabled:1; 2002 #endif 2003 } OnOffProperties; 2004 u_int8_t autoSnapVDSpace; 2005 u_int8_t viewSpace; 2006 u_int16_t spinDownTime; 2007 u_int8_t reserved[24]; 2008 2009 }; 2010 2011 #pragma pack() 2012 2013 /* 2014 * SAS controller information 2015 */ 2016 struct mrsas_ctrl_info { 2017 /* 2018 * PCI device information 2019 */ 2020 struct { 2021 u_int16_t vendor_id; 2022 u_int16_t device_id; 2023 u_int16_t sub_vendor_id; 2024 u_int16_t sub_device_id; 2025 u_int8_t reserved[24]; 2026 } __packed pci; 2027 /* 2028 * Host interface information 2029 */ 2030 struct { 2031 u_int8_t PCIX:1; 2032 u_int8_t PCIE:1; 2033 u_int8_t iSCSI:1; 2034 u_int8_t SAS_3G:1; 2035 u_int8_t reserved_0:4; 2036 u_int8_t reserved_1[6]; 2037 u_int8_t port_count; 2038 u_int64_t port_addr[8]; 2039 } __packed host_interface; 2040 /* 2041 * Device (backend) interface information 2042 */ 2043 struct { 2044 u_int8_t SPI:1; 2045 u_int8_t SAS_3G:1; 2046 u_int8_t SATA_1_5G:1; 2047 u_int8_t SATA_3G:1; 2048 u_int8_t reserved_0:4; 2049 u_int8_t reserved_1[6]; 2050 u_int8_t port_count; 2051 u_int64_t port_addr[8]; 2052 } __packed device_interface; 2053 2054 u_int32_t image_check_word; 2055 u_int32_t image_component_count; 2056 2057 struct { 2058 char name[8]; 2059 char version[32]; 2060 char build_date[16]; 2061 char built_time[16]; 2062 } __packed image_component[8]; 2063 2064 u_int32_t pending_image_component_count; 2065 2066 struct { 2067 char name[8]; 2068 char version[32]; 2069 char build_date[16]; 2070 char build_time[16]; 2071 } __packed pending_image_component[8]; 2072 2073 u_int8_t max_arms; 2074 u_int8_t max_spans; 2075 u_int8_t max_arrays; 2076 u_int8_t max_lds; 2077 char product_name[80]; 2078 char serial_no[32]; 2079 2080 /* 2081 * Other physical/controller/operation information. Indicates the 2082 * presence of the hardware 2083 */ 2084 struct { 2085 u_int32_t bbu:1; 2086 u_int32_t alarm:1; 2087 u_int32_t nvram:1; 2088 u_int32_t uart:1; 2089 u_int32_t reserved:28; 2090 } __packed hw_present; 2091 2092 u_int32_t current_fw_time; 2093 2094 /* 2095 * Maximum data transfer sizes 2096 */ 2097 u_int16_t max_concurrent_cmds; 2098 u_int16_t max_sge_count; 2099 u_int32_t max_request_size; 2100 2101 /* 2102 * Logical and physical device counts 2103 */ 2104 u_int16_t ld_present_count; 2105 u_int16_t ld_degraded_count; 2106 u_int16_t ld_offline_count; 2107 2108 u_int16_t pd_present_count; 2109 u_int16_t pd_disk_present_count; 2110 u_int16_t pd_disk_pred_failure_count; 2111 u_int16_t pd_disk_failed_count; 2112 2113 /* 2114 * Memory size information 2115 */ 2116 u_int16_t nvram_size; 2117 u_int16_t memory_size; 2118 u_int16_t flash_size; 2119 2120 /* 2121 * Error counters 2122 */ 2123 u_int16_t mem_correctable_error_count; 2124 u_int16_t mem_uncorrectable_error_count; 2125 2126 /* 2127 * Cluster information 2128 */ 2129 u_int8_t cluster_permitted; 2130 u_int8_t cluster_active; 2131 2132 /* 2133 * Additional max data transfer sizes 2134 */ 2135 u_int16_t max_strips_per_io; 2136 2137 /* 2138 * Controller capabilities structures 2139 */ 2140 struct { 2141 u_int32_t raid_level_0:1; 2142 u_int32_t raid_level_1:1; 2143 u_int32_t raid_level_5:1; 2144 u_int32_t raid_level_1E:1; 2145 u_int32_t raid_level_6:1; 2146 u_int32_t reserved:27; 2147 } __packed raid_levels; 2148 2149 struct { 2150 u_int32_t rbld_rate:1; 2151 u_int32_t cc_rate:1; 2152 u_int32_t bgi_rate:1; 2153 u_int32_t recon_rate:1; 2154 u_int32_t patrol_rate:1; 2155 u_int32_t alarm_control:1; 2156 u_int32_t cluster_supported:1; 2157 u_int32_t bbu:1; 2158 u_int32_t spanning_allowed:1; 2159 u_int32_t dedicated_hotspares:1; 2160 u_int32_t revertible_hotspares:1; 2161 u_int32_t foreign_config_import:1; 2162 u_int32_t self_diagnostic:1; 2163 u_int32_t mixed_redundancy_arr:1; 2164 u_int32_t global_hot_spares:1; 2165 u_int32_t reserved:17; 2166 } __packed adapter_operations; 2167 2168 struct { 2169 u_int32_t read_policy:1; 2170 u_int32_t write_policy:1; 2171 u_int32_t io_policy:1; 2172 u_int32_t access_policy:1; 2173 u_int32_t disk_cache_policy:1; 2174 u_int32_t reserved:27; 2175 } __packed ld_operations; 2176 2177 struct { 2178 u_int8_t min; 2179 u_int8_t max; 2180 u_int8_t reserved[2]; 2181 } __packed stripe_sz_ops; 2182 2183 struct { 2184 u_int32_t force_online:1; 2185 u_int32_t force_offline:1; 2186 u_int32_t force_rebuild:1; 2187 u_int32_t reserved:29; 2188 } __packed pd_operations; 2189 2190 struct { 2191 u_int32_t ctrl_supports_sas:1; 2192 u_int32_t ctrl_supports_sata:1; 2193 u_int32_t allow_mix_in_encl:1; 2194 u_int32_t allow_mix_in_ld:1; 2195 u_int32_t allow_sata_in_cluster:1; 2196 u_int32_t reserved:27; 2197 } __packed pd_mix_support; 2198 2199 /* 2200 * Define ECC single-bit-error bucket information 2201 */ 2202 u_int8_t ecc_bucket_count; 2203 u_int8_t reserved_2[11]; 2204 2205 /* 2206 * Include the controller properties (changeable items) 2207 */ 2208 struct mrsas_ctrl_prop properties; 2209 2210 /* 2211 * Define FW pkg version (set in envt v'bles on OEM basis) 2212 */ 2213 char package_version[0x60]; 2214 2215 u_int64_t deviceInterfacePortAddr2[8]; 2216 u_int8_t reserved3[128]; 2217 2218 struct { 2219 u_int16_t minPdRaidLevel_0:4; 2220 u_int16_t maxPdRaidLevel_0:12; 2221 2222 u_int16_t minPdRaidLevel_1:4; 2223 u_int16_t maxPdRaidLevel_1:12; 2224 2225 u_int16_t minPdRaidLevel_5:4; 2226 u_int16_t maxPdRaidLevel_5:12; 2227 2228 u_int16_t minPdRaidLevel_1E:4; 2229 u_int16_t maxPdRaidLevel_1E:12; 2230 2231 u_int16_t minPdRaidLevel_6:4; 2232 u_int16_t maxPdRaidLevel_6:12; 2233 2234 u_int16_t minPdRaidLevel_10:4; 2235 u_int16_t maxPdRaidLevel_10:12; 2236 2237 u_int16_t minPdRaidLevel_50:4; 2238 u_int16_t maxPdRaidLevel_50:12; 2239 2240 u_int16_t minPdRaidLevel_60:4; 2241 u_int16_t maxPdRaidLevel_60:12; 2242 2243 u_int16_t minPdRaidLevel_1E_RLQ0:4; 2244 u_int16_t maxPdRaidLevel_1E_RLQ0:12; 2245 2246 u_int16_t minPdRaidLevel_1E0_RLQ0:4; 2247 u_int16_t maxPdRaidLevel_1E0_RLQ0:12; 2248 2249 u_int16_t reserved[6]; 2250 } pdsForRaidLevels; 2251 2252 u_int16_t maxPds; /* 0x780 */ 2253 u_int16_t maxDedHSPs; /* 0x782 */ 2254 u_int16_t maxGlobalHSPs; /* 0x784 */ 2255 u_int16_t ddfSize; /* 0x786 */ 2256 u_int8_t maxLdsPerArray; /* 0x788 */ 2257 u_int8_t partitionsInDDF; /* 0x789 */ 2258 u_int8_t lockKeyBinding; /* 0x78a */ 2259 u_int8_t maxPITsPerLd; /* 0x78b */ 2260 u_int8_t maxViewsPerLd; /* 0x78c */ 2261 u_int8_t maxTargetId; /* 0x78d */ 2262 u_int16_t maxBvlVdSize; /* 0x78e */ 2263 2264 u_int16_t maxConfigurableSSCSize; /* 0x790 */ 2265 u_int16_t currentSSCsize; /* 0x792 */ 2266 2267 char expanderFwVersion[12]; /* 0x794 */ 2268 2269 u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */ 2270 2271 u_int16_t cacheMemorySize; /* 0x7A2 */ 2272 2273 struct { /* 0x7A4 */ 2274 #if _BYTE_ORDER == _LITTLE_ENDIAN 2275 u_int32_t supportPIcontroller:1; 2276 u_int32_t supportLdPIType1:1; 2277 u_int32_t supportLdPIType2:1; 2278 u_int32_t supportLdPIType3:1; 2279 u_int32_t supportLdBBMInfo:1; 2280 u_int32_t supportShieldState:1; 2281 u_int32_t blockSSDWriteCacheChange:1; 2282 u_int32_t supportSuspendResumeBGops:1; 2283 u_int32_t supportEmergencySpares:1; 2284 u_int32_t supportSetLinkSpeed:1; 2285 u_int32_t supportBootTimePFKChange:1; 2286 u_int32_t supportJBOD:1; 2287 u_int32_t disableOnlinePFKChange:1; 2288 u_int32_t supportPerfTuning:1; 2289 u_int32_t supportSSDPatrolRead:1; 2290 u_int32_t realTimeScheduler:1; 2291 2292 u_int32_t supportResetNow:1; 2293 u_int32_t supportEmulatedDrives:1; 2294 u_int32_t headlessMode:1; 2295 u_int32_t dedicatedHotSparesLimited:1; 2296 2297 u_int32_t supportUnevenSpans:1; 2298 u_int32_t reserved:11; 2299 #else 2300 u_int32_t reserved:11; 2301 u_int32_t supportUnevenSpans:1; 2302 u_int32_t dedicatedHotSparesLimited:1; 2303 u_int32_t headlessMode:1; 2304 u_int32_t supportEmulatedDrives:1; 2305 u_int32_t supportResetNow:1; 2306 u_int32_t realTimeScheduler:1; 2307 u_int32_t supportSSDPatrolRead:1; 2308 u_int32_t supportPerfTuning:1; 2309 u_int32_t disableOnlinePFKChange:1; 2310 u_int32_t supportJBOD:1; 2311 u_int32_t supportBootTimePFKChange:1; 2312 u_int32_t supportSetLinkSpeed:1; 2313 u_int32_t supportEmergencySpares:1; 2314 u_int32_t supportSuspendResumeBGops:1; 2315 u_int32_t blockSSDWriteCacheChange:1; 2316 u_int32_t supportShieldState:1; 2317 u_int32_t supportLdBBMInfo:1; 2318 u_int32_t supportLdPIType3:1; 2319 u_int32_t supportLdPIType2:1; 2320 u_int32_t supportLdPIType1:1; 2321 u_int32_t supportPIcontroller:1; 2322 #endif 2323 } adapterOperations2; 2324 2325 u_int8_t driverVersion[32]; /* 0x7A8 */ 2326 u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */ 2327 u_int8_t temperatureROC; /* 0x7C9 */ 2328 u_int8_t temperatureCtrl; /* 0x7CA */ 2329 u_int8_t reserved4; /* 0x7CB */ 2330 u_int16_t maxConfigurablePds; /* 0x7CC */ 2331 2332 u_int8_t reserved5[2]; /* 0x7CD reserved */ 2333 2334 struct { 2335 #if _BYTE_ORDER == _LITTLE_ENDIAN 2336 u_int32_t peerIsPresent:1; 2337 u_int32_t peerIsIncompatible:1; 2338 2339 u_int32_t hwIncompatible:1; 2340 u_int32_t fwVersionMismatch:1; 2341 u_int32_t ctrlPropIncompatible:1; 2342 u_int32_t premiumFeatureMismatch:1; 2343 u_int32_t reserved:26; 2344 #else 2345 u_int32_t reserved:26; 2346 u_int32_t premiumFeatureMismatch:1; 2347 u_int32_t ctrlPropIncompatible:1; 2348 u_int32_t fwVersionMismatch:1; 2349 u_int32_t hwIncompatible:1; 2350 u_int32_t peerIsIncompatible:1; 2351 u_int32_t peerIsPresent:1; 2352 #endif 2353 } cluster; 2354 2355 char clusterId[16]; /* 0x7D4 */ 2356 2357 char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ 2358 2359 struct { /* 0x7E8 */ 2360 #if _BYTE_ORDER == _LITTLE_ENDIAN 2361 u_int32_t supportPersonalityChange:2; 2362 u_int32_t supportThermalPollInterval:1; 2363 u_int32_t supportDisableImmediateIO:1; 2364 u_int32_t supportT10RebuildAssist:1; 2365 u_int32_t supportMaxExtLDs:1; 2366 u_int32_t supportCrashDump:1; 2367 u_int32_t supportSwZone:1; 2368 u_int32_t supportDebugQueue:1; 2369 u_int32_t supportNVCacheErase:1; 2370 u_int32_t supportForceTo512e:1; 2371 u_int32_t supportHOQRebuild:1; 2372 u_int32_t supportAllowedOpsforDrvRemoval:1; 2373 u_int32_t supportDrvActivityLEDSetting:1; 2374 u_int32_t supportNVDRAM:1; 2375 u_int32_t supportForceFlash:1; 2376 u_int32_t supportDisableSESMonitoring:1; 2377 u_int32_t supportCacheBypassModes:1; 2378 u_int32_t supportSecurityonJBOD:1; 2379 u_int32_t discardCacheDuringLDDelete:1; 2380 u_int32_t supportTTYLogCompression:1; 2381 u_int32_t supportCPLDUpdate:1; 2382 u_int32_t supportDiskCacheSettingForSysPDs:1; 2383 u_int32_t supportExtendedSSCSize:1; 2384 u_int32_t useSeqNumJbodFP:1; 2385 u_int32_t reserved:7; 2386 #else 2387 u_int32_t reserved:7; 2388 u_int32_t useSeqNumJbodFP:1; 2389 u_int32_t supportExtendedSSCSize:1; 2390 u_int32_t supportDiskCacheSettingForSysPDs:1; 2391 u_int32_t supportCPLDUpdate:1; 2392 u_int32_t supportTTYLogCompression:1; 2393 u_int32_t discardCacheDuringLDDelete:1; 2394 u_int32_t supportSecurityonJBOD:1; 2395 u_int32_t supportCacheBypassModes:1; 2396 u_int32_t supportDisableSESMonitoring:1; 2397 u_int32_t supportForceFlash:1; 2398 u_int32_t supportNVDRAM:1; 2399 u_int32_t supportDrvActivityLEDSetting:1; 2400 u_int32_t supportAllowedOpsforDrvRemoval:1; 2401 u_int32_t supportHOQRebuild:1; 2402 u_int32_t supportForceTo512e:1; 2403 u_int32_t supportNVCacheErase:1; 2404 u_int32_t supportDebugQueue:1; 2405 u_int32_t supportSwZone:1; 2406 u_int32_t supportCrashDump:1; 2407 u_int32_t supportMaxExtLDs:1; 2408 u_int32_t supportT10RebuildAssist:1; 2409 u_int32_t supportDisableImmediateIO:1; 2410 u_int32_t supportThermalPollInterval:1; 2411 u_int32_t supportPersonalityChange:2; 2412 #endif 2413 } adapterOperations3; 2414 2415 u_int8_t pad_cpld[16]; 2416 2417 struct { 2418 #if _BYTE_ORDER == _LITTLE_ENDIAN 2419 u_int16_t ctrlInfoExtSupported:1; 2420 u_int16_t supportIbuttonLess:1; 2421 u_int16_t supportedEncAlgo:1; 2422 u_int16_t supportEncryptedMfc:1; 2423 u_int16_t imageUploadSupported:1; 2424 u_int16_t supportSESCtrlInMultipathCfg:1; 2425 u_int16_t supportPdMapTargetId:1; 2426 u_int16_t FWSwapsBBUVPDInfo:1; 2427 u_int16_t reserved:8; 2428 #else 2429 u_int16_t reserved:8; 2430 u_int16_t FWSwapsBBUVPDInfo:1; 2431 u_int16_t supportPdMapTargetId:1; 2432 u_int16_t supportSESCtrlInMultipathCfg:1; 2433 u_int16_t imageUploadSupported:1; 2434 u_int16_t supportEncryptedMfc:1; 2435 u_int16_t supportedEncAlgo:1; 2436 u_int16_t supportIbuttonLess:1; 2437 u_int16_t ctrlInfoExtSupported:1; 2438 #endif 2439 } adapterOperations4; 2440 2441 u_int8_t pad[0x800 - 0x7FE]; /* 0x7FE */ 2442 } __packed; 2443 2444 /* 2445 * When SCSI mid-layer calls driver's reset routine, driver waits for 2446 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 2447 * that the driver cannot _actually_ abort or reset pending commands. While 2448 * it is waiting for the commands to complete, it prints a diagnostic message 2449 * every MRSAS_RESET_NOTICE_INTERVAL seconds 2450 */ 2451 #define MRSAS_RESET_WAIT_TIME 180 2452 #define MRSAS_INTERNAL_CMD_WAIT_TIME 180 2453 #define MRSAS_RESET_NOTICE_INTERVAL 5 2454 #define MRSAS_IOCTL_CMD 0 2455 #define MRSAS_DEFAULT_CMD_TIMEOUT 90 2456 #define MRSAS_THROTTLE_QUEUE_DEPTH 16 2457 2458 /* 2459 * MSI-x regsiters offset defines 2460 */ 2461 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) 2462 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 2463 #define MR_MAX_REPLY_QUEUES_OFFSET (0x0000001F) 2464 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET (0x003FC000) 2465 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 2466 #define MR_MAX_MSIX_REG_ARRAY 16 2467 2468 /* 2469 * SYNC CACHE offset define 2470 */ 2471 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000 2472 2473 #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET (1 << 24) 2474 2475 /* 2476 * FW reports the maximum of number of commands that it can accept (maximum 2477 * commands that can be outstanding) at any time. The driver must report a 2478 * lower number to the mid layer because it can issue a few internal commands 2479 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 2480 * is shown below 2481 */ 2482 #define MRSAS_INT_CMDS 32 2483 #define MRSAS_SKINNY_INT_CMDS 5 2484 #define MRSAS_MAX_MSIX_QUEUES 128 2485 2486 /* 2487 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs 2488 * based on the size of bus_addr_t 2489 */ 2490 #define IS_DMA64 (sizeof(bus_addr_t) == 8) 2491 2492 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 2493 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 2494 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 2495 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 2496 2497 #define MFI_OB_INTR_STATUS_MASK 0x00000002 2498 #define MFI_POLL_TIMEOUT_SECS 60 2499 2500 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 2501 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 2502 #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001 2503 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 2504 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 2505 #define MFI_1068_PCSR_OFFSET 0x84 2506 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 2507 #define MFI_1068_FW_READY 0xDDDD0000 2508 2509 typedef union _MFI_CAPABILITIES { 2510 struct { 2511 #if _BYTE_ORDER == _LITTLE_ENDIAN 2512 u_int32_t support_fp_remote_lun:1; 2513 u_int32_t support_additional_msix:1; 2514 u_int32_t support_fastpath_wb:1; 2515 u_int32_t support_max_255lds:1; 2516 u_int32_t support_ndrive_r1_lb:1; 2517 u_int32_t support_core_affinity:1; 2518 u_int32_t security_protocol_cmds_fw:1; 2519 u_int32_t support_ext_queue_depth:1; 2520 u_int32_t support_ext_io_size:1; 2521 u_int32_t reserved:23; 2522 #else 2523 u_int32_t reserved:23; 2524 u_int32_t support_ext_io_size:1; 2525 u_int32_t support_ext_queue_depth:1; 2526 u_int32_t security_protocol_cmds_fw:1; 2527 u_int32_t support_core_affinity:1; 2528 u_int32_t support_ndrive_r1_lb:1; 2529 u_int32_t support_max_255lds:1; 2530 u_int32_t support_fastpath_wb:1; 2531 u_int32_t support_additional_msix:1; 2532 u_int32_t support_fp_remote_lun:1; 2533 #endif 2534 } mfi_capabilities; 2535 u_int32_t reg; 2536 } MFI_CAPABILITIES; 2537 2538 #pragma pack(1) 2539 struct mrsas_sge32 { 2540 u_int32_t phys_addr; 2541 u_int32_t length; 2542 }; 2543 2544 #pragma pack() 2545 2546 #pragma pack(1) 2547 struct mrsas_sge64 { 2548 u_int64_t phys_addr; 2549 u_int32_t length; 2550 }; 2551 2552 #pragma pack() 2553 2554 #pragma pack() 2555 union mrsas_sgl { 2556 struct mrsas_sge32 sge32[1]; 2557 struct mrsas_sge64 sge64[1]; 2558 }; 2559 2560 #pragma pack() 2561 2562 #pragma pack(1) 2563 struct mrsas_header { 2564 u_int8_t cmd; /* 00e */ 2565 u_int8_t sense_len; /* 01h */ 2566 u_int8_t cmd_status; /* 02h */ 2567 u_int8_t scsi_status; /* 03h */ 2568 2569 u_int8_t target_id; /* 04h */ 2570 u_int8_t lun; /* 05h */ 2571 u_int8_t cdb_len; /* 06h */ 2572 u_int8_t sge_count; /* 07h */ 2573 2574 u_int32_t context; /* 08h */ 2575 u_int32_t pad_0; /* 0Ch */ 2576 2577 u_int16_t flags; /* 10h */ 2578 u_int16_t timeout; /* 12h */ 2579 u_int32_t data_xferlen; /* 14h */ 2580 }; 2581 2582 #pragma pack() 2583 2584 #pragma pack(1) 2585 struct mrsas_init_frame { 2586 u_int8_t cmd; /* 00h */ 2587 u_int8_t reserved_0; /* 01h */ 2588 u_int8_t cmd_status; /* 02h */ 2589 2590 u_int8_t reserved_1; /* 03h */ 2591 MFI_CAPABILITIES driver_operations; /* 04h */ 2592 u_int32_t context; /* 08h */ 2593 u_int32_t pad_0; /* 0Ch */ 2594 2595 u_int16_t flags; /* 10h */ 2596 u_int16_t reserved_3; /* 12h */ 2597 u_int32_t data_xfer_len; /* 14h */ 2598 2599 u_int32_t queue_info_new_phys_addr_lo; /* 18h */ 2600 u_int32_t queue_info_new_phys_addr_hi; /* 1Ch */ 2601 u_int32_t queue_info_old_phys_addr_lo; /* 20h */ 2602 u_int32_t queue_info_old_phys_addr_hi; /* 24h */ 2603 u_int32_t driver_ver_lo; /* 28h */ 2604 u_int32_t driver_ver_hi; /* 2Ch */ 2605 u_int32_t reserved_4[4]; /* 30h */ 2606 }; 2607 2608 #pragma pack() 2609 2610 #pragma pack(1) 2611 struct mrsas_io_frame { 2612 u_int8_t cmd; /* 00h */ 2613 u_int8_t sense_len; /* 01h */ 2614 u_int8_t cmd_status; /* 02h */ 2615 u_int8_t scsi_status; /* 03h */ 2616 2617 u_int8_t target_id; /* 04h */ 2618 u_int8_t access_byte; /* 05h */ 2619 u_int8_t reserved_0; /* 06h */ 2620 u_int8_t sge_count; /* 07h */ 2621 2622 u_int32_t context; /* 08h */ 2623 u_int32_t pad_0; /* 0Ch */ 2624 2625 u_int16_t flags; /* 10h */ 2626 u_int16_t timeout; /* 12h */ 2627 u_int32_t lba_count; /* 14h */ 2628 2629 u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2630 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2631 2632 u_int32_t start_lba_lo; /* 20h */ 2633 u_int32_t start_lba_hi; /* 24h */ 2634 2635 union mrsas_sgl sgl; /* 28h */ 2636 }; 2637 2638 #pragma pack() 2639 2640 #pragma pack(1) 2641 struct mrsas_pthru_frame { 2642 u_int8_t cmd; /* 00h */ 2643 u_int8_t sense_len; /* 01h */ 2644 u_int8_t cmd_status; /* 02h */ 2645 u_int8_t scsi_status; /* 03h */ 2646 2647 u_int8_t target_id; /* 04h */ 2648 u_int8_t lun; /* 05h */ 2649 u_int8_t cdb_len; /* 06h */ 2650 u_int8_t sge_count; /* 07h */ 2651 2652 u_int32_t context; /* 08h */ 2653 u_int32_t pad_0; /* 0Ch */ 2654 2655 u_int16_t flags; /* 10h */ 2656 u_int16_t timeout; /* 12h */ 2657 u_int32_t data_xfer_len; /* 14h */ 2658 2659 u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2660 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2661 2662 u_int8_t cdb[16]; /* 20h */ 2663 union mrsas_sgl sgl; /* 30h */ 2664 }; 2665 2666 #pragma pack() 2667 2668 #pragma pack(1) 2669 struct mrsas_dcmd_frame { 2670 u_int8_t cmd; /* 00h */ 2671 u_int8_t reserved_0; /* 01h */ 2672 u_int8_t cmd_status; /* 02h */ 2673 u_int8_t reserved_1[4]; /* 03h */ 2674 u_int8_t sge_count; /* 07h */ 2675 2676 u_int32_t context; /* 08h */ 2677 u_int32_t pad_0; /* 0Ch */ 2678 2679 u_int16_t flags; /* 10h */ 2680 u_int16_t timeout; /* 12h */ 2681 2682 u_int32_t data_xfer_len; /* 14h */ 2683 u_int32_t opcode; /* 18h */ 2684 2685 union { /* 1Ch */ 2686 u_int8_t b[12]; 2687 u_int16_t s[6]; 2688 u_int32_t w[3]; 2689 } mbox; 2690 2691 union mrsas_sgl sgl; /* 28h */ 2692 }; 2693 2694 #pragma pack() 2695 2696 #pragma pack(1) 2697 struct mrsas_abort_frame { 2698 u_int8_t cmd; /* 00h */ 2699 u_int8_t reserved_0; /* 01h */ 2700 u_int8_t cmd_status; /* 02h */ 2701 2702 u_int8_t reserved_1; /* 03h */ 2703 MFI_CAPABILITIES driver_operations; /* 04h */ 2704 u_int32_t context; /* 08h */ 2705 u_int32_t pad_0; /* 0Ch */ 2706 2707 u_int16_t flags; /* 10h */ 2708 u_int16_t reserved_3; /* 12h */ 2709 u_int32_t reserved_4; /* 14h */ 2710 2711 u_int32_t abort_context; /* 18h */ 2712 u_int32_t pad_1; /* 1Ch */ 2713 2714 u_int32_t abort_mfi_phys_addr_lo; /* 20h */ 2715 u_int32_t abort_mfi_phys_addr_hi; /* 24h */ 2716 2717 u_int32_t reserved_5[6]; /* 28h */ 2718 }; 2719 2720 #pragma pack() 2721 2722 #pragma pack(1) 2723 struct mrsas_smp_frame { 2724 u_int8_t cmd; /* 00h */ 2725 u_int8_t reserved_1; /* 01h */ 2726 u_int8_t cmd_status; /* 02h */ 2727 u_int8_t connection_status; /* 03h */ 2728 2729 u_int8_t reserved_2[3]; /* 04h */ 2730 u_int8_t sge_count; /* 07h */ 2731 2732 u_int32_t context; /* 08h */ 2733 u_int32_t pad_0; /* 0Ch */ 2734 2735 u_int16_t flags; /* 10h */ 2736 u_int16_t timeout; /* 12h */ 2737 2738 u_int32_t data_xfer_len; /* 14h */ 2739 u_int64_t sas_addr; /* 18h */ 2740 2741 union { 2742 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */ 2743 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */ 2744 } sgl; 2745 }; 2746 2747 #pragma pack() 2748 2749 #pragma pack(1) 2750 struct mrsas_stp_frame { 2751 u_int8_t cmd; /* 00h */ 2752 u_int8_t reserved_1; /* 01h */ 2753 u_int8_t cmd_status; /* 02h */ 2754 u_int8_t reserved_2; /* 03h */ 2755 2756 u_int8_t target_id; /* 04h */ 2757 u_int8_t reserved_3[2]; /* 05h */ 2758 u_int8_t sge_count; /* 07h */ 2759 2760 u_int32_t context; /* 08h */ 2761 u_int32_t pad_0; /* 0Ch */ 2762 2763 u_int16_t flags; /* 10h */ 2764 u_int16_t timeout; /* 12h */ 2765 2766 u_int32_t data_xfer_len; /* 14h */ 2767 2768 u_int16_t fis[10]; /* 18h */ 2769 u_int32_t stp_flags; 2770 2771 union { 2772 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */ 2773 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */ 2774 } sgl; 2775 }; 2776 2777 #pragma pack() 2778 2779 union mrsas_frame { 2780 struct mrsas_header hdr; 2781 struct mrsas_init_frame init; 2782 struct mrsas_io_frame io; 2783 struct mrsas_pthru_frame pthru; 2784 struct mrsas_dcmd_frame dcmd; 2785 struct mrsas_abort_frame abort; 2786 struct mrsas_smp_frame smp; 2787 struct mrsas_stp_frame stp; 2788 u_int8_t raw_bytes[64]; 2789 }; 2790 2791 #pragma pack(1) 2792 union mrsas_evt_class_locale { 2793 struct { 2794 #if _BYTE_ORDER == _LITTLE_ENDIAN 2795 u_int16_t locale; 2796 u_int8_t reserved; 2797 int8_t class; 2798 #else 2799 int8_t class; 2800 u_int8_t reserved; 2801 u_int16_t locale; 2802 #endif 2803 } __packed members; 2804 2805 u_int32_t word; 2806 2807 } __packed; 2808 2809 #pragma pack() 2810 2811 #pragma pack(1) 2812 struct mrsas_evt_log_info { 2813 u_int32_t newest_seq_num; 2814 u_int32_t oldest_seq_num; 2815 u_int32_t clear_seq_num; 2816 u_int32_t shutdown_seq_num; 2817 u_int32_t boot_seq_num; 2818 2819 } __packed; 2820 2821 #pragma pack() 2822 2823 struct mrsas_progress { 2824 u_int16_t progress; 2825 u_int16_t elapsed_seconds; 2826 2827 } __packed; 2828 2829 struct mrsas_evtarg_ld { 2830 u_int16_t target_id; 2831 u_int8_t ld_index; 2832 u_int8_t reserved; 2833 2834 } __packed; 2835 2836 struct mrsas_evtarg_pd { 2837 u_int16_t device_id; 2838 u_int8_t encl_index; 2839 u_int8_t slot_number; 2840 2841 } __packed; 2842 2843 struct mrsas_evt_detail { 2844 u_int32_t seq_num; 2845 u_int32_t time_stamp; 2846 u_int32_t code; 2847 union mrsas_evt_class_locale cl; 2848 u_int8_t arg_type; 2849 u_int8_t reserved1[15]; 2850 2851 union { 2852 struct { 2853 struct mrsas_evtarg_pd pd; 2854 u_int8_t cdb_length; 2855 u_int8_t sense_length; 2856 u_int8_t reserved[2]; 2857 u_int8_t cdb[16]; 2858 u_int8_t sense[64]; 2859 } __packed cdbSense; 2860 2861 struct mrsas_evtarg_ld ld; 2862 2863 struct { 2864 struct mrsas_evtarg_ld ld; 2865 u_int64_t count; 2866 } __packed ld_count; 2867 2868 struct { 2869 u_int64_t lba; 2870 struct mrsas_evtarg_ld ld; 2871 } __packed ld_lba; 2872 2873 struct { 2874 struct mrsas_evtarg_ld ld; 2875 u_int32_t prevOwner; 2876 u_int32_t newOwner; 2877 } __packed ld_owner; 2878 2879 struct { 2880 u_int64_t ld_lba; 2881 u_int64_t pd_lba; 2882 struct mrsas_evtarg_ld ld; 2883 struct mrsas_evtarg_pd pd; 2884 } __packed ld_lba_pd_lba; 2885 2886 struct { 2887 struct mrsas_evtarg_ld ld; 2888 struct mrsas_progress prog; 2889 } __packed ld_prog; 2890 2891 struct { 2892 struct mrsas_evtarg_ld ld; 2893 u_int32_t prev_state; 2894 u_int32_t new_state; 2895 } __packed ld_state; 2896 2897 struct { 2898 u_int64_t strip; 2899 struct mrsas_evtarg_ld ld; 2900 } __packed ld_strip; 2901 2902 struct mrsas_evtarg_pd pd; 2903 2904 struct { 2905 struct mrsas_evtarg_pd pd; 2906 u_int32_t err; 2907 } __packed pd_err; 2908 2909 struct { 2910 u_int64_t lba; 2911 struct mrsas_evtarg_pd pd; 2912 } __packed pd_lba; 2913 2914 struct { 2915 u_int64_t lba; 2916 struct mrsas_evtarg_pd pd; 2917 struct mrsas_evtarg_ld ld; 2918 } __packed pd_lba_ld; 2919 2920 struct { 2921 struct mrsas_evtarg_pd pd; 2922 struct mrsas_progress prog; 2923 } __packed pd_prog; 2924 2925 struct { 2926 struct mrsas_evtarg_pd pd; 2927 u_int32_t prevState; 2928 u_int32_t newState; 2929 } __packed pd_state; 2930 2931 struct { 2932 u_int16_t vendorId; 2933 u_int16_t deviceId; 2934 u_int16_t subVendorId; 2935 u_int16_t subDeviceId; 2936 } __packed pci; 2937 2938 u_int32_t rate; 2939 char str[96]; 2940 2941 struct { 2942 u_int32_t rtc; 2943 u_int32_t elapsedSeconds; 2944 } __packed time; 2945 2946 struct { 2947 u_int32_t ecar; 2948 u_int32_t elog; 2949 char str[64]; 2950 } __packed ecc; 2951 2952 u_int8_t b[96]; 2953 u_int16_t s[48]; 2954 u_int32_t w[24]; 2955 u_int64_t d[12]; 2956 } args; 2957 2958 char description[128]; 2959 2960 } __packed; 2961 2962 struct mrsas_irq_context { 2963 struct mrsas_softc *sc; 2964 uint32_t MSIxIndex; 2965 }; 2966 2967 enum MEGASAS_OCR_REASON { 2968 FW_FAULT_OCR = 0, 2969 MFI_DCMD_TIMEOUT_OCR = 1, 2970 }; 2971 2972 /* Controller management info added to support Linux Emulator */ 2973 #define MAX_MGMT_ADAPTERS 1024 2974 2975 struct mrsas_mgmt_info { 2976 u_int16_t count; 2977 struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS]; 2978 int max_index; 2979 }; 2980 2981 #define PCI_TYPE0_ADDRESSES 6 2982 #define PCI_TYPE1_ADDRESSES 2 2983 #define PCI_TYPE2_ADDRESSES 5 2984 2985 typedef struct _MRSAS_DRV_PCI_COMMON_HEADER { 2986 u_int16_t vendorID; 2987 //(ro) 2988 u_int16_t deviceID; 2989 //(ro) 2990 u_int16_t command; 2991 //Device control 2992 u_int16_t status; 2993 u_int8_t revisionID; 2994 //(ro) 2995 u_int8_t progIf; 2996 //(ro) 2997 u_int8_t subClass; 2998 //(ro) 2999 u_int8_t baseClass; 3000 //(ro) 3001 u_int8_t cacheLineSize; 3002 //(ro +) 3003 u_int8_t latencyTimer; 3004 //(ro +) 3005 u_int8_t headerType; 3006 //(ro) 3007 u_int8_t bist; 3008 //Built in self test 3009 3010 union { 3011 struct _MRSAS_DRV_PCI_HEADER_TYPE_0 { 3012 u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 3013 u_int32_t cis; 3014 u_int16_t subVendorID; 3015 u_int16_t subSystemID; 3016 u_int32_t romBaseAddress; 3017 u_int8_t capabilitiesPtr; 3018 u_int8_t reserved1[3]; 3019 u_int32_t reserved2; 3020 u_int8_t interruptLine; 3021 u_int8_t interruptPin; 3022 //(ro) 3023 u_int8_t minimumGrant; 3024 //(ro) 3025 u_int8_t maximumLatency; 3026 //(ro) 3027 } type0; 3028 3029 /* 3030 * PCI to PCI Bridge 3031 */ 3032 3033 struct _MRSAS_DRV_PCI_HEADER_TYPE_1 { 3034 u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 3035 u_int8_t primaryBus; 3036 u_int8_t secondaryBus; 3037 u_int8_t subordinateBus; 3038 u_int8_t secondaryLatency; 3039 u_int8_t ioBase; 3040 u_int8_t ioLimit; 3041 u_int16_t secondaryStatus; 3042 u_int16_t memoryBase; 3043 u_int16_t memoryLimit; 3044 u_int16_t prefetchBase; 3045 u_int16_t prefetchLimit; 3046 u_int32_t prefetchBaseUpper32; 3047 u_int32_t prefetchLimitUpper32; 3048 u_int16_t ioBaseUpper16; 3049 u_int16_t ioLimitUpper16; 3050 u_int8_t capabilitiesPtr; 3051 u_int8_t reserved1[3]; 3052 u_int32_t romBaseAddress; 3053 u_int8_t interruptLine; 3054 u_int8_t interruptPin; 3055 u_int16_t bridgeControl; 3056 } type1; 3057 3058 /* 3059 * PCI to CARDBUS Bridge 3060 */ 3061 3062 struct _MRSAS_DRV_PCI_HEADER_TYPE_2 { 3063 u_int32_t socketRegistersBaseAddress; 3064 u_int8_t capabilitiesPtr; 3065 u_int8_t reserved; 3066 u_int16_t secondaryStatus; 3067 u_int8_t primaryBus; 3068 u_int8_t secondaryBus; 3069 u_int8_t subordinateBus; 3070 u_int8_t secondaryLatency; 3071 struct { 3072 u_int32_t base; 3073 u_int32_t limit; 3074 } range [PCI_TYPE2_ADDRESSES - 1]; 3075 u_int8_t interruptLine; 3076 u_int8_t interruptPin; 3077 u_int16_t bridgeControl; 3078 } type2; 3079 } u; 3080 3081 } MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER; 3082 3083 #define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes 3084 3085 typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY { 3086 union { 3087 struct { 3088 #if _BYTE_ORDER == _LITTLE_ENDIAN 3089 u_int32_t linkSpeed:4; 3090 u_int32_t linkWidth:6; 3091 u_int32_t aspmSupport:2; 3092 u_int32_t losExitLatency:3; 3093 u_int32_t l1ExitLatency:3; 3094 u_int32_t rsvdp:6; 3095 u_int32_t portNumber:8; 3096 #else 3097 u_int32_t portNumber:8; 3098 u_int32_t rsvdp:6; 3099 u_int32_t l1ExitLatency:3; 3100 u_int32_t losExitLatency:3; 3101 u_int32_t aspmSupport:2; 3102 u_int32_t linkWidth:6; 3103 u_int32_t linkSpeed:4; 3104 #endif 3105 } bits; 3106 3107 u_int32_t asUlong; 3108 } u; 3109 } MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY; 3110 3111 #define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY) 3112 3113 typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY { 3114 union { 3115 struct { 3116 #if _BYTE_ORDER == _LITTLE_ENDIAN 3117 u_int16_t linkSpeed:4; 3118 u_int16_t negotiatedLinkWidth:6; 3119 u_int16_t linkTrainingError:1; 3120 u_int16_t linkTraning:1; 3121 u_int16_t slotClockConfig:1; 3122 u_int16_t rsvdZ:3; 3123 #else 3124 u_int16_t rsvdZ:3; 3125 u_int16_t slotClockConfig:1; 3126 u_int16_t linkTraning:1; 3127 u_int16_t linkTrainingError:1; 3128 u_int16_t negotiatedLinkWidth:6; 3129 u_int16_t linkSpeed:4; 3130 #endif 3131 } bits; 3132 3133 u_int16_t asUshort; 3134 } u; 3135 u_int16_t reserved; 3136 } MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY; 3137 3138 #define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY) 3139 3140 typedef struct _MRSAS_DRV_PCI_CAPABILITIES { 3141 MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability; 3142 MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability; 3143 } MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES; 3144 3145 #define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES) 3146 3147 /* PCI information */ 3148 typedef struct _MRSAS_DRV_PCI_INFORMATION { 3149 u_int32_t busNumber; 3150 u_int8_t deviceNumber; 3151 u_int8_t functionNumber; 3152 u_int8_t interruptVector; 3153 u_int8_t reserved1; 3154 MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo; 3155 MRSAS_DRV_PCI_CAPABILITIES capability; 3156 u_int32_t domainID; 3157 u_int8_t reserved2[28]; 3158 } MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION; 3159 3160 typedef enum _MR_PD_TYPE { 3161 UNKNOWN_DRIVE = 0, 3162 PARALLEL_SCSI = 1, 3163 SAS_PD = 2, 3164 SATA_PD = 3, 3165 FC_PD = 4, 3166 NVME_PD = 5, 3167 } MR_PD_TYPE; 3168 3169 typedef union _MR_PD_REF { 3170 struct { 3171 u_int16_t deviceId; 3172 u_int16_t seqNum; 3173 } mrPdRef; 3174 u_int32_t ref; 3175 } MR_PD_REF; 3176 3177 /* 3178 * define the DDF Type bit structure 3179 */ 3180 union MR_PD_DDF_TYPE { 3181 struct { 3182 union { 3183 struct { 3184 #if _BYTE_ORDER == _LITTLE_ENDIAN 3185 u_int16_t forcedPDGUID:1; 3186 u_int16_t inVD:1; 3187 u_int16_t isGlobalSpare:1; 3188 u_int16_t isSpare:1; 3189 u_int16_t isForeign:1; 3190 u_int16_t reserved:7; 3191 u_int16_t intf:4; 3192 #else 3193 u_int16_t intf:4; 3194 u_int16_t reserved:7; 3195 u_int16_t isForeign:1; 3196 u_int16_t isSpare:1; 3197 u_int16_t isGlobalSpare:1; 3198 u_int16_t inVD:1; 3199 u_int16_t forcedPDGUID:1; 3200 #endif 3201 } pdType; 3202 u_int16_t type; 3203 }; 3204 u_int16_t reserved; 3205 } ddf; 3206 struct { 3207 u_int32_t reserved; 3208 } nonDisk; 3209 u_int32_t type; 3210 } __packed; 3211 3212 /* 3213 * defines the progress structure 3214 */ 3215 union MR_PROGRESS { 3216 struct { 3217 u_int16_t progress; 3218 union { 3219 u_int16_t elapsedSecs; 3220 u_int16_t elapsedSecsForLastPercent; 3221 }; 3222 } mrProgress; 3223 u_int32_t w; 3224 } __packed; 3225 3226 /* 3227 * defines the physical drive progress structure 3228 */ 3229 struct MR_PD_PROGRESS { 3230 struct { 3231 #if _BYTE_ORDER == _LITTLE_ENDIAN 3232 u_int32_t rbld:1; 3233 u_int32_t patrol:1; 3234 u_int32_t clear:1; 3235 u_int32_t copyBack:1; 3236 u_int32_t erase:1; 3237 u_int32_t locate:1; 3238 u_int32_t reserved:26; 3239 #else 3240 u_int32_t reserved:26; 3241 u_int32_t locate:1; 3242 u_int32_t erase:1; 3243 u_int32_t copyBack:1; 3244 u_int32_t clear:1; 3245 u_int32_t patrol:1; 3246 u_int32_t rbld:1; 3247 #endif 3248 } active; 3249 union MR_PROGRESS rbld; 3250 union MR_PROGRESS patrol; 3251 union { 3252 union MR_PROGRESS clear; 3253 union MR_PROGRESS erase; 3254 }; 3255 3256 struct { 3257 #if _BYTE_ORDER == _LITTLE_ENDIAN 3258 u_int32_t rbld:1; 3259 u_int32_t patrol:1; 3260 u_int32_t clear:1; 3261 u_int32_t copyBack:1; 3262 u_int32_t erase:1; 3263 u_int32_t reserved:27; 3264 #else 3265 u_int32_t reserved:27; 3266 u_int32_t erase:1; 3267 u_int32_t copyBack:1; 3268 u_int32_t clear:1; 3269 u_int32_t patrol:1; 3270 u_int32_t rbld:1; 3271 #endif 3272 } pause; 3273 3274 union MR_PROGRESS reserved[3]; 3275 } __packed; 3276 3277 struct mrsas_pd_info { 3278 MR_PD_REF ref; 3279 u_int8_t inquiryData[96]; 3280 u_int8_t vpdPage83[64]; 3281 3282 u_int8_t notSupported; 3283 u_int8_t scsiDevType; 3284 3285 union { 3286 u_int8_t connectedPortBitmap; 3287 u_int8_t connectedPortNumbers; 3288 }; 3289 3290 u_int8_t deviceSpeed; 3291 u_int32_t mediaErrCount; 3292 u_int32_t otherErrCount; 3293 u_int32_t predFailCount; 3294 u_int32_t lastPredFailEventSeqNum; 3295 3296 u_int16_t fwState; 3297 u_int8_t disabledForRemoval; 3298 u_int8_t linkSpeed; 3299 union MR_PD_DDF_TYPE state; 3300 3301 struct { 3302 u_int8_t count; 3303 #if _BYTE_ORDER == _LITTLE_ENDIAN 3304 u_int8_t isPathBroken:4; 3305 u_int8_t reserved3:3; 3306 u_int8_t widePortCapable:1; 3307 #else 3308 u_int8_t widePortCapable:1; 3309 u_int8_t reserved3:3; 3310 u_int8_t isPathBroken:4; 3311 #endif 3312 u_int8_t connectorIndex[2]; 3313 u_int8_t reserved[4]; 3314 u_int64_t sasAddr[2]; 3315 u_int8_t reserved2[16]; 3316 } pathInfo; 3317 3318 u_int64_t rawSize; 3319 u_int64_t nonCoercedSize; 3320 u_int64_t coercedSize; 3321 u_int16_t enclDeviceId; 3322 u_int8_t enclIndex; 3323 3324 union { 3325 u_int8_t slotNumber; 3326 u_int8_t enclConnectorIndex; 3327 }; 3328 3329 struct MR_PD_PROGRESS progInfo; 3330 u_int8_t badBlockTableFull; 3331 u_int8_t unusableInCurrentConfig; 3332 u_int8_t vpdPage83Ext[64]; 3333 u_int8_t powerState; 3334 u_int8_t enclPosition; 3335 u_int32_t allowedOps; 3336 u_int16_t copyBackPartnerId; 3337 u_int16_t enclPartnerDeviceId; 3338 struct { 3339 #if _BYTE_ORDER == _LITTLE_ENDIAN 3340 u_int16_t fdeCapable:1; 3341 u_int16_t fdeEnabled:1; 3342 u_int16_t secured:1; 3343 u_int16_t locked:1; 3344 u_int16_t foreign:1; 3345 u_int16_t needsEKM:1; 3346 u_int16_t reserved:10; 3347 #else 3348 u_int16_t reserved:10; 3349 u_int16_t needsEKM:1; 3350 u_int16_t foreign:1; 3351 u_int16_t locked:1; 3352 u_int16_t secured:1; 3353 u_int16_t fdeEnabled:1; 3354 u_int16_t fdeCapable:1; 3355 #endif 3356 } security; 3357 u_int8_t mediaType; 3358 u_int8_t notCertified; 3359 u_int8_t bridgeVendor[8]; 3360 u_int8_t bridgeProductIdentification[16]; 3361 u_int8_t bridgeProductRevisionLevel[4]; 3362 u_int8_t satBridgeExists; 3363 3364 u_int8_t interfaceType; 3365 u_int8_t temperature; 3366 u_int8_t emulatedBlockSize; 3367 u_int16_t userDataBlockSize; 3368 u_int16_t reserved2; 3369 3370 struct { 3371 #if _BYTE_ORDER == _LITTLE_ENDIAN 3372 u_int32_t piType:3; 3373 u_int32_t piFormatted:1; 3374 u_int32_t piEligible:1; 3375 u_int32_t NCQ:1; 3376 u_int32_t WCE:1; 3377 u_int32_t commissionedSpare:1; 3378 u_int32_t emergencySpare:1; 3379 u_int32_t ineligibleForSSCD:1; 3380 u_int32_t ineligibleForLd:1; 3381 u_int32_t useSSEraseType:1; 3382 u_int32_t wceUnchanged:1; 3383 u_int32_t supportScsiUnmap:1; 3384 u_int32_t reserved:18; 3385 #else 3386 u_int32_t reserved:18; 3387 u_int32_t supportScsiUnmap:1; 3388 u_int32_t wceUnchanged:1; 3389 u_int32_t useSSEraseType:1; 3390 u_int32_t ineligibleForLd:1; 3391 u_int32_t ineligibleForSSCD:1; 3392 u_int32_t emergencySpare:1; 3393 u_int32_t commissionedSpare:1; 3394 u_int32_t WCE:1; 3395 u_int32_t NCQ:1; 3396 u_int32_t piEligible:1; 3397 u_int32_t piFormatted:1; 3398 u_int32_t piType:3; 3399 #endif 3400 } properties; 3401 3402 u_int64_t shieldDiagCompletionTime; 3403 u_int8_t shieldCounter; 3404 3405 u_int8_t linkSpeedOther; 3406 u_int8_t reserved4[2]; 3407 3408 struct { 3409 #if _BYTE_ORDER == _LITTLE_ENDIAN 3410 u_int32_t bbmErrCountSupported:1; 3411 u_int32_t bbmErrCount:31; 3412 #else 3413 u_int32_t bbmErrCount:31; 3414 u_int32_t bbmErrCountSupported:1; 3415 #endif 3416 } bbmErr; 3417 3418 u_int8_t reserved1[512-428]; 3419 } __packed; 3420 3421 struct mrsas_target { 3422 u_int16_t target_id; 3423 u_int32_t queue_depth; 3424 u_int8_t interface_type; 3425 u_int32_t max_io_size_kb; 3426 } __packed; 3427 3428 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF 3429 #define MR_DEFAULT_NVME_PAGE_SIZE 4096 3430 #define MR_DEFAULT_NVME_PAGE_SHIFT 12 3431 3432 /******************************************************************* 3433 * per-instance data 3434 ********************************************************************/ 3435 struct mrsas_softc { 3436 device_t mrsas_dev; 3437 struct cdev *mrsas_cdev; 3438 struct intr_config_hook mrsas_ich; 3439 struct cdev *mrsas_linux_emulator_cdev; 3440 uint16_t device_id; 3441 struct resource *reg_res; 3442 int reg_res_id; 3443 bus_space_tag_t bus_tag; 3444 bus_space_handle_t bus_handle; 3445 bus_dma_tag_t mrsas_parent_tag; 3446 bus_dma_tag_t verbuf_tag; 3447 bus_dmamap_t verbuf_dmamap; 3448 void *verbuf_mem; 3449 bus_addr_t verbuf_phys_addr; 3450 bus_dma_tag_t sense_tag; 3451 bus_dmamap_t sense_dmamap; 3452 void *sense_mem; 3453 bus_addr_t sense_phys_addr; 3454 bus_dma_tag_t io_request_tag; 3455 bus_dmamap_t io_request_dmamap; 3456 void *io_request_mem; 3457 bus_addr_t io_request_phys_addr; 3458 bus_dma_tag_t chain_frame_tag; 3459 bus_dmamap_t chain_frame_dmamap; 3460 void *chain_frame_mem; 3461 bus_addr_t chain_frame_phys_addr; 3462 bus_dma_tag_t reply_desc_tag; 3463 bus_dmamap_t reply_desc_dmamap; 3464 void *reply_desc_mem; 3465 bus_addr_t reply_desc_phys_addr; 3466 bus_dma_tag_t ioc_init_tag; 3467 bus_dmamap_t ioc_init_dmamap; 3468 void *ioc_init_mem; 3469 bus_addr_t ioc_init_phys_mem; 3470 bus_dma_tag_t data_tag; 3471 struct cam_sim *sim_0; 3472 struct cam_sim *sim_1; 3473 struct cam_path *path_0; 3474 struct cam_path *path_1; 3475 struct mtx sim_lock; 3476 struct mtx pci_lock; 3477 struct mtx io_lock; 3478 struct mtx ioctl_lock; 3479 struct mtx mpt_cmd_pool_lock; 3480 struct mtx mfi_cmd_pool_lock; 3481 struct mtx raidmap_lock; 3482 struct mtx aen_lock; 3483 struct mtx stream_lock; 3484 struct selinfo mrsas_select; 3485 uint32_t mrsas_aen_triggered; 3486 uint32_t mrsas_poll_waiting; 3487 3488 struct sema ioctl_count_sema; 3489 uint32_t max_fw_cmds; 3490 uint16_t max_scsi_cmds; 3491 uint32_t max_num_sge; 3492 struct resource *mrsas_irq[MAX_MSIX_COUNT]; 3493 void *intr_handle[MAX_MSIX_COUNT]; 3494 int irq_id[MAX_MSIX_COUNT]; 3495 struct mrsas_irq_context irq_context[MAX_MSIX_COUNT]; 3496 int msix_vectors; 3497 int msix_enable; 3498 uint32_t msix_reg_offset[16]; 3499 uint8_t mask_interrupts; 3500 uint16_t max_chain_frame_sz; 3501 struct mrsas_mpt_cmd **mpt_cmd_list; 3502 struct mrsas_mfi_cmd **mfi_cmd_list; 3503 TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head; 3504 TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head; 3505 bus_addr_t req_frames_desc_phys; 3506 u_int8_t *req_frames_desc; 3507 u_int8_t *req_desc; 3508 bus_addr_t io_request_frames_phys; 3509 u_int8_t *io_request_frames; 3510 bus_addr_t reply_frames_desc_phys; 3511 u_int16_t last_reply_idx[MAX_MSIX_COUNT]; 3512 u_int32_t reply_q_depth; 3513 u_int32_t request_alloc_sz; 3514 u_int32_t reply_alloc_sz; 3515 u_int32_t io_frames_alloc_sz; 3516 u_int32_t chain_frames_alloc_sz; 3517 u_int16_t max_sge_in_main_msg; 3518 u_int16_t max_sge_in_chain; 3519 u_int8_t chain_offset_io_request; 3520 u_int8_t chain_offset_mfi_pthru; 3521 u_int32_t map_sz; 3522 u_int64_t map_id; 3523 u_int64_t pd_seq_map_id; 3524 struct mrsas_mfi_cmd *map_update_cmd; 3525 struct mrsas_mfi_cmd *jbod_seq_cmd; 3526 struct mrsas_mfi_cmd *aen_cmd; 3527 u_int8_t fast_path_io; 3528 void *chan; 3529 void *ocr_chan; 3530 u_int8_t adprecovery; 3531 u_int8_t remove_in_progress; 3532 u_int8_t ocr_thread_active; 3533 u_int8_t do_timedout_reset; 3534 u_int32_t reset_in_progress; 3535 u_int32_t reset_count; 3536 u_int32_t block_sync_cache; 3537 u_int32_t drv_stream_detection; 3538 u_int8_t fw_sync_cache_support; 3539 mrsas_atomic_t target_reset_outstanding; 3540 #define MRSAS_MAX_TM_TARGETS (MRSAS_MAX_PD + MRSAS_MAX_LD_IDS) 3541 struct mrsas_mpt_cmd *target_reset_pool[MRSAS_MAX_TM_TARGETS]; 3542 3543 bus_dma_tag_t jbodmap_tag[2]; 3544 bus_dmamap_t jbodmap_dmamap[2]; 3545 void *jbodmap_mem[2]; 3546 bus_addr_t jbodmap_phys_addr[2]; 3547 3548 bus_dma_tag_t raidmap_tag[2]; 3549 bus_dmamap_t raidmap_dmamap[2]; 3550 void *raidmap_mem[2]; 3551 bus_addr_t raidmap_phys_addr[2]; 3552 bus_dma_tag_t mficmd_frame_tag; 3553 bus_dma_tag_t mficmd_sense_tag; 3554 bus_addr_t evt_detail_phys_addr; 3555 bus_dma_tag_t evt_detail_tag; 3556 bus_dmamap_t evt_detail_dmamap; 3557 struct mrsas_evt_detail *evt_detail_mem; 3558 bus_addr_t pd_info_phys_addr; 3559 bus_dma_tag_t pd_info_tag; 3560 bus_dmamap_t pd_info_dmamap; 3561 struct mrsas_pd_info *pd_info_mem; 3562 struct mrsas_ctrl_info *ctrl_info; 3563 bus_dma_tag_t ctlr_info_tag; 3564 bus_dmamap_t ctlr_info_dmamap; 3565 void *ctlr_info_mem; 3566 bus_addr_t ctlr_info_phys_addr; 3567 u_int32_t max_sectors_per_req; 3568 u_int32_t disableOnlineCtrlReset; 3569 mrsas_atomic_t fw_outstanding; 3570 mrsas_atomic_t prp_count; 3571 mrsas_atomic_t sge_holes; 3572 3573 u_int32_t mrsas_debug; 3574 u_int32_t mrsas_io_timeout; 3575 u_int32_t mrsas_fw_fault_check_delay; 3576 u_int32_t io_cmds_highwater; 3577 u_int8_t UnevenSpanSupport; 3578 struct sysctl_ctx_list sysctl_ctx; 3579 struct sysctl_oid *sysctl_tree; 3580 struct proc *ocr_thread; 3581 u_int32_t last_seq_num; 3582 bus_dma_tag_t el_info_tag; 3583 bus_dmamap_t el_info_dmamap; 3584 void *el_info_mem; 3585 bus_addr_t el_info_phys_addr; 3586 struct mrsas_pd_list pd_list[MRSAS_MAX_PD]; 3587 struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD]; 3588 struct mrsas_target target_list[MRSAS_MAX_TM_TARGETS]; 3589 u_int8_t ld_ids[MRSAS_MAX_LD_IDS]; 3590 struct taskqueue *ev_tq; 3591 struct task ev_task; 3592 u_int32_t CurLdCount; 3593 u_int64_t reset_flags; 3594 int lb_pending_cmds; 3595 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT]; 3596 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT]; 3597 3598 u_int8_t mrsas_gen3_ctrl; 3599 u_int8_t secure_jbod_support; 3600 u_int8_t use_seqnum_jbod_fp; 3601 /* FW suport for more than 256 PD/JBOD */ 3602 u_int32_t support_morethan256jbod; 3603 u_int8_t max256vdSupport; 3604 u_int16_t fw_supported_vd_count; 3605 u_int16_t fw_supported_pd_count; 3606 3607 u_int16_t drv_supported_vd_count; 3608 u_int16_t drv_supported_pd_count; 3609 3610 u_int32_t max_map_sz; 3611 u_int32_t current_map_sz; 3612 u_int32_t old_map_sz; 3613 u_int32_t new_map_sz; 3614 u_int32_t drv_map_sz; 3615 3616 u_int32_t nvme_page_size; 3617 boolean_t is_ventura; 3618 boolean_t is_aero; 3619 boolean_t msix_combined; 3620 boolean_t atomic_desc_support; 3621 u_int16_t maxRaidMapSize; 3622 3623 /* Non dma-able memory. Driver local copy. */ 3624 MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; 3625 PTR_LD_STREAM_DETECT *streamDetectByLD; 3626 }; 3627 3628 /* Compatibility shims for different OS versions */ 3629 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 3630 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 3631 #define mrsas_kproc_exit(arg) kproc_exit(arg) 3632 3633 static __inline void 3634 mrsas_clear_bit(int b, volatile void *p) 3635 { 3636 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 3637 } 3638 3639 static __inline void 3640 mrsas_set_bit(int b, volatile void *p) 3641 { 3642 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 3643 } 3644 3645 static __inline int 3646 mrsas_test_bit(int b, volatile void *p) 3647 { 3648 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 3649 } 3650 3651 #endif /* MRSAS_H */ 3652