10dbe28b3SPyun YongHyeon /****************************************************************************** 20dbe28b3SPyun YongHyeon * 30dbe28b3SPyun YongHyeon * Name: skgehw.h 40dbe28b3SPyun YongHyeon * Project: Gigabit Ethernet Adapters, Common Modules 50dbe28b3SPyun YongHyeon * Version: $Revision: 2.49 $ 60dbe28b3SPyun YongHyeon * Date: $Date: 2005/01/20 13:01:35 $ 70dbe28b3SPyun YongHyeon * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family 80dbe28b3SPyun YongHyeon * 90dbe28b3SPyun YongHyeon ******************************************************************************/ 100dbe28b3SPyun YongHyeon 110dbe28b3SPyun YongHyeon /****************************************************************************** 120dbe28b3SPyun YongHyeon * 130dbe28b3SPyun YongHyeon * LICENSE: 140dbe28b3SPyun YongHyeon * Copyright (C) Marvell International Ltd. and/or its affiliates 150dbe28b3SPyun YongHyeon * 160dbe28b3SPyun YongHyeon * The computer program files contained in this folder ("Files") 170dbe28b3SPyun YongHyeon * are provided to you under the BSD-type license terms provided 180dbe28b3SPyun YongHyeon * below, and any use of such Files and any derivative works 190dbe28b3SPyun YongHyeon * thereof created by you shall be governed by the following terms 200dbe28b3SPyun YongHyeon * and conditions: 210dbe28b3SPyun YongHyeon * 220dbe28b3SPyun YongHyeon * - Redistributions of source code must retain the above copyright 230dbe28b3SPyun YongHyeon * notice, this list of conditions and the following disclaimer. 240dbe28b3SPyun YongHyeon * - Redistributions in binary form must reproduce the above 250dbe28b3SPyun YongHyeon * copyright notice, this list of conditions and the following 260dbe28b3SPyun YongHyeon * disclaimer in the documentation and/or other materials provided 270dbe28b3SPyun YongHyeon * with the distribution. 280dbe28b3SPyun YongHyeon * - Neither the name of Marvell nor the names of its contributors 290dbe28b3SPyun YongHyeon * may be used to endorse or promote products derived from this 300dbe28b3SPyun YongHyeon * software without specific prior written permission. 310dbe28b3SPyun YongHyeon * 320dbe28b3SPyun YongHyeon * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 330dbe28b3SPyun YongHyeon * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 340dbe28b3SPyun YongHyeon * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 350dbe28b3SPyun YongHyeon * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 360dbe28b3SPyun YongHyeon * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 370dbe28b3SPyun YongHyeon * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 380dbe28b3SPyun YongHyeon * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 390dbe28b3SPyun YongHyeon * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 400dbe28b3SPyun YongHyeon * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 410dbe28b3SPyun YongHyeon * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 420dbe28b3SPyun YongHyeon * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 430dbe28b3SPyun YongHyeon * OF THE POSSIBILITY OF SUCH DAMAGE. 440dbe28b3SPyun YongHyeon * /LICENSE 450dbe28b3SPyun YongHyeon * 460dbe28b3SPyun YongHyeon ******************************************************************************/ 470dbe28b3SPyun YongHyeon 480dbe28b3SPyun YongHyeon /*- 49df57947fSPedro F. Giffuni * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause 50df57947fSPedro F. Giffuni * 510dbe28b3SPyun YongHyeon * Copyright (c) 1997, 1998, 1999, 2000 520dbe28b3SPyun YongHyeon * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 530dbe28b3SPyun YongHyeon * 540dbe28b3SPyun YongHyeon * Redistribution and use in source and binary forms, with or without 550dbe28b3SPyun YongHyeon * modification, are permitted provided that the following conditions 560dbe28b3SPyun YongHyeon * are met: 570dbe28b3SPyun YongHyeon * 1. Redistributions of source code must retain the above copyright 580dbe28b3SPyun YongHyeon * notice, this list of conditions and the following disclaimer. 590dbe28b3SPyun YongHyeon * 2. Redistributions in binary form must reproduce the above copyright 600dbe28b3SPyun YongHyeon * notice, this list of conditions and the following disclaimer in the 610dbe28b3SPyun YongHyeon * documentation and/or other materials provided with the distribution. 620dbe28b3SPyun YongHyeon * 3. All advertising materials mentioning features or use of this software 630dbe28b3SPyun YongHyeon * must display the following acknowledgement: 640dbe28b3SPyun YongHyeon * This product includes software developed by Bill Paul. 650dbe28b3SPyun YongHyeon * 4. Neither the name of the author nor the names of any co-contributors 660dbe28b3SPyun YongHyeon * may be used to endorse or promote products derived from this software 670dbe28b3SPyun YongHyeon * without specific prior written permission. 680dbe28b3SPyun YongHyeon * 690dbe28b3SPyun YongHyeon * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 700dbe28b3SPyun YongHyeon * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 710dbe28b3SPyun YongHyeon * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 720dbe28b3SPyun YongHyeon * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 730dbe28b3SPyun YongHyeon * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 740dbe28b3SPyun YongHyeon * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 750dbe28b3SPyun YongHyeon * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 760dbe28b3SPyun YongHyeon * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 770dbe28b3SPyun YongHyeon * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 780dbe28b3SPyun YongHyeon * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 790dbe28b3SPyun YongHyeon * THE POSSIBILITY OF SUCH DAMAGE. 800dbe28b3SPyun YongHyeon */ 810dbe28b3SPyun YongHyeon 820dbe28b3SPyun YongHyeon /*- 830dbe28b3SPyun YongHyeon * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 840dbe28b3SPyun YongHyeon * 850dbe28b3SPyun YongHyeon * Permission to use, copy, modify, and distribute this software for any 860dbe28b3SPyun YongHyeon * purpose with or without fee is hereby granted, provided that the above 870dbe28b3SPyun YongHyeon * copyright notice and this permission notice appear in all copies. 880dbe28b3SPyun YongHyeon * 890dbe28b3SPyun YongHyeon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 900dbe28b3SPyun YongHyeon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 910dbe28b3SPyun YongHyeon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 920dbe28b3SPyun YongHyeon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 930dbe28b3SPyun YongHyeon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 940dbe28b3SPyun YongHyeon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 950dbe28b3SPyun YongHyeon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 960dbe28b3SPyun YongHyeon */ 970dbe28b3SPyun YongHyeon 980dbe28b3SPyun YongHyeon 990dbe28b3SPyun YongHyeon /* 1000dbe28b3SPyun YongHyeon * SysKonnect PCI vendor ID 1010dbe28b3SPyun YongHyeon */ 1020dbe28b3SPyun YongHyeon #define VENDORID_SK 0x1148 1030dbe28b3SPyun YongHyeon 1040dbe28b3SPyun YongHyeon /* 1050dbe28b3SPyun YongHyeon * Marvell PCI vendor ID 1060dbe28b3SPyun YongHyeon */ 1070dbe28b3SPyun YongHyeon #define VENDORID_MARVELL 0x11AB 1080dbe28b3SPyun YongHyeon 1090dbe28b3SPyun YongHyeon /* 1100dbe28b3SPyun YongHyeon * D-Link PCI vendor ID 1110dbe28b3SPyun YongHyeon */ 1120dbe28b3SPyun YongHyeon #define VENDORID_DLINK 0x1186 1130dbe28b3SPyun YongHyeon 1140dbe28b3SPyun YongHyeon /* 1150dbe28b3SPyun YongHyeon * SysKonnect ethernet device IDs 1160dbe28b3SPyun YongHyeon */ 1170dbe28b3SPyun YongHyeon #define DEVICEID_SK_YUKON2 0x9000 1180dbe28b3SPyun YongHyeon #define DEVICEID_SK_YUKON2_EXPR 0x9e00 1190dbe28b3SPyun YongHyeon 1200dbe28b3SPyun YongHyeon /* 1210dbe28b3SPyun YongHyeon * Marvell gigabit ethernet device IDs 1220dbe28b3SPyun YongHyeon */ 1230dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_8021CU 0x4340 1240dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_8022CU 0x4341 1250dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_8061CU 0x4342 1260dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_8062CU 0x4343 1270dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_8021X 0x4344 1280dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_8022X 0x4345 1290dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_8061X 0x4346 1300dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_8062X 0x4347 1310dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_8035 0x4350 1320dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_8036 0x4351 1330dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_8038 0x4352 13412909985SPyun YongHyeon #define DEVICEID_MRVL_8039 0x4353 13512909985SPyun YongHyeon #define DEVICEID_MRVL_8040 0x4354 13612909985SPyun YongHyeon #define DEVICEID_MRVL_8040T 0x4355 1370e0ed74fSUlf Lilleengen #define DEVICEID_MRVL_8042 0x4357 13812909985SPyun YongHyeon #define DEVICEID_MRVL_8048 0x435A 1390dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_4360 0x4360 1400dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_4361 0x4361 1410dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_4362 0x4362 1420dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_4363 0x4363 1430dbe28b3SPyun YongHyeon #define DEVICEID_MRVL_4364 0x4364 144a56fe1f0SPyun YongHyeon #define DEVICEID_MRVL_4365 0x4365 14575ef16dfSPyun YongHyeon #define DEVICEID_MRVL_436A 0x436A 146a56fe1f0SPyun YongHyeon #define DEVICEID_MRVL_436B 0x436B 147a56fe1f0SPyun YongHyeon #define DEVICEID_MRVL_436C 0x436C 148e0029a72SPyun YongHyeon #define DEVICEID_MRVL_436D 0x436D 149e0029a72SPyun YongHyeon #define DEVICEID_MRVL_4370 0x4370 15076202a16SPyun YongHyeon #define DEVICEID_MRVL_4380 0x4380 151e19bd6eeSPyun YongHyeon #define DEVICEID_MRVL_4381 0x4381 1520dbe28b3SPyun YongHyeon 1530dbe28b3SPyun YongHyeon /* 1540dbe28b3SPyun YongHyeon * D-Link gigabit ethernet device ID 1550dbe28b3SPyun YongHyeon */ 1560dbe28b3SPyun YongHyeon #define DEVICEID_DLINK_DGE550SX 0x4001 15760d3251aSPyun YongHyeon #define DEVICEID_DLINK_DGE560SX 0x4002 1580dbe28b3SPyun YongHyeon #define DEVICEID_DLINK_DGE560T 0x4b00 1590dbe28b3SPyun YongHyeon 1607a22215cSEitan Adler #define BIT_31 (1U << 31) 1610dbe28b3SPyun YongHyeon #define BIT_30 (1 << 30) 1620dbe28b3SPyun YongHyeon #define BIT_29 (1 << 29) 1630dbe28b3SPyun YongHyeon #define BIT_28 (1 << 28) 1640dbe28b3SPyun YongHyeon #define BIT_27 (1 << 27) 1650dbe28b3SPyun YongHyeon #define BIT_26 (1 << 26) 1660dbe28b3SPyun YongHyeon #define BIT_25 (1 << 25) 1670dbe28b3SPyun YongHyeon #define BIT_24 (1 << 24) 1680dbe28b3SPyun YongHyeon #define BIT_23 (1 << 23) 1690dbe28b3SPyun YongHyeon #define BIT_22 (1 << 22) 1700dbe28b3SPyun YongHyeon #define BIT_21 (1 << 21) 1710dbe28b3SPyun YongHyeon #define BIT_20 (1 << 20) 1720dbe28b3SPyun YongHyeon #define BIT_19 (1 << 19) 1730dbe28b3SPyun YongHyeon #define BIT_18 (1 << 18) 1740dbe28b3SPyun YongHyeon #define BIT_17 (1 << 17) 1750dbe28b3SPyun YongHyeon #define BIT_16 (1 << 16) 1760dbe28b3SPyun YongHyeon #define BIT_15 (1 << 15) 1770dbe28b3SPyun YongHyeon #define BIT_14 (1 << 14) 1780dbe28b3SPyun YongHyeon #define BIT_13 (1 << 13) 1790dbe28b3SPyun YongHyeon #define BIT_12 (1 << 12) 1800dbe28b3SPyun YongHyeon #define BIT_11 (1 << 11) 1810dbe28b3SPyun YongHyeon #define BIT_10 (1 << 10) 1820dbe28b3SPyun YongHyeon #define BIT_9 (1 << 9) 1830dbe28b3SPyun YongHyeon #define BIT_8 (1 << 8) 1840dbe28b3SPyun YongHyeon #define BIT_7 (1 << 7) 1850dbe28b3SPyun YongHyeon #define BIT_6 (1 << 6) 1860dbe28b3SPyun YongHyeon #define BIT_5 (1 << 5) 1870dbe28b3SPyun YongHyeon #define BIT_4 (1 << 4) 1880dbe28b3SPyun YongHyeon #define BIT_3 (1 << 3) 1890dbe28b3SPyun YongHyeon #define BIT_2 (1 << 2) 1900dbe28b3SPyun YongHyeon #define BIT_1 (1 << 1) 1910dbe28b3SPyun YongHyeon #define BIT_0 (1 << 0) 1920dbe28b3SPyun YongHyeon 1930dbe28b3SPyun YongHyeon #define SHIFT31(x) ((x) << 31) 1940dbe28b3SPyun YongHyeon #define SHIFT30(x) ((x) << 30) 1950dbe28b3SPyun YongHyeon #define SHIFT29(x) ((x) << 29) 1960dbe28b3SPyun YongHyeon #define SHIFT28(x) ((x) << 28) 1970dbe28b3SPyun YongHyeon #define SHIFT27(x) ((x) << 27) 1980dbe28b3SPyun YongHyeon #define SHIFT26(x) ((x) << 26) 1990dbe28b3SPyun YongHyeon #define SHIFT25(x) ((x) << 25) 2000dbe28b3SPyun YongHyeon #define SHIFT24(x) ((x) << 24) 2010dbe28b3SPyun YongHyeon #define SHIFT23(x) ((x) << 23) 2020dbe28b3SPyun YongHyeon #define SHIFT22(x) ((x) << 22) 2030dbe28b3SPyun YongHyeon #define SHIFT21(x) ((x) << 21) 2040dbe28b3SPyun YongHyeon #define SHIFT20(x) ((x) << 20) 2050dbe28b3SPyun YongHyeon #define SHIFT19(x) ((x) << 19) 2060dbe28b3SPyun YongHyeon #define SHIFT18(x) ((x) << 18) 2070dbe28b3SPyun YongHyeon #define SHIFT17(x) ((x) << 17) 2080dbe28b3SPyun YongHyeon #define SHIFT16(x) ((x) << 16) 2090dbe28b3SPyun YongHyeon #define SHIFT15(x) ((x) << 15) 2100dbe28b3SPyun YongHyeon #define SHIFT14(x) ((x) << 14) 2110dbe28b3SPyun YongHyeon #define SHIFT13(x) ((x) << 13) 2120dbe28b3SPyun YongHyeon #define SHIFT12(x) ((x) << 12) 2130dbe28b3SPyun YongHyeon #define SHIFT11(x) ((x) << 11) 2140dbe28b3SPyun YongHyeon #define SHIFT10(x) ((x) << 10) 2150dbe28b3SPyun YongHyeon #define SHIFT9(x) ((x) << 9) 2160dbe28b3SPyun YongHyeon #define SHIFT8(x) ((x) << 8) 2170dbe28b3SPyun YongHyeon #define SHIFT7(x) ((x) << 7) 2180dbe28b3SPyun YongHyeon #define SHIFT6(x) ((x) << 6) 2190dbe28b3SPyun YongHyeon #define SHIFT5(x) ((x) << 5) 2200dbe28b3SPyun YongHyeon #define SHIFT4(x) ((x) << 4) 2210dbe28b3SPyun YongHyeon #define SHIFT3(x) ((x) << 3) 2220dbe28b3SPyun YongHyeon #define SHIFT2(x) ((x) << 2) 2230dbe28b3SPyun YongHyeon #define SHIFT1(x) ((x) << 1) 2240dbe28b3SPyun YongHyeon #define SHIFT0(x) ((x) << 0) 2250dbe28b3SPyun YongHyeon 2260dbe28b3SPyun YongHyeon /* 2270dbe28b3SPyun YongHyeon * PCI Configuration Space header 2280dbe28b3SPyun YongHyeon */ 2290dbe28b3SPyun YongHyeon #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ 2300dbe28b3SPyun YongHyeon #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ 2310dbe28b3SPyun YongHyeon #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ 2320dbe28b3SPyun YongHyeon #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ 2330dbe28b3SPyun YongHyeon #define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */ 2340dbe28b3SPyun YongHyeon #define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */ 2350dbe28b3SPyun YongHyeon #define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */ 2360dbe28b3SPyun YongHyeon #define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */ 237daf29227SPyun YongHyeon #define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */ 238daf29227SPyun YongHyeon #define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */ 2390dbe28b3SPyun YongHyeon 2400dbe28b3SPyun YongHyeon /* PCI Express Capability */ 2410dbe28b3SPyun YongHyeon #define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */ 2420dbe28b3SPyun YongHyeon #define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */ 2430dbe28b3SPyun YongHyeon #define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */ 2440dbe28b3SPyun YongHyeon #define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */ 2450dbe28b3SPyun YongHyeon #define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */ 2460dbe28b3SPyun YongHyeon #define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */ 2470dbe28b3SPyun YongHyeon #define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */ 2480dbe28b3SPyun YongHyeon #define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */ 2490dbe28b3SPyun YongHyeon #define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */ 2500dbe28b3SPyun YongHyeon 2510dbe28b3SPyun YongHyeon /* PCI Express Extended Capabilities */ 2520dbe28b3SPyun YongHyeon #define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */ 2530dbe28b3SPyun YongHyeon #define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */ 2540dbe28b3SPyun YongHyeon #define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */ 2550dbe28b3SPyun YongHyeon #define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */ 2560dbe28b3SPyun YongHyeon #define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */ 2570dbe28b3SPyun YongHyeon #define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */ 2580dbe28b3SPyun YongHyeon #define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */ 2590dbe28b3SPyun YongHyeon #define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */ 2600dbe28b3SPyun YongHyeon 2610dbe28b3SPyun YongHyeon /* PCI_OUR_REG_1 32 bit Our Register 1 */ 2620dbe28b3SPyun YongHyeon #define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */ 2630dbe28b3SPyun YongHyeon #define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */ 2640dbe28b3SPyun YongHyeon #define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */ 2650dbe28b3SPyun YongHyeon #define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */ 2660dbe28b3SPyun YongHyeon #define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */ 2670dbe28b3SPyun YongHyeon #define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */ 2680dbe28b3SPyun YongHyeon #define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ 2690dbe28b3SPyun YongHyeon #define PCI_EN_IO BIT_23 /* Mapping to I/O space */ 2700dbe28b3SPyun YongHyeon #define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ 2710dbe28b3SPyun YongHyeon /* 1 = Map Flash to memory */ 2720dbe28b3SPyun YongHyeon /* 0 = Disable addr. dec */ 2730dbe28b3SPyun YongHyeon #define PCI_PAGESIZE (3L<<20)/* Bit 21..20: FLASH Page Size */ 2740dbe28b3SPyun YongHyeon #define PCI_PAGE_16 (0L<<20)/* 16 k pages */ 2750dbe28b3SPyun YongHyeon #define PCI_PAGE_32K (1L<<20)/* 32 k pages */ 2760dbe28b3SPyun YongHyeon #define PCI_PAGE_64K (2L<<20)/* 64 k pages */ 2770dbe28b3SPyun YongHyeon #define PCI_PAGE_128K (3L<<20)/* 128 k pages */ 2780dbe28b3SPyun YongHyeon #define PCI_PAGEREG (7L<<16)/* Bit 18..16: Page Register */ 2790dbe28b3SPyun YongHyeon #define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */ 2800dbe28b3SPyun YongHyeon #define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ 2810dbe28b3SPyun YongHyeon #define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ 2820dbe28b3SPyun YongHyeon #define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ 2830dbe28b3SPyun YongHyeon #define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */ 2840dbe28b3SPyun YongHyeon #define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */ 2850dbe28b3SPyun YongHyeon #define PCI_BURST_DIS BIT_9 /* Burst Disable */ 2860dbe28b3SPyun YongHyeon #define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */ 2870dbe28b3SPyun YongHyeon #define PCI_SKEW_DAS (0xfL<<4)/* Bit 7.. 4: Skew Ctrl, DAS Ext */ 2880dbe28b3SPyun YongHyeon #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ 2890dbe28b3SPyun YongHyeon #define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */ 2900dbe28b3SPyun YongHyeon 2910dbe28b3SPyun YongHyeon /* PCI_OUR_REG_2 32 bit Our Register 2 */ 2920dbe28b3SPyun YongHyeon #define PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */ 2930dbe28b3SPyun YongHyeon #define PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */ 2940dbe28b3SPyun YongHyeon #define PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */ 2950dbe28b3SPyun YongHyeon /* Bit 13..12: reserved */ 2960dbe28b3SPyun YongHyeon #define PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ 2970dbe28b3SPyun YongHyeon #define PCI_PATCH_DIR_3 BIT_11 2980dbe28b3SPyun YongHyeon #define PCI_PATCH_DIR_2 BIT_10 2990dbe28b3SPyun YongHyeon #define PCI_PATCH_DIR_1 BIT_9 3000dbe28b3SPyun YongHyeon #define PCI_PATCH_DIR_0 BIT_8 3010dbe28b3SPyun YongHyeon #define PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */ 3020dbe28b3SPyun YongHyeon #define PCI_EXT_PATCH_3 BIT_7 3030dbe28b3SPyun YongHyeon #define PCI_EXT_PATCH_2 BIT_6 3040dbe28b3SPyun YongHyeon #define PCI_EXT_PATCH_1 BIT_5 3050dbe28b3SPyun YongHyeon #define PCI_EXT_PATCH_0 BIT_4 3060dbe28b3SPyun YongHyeon #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ 3070dbe28b3SPyun YongHyeon #define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ 3080dbe28b3SPyun YongHyeon #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ 3090dbe28b3SPyun YongHyeon 3100dbe28b3SPyun YongHyeon /* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */ 3110dbe28b3SPyun YongHyeon #define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */ 3120dbe28b3SPyun YongHyeon #define PCI_OS_PCIX BIT_30 /* PCI-X Bus */ 3130dbe28b3SPyun YongHyeon #define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */ 3140dbe28b3SPyun YongHyeon #define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */ 3150dbe28b3SPyun YongHyeon #define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */ 3160dbe28b3SPyun YongHyeon #define PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */ 3170dbe28b3SPyun YongHyeon #define PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Counters Values */ 3180dbe28b3SPyun YongHyeon #define PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Counters Values */ 3190dbe28b3SPyun YongHyeon 3200dbe28b3SPyun YongHyeon #define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */ 3210dbe28b3SPyun YongHyeon /* possible values for the speed field of the register */ 3220dbe28b3SPyun YongHyeon #define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */ 3230dbe28b3SPyun YongHyeon #define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */ 3240dbe28b3SPyun YongHyeon #define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */ 3250dbe28b3SPyun YongHyeon #define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */ 3260dbe28b3SPyun YongHyeon 327e0029a72SPyun YongHyeon /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */ 328e0029a72SPyun YongHyeon #define PCI_CLK_MACSEC_DIS BIT_17 /* Disable Clock MACSec. */ 329e0029a72SPyun YongHyeon 3300dbe28b3SPyun YongHyeon /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ 3310dbe28b3SPyun YongHyeon #define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */ 3320dbe28b3SPyun YongHyeon #define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */ 3330dbe28b3SPyun YongHyeon #define PCI_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */ 3340dbe28b3SPyun YongHyeon #define PCI_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */ 3350dbe28b3SPyun YongHyeon #define PCI_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */ 3360dbe28b3SPyun YongHyeon #define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */ 3370dbe28b3SPyun YongHyeon #define PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */ 3380dbe28b3SPyun YongHyeon #define PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */ 3390dbe28b3SPyun YongHyeon #define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */ 3400dbe28b3SPyun YongHyeon #define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */ 3410dbe28b3SPyun YongHyeon 342daf29227SPyun YongHyeon /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ 343daf29227SPyun YongHyeon /* Bit 31..27: for A3 & later */ 344daf29227SPyun YongHyeon #define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */ 345daf29227SPyun YongHyeon #define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */ 346daf29227SPyun YongHyeon #define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */ 347daf29227SPyun YongHyeon #define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */ 348daf29227SPyun YongHyeon #define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */ 349daf29227SPyun YongHyeon #define PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27) 350daf29227SPyun YongHyeon /* Bit 26..16: Release Clock on Event */ 351daf29227SPyun YongHyeon #define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */ 352daf29227SPyun YongHyeon #define PCI_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */ 353daf29227SPyun YongHyeon #define PCI_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */ 354daf29227SPyun YongHyeon #define PCI_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */ 355daf29227SPyun YongHyeon #define PCI_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */ 356daf29227SPyun YongHyeon #define PCI_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */ 357daf29227SPyun YongHyeon #define PCI_REL_PME_ASSERTED BIT_20 /* PME Asserted */ 358daf29227SPyun YongHyeon #define PCI_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */ 359daf29227SPyun YongHyeon #define PCI_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */ 360daf29227SPyun YongHyeon #define PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */ 361daf29227SPyun YongHyeon #define PCI_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */ 362daf29227SPyun YongHyeon /* Bit 10.. 0: Mask for Gate Clock */ 363daf29227SPyun YongHyeon #define PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */ 364daf29227SPyun YongHyeon #define PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */ 365daf29227SPyun YongHyeon #define PCI_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */ 366daf29227SPyun YongHyeon #define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */ 367daf29227SPyun YongHyeon #define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */ 368daf29227SPyun YongHyeon #define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */ 369daf29227SPyun YongHyeon #define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */ 370daf29227SPyun YongHyeon #define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */ 371daf29227SPyun YongHyeon #define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */ 372daf29227SPyun YongHyeon #define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */ 373daf29227SPyun YongHyeon #define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */ 374daf29227SPyun YongHyeon 375daf29227SPyun YongHyeon /* PCI_CFG_REG_1 32 bit Config Register 1 */ 376daf29227SPyun YongHyeon #define PCI_CF1_DIS_REL_EVT_RST BIT_24 /* Dis. Rel. Event during PCIE reset */ 377daf29227SPyun YongHyeon /* Bit 23..21: Release Clock on Event */ 378daf29227SPyun YongHyeon #define PCI_CF1_REL_LDR_NOT_FIN BIT_23 /* EEPROM Loader Not Finished */ 379daf29227SPyun YongHyeon #define PCI_CF1_REL_VMAIN_AVLBL BIT_22 /* Vmain available */ 380daf29227SPyun YongHyeon #define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */ 381daf29227SPyun YongHyeon /* Bit 20..18: Gate Clock on Event */ 382daf29227SPyun YongHyeon #define PCI_CF1_GAT_LDR_NOT_FIN BIT_20 /* EEPROM Loader Finished */ 383daf29227SPyun YongHyeon #define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */ 384daf29227SPyun YongHyeon #define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */ 385daf29227SPyun YongHyeon #define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */ 386daf29227SPyun YongHyeon #define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */ 387daf29227SPyun YongHyeon 388daf29227SPyun YongHyeon #define PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */ 389daf29227SPyun YongHyeon #define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */ 390daf29227SPyun YongHyeon #define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */ 391daf29227SPyun YongHyeon 3920dbe28b3SPyun YongHyeon /* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */ 3930dbe28b3SPyun YongHyeon #define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */ 3940dbe28b3SPyun YongHyeon #define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */ 3950dbe28b3SPyun YongHyeon #define PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */ 3960dbe28b3SPyun YongHyeon #define PEX_DC_EN_PHANTOM BIT_9 /* Enable Phantom Functions */ 3970dbe28b3SPyun YongHyeon #define PEX_DC_EN_EXT_TAG BIT_8 /* Enable Extended Tag Field */ 3980dbe28b3SPyun YongHyeon #define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */ 3990dbe28b3SPyun YongHyeon #define PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */ 4000dbe28b3SPyun YongHyeon #define PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */ 4010dbe28b3SPyun YongHyeon #define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */ 4020dbe28b3SPyun YongHyeon #define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */ 4030dbe28b3SPyun YongHyeon #define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */ 4040dbe28b3SPyun YongHyeon 4050dbe28b3SPyun YongHyeon #define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK) 4060dbe28b3SPyun YongHyeon 4070dbe28b3SPyun YongHyeon /* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */ 4080dbe28b3SPyun YongHyeon #define PEX_LS_SLOT_CLK_CFG BIT_12 /* Slot Clock Config */ 4090dbe28b3SPyun YongHyeon #define PEX_LS_LINK_TRAIN BIT_11 /* Link Training */ 4100dbe28b3SPyun YongHyeon #define PEX_LS_TRAIN_ERROR BIT_10 /* Training Error */ 4110dbe28b3SPyun YongHyeon #define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */ 4120dbe28b3SPyun YongHyeon #define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */ 4130dbe28b3SPyun YongHyeon 4140dbe28b3SPyun YongHyeon /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */ 4150dbe28b3SPyun YongHyeon #define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */ 4160dbe28b3SPyun YongHyeon #define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */ 4170dbe28b3SPyun YongHyeon #define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */ 4180dbe28b3SPyun YongHyeon #define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */ 4190dbe28b3SPyun YongHyeon #define PEX_COMP_TO BIT_14 /* Completion Timeout */ 4200dbe28b3SPyun YongHyeon #define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */ 4210dbe28b3SPyun YongHyeon #define PEX_POIS_TLP BIT_12 /* Poisoned TLP */ 4220dbe28b3SPyun YongHyeon #define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */ 4230dbe28b3SPyun YongHyeon 4240dbe28b3SPyun YongHyeon #define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P) 4250dbe28b3SPyun YongHyeon 4260dbe28b3SPyun YongHyeon /* Control Register File (Address Map) */ 4270dbe28b3SPyun YongHyeon 4280dbe28b3SPyun YongHyeon /* 4290dbe28b3SPyun YongHyeon * Bank 0 4300dbe28b3SPyun YongHyeon */ 4310dbe28b3SPyun YongHyeon #define B0_RAP 0x0000 /* 8 bit Register Address Port */ 4320dbe28b3SPyun YongHyeon #define B0_CTST 0x0004 /* 16 bit Control/Status register */ 4330dbe28b3SPyun YongHyeon #define B0_LED 0x0006 /* 8 Bit LED register */ 4340dbe28b3SPyun YongHyeon #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */ 4350dbe28b3SPyun YongHyeon #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */ 4360dbe28b3SPyun YongHyeon #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ 4370dbe28b3SPyun YongHyeon #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ 4380dbe28b3SPyun YongHyeon #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ 4390dbe28b3SPyun YongHyeon #define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */ 4400dbe28b3SPyun YongHyeon 4410dbe28b3SPyun YongHyeon /* Special ISR registers (Yukon-2 only) */ 4420dbe28b3SPyun YongHyeon #define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */ 4430dbe28b3SPyun YongHyeon #define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */ 4440dbe28b3SPyun YongHyeon #define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */ 4450dbe28b3SPyun YongHyeon #define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */ 4460dbe28b3SPyun YongHyeon #define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */ 4470dbe28b3SPyun YongHyeon 4480dbe28b3SPyun YongHyeon /* 4490dbe28b3SPyun YongHyeon * Bank 1 4500dbe28b3SPyun YongHyeon * - completely empty (this is the RAP Block window) 4510dbe28b3SPyun YongHyeon * Note: if RAP = 1 this page is reserved 4520dbe28b3SPyun YongHyeon */ 4530dbe28b3SPyun YongHyeon 4540dbe28b3SPyun YongHyeon /* 4550dbe28b3SPyun YongHyeon * Bank 2 4560dbe28b3SPyun YongHyeon */ 4570dbe28b3SPyun YongHyeon /* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */ 4580dbe28b3SPyun YongHyeon #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */ 4590dbe28b3SPyun YongHyeon #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */ 4600dbe28b3SPyun YongHyeon #define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */ 4610dbe28b3SPyun YongHyeon #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */ 4620dbe28b3SPyun YongHyeon #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ 4630dbe28b3SPyun YongHyeon #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ 4640dbe28b3SPyun YongHyeon #define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ 4650dbe28b3SPyun YongHyeon #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ 4660dbe28b3SPyun YongHyeon #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ 4670dbe28b3SPyun YongHyeon #define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */ 4680dbe28b3SPyun YongHyeon #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ 4690dbe28b3SPyun YongHyeon #define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */ 4700dbe28b3SPyun YongHyeon #define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */ 4710dbe28b3SPyun YongHyeon #define B2_TI_VAL 0x0134 /* 32 bit Timer Value */ 4720dbe28b3SPyun YongHyeon #define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */ 4730dbe28b3SPyun YongHyeon #define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */ 4740dbe28b3SPyun YongHyeon #define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/ 4750dbe28b3SPyun YongHyeon #define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */ 4760dbe28b3SPyun YongHyeon #define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */ 4770dbe28b3SPyun YongHyeon #define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */ 4780dbe28b3SPyun YongHyeon #define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ 4790dbe28b3SPyun YongHyeon #define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */ 4800dbe28b3SPyun YongHyeon #define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */ 4810dbe28b3SPyun YongHyeon #define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */ 4820dbe28b3SPyun YongHyeon #define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */ 4830dbe28b3SPyun YongHyeon #define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */ 4840dbe28b3SPyun YongHyeon #define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */ 4850dbe28b3SPyun YongHyeon #define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */ 4860dbe28b3SPyun YongHyeon #define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */ 4870dbe28b3SPyun YongHyeon 4880dbe28b3SPyun YongHyeon #define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */ 4890dbe28b3SPyun YongHyeon #define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */ 4900dbe28b3SPyun YongHyeon 4910dbe28b3SPyun YongHyeon /* 4920dbe28b3SPyun YongHyeon * Bank 3 4930dbe28b3SPyun YongHyeon */ 4940dbe28b3SPyun YongHyeon /* RAM Random Registers */ 4950dbe28b3SPyun YongHyeon #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ 4960dbe28b3SPyun YongHyeon #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ 4970dbe28b3SPyun YongHyeon #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ 4980dbe28b3SPyun YongHyeon 4990dbe28b3SPyun YongHyeon #define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */ 5000dbe28b3SPyun YongHyeon 5010dbe28b3SPyun YongHyeon /* RAM Interface Registers */ 5020dbe28b3SPyun YongHyeon /* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */ 5030dbe28b3SPyun YongHyeon /* 5040dbe28b3SPyun YongHyeon * The HW-Spec. calls this registers Timeout Value 0..11. But this names are 5050dbe28b3SPyun YongHyeon * not usable in SW. Please notice these are NOT real timeouts, these are 5060dbe28b3SPyun YongHyeon * the number of qWords transferred continuously. 5070dbe28b3SPyun YongHyeon */ 5080dbe28b3SPyun YongHyeon #define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */ 5090dbe28b3SPyun YongHyeon #define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */ 5100dbe28b3SPyun YongHyeon #define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */ 5110dbe28b3SPyun YongHyeon #define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */ 5120dbe28b3SPyun YongHyeon #define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */ 5130dbe28b3SPyun YongHyeon #define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */ 5140dbe28b3SPyun YongHyeon #define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */ 5150dbe28b3SPyun YongHyeon #define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */ 5160dbe28b3SPyun YongHyeon #define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */ 5170dbe28b3SPyun YongHyeon #define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */ 5180dbe28b3SPyun YongHyeon #define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/ 5190dbe28b3SPyun YongHyeon #define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/ 5200dbe28b3SPyun YongHyeon #define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */ 5210dbe28b3SPyun YongHyeon #define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */ 5220dbe28b3SPyun YongHyeon #define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */ 5230dbe28b3SPyun YongHyeon 5240dbe28b3SPyun YongHyeon /* 5250dbe28b3SPyun YongHyeon * Bank 4 - 5 5260dbe28b3SPyun YongHyeon */ 5270dbe28b3SPyun YongHyeon /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 5280dbe28b3SPyun YongHyeon #define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/ 5290dbe28b3SPyun YongHyeon #define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */ 5300dbe28b3SPyun YongHyeon #define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */ 5310dbe28b3SPyun YongHyeon #define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */ 5320dbe28b3SPyun YongHyeon #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ 5330dbe28b3SPyun YongHyeon #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ 5340dbe28b3SPyun YongHyeon #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ 5350dbe28b3SPyun YongHyeon 5360dbe28b3SPyun YongHyeon #define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs)) 5370dbe28b3SPyun YongHyeon 5380dbe28b3SPyun YongHyeon /* RSS key registers for Yukon-2 Family */ 5390dbe28b3SPyun YongHyeon #define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */ 5400dbe28b3SPyun YongHyeon /* RSS key register offsets */ 5410dbe28b3SPyun YongHyeon #define KEY_IDX_0 0 /* offset for location of KEY 0 */ 5420dbe28b3SPyun YongHyeon #define KEY_IDX_1 4 /* offset for location of KEY 1 */ 5430dbe28b3SPyun YongHyeon #define KEY_IDX_2 8 /* offset for location of KEY 2 */ 5440dbe28b3SPyun YongHyeon #define KEY_IDX_3 12 /* offset for location of KEY 3 */ 5450dbe28b3SPyun YongHyeon /* 0x0280 - 0x0292: MAC 2 */ 5460dbe28b3SPyun YongHyeon #define RSS_KEY_ADDR(Port, KeyIndex) \ 5470dbe28b3SPyun YongHyeon ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex)) 5480dbe28b3SPyun YongHyeon 5490dbe28b3SPyun YongHyeon /* 5500dbe28b3SPyun YongHyeon * Bank 8 - 15 5510dbe28b3SPyun YongHyeon */ 5520dbe28b3SPyun YongHyeon /* Receive and Transmit Queue Registers, use Q_ADDR() to access */ 5530dbe28b3SPyun YongHyeon #define B8_Q_REGS 0x0400 5540dbe28b3SPyun YongHyeon 5550dbe28b3SPyun YongHyeon /* Queue Register Offsets, use Q_ADDR() to access */ 5560dbe28b3SPyun YongHyeon #define Q_D 0x00 /* 8*32 bit Current Descriptor */ 5570dbe28b3SPyun YongHyeon #define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */ 5580dbe28b3SPyun YongHyeon #define Q_DONE 0x24 /* 16 bit Done Index */ 5590dbe28b3SPyun YongHyeon #define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */ 5600dbe28b3SPyun YongHyeon #define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */ 5610dbe28b3SPyun YongHyeon #define Q_BC 0x30 /* 32 bit Current Byte Counter */ 5620dbe28b3SPyun YongHyeon #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ 5630dbe28b3SPyun YongHyeon #define Q_F 0x38 /* 32 bit Flag Register */ 5640dbe28b3SPyun YongHyeon #define Q_T1 0x3c /* 32 bit Test Register 1 */ 5650dbe28b3SPyun YongHyeon #define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */ 5660dbe28b3SPyun YongHyeon #define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */ 5670dbe28b3SPyun YongHyeon #define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */ 5680dbe28b3SPyun YongHyeon #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ 5690dbe28b3SPyun YongHyeon #define Q_WM 0x40 /* 16 bit FIFO Watermark */ 5700dbe28b3SPyun YongHyeon #define Q_AL 0x42 /* 8 bit FIFO Alignment */ 5710dbe28b3SPyun YongHyeon #define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */ 5720dbe28b3SPyun YongHyeon #define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */ 5730dbe28b3SPyun YongHyeon #define Q_RP 0x48 /* 8 bit FIFO Read Pointer */ 5740dbe28b3SPyun YongHyeon #define Q_RL 0x4a /* 8 bit FIFO Read Level */ 5750dbe28b3SPyun YongHyeon #define Q_WP 0x4c /* 8 bit FIFO Write Pointer */ 5760dbe28b3SPyun YongHyeon #define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */ 5770dbe28b3SPyun YongHyeon #define Q_WL 0x4e /* 8 bit FIFO Write Level */ 5780dbe28b3SPyun YongHyeon #define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */ 5790dbe28b3SPyun YongHyeon 5800dbe28b3SPyun YongHyeon #define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs)) 5810dbe28b3SPyun YongHyeon 5820dbe28b3SPyun YongHyeon /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address */ 5830dbe28b3SPyun YongHyeon #define Y2_B8_PREF_REGS 0x0450 5840dbe28b3SPyun YongHyeon 5850dbe28b3SPyun YongHyeon #define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */ 5860dbe28b3SPyun YongHyeon #define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */ 5870dbe28b3SPyun YongHyeon #define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */ 5880dbe28b3SPyun YongHyeon #define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/ 5890dbe28b3SPyun YongHyeon #define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */ 5900dbe28b3SPyun YongHyeon #define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */ 5910dbe28b3SPyun YongHyeon #define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */ 5920dbe28b3SPyun YongHyeon #define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */ 5930dbe28b3SPyun YongHyeon #define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */ 5940dbe28b3SPyun YongHyeon #define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */ 5950dbe28b3SPyun YongHyeon 5960dbe28b3SPyun YongHyeon #define PREF_UNIT_MASK_IDX 0x0fff 5970dbe28b3SPyun YongHyeon 5980dbe28b3SPyun YongHyeon #define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs)) 5990dbe28b3SPyun YongHyeon 6000dbe28b3SPyun YongHyeon /* 6010dbe28b3SPyun YongHyeon * Bank 16 - 23 6020dbe28b3SPyun YongHyeon */ 6030dbe28b3SPyun YongHyeon /* RAM Buffer Registers */ 6040dbe28b3SPyun YongHyeon #define B16_RAM_REGS 0x0800 6050dbe28b3SPyun YongHyeon 6060dbe28b3SPyun YongHyeon /* RAM Buffer Register Offsets, use RB_ADDR() to access */ 6070dbe28b3SPyun YongHyeon #define RB_START 0x00 /* 32 bit RAM Buffer Start Address */ 6080dbe28b3SPyun YongHyeon #define RB_END 0x04 /* 32 bit RAM Buffer End Address */ 6090dbe28b3SPyun YongHyeon #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ 6100dbe28b3SPyun YongHyeon #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ 6110dbe28b3SPyun YongHyeon #define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */ 6120dbe28b3SPyun YongHyeon #define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */ 6130dbe28b3SPyun YongHyeon #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ 6140dbe28b3SPyun YongHyeon #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ 6150dbe28b3SPyun YongHyeon #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ 6160dbe28b3SPyun YongHyeon #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ 6170dbe28b3SPyun YongHyeon #define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ 6180dbe28b3SPyun YongHyeon #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ 6190dbe28b3SPyun YongHyeon #define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */ 6200dbe28b3SPyun YongHyeon 6210dbe28b3SPyun YongHyeon /* 6220dbe28b3SPyun YongHyeon * Bank 24 6230dbe28b3SPyun YongHyeon */ 6240dbe28b3SPyun YongHyeon /* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 6250dbe28b3SPyun YongHyeon #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ 6260dbe28b3SPyun YongHyeon #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ 6270dbe28b3SPyun YongHyeon #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ 6280dbe28b3SPyun YongHyeon #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ 6290dbe28b3SPyun YongHyeon #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ 6300dbe28b3SPyun YongHyeon #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ 631106b2e2fSPyun YongHyeon #define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ 632106b2e2fSPyun YongHyeon #define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ 6330dbe28b3SPyun YongHyeon #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ 6340dbe28b3SPyun YongHyeon #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ 6350dbe28b3SPyun YongHyeon #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ 6360dbe28b3SPyun YongHyeon #define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ 6370dbe28b3SPyun YongHyeon #define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ 6380dbe28b3SPyun YongHyeon 6390dbe28b3SPyun YongHyeon /* 6400dbe28b3SPyun YongHyeon * Bank 25 6410dbe28b3SPyun YongHyeon */ 6420dbe28b3SPyun YongHyeon /* 0x0c80 - 0x0cbf: MAC 2 */ 6430dbe28b3SPyun YongHyeon /* 0x0cc0 - 0x0cff: reserved */ 6440dbe28b3SPyun YongHyeon 6450dbe28b3SPyun YongHyeon /* 6460dbe28b3SPyun YongHyeon * Bank 26 6470dbe28b3SPyun YongHyeon */ 6480dbe28b3SPyun YongHyeon /* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 6490dbe28b3SPyun YongHyeon #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ 6500dbe28b3SPyun YongHyeon #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 6510dbe28b3SPyun YongHyeon #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ 6520dbe28b3SPyun YongHyeon #define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */ 6530dbe28b3SPyun YongHyeon #define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ 6540dbe28b3SPyun YongHyeon #define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */ 6550dbe28b3SPyun YongHyeon #define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ 6560dbe28b3SPyun YongHyeon #define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ 6570dbe28b3SPyun YongHyeon #define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ 6580dbe28b3SPyun YongHyeon #define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ 6590dbe28b3SPyun YongHyeon 6600dbe28b3SPyun YongHyeon /* 6610dbe28b3SPyun YongHyeon * Bank 27 6620dbe28b3SPyun YongHyeon */ 6630dbe28b3SPyun YongHyeon /* 0x0d80 - 0x0dbf: MAC 2 */ 6640dbe28b3SPyun YongHyeon /* 0x0daa - 0x0dff: reserved */ 6650dbe28b3SPyun YongHyeon 6660dbe28b3SPyun YongHyeon /* 6670dbe28b3SPyun YongHyeon * Bank 28 6680dbe28b3SPyun YongHyeon */ 6690dbe28b3SPyun YongHyeon /* Descriptor Poll Timer Registers */ 6700dbe28b3SPyun YongHyeon #define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */ 6710dbe28b3SPyun YongHyeon #define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */ 6720dbe28b3SPyun YongHyeon #define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */ 6730dbe28b3SPyun YongHyeon #define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */ 6740dbe28b3SPyun YongHyeon /* Time Stamp Timer Registers (YUKON only) */ 6750dbe28b3SPyun YongHyeon #define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */ 6760dbe28b3SPyun YongHyeon #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ 6770dbe28b3SPyun YongHyeon #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ 6780dbe28b3SPyun YongHyeon /* Polling Unit Registers (Yukon-2 only) */ 6790dbe28b3SPyun YongHyeon #define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */ 6800dbe28b3SPyun YongHyeon #define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */ 6810dbe28b3SPyun YongHyeon #define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */ 6820dbe28b3SPyun YongHyeon #define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */ 6830dbe28b3SPyun YongHyeon /* ASF Subsystem Registers (Yukon-2 only) */ 6840dbe28b3SPyun YongHyeon #define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */ 6850dbe28b3SPyun YongHyeon #define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */ 686fe0b141eSPyun YongHyeon #define B28_Y2_CPU_WDOG 0x0e48 /* 32 bit Watchdog Register */ 6870dbe28b3SPyun YongHyeon #define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */ 6880dbe28b3SPyun YongHyeon #define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */ 689daf29227SPyun YongHyeon #define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */ 6900dbe28b3SPyun YongHyeon #define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */ 6910dbe28b3SPyun YongHyeon #define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */ 6920dbe28b3SPyun YongHyeon #define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */ 6930dbe28b3SPyun YongHyeon #define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */ 6940dbe28b3SPyun YongHyeon #define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */ 6950dbe28b3SPyun YongHyeon 6960dbe28b3SPyun YongHyeon /* 6970dbe28b3SPyun YongHyeon * Bank 29 6980dbe28b3SPyun YongHyeon */ 6990dbe28b3SPyun YongHyeon 7000dbe28b3SPyun YongHyeon /* Status BMU Registers (Yukon-2 only)*/ 7010dbe28b3SPyun YongHyeon #define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */ 7020dbe28b3SPyun YongHyeon #define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */ 7030dbe28b3SPyun YongHyeon #define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */ 7040dbe28b3SPyun YongHyeon #define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */ 7050dbe28b3SPyun YongHyeon #define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */ 7060dbe28b3SPyun YongHyeon #define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */ 7070dbe28b3SPyun YongHyeon #define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */ 7080dbe28b3SPyun YongHyeon #define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */ 7090dbe28b3SPyun YongHyeon #define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */ 7100dbe28b3SPyun YongHyeon #define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */ 7110dbe28b3SPyun YongHyeon /* FIFO Control/Status Registers (Yukon-2 only)*/ 7120dbe28b3SPyun YongHyeon #define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */ 7130dbe28b3SPyun YongHyeon #define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */ 7140dbe28b3SPyun YongHyeon #define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */ 7150dbe28b3SPyun YongHyeon #define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */ 7160dbe28b3SPyun YongHyeon #define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */ 7170dbe28b3SPyun YongHyeon #define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */ 7180dbe28b3SPyun YongHyeon #define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */ 7190dbe28b3SPyun YongHyeon /* Level and ISR Timer Registers (Yukon-2 only)*/ 7200dbe28b3SPyun YongHyeon #define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */ 7210dbe28b3SPyun YongHyeon #define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */ 7220dbe28b3SPyun YongHyeon #define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */ 7230dbe28b3SPyun YongHyeon #define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */ 7240dbe28b3SPyun YongHyeon #define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */ 7250dbe28b3SPyun YongHyeon #define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */ 7260dbe28b3SPyun YongHyeon #define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */ 7270dbe28b3SPyun YongHyeon #define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */ 7280dbe28b3SPyun YongHyeon #define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */ 7290dbe28b3SPyun YongHyeon #define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */ 7300dbe28b3SPyun YongHyeon #define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */ 7310dbe28b3SPyun YongHyeon #define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */ 7320dbe28b3SPyun YongHyeon 7330dbe28b3SPyun YongHyeon #define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */ 7340dbe28b3SPyun YongHyeon #define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */ 7350dbe28b3SPyun YongHyeon #define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */ 7360dbe28b3SPyun YongHyeon #define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */ 7370dbe28b3SPyun YongHyeon 7380dbe28b3SPyun YongHyeon /* 7390dbe28b3SPyun YongHyeon * Bank 30 7400dbe28b3SPyun YongHyeon */ 7410dbe28b3SPyun YongHyeon /* GMAC and GPHY Control Registers (YUKON only) */ 7420dbe28b3SPyun YongHyeon #define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */ 7430dbe28b3SPyun YongHyeon #define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */ 7440dbe28b3SPyun YongHyeon #define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */ 7450dbe28b3SPyun YongHyeon #define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */ 7460dbe28b3SPyun YongHyeon #define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */ 7470dbe28b3SPyun YongHyeon 7480dbe28b3SPyun YongHyeon /* Wake-up Frame Pattern Match Control Registers (YUKON only) */ 7490dbe28b3SPyun YongHyeon 7500dbe28b3SPyun YongHyeon #define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */ 7510dbe28b3SPyun YongHyeon 7520dbe28b3SPyun YongHyeon #define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */ 7530dbe28b3SPyun YongHyeon #define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */ 7540dbe28b3SPyun YongHyeon #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ 7550dbe28b3SPyun YongHyeon #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ 7560dbe28b3SPyun YongHyeon #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ 7570dbe28b3SPyun YongHyeon #define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */ 7580dbe28b3SPyun YongHyeon #define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */ 7590dbe28b3SPyun YongHyeon #define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */ 7600dbe28b3SPyun YongHyeon 7610dbe28b3SPyun YongHyeon /* WOL Pattern Length Registers (YUKON only) */ 7620dbe28b3SPyun YongHyeon 7630dbe28b3SPyun YongHyeon #define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */ 7640dbe28b3SPyun YongHyeon #define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */ 7650dbe28b3SPyun YongHyeon 7660dbe28b3SPyun YongHyeon /* WOL Pattern Counter Registers (YUKON only) */ 7670dbe28b3SPyun YongHyeon 7680dbe28b3SPyun YongHyeon #define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */ 7690dbe28b3SPyun YongHyeon #define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */ 7700dbe28b3SPyun YongHyeon 7710dbe28b3SPyun YongHyeon /* 7720dbe28b3SPyun YongHyeon * Bank 32 - 33 7730dbe28b3SPyun YongHyeon */ 7740dbe28b3SPyun YongHyeon #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ 7750dbe28b3SPyun YongHyeon #define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */ 7760dbe28b3SPyun YongHyeon 7770dbe28b3SPyun YongHyeon /* offset to configuration space on Yukon-2 */ 7780dbe28b3SPyun YongHyeon #define Y2_CFG_SPC 0x1c00 7790dbe28b3SPyun YongHyeon #define BASE_GMAC_1 0x2800 /* GMAC 1 registers */ 7800dbe28b3SPyun YongHyeon #define BASE_GMAC_2 0x3800 /* GMAC 2 registers */ 7810dbe28b3SPyun YongHyeon 7820dbe28b3SPyun YongHyeon /* 7830dbe28b3SPyun YongHyeon * Control Register Bit Definitions: 7840dbe28b3SPyun YongHyeon */ 7850dbe28b3SPyun YongHyeon /* B0_CTST 24 bit Control/Status register */ 7860dbe28b3SPyun YongHyeon #define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */ 7870dbe28b3SPyun YongHyeon #define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */ 7880dbe28b3SPyun YongHyeon #define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */ 7890dbe28b3SPyun YongHyeon #define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */ 7900dbe28b3SPyun YongHyeon #define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */ 7910dbe28b3SPyun YongHyeon #define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */ 7920dbe28b3SPyun YongHyeon #define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */ 7930dbe28b3SPyun YongHyeon #define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */ 7940dbe28b3SPyun YongHyeon #define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */ 7950dbe28b3SPyun YongHyeon #define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */ 7960dbe28b3SPyun YongHyeon #define CS_ST_SW_IRQ BIT_7 /* Set IRQ SW Request */ 7970dbe28b3SPyun YongHyeon #define CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */ 7980dbe28b3SPyun YongHyeon #define CS_STOP_DONE BIT_5 /* Stop Master is finished */ 7990dbe28b3SPyun YongHyeon #define CS_STOP_MAST BIT_4 /* Command Bit to stop the master */ 8000dbe28b3SPyun YongHyeon #define CS_MRST_CLR BIT_3 /* Clear Master Reset */ 8010dbe28b3SPyun YongHyeon #define CS_MRST_SET BIT_2 /* Set Master Reset */ 8020dbe28b3SPyun YongHyeon #define CS_RST_CLR BIT_1 /* Clear Software Reset */ 8030dbe28b3SPyun YongHyeon #define CS_RST_SET BIT_0 /* Set Software Reset */ 8040dbe28b3SPyun YongHyeon 8050dbe28b3SPyun YongHyeon #define LED_STAT_ON BIT_1 /* Status LED On */ 8060dbe28b3SPyun YongHyeon #define LED_STAT_OFF BIT_0 /* Status LED Off */ 8070dbe28b3SPyun YongHyeon 8080dbe28b3SPyun YongHyeon /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ 8090dbe28b3SPyun YongHyeon #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ 8100dbe28b3SPyun YongHyeon #define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ 8110dbe28b3SPyun YongHyeon #define PC_VCC_ENA BIT_5 /* Switch VCC Enable */ 8120dbe28b3SPyun YongHyeon #define PC_VCC_DIS BIT_4 /* Switch VCC Disable */ 8130dbe28b3SPyun YongHyeon #define PC_VAUX_ON BIT_3 /* Switch VAUX On */ 8140dbe28b3SPyun YongHyeon #define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ 8150dbe28b3SPyun YongHyeon #define PC_VCC_ON BIT_1 /* Switch VCC On */ 8160dbe28b3SPyun YongHyeon #define PC_VCC_OFF BIT_0 /* Switch VCC Off */ 8170dbe28b3SPyun YongHyeon 8180dbe28b3SPyun YongHyeon /* B0_ISRC 32 bit Interrupt Source Register */ 8190dbe28b3SPyun YongHyeon /* B0_IMSK 32 bit Interrupt Mask Register */ 8200dbe28b3SPyun YongHyeon /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ 8210dbe28b3SPyun YongHyeon /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ 8220dbe28b3SPyun YongHyeon /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ 8230dbe28b3SPyun YongHyeon /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ 8240dbe28b3SPyun YongHyeon /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ 8250dbe28b3SPyun YongHyeon /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ 8260dbe28b3SPyun YongHyeon #define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8)) 8270dbe28b3SPyun YongHyeon #define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */ 8280dbe28b3SPyun YongHyeon #define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */ 8290dbe28b3SPyun YongHyeon #define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */ 8300dbe28b3SPyun YongHyeon #define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */ 8310dbe28b3SPyun YongHyeon #define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */ 8320dbe28b3SPyun YongHyeon #define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */ 8330dbe28b3SPyun YongHyeon #define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */ 8340dbe28b3SPyun YongHyeon #define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */ 8350dbe28b3SPyun YongHyeon #define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */ 8360dbe28b3SPyun YongHyeon #define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */ 8370dbe28b3SPyun YongHyeon #define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */ 8380dbe28b3SPyun YongHyeon #define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */ 839e19bd6eeSPyun YongHyeon #define Y2_IS_PSM_ACK BIT_7 /* PSM Ack (Yukon Optima) */ 840e19bd6eeSPyun YongHyeon #define Y2_IS_PTP_TIST BIT_6 /* PTP TIme Stamp (Yukon Optima) */ 841e19bd6eeSPyun YongHyeon #define Y2_IS_PHY_QLNK BIT_5 /* PHY Quick Link (Yukon Optima) */ 8420dbe28b3SPyun YongHyeon #define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */ 8430dbe28b3SPyun YongHyeon #define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */ 8440dbe28b3SPyun YongHyeon #define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */ 8450dbe28b3SPyun YongHyeon #define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */ 8460dbe28b3SPyun YongHyeon #define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */ 8470dbe28b3SPyun YongHyeon 8480dbe28b3SPyun YongHyeon #define Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */ 8490dbe28b3SPyun YongHyeon 8500dbe28b3SPyun YongHyeon #define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */ 8510dbe28b3SPyun YongHyeon 8520dbe28b3SPyun YongHyeon #define Y2_IS_ALL_MSK 0xef001f1f /* All Interrupt bits */ 8530dbe28b3SPyun YongHyeon 8540dbe28b3SPyun YongHyeon #define Y2_IS_PORT_A \ 8550dbe28b3SPyun YongHyeon (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1) 8560dbe28b3SPyun YongHyeon #define Y2_IS_PORT_B \ 8570dbe28b3SPyun YongHyeon (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2) 8580dbe28b3SPyun YongHyeon 8590dbe28b3SPyun YongHyeon /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ 8600dbe28b3SPyun YongHyeon /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ 8610dbe28b3SPyun YongHyeon /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ 8620dbe28b3SPyun YongHyeon #define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */ 8630dbe28b3SPyun YongHyeon #define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */ 8640dbe28b3SPyun YongHyeon #define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */ 8650dbe28b3SPyun YongHyeon #define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */ 8660dbe28b3SPyun YongHyeon #define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */ 8670dbe28b3SPyun YongHyeon #define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */ 8680dbe28b3SPyun YongHyeon #define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */ 8690dbe28b3SPyun YongHyeon #define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */ 8700dbe28b3SPyun YongHyeon #define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */ 8710dbe28b3SPyun YongHyeon #define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */ 8720dbe28b3SPyun YongHyeon #define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */ 8730dbe28b3SPyun YongHyeon #define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */ 8740dbe28b3SPyun YongHyeon #define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */ 8750dbe28b3SPyun YongHyeon #define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */ 8760dbe28b3SPyun YongHyeon #define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */ 8770dbe28b3SPyun YongHyeon #define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */ 8780dbe28b3SPyun YongHyeon #define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */ 8790dbe28b3SPyun YongHyeon #define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */ 8800dbe28b3SPyun YongHyeon 8810dbe28b3SPyun YongHyeon #define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\ 8820dbe28b3SPyun YongHyeon Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1) 8830dbe28b3SPyun YongHyeon #define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\ 8840dbe28b3SPyun YongHyeon Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2) 8850dbe28b3SPyun YongHyeon 8860dbe28b3SPyun YongHyeon #define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\ 8870dbe28b3SPyun YongHyeon Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |\ 8880dbe28b3SPyun YongHyeon Y2_HWE_L1_MASK | Y2_HWE_L2_MASK) 8890dbe28b3SPyun YongHyeon 8900dbe28b3SPyun YongHyeon /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ 8910dbe28b3SPyun YongHyeon #define CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */ 8920dbe28b3SPyun YongHyeon #define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */ 8930dbe28b3SPyun YongHyeon #define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */ 8940dbe28b3SPyun YongHyeon 8950dbe28b3SPyun YongHyeon /* B2_CHIP_ID 8 bit Chip Identification Number */ 8960dbe28b3SPyun YongHyeon #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ 8970dbe28b3SPyun YongHyeon #define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ 8980dbe28b3SPyun YongHyeon #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */ 8990dbe28b3SPyun YongHyeon #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */ 9000dbe28b3SPyun YongHyeon #define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */ 9010dbe28b3SPyun YongHyeon #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */ 902daf29227SPyun YongHyeon #define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */ 9030dbe28b3SPyun YongHyeon #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ 9040dbe28b3SPyun YongHyeon #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ 90561708f4cSPyun YongHyeon #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */ 90676202a16SPyun YongHyeon #define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */ 90776202a16SPyun YongHyeon #define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */ 908e19bd6eeSPyun YongHyeon #define CHIP_ID_YUKON_UNKNOWN 0xbb 909e19bd6eeSPyun YongHyeon #define CHIP_ID_YUKON_OPT 0xbc /* Chip ID for YUKON-2 Optima */ 9100dbe28b3SPyun YongHyeon 9110dbe28b3SPyun YongHyeon #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ 9120dbe28b3SPyun YongHyeon #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ 9130dbe28b3SPyun YongHyeon #define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */ 9140dbe28b3SPyun YongHyeon #define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */ 9150dbe28b3SPyun YongHyeon 9160dbe28b3SPyun YongHyeon #define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */ 9170dbe28b3SPyun YongHyeon #define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */ 9180dbe28b3SPyun YongHyeon #define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */ 9190dbe28b3SPyun YongHyeon 920a109c74fSPyun YongHyeon #define CHIP_REV_YU_EC_U_A0 1 921a109c74fSPyun YongHyeon #define CHIP_REV_YU_EC_U_A1 2 9220dbe28b3SPyun YongHyeon 92361708f4cSPyun YongHyeon #define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */ 92461708f4cSPyun YongHyeon 925daf29227SPyun YongHyeon #define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */ 926daf29227SPyun YongHyeon #define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */ 927daf29227SPyun YongHyeon 928e0029a72SPyun YongHyeon #define CHIP_REV_YU_SU_A0 0 /* Chip Rev. for Yukon-2 SUPR A0 */ 929e0029a72SPyun YongHyeon #define CHIP_REV_YU_SU_B0 1 /* Chip Rev. for Yukon-2 SUPR B0 */ 930e0029a72SPyun YongHyeon #define CHIP_REV_YU_SU_B1 3 /* Chip Rev. for Yukon-2 SUPR B1 */ 931e0029a72SPyun YongHyeon 9320dbe28b3SPyun YongHyeon /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 9330dbe28b3SPyun YongHyeon #define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */ 9340dbe28b3SPyun YongHyeon #define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */ 9350dbe28b3SPyun YongHyeon #define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */ 9360dbe28b3SPyun YongHyeon #define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */ 9370dbe28b3SPyun YongHyeon #define Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */ 9380dbe28b3SPyun YongHyeon #define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */ 9390dbe28b3SPyun YongHyeon #define Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */ 9400dbe28b3SPyun YongHyeon #define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */ 9410dbe28b3SPyun YongHyeon 9420dbe28b3SPyun YongHyeon /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ 9430dbe28b3SPyun YongHyeon #define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */ 9440dbe28b3SPyun YongHyeon #define CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */ 9450dbe28b3SPyun YongHyeon #define CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */ 9460dbe28b3SPyun YongHyeon 9470dbe28b3SPyun YongHyeon #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) 9480dbe28b3SPyun YongHyeon #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) 9490dbe28b3SPyun YongHyeon 9500dbe28b3SPyun YongHyeon /* B2_E_3 8 bit lower 4 bits used for HW self test result */ 9510dbe28b3SPyun YongHyeon #define B2_E3_RES_MASK 0x0f 9520dbe28b3SPyun YongHyeon 9530dbe28b3SPyun YongHyeon /* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */ 9540dbe28b3SPyun YongHyeon /* Yukon-EC/FE */ 9550dbe28b3SPyun YongHyeon #define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */ 9560dbe28b3SPyun YongHyeon #define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK) 9570dbe28b3SPyun YongHyeon /* Yukon-2 */ 9580dbe28b3SPyun YongHyeon #define Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */ 9590dbe28b3SPyun YongHyeon #define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */ 9600dbe28b3SPyun YongHyeon #define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK) 9610dbe28b3SPyun YongHyeon #define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK) 9620dbe28b3SPyun YongHyeon #define Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */ 9630dbe28b3SPyun YongHyeon #define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */ 9640dbe28b3SPyun YongHyeon 9650dbe28b3SPyun YongHyeon /* B2_TI_CTRL 8 bit Timer control */ 9660dbe28b3SPyun YongHyeon /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ 9670dbe28b3SPyun YongHyeon #define TIM_START BIT_2 /* Start Timer */ 9680dbe28b3SPyun YongHyeon #define TIM_STOP BIT_1 /* Stop Timer */ 9690dbe28b3SPyun YongHyeon #define TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */ 9700dbe28b3SPyun YongHyeon 9710dbe28b3SPyun YongHyeon /* B2_TI_TEST 8 Bit Timer Test */ 9720dbe28b3SPyun YongHyeon /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ 9730dbe28b3SPyun YongHyeon /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ 9740dbe28b3SPyun YongHyeon #define TIM_T_ON BIT_2 /* Test mode on */ 9750dbe28b3SPyun YongHyeon #define TIM_T_OFF BIT_1 /* Test mode off */ 9760dbe28b3SPyun YongHyeon #define TIM_T_STEP BIT_0 /* Test step */ 9770dbe28b3SPyun YongHyeon 9780dbe28b3SPyun YongHyeon /* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */ 9790dbe28b3SPyun YongHyeon /* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */ 9800dbe28b3SPyun YongHyeon #define DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */ 9810dbe28b3SPyun YongHyeon 9820dbe28b3SPyun YongHyeon /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ 9830dbe28b3SPyun YongHyeon #define DPT_START BIT_1 /* Start Descriptor Poll Timer */ 9840dbe28b3SPyun YongHyeon #define DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */ 9850dbe28b3SPyun YongHyeon 9860dbe28b3SPyun YongHyeon /* B2_TST_CTRL1 8 bit Test Control Register 1 */ 9870dbe28b3SPyun YongHyeon #define TST_FRC_DPERR_MR BIT_7 /* force DATAPERR on MST RD */ 9880dbe28b3SPyun YongHyeon #define TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */ 9890dbe28b3SPyun YongHyeon #define TST_FRC_DPERR_TR BIT_5 /* force DATAPERR on TRG RD */ 9900dbe28b3SPyun YongHyeon #define TST_FRC_DPERR_TW BIT_4 /* force DATAPERR on TRG WR */ 9910dbe28b3SPyun YongHyeon #define TST_FRC_APERR_M BIT_3 /* force ADDRPERR on MST */ 9920dbe28b3SPyun YongHyeon #define TST_FRC_APERR_T BIT_2 /* force ADDRPERR on TRG */ 9930dbe28b3SPyun YongHyeon #define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */ 9940dbe28b3SPyun YongHyeon #define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */ 9950dbe28b3SPyun YongHyeon 996daf29227SPyun YongHyeon /* B2_GP_IO */ 997daf29227SPyun YongHyeon #define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */ 998daf29227SPyun YongHyeon #define GLB_GPIO_CLK_DBG_MSK 0x3c000000 /* Clock Debug */ 999daf29227SPyun YongHyeon 1000daf29227SPyun YongHyeon #define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */ 1001daf29227SPyun YongHyeon #define GLB_GPIO_LED_PAD_SPEED_UP BIT_14 /* LED PAD Speed Up */ 1002daf29227SPyun YongHyeon #define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */ 1003daf29227SPyun YongHyeon #define GLB_GPIO_TEST_SEL_MSK 0x00001800 /* Testmode Select */ 1004daf29227SPyun YongHyeon #define GLB_GPIO_TEST_SEL_BASE BIT_11 1005daf29227SPyun YongHyeon #define GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */ 1006daf29227SPyun YongHyeon #define GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */ 1007daf29227SPyun YongHyeon 10080dbe28b3SPyun YongHyeon /* B2_I2C_CTRL 32 bit I2C HW Control Register */ 10090dbe28b3SPyun YongHyeon #define I2C_FLAG BIT_31 /* Start read/write if WR */ 10100dbe28b3SPyun YongHyeon #define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */ 10110dbe28b3SPyun YongHyeon #define I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */ 10120dbe28b3SPyun YongHyeon #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ 10130dbe28b3SPyun YongHyeon #define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */ 10140dbe28b3SPyun YongHyeon #define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */ 10150dbe28b3SPyun YongHyeon #define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */ 10160dbe28b3SPyun YongHyeon #define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */ 10170dbe28b3SPyun YongHyeon #define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */ 10180dbe28b3SPyun YongHyeon #define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */ 10190dbe28b3SPyun YongHyeon #define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */ 10200dbe28b3SPyun YongHyeon #define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */ 10210dbe28b3SPyun YongHyeon #define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */ 10220dbe28b3SPyun YongHyeon #define I2C_STOP BIT_0 /* Interrupt I2C transfer */ 10230dbe28b3SPyun YongHyeon 10240dbe28b3SPyun YongHyeon /* B2_I2C_IRQ 32 bit I2C HW IRQ Register */ 10250dbe28b3SPyun YongHyeon #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ 10260dbe28b3SPyun YongHyeon 10270dbe28b3SPyun YongHyeon /* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */ 10280dbe28b3SPyun YongHyeon #define I2C_DATA_DIR BIT_2 /* direction of I2C_DATA */ 10290dbe28b3SPyun YongHyeon #define I2C_DATA BIT_1 /* I2C Data Port */ 10300dbe28b3SPyun YongHyeon #define I2C_CLK BIT_0 /* I2C Clock Port */ 10310dbe28b3SPyun YongHyeon 10320dbe28b3SPyun YongHyeon /* I2C Address */ 10330dbe28b3SPyun YongHyeon #define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */ 10340dbe28b3SPyun YongHyeon 10350dbe28b3SPyun YongHyeon 10360dbe28b3SPyun YongHyeon /* B2_BSC_CTRL 8 bit Blink Source Counter Control */ 10370dbe28b3SPyun YongHyeon #define BSC_START BIT_1 /* Start Blink Source Counter */ 10380dbe28b3SPyun YongHyeon #define BSC_STOP BIT_0 /* Stop Blink Source Counter */ 10390dbe28b3SPyun YongHyeon 10400dbe28b3SPyun YongHyeon /* B2_BSC_STAT 8 bit Blink Source Counter Status */ 10410dbe28b3SPyun YongHyeon #define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */ 10420dbe28b3SPyun YongHyeon 10430dbe28b3SPyun YongHyeon /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ 10440dbe28b3SPyun YongHyeon #define BSC_T_ON BIT_2 /* Test mode on */ 10450dbe28b3SPyun YongHyeon #define BSC_T_OFF BIT_1 /* Test mode off */ 10460dbe28b3SPyun YongHyeon #define BSC_T_STEP BIT_0 /* Test step */ 10470dbe28b3SPyun YongHyeon 10480dbe28b3SPyun YongHyeon /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */ 10490dbe28b3SPyun YongHyeon #define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */ 10500dbe28b3SPyun YongHyeon #define PEX_DB_ACCESS BIT_30 /* Access to debug register */ 10510dbe28b3SPyun YongHyeon 10520dbe28b3SPyun YongHyeon /* B3_RAM_ADDR 32 bit RAM Address, to read or write */ 10530dbe28b3SPyun YongHyeon #define RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */ 10540dbe28b3SPyun YongHyeon 10550dbe28b3SPyun YongHyeon /* RAM Interface Registers */ 10560dbe28b3SPyun YongHyeon /* B3_RI_CTRL 16 bit RAM Interface Control Register */ 10570dbe28b3SPyun YongHyeon #define RI_CLR_RD_PERR BIT_9 /* Clear IRQ RAM Read Parity Err */ 10580dbe28b3SPyun YongHyeon #define RI_CLR_WR_PERR BIT_8 /* Clear IRQ RAM Write Parity Err */ 10590dbe28b3SPyun YongHyeon #define RI_RST_CLR BIT_1 /* Clear RAM Interface Reset */ 10600dbe28b3SPyun YongHyeon #define RI_RST_SET BIT_0 /* Set RAM Interface Reset */ 10610dbe28b3SPyun YongHyeon 10620dbe28b3SPyun YongHyeon #define MSK_RI_TO_53 36 /* RAM interface timeout */ 10630dbe28b3SPyun YongHyeon 10640dbe28b3SPyun YongHyeon /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 10650dbe28b3SPyun YongHyeon /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 10660dbe28b3SPyun YongHyeon /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 10670dbe28b3SPyun YongHyeon /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 10680dbe28b3SPyun YongHyeon /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ 10690dbe28b3SPyun YongHyeon #define TXA_MAX_VAL 0x00ffffff/* Bit 23.. 0: Max TXA Timer/Cnt Val */ 10700dbe28b3SPyun YongHyeon 10710dbe28b3SPyun YongHyeon /* TXA_CTRL 8 bit Tx Arbiter Control Register */ 10720dbe28b3SPyun YongHyeon #define TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */ 10730dbe28b3SPyun YongHyeon #define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */ 10740dbe28b3SPyun YongHyeon #define TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */ 10750dbe28b3SPyun YongHyeon #define TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */ 10760dbe28b3SPyun YongHyeon #define TXA_START_RC BIT_3 /* Start sync Rate Control */ 10770dbe28b3SPyun YongHyeon #define TXA_STOP_RC BIT_2 /* Stop sync Rate Control */ 10780dbe28b3SPyun YongHyeon #define TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */ 10790dbe28b3SPyun YongHyeon #define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */ 10800dbe28b3SPyun YongHyeon 10810dbe28b3SPyun YongHyeon /* TXA_TEST 8 bit Tx Arbiter Test Register */ 10820dbe28b3SPyun YongHyeon #define TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */ 10830dbe28b3SPyun YongHyeon #define TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */ 10840dbe28b3SPyun YongHyeon #define TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */ 10850dbe28b3SPyun YongHyeon #define TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */ 10860dbe28b3SPyun YongHyeon #define TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */ 10870dbe28b3SPyun YongHyeon #define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */ 10880dbe28b3SPyun YongHyeon 10890dbe28b3SPyun YongHyeon /* TXA_STAT 8 bit Tx Arbiter Status Register */ 10900dbe28b3SPyun YongHyeon #define TXA_PRIO_XS BIT_0 /* sync queue has prio to send */ 10910dbe28b3SPyun YongHyeon 10920dbe28b3SPyun YongHyeon /* Q_BC 32 bit Current Byte Counter */ 10930dbe28b3SPyun YongHyeon #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ 10940dbe28b3SPyun YongHyeon 10950dbe28b3SPyun YongHyeon /* Rx BMU Control / Status Registers (Yukon-2) */ 10960dbe28b3SPyun YongHyeon #define BMU_IDLE BIT_31 /* BMU Idle State */ 10970dbe28b3SPyun YongHyeon #define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */ 10980dbe28b3SPyun YongHyeon #define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */ 10990dbe28b3SPyun YongHyeon #define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */ 11000dbe28b3SPyun YongHyeon #define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */ 11010dbe28b3SPyun YongHyeon #define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */ 11020dbe28b3SPyun YongHyeon #define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */ 11030dbe28b3SPyun YongHyeon #define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */ 11040dbe28b3SPyun YongHyeon #define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */ 11050dbe28b3SPyun YongHyeon #define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */ 11060dbe28b3SPyun YongHyeon #define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */ 11070dbe28b3SPyun YongHyeon #define BMU_START BIT_8 /* Start Rx/Tx Queue */ 11080dbe28b3SPyun YongHyeon #define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */ 11090dbe28b3SPyun YongHyeon #define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */ 11100dbe28b3SPyun YongHyeon #define BMU_FIFO_ENA BIT_5 /* Enable FIFO */ 11110dbe28b3SPyun YongHyeon #define BMU_FIFO_RST BIT_4 /* Reset FIFO */ 11120dbe28b3SPyun YongHyeon #define BMU_OP_ON BIT_3 /* BMU Operational On */ 11130dbe28b3SPyun YongHyeon #define BMU_OP_OFF BIT_2 /* BMU Operational Off */ 11140dbe28b3SPyun YongHyeon #define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */ 11150dbe28b3SPyun YongHyeon #define BMU_RST_SET BIT_0 /* Set BMU Reset */ 11160dbe28b3SPyun YongHyeon 11170dbe28b3SPyun YongHyeon #define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR) 11180dbe28b3SPyun YongHyeon #define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | \ 11190dbe28b3SPyun YongHyeon BMU_START | BMU_FIFO_ENA | BMU_OP_ON) 11200dbe28b3SPyun YongHyeon 11210dbe28b3SPyun YongHyeon /* Tx BMU Control / Status Registers (Yukon-2) */ 11220dbe28b3SPyun YongHyeon /* Bit 31: same as for Rx */ 11230dbe28b3SPyun YongHyeon #define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */ 11240dbe28b3SPyun YongHyeon #define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */ 11250dbe28b3SPyun YongHyeon #define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */ 11260dbe28b3SPyun YongHyeon /* Bit 10..0: same as for Rx */ 11270dbe28b3SPyun YongHyeon 11280dbe28b3SPyun YongHyeon /* Q_F 32 bit Flag Register */ 1129daf29227SPyun YongHyeon #define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/ 1130daf29227SPyun YongHyeon #define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/ 1131daf29227SPyun YongHyeon #define F_ALM_FULL BIT_28 /* Rx FIFO: almost full */ 11320dbe28b3SPyun YongHyeon #define F_EMPTY BIT_27 /* Tx FIFO: empty flag */ 11330dbe28b3SPyun YongHyeon #define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */ 11340dbe28b3SPyun YongHyeon #define F_WM_REACHED BIT_25 /* Watermark reached */ 11350dbe28b3SPyun YongHyeon #define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */ 1136daf29227SPyun YongHyeon #define F_FIFO_LEVEL (0x1f<<16) 1137daf29227SPyun YongHyeon /* Bit 23..16: # of Qwords in FIFO */ 11380dbe28b3SPyun YongHyeon #define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */ 11390dbe28b3SPyun YongHyeon 11400dbe28b3SPyun YongHyeon /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/ 11410dbe28b3SPyun YongHyeon /* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */ 11420dbe28b3SPyun YongHyeon #define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */ 11430dbe28b3SPyun YongHyeon #define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */ 11440dbe28b3SPyun YongHyeon #define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */ 11450dbe28b3SPyun YongHyeon #define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */ 11460dbe28b3SPyun YongHyeon 11470dbe28b3SPyun YongHyeon /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ 11480dbe28b3SPyun YongHyeon /* RB_START 32 bit RAM Buffer Start Address */ 11490dbe28b3SPyun YongHyeon /* RB_END 32 bit RAM Buffer End Address */ 11500dbe28b3SPyun YongHyeon /* RB_WP 32 bit RAM Buffer Write Pointer */ 11510dbe28b3SPyun YongHyeon /* RB_RP 32 bit RAM Buffer Read Pointer */ 11520dbe28b3SPyun YongHyeon /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ 11530dbe28b3SPyun YongHyeon /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ 11540dbe28b3SPyun YongHyeon /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ 11550dbe28b3SPyun YongHyeon /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ 11560dbe28b3SPyun YongHyeon /* RB_PC 32 bit RAM Buffer Packet Counter */ 11570dbe28b3SPyun YongHyeon /* RB_LEV 32 bit RAM Buffer Level Register */ 11580dbe28b3SPyun YongHyeon #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ 11590dbe28b3SPyun YongHyeon 11600dbe28b3SPyun YongHyeon /* RB_TST2 8 bit RAM Buffer Test Register 2 */ 11610dbe28b3SPyun YongHyeon #define RB_PC_DEC BIT_3 /* Packet Counter Decrement */ 11620dbe28b3SPyun YongHyeon #define RB_PC_T_ON BIT_2 /* Packet Counter Test On */ 11630dbe28b3SPyun YongHyeon #define RB_PC_T_OFF BIT_1 /* Packet Counter Test Off */ 11640dbe28b3SPyun YongHyeon #define RB_PC_INC BIT_0 /* Packet Counter Increment */ 11650dbe28b3SPyun YongHyeon 11660dbe28b3SPyun YongHyeon /* RB_TST1 8 bit RAM Buffer Test Register 1 */ 11670dbe28b3SPyun YongHyeon #define RB_WP_T_ON BIT_6 /* Write Pointer Test On */ 11680dbe28b3SPyun YongHyeon #define RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */ 11690dbe28b3SPyun YongHyeon #define RB_WP_INC BIT_4 /* Write Pointer Increment */ 11700dbe28b3SPyun YongHyeon #define RB_RP_T_ON BIT_2 /* Read Pointer Test On */ 11710dbe28b3SPyun YongHyeon #define RB_RP_T_OFF BIT_1 /* Read Pointer Test Off */ 11720dbe28b3SPyun YongHyeon #define RB_RP_INC BIT_0 /* Read Pointer Increment */ 11730dbe28b3SPyun YongHyeon 11740dbe28b3SPyun YongHyeon /* RB_CTRL 8 bit RAM Buffer Control Register */ 11750dbe28b3SPyun YongHyeon #define RB_ENA_STFWD BIT_5 /* Enable Store & Forward */ 11760dbe28b3SPyun YongHyeon #define RB_DIS_STFWD BIT_4 /* Disable Store & Forward */ 11770dbe28b3SPyun YongHyeon #define RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */ 11780dbe28b3SPyun YongHyeon #define RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */ 11790dbe28b3SPyun YongHyeon #define RB_RST_CLR BIT_1 /* Clear RAM Buf STM Reset */ 11800dbe28b3SPyun YongHyeon #define RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */ 11810dbe28b3SPyun YongHyeon 11820dbe28b3SPyun YongHyeon /* RAM Buffer High Pause Threshold values */ 11830dbe28b3SPyun YongHyeon #define MSK_RB_ULPP (8 * 1024) /* Upper Level in kB/8 */ 11840dbe28b3SPyun YongHyeon #define MSK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */ 11850dbe28b3SPyun YongHyeon #define MSK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ 11860dbe28b3SPyun YongHyeon 11870dbe28b3SPyun YongHyeon /* Threshold values for Yukon-EC Ultra */ 11880dbe28b3SPyun YongHyeon #define MSK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */ 11890dbe28b3SPyun YongHyeon #define MSK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */ 1190a109c74fSPyun YongHyeon #define MSK_ECU_AE_THR 0x0070 /* Almost Empty Threshold */ 11910dbe28b3SPyun YongHyeon #define MSK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */ 1192a109c74fSPyun YongHyeon #define MSK_ECU_JUMBO_WM 0x01 11930dbe28b3SPyun YongHyeon 11940dbe28b3SPyun YongHyeon #define MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ 11950dbe28b3SPyun YongHyeon #define MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ 11960dbe28b3SPyun YongHyeon /* performance sensitive drivers should set this define to 0x80 */ 11970dbe28b3SPyun YongHyeon #define MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */ 11980dbe28b3SPyun YongHyeon 11990dbe28b3SPyun YongHyeon /* Receive and Transmit Queues */ 12000dbe28b3SPyun YongHyeon #define Q_R1 0x0000 /* Receive Queue 1 */ 12010dbe28b3SPyun YongHyeon #define Q_R2 0x0080 /* Receive Queue 2 */ 12020dbe28b3SPyun YongHyeon #define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */ 12030dbe28b3SPyun YongHyeon #define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */ 12040dbe28b3SPyun YongHyeon #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ 12050dbe28b3SPyun YongHyeon #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ 12060dbe28b3SPyun YongHyeon 12070dbe28b3SPyun YongHyeon #define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */ 12080dbe28b3SPyun YongHyeon #define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */ 12090dbe28b3SPyun YongHyeon #define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */ 12100dbe28b3SPyun YongHyeon #define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */ 12110dbe28b3SPyun YongHyeon 12120dbe28b3SPyun YongHyeon #define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) 12130dbe28b3SPyun YongHyeon 12140dbe28b3SPyun YongHyeon /* Minimum RAM Buffer Rx Queue Size */ 12150dbe28b3SPyun YongHyeon #define MSK_MIN_RXQ_SIZE 10 12160dbe28b3SPyun YongHyeon /* Minimum RAM Buffer Tx Queue Size */ 12170dbe28b3SPyun YongHyeon #define MSK_MIN_TXQ_SIZE 10 12180dbe28b3SPyun YongHyeon /* Percentage of queue size from whole memory. 80 % for receive */ 12190dbe28b3SPyun YongHyeon #define MSK_RAM_QUOTA_RX 80 12200dbe28b3SPyun YongHyeon 12210dbe28b3SPyun YongHyeon /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ 12220dbe28b3SPyun YongHyeon #define WOL_CTL_LINK_CHG_OCC BIT_15 12230dbe28b3SPyun YongHyeon #define WOL_CTL_MAGIC_PKT_OCC BIT_14 12240dbe28b3SPyun YongHyeon #define WOL_CTL_PATTERN_OCC BIT_13 12250dbe28b3SPyun YongHyeon #define WOL_CTL_CLEAR_RESULT BIT_12 12260dbe28b3SPyun YongHyeon #define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11 12270dbe28b3SPyun YongHyeon #define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10 12280dbe28b3SPyun YongHyeon #define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9 12290dbe28b3SPyun YongHyeon #define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8 12300dbe28b3SPyun YongHyeon #define WOL_CTL_ENA_PME_ON_PATTERN BIT_7 12310dbe28b3SPyun YongHyeon #define WOL_CTL_DIS_PME_ON_PATTERN BIT_6 12320dbe28b3SPyun YongHyeon #define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5 12330dbe28b3SPyun YongHyeon #define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4 12340dbe28b3SPyun YongHyeon #define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3 12350dbe28b3SPyun YongHyeon #define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2 12360dbe28b3SPyun YongHyeon #define WOL_CTL_ENA_PATTERN_UNIT BIT_1 12370dbe28b3SPyun YongHyeon #define WOL_CTL_DIS_PATTERN_UNIT BIT_0 12380dbe28b3SPyun YongHyeon 12390dbe28b3SPyun YongHyeon #define WOL_CTL_DEFAULT \ 12400dbe28b3SPyun YongHyeon (WOL_CTL_DIS_PME_ON_LINK_CHG | \ 12410dbe28b3SPyun YongHyeon WOL_CTL_DIS_PME_ON_PATTERN | \ 12420dbe28b3SPyun YongHyeon WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ 12430dbe28b3SPyun YongHyeon WOL_CTL_DIS_LINK_CHG_UNIT | \ 12440dbe28b3SPyun YongHyeon WOL_CTL_DIS_PATTERN_UNIT | \ 12450dbe28b3SPyun YongHyeon WOL_CTL_DIS_MAGIC_PKT_UNIT) 12460dbe28b3SPyun YongHyeon 12470dbe28b3SPyun YongHyeon /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ 12480dbe28b3SPyun YongHyeon #define WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) 12490dbe28b3SPyun YongHyeon 12500dbe28b3SPyun YongHyeon /* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */ 12510dbe28b3SPyun YongHyeon #define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */ 12520dbe28b3SPyun YongHyeon #define WOL_PATT_MATCH_PME_ALL 0x7f 12530dbe28b3SPyun YongHyeon 12540dbe28b3SPyun YongHyeon 12550dbe28b3SPyun YongHyeon /* 12560dbe28b3SPyun YongHyeon * Marvel-PHY Registers, indirect addressed over GMAC 12570dbe28b3SPyun YongHyeon */ 12580dbe28b3SPyun YongHyeon #define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 12590dbe28b3SPyun YongHyeon #define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */ 12600dbe28b3SPyun YongHyeon #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ 12610dbe28b3SPyun YongHyeon #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ 12620dbe28b3SPyun YongHyeon #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ 12630dbe28b3SPyun YongHyeon #define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ 12640dbe28b3SPyun YongHyeon #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ 12650dbe28b3SPyun YongHyeon #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ 12660dbe28b3SPyun YongHyeon #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ 12670dbe28b3SPyun YongHyeon /* Marvel-specific registers */ 12680dbe28b3SPyun YongHyeon #define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ 12690dbe28b3SPyun YongHyeon #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ 12700dbe28b3SPyun YongHyeon /* 0x0b - 0x0e: reserved */ 12710dbe28b3SPyun YongHyeon #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ 12720dbe28b3SPyun YongHyeon #define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */ 12730dbe28b3SPyun YongHyeon #define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */ 12740dbe28b3SPyun YongHyeon #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ 12750dbe28b3SPyun YongHyeon #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ 12760dbe28b3SPyun YongHyeon #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ 12770dbe28b3SPyun YongHyeon #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ 12780dbe28b3SPyun YongHyeon #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ 12790dbe28b3SPyun YongHyeon #define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */ 12800dbe28b3SPyun YongHyeon #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ 12810dbe28b3SPyun YongHyeon #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ 12820dbe28b3SPyun YongHyeon #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ 12830dbe28b3SPyun YongHyeon #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ 12840dbe28b3SPyun YongHyeon #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ 12850dbe28b3SPyun YongHyeon #define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */ 12860dbe28b3SPyun YongHyeon #define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */ 12870dbe28b3SPyun YongHyeon 12880dbe28b3SPyun YongHyeon /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 12890dbe28b3SPyun YongHyeon #define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */ 12900dbe28b3SPyun YongHyeon #define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */ 12910dbe28b3SPyun YongHyeon #define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */ 12920dbe28b3SPyun YongHyeon #define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */ 12930dbe28b3SPyun YongHyeon #define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */ 12940dbe28b3SPyun YongHyeon 12950dbe28b3SPyun YongHyeon #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ 12960dbe28b3SPyun YongHyeon #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ 12970dbe28b3SPyun YongHyeon #define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */ 12980dbe28b3SPyun YongHyeon #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ 12990dbe28b3SPyun YongHyeon #define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */ 13000dbe28b3SPyun YongHyeon #define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */ 13010dbe28b3SPyun YongHyeon #define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ 13020dbe28b3SPyun YongHyeon #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ 13030dbe28b3SPyun YongHyeon #define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */ 13040dbe28b3SPyun YongHyeon #define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */ 13050dbe28b3SPyun YongHyeon 13060dbe28b3SPyun YongHyeon #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ 13070dbe28b3SPyun YongHyeon #define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */ 13080dbe28b3SPyun YongHyeon #define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */ 13090dbe28b3SPyun YongHyeon 13100dbe28b3SPyun YongHyeon #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ 13110dbe28b3SPyun YongHyeon #define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */ 13120dbe28b3SPyun YongHyeon #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ 1313453130d9SPedro F. Giffuni #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occurred */ 13140dbe28b3SPyun YongHyeon #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ 13150dbe28b3SPyun YongHyeon #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ 13160dbe28b3SPyun YongHyeon #define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */ 13170dbe28b3SPyun YongHyeon #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ 13180dbe28b3SPyun YongHyeon 13190dbe28b3SPyun YongHyeon #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ 13200dbe28b3SPyun YongHyeon #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ 13210dbe28b3SPyun YongHyeon #define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */ 13220dbe28b3SPyun YongHyeon 13230dbe28b3SPyun YongHyeon /* different Marvell PHY Ids */ 13240dbe28b3SPyun YongHyeon #define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */ 13250dbe28b3SPyun YongHyeon 13260dbe28b3SPyun YongHyeon #define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1011) */ 13270dbe28b3SPyun YongHyeon #define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */ 13280dbe28b3SPyun YongHyeon #define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */ 13290dbe28b3SPyun YongHyeon #define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */ 13300dbe28b3SPyun YongHyeon #define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */ 13310dbe28b3SPyun YongHyeon #define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */ 13320dbe28b3SPyun YongHyeon 13330dbe28b3SPyun YongHyeon /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 13340dbe28b3SPyun YongHyeon #define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 13350dbe28b3SPyun YongHyeon #define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 13360dbe28b3SPyun YongHyeon #define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 13370dbe28b3SPyun YongHyeon #define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ 13380dbe28b3SPyun YongHyeon #define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 13390dbe28b3SPyun YongHyeon #define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 13400dbe28b3SPyun YongHyeon #define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ 13410dbe28b3SPyun YongHyeon 13420dbe28b3SPyun YongHyeon /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ 13430dbe28b3SPyun YongHyeon /***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/ 13440dbe28b3SPyun YongHyeon #define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ 13450dbe28b3SPyun YongHyeon #define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ 13460dbe28b3SPyun YongHyeon #define PHY_M_AN_RF BIT_13 /* Remote Fault */ 13470dbe28b3SPyun YongHyeon #define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ 13480dbe28b3SPyun YongHyeon #define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ 13490dbe28b3SPyun YongHyeon #define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */ 13500dbe28b3SPyun YongHyeon #define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ 13510dbe28b3SPyun YongHyeon #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ 13520dbe28b3SPyun YongHyeon #define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ 13530dbe28b3SPyun YongHyeon #define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ 13540dbe28b3SPyun YongHyeon #define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */ 13550dbe28b3SPyun YongHyeon 13560dbe28b3SPyun YongHyeon /* special defines for FIBER (88E1011S only) */ 13570dbe28b3SPyun YongHyeon #define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ 13580dbe28b3SPyun YongHyeon #define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ 13590dbe28b3SPyun YongHyeon #define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ 13600dbe28b3SPyun YongHyeon #define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ 13610dbe28b3SPyun YongHyeon 13620dbe28b3SPyun YongHyeon /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ 13630dbe28b3SPyun YongHyeon #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ 13640dbe28b3SPyun YongHyeon #define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */ 13650dbe28b3SPyun YongHyeon #define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */ 13660dbe28b3SPyun YongHyeon #define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */ 13670dbe28b3SPyun YongHyeon 13680dbe28b3SPyun YongHyeon /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 13690dbe28b3SPyun YongHyeon #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 13700dbe28b3SPyun YongHyeon #define PHY_M_1000C_MSE BIT_12 /* Manual Master/Slave Enable */ 13710dbe28b3SPyun YongHyeon #define PHY_M_1000C_MSC BIT_11 /* M/S Configuration (1=Master) */ 13720dbe28b3SPyun YongHyeon #define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */ 13730dbe28b3SPyun YongHyeon #define PHY_M_1000C_AFD BIT_9 /* Advertise Full Duplex */ 13740dbe28b3SPyun YongHyeon #define PHY_M_1000C_AHD BIT_8 /* Advertise Half Duplex */ 13750dbe28b3SPyun YongHyeon 13760dbe28b3SPyun YongHyeon /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ 13770dbe28b3SPyun YongHyeon #define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ 13780dbe28b3SPyun YongHyeon #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ 13790dbe28b3SPyun YongHyeon #define PHY_M_PC_ASS_CRS_TX BIT_11 /* Assert CRS on Transmit */ 13800dbe28b3SPyun YongHyeon #define PHY_M_PC_FL_GOOD BIT_10 /* Force Link Good */ 13810dbe28b3SPyun YongHyeon #define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ 13820dbe28b3SPyun YongHyeon #define PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */ 13830dbe28b3SPyun YongHyeon #define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ 13840dbe28b3SPyun YongHyeon #define PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */ 13850dbe28b3SPyun YongHyeon #define PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */ 13860dbe28b3SPyun YongHyeon #define PHY_M_PC_SQE_T_ENA BIT_2 /* SQE Test Enabled */ 13870dbe28b3SPyun YongHyeon #define PHY_M_PC_POL_R_DIS BIT_1 /* Polarity Reversal Disabled */ 13880dbe28b3SPyun YongHyeon #define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */ 13890dbe28b3SPyun YongHyeon 13900dbe28b3SPyun YongHyeon #define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */ 13910dbe28b3SPyun YongHyeon #define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */ 13920dbe28b3SPyun YongHyeon 13930dbe28b3SPyun YongHyeon #define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK) 13940dbe28b3SPyun YongHyeon 13950dbe28b3SPyun YongHyeon #define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ 13960dbe28b3SPyun YongHyeon #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ 13970dbe28b3SPyun YongHyeon #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ 13980dbe28b3SPyun YongHyeon 13990dbe28b3SPyun YongHyeon /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 14000dbe28b3SPyun YongHyeon #define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */ 14010dbe28b3SPyun YongHyeon #define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */ 14020dbe28b3SPyun YongHyeon #define PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */ 14030dbe28b3SPyun YongHyeon /* !!! Errata in spec. (1 = disable) */ 14040dbe28b3SPyun YongHyeon 14050dbe28b3SPyun YongHyeon #define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK) 14060dbe28b3SPyun YongHyeon /* 000=1x; 001=2x; 010=3x; 011=4x */ 14070dbe28b3SPyun YongHyeon /* 100=5x; 101=6x; 110=7x; 111=8x */ 14080dbe28b3SPyun YongHyeon 14090dbe28b3SPyun YongHyeon /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 14100dbe28b3SPyun YongHyeon #define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */ 14110dbe28b3SPyun YongHyeon #define PHY_M_PC_ENA_ENE_DT BIT_14 /* Enable Energy Detect (sense & pulse) */ 14120dbe28b3SPyun YongHyeon #define PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */ 14130dbe28b3SPyun YongHyeon #define PHY_M_PC_ENA_LIP_NP BIT_12 /* Enable Link Partner Next Page Reg. */ 14140dbe28b3SPyun YongHyeon #define PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */ 14150dbe28b3SPyun YongHyeon #define PHY_M_PC_DIS_SCRAMB BIT_9 /* Disable Scrambler */ 14160dbe28b3SPyun YongHyeon #define PHY_M_PC_DIS_FEFI BIT_8 /* Disable Far End Fault Indic. (FEFI) */ 14170dbe28b3SPyun YongHyeon #define PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */ 14180dbe28b3SPyun YongHyeon #define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */ 14190dbe28b3SPyun YongHyeon 14200dbe28b3SPyun YongHyeon /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ 14210dbe28b3SPyun YongHyeon #define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ 14220dbe28b3SPyun YongHyeon #define PHY_M_PS_SPEED_1000 BIT_15 /* 10 = 1000 Mbps */ 14230dbe28b3SPyun YongHyeon #define PHY_M_PS_SPEED_100 BIT_14 /* 01 = 100 Mbps */ 14240dbe28b3SPyun YongHyeon #define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ 14250dbe28b3SPyun YongHyeon #define PHY_M_PS_FULL_DUP BIT_13 /* Full Duplex */ 14260dbe28b3SPyun YongHyeon #define PHY_M_PS_PAGE_REC BIT_12 /* Page Received */ 14270dbe28b3SPyun YongHyeon #define PHY_M_PS_SPDUP_RES BIT_11 /* Speed & Duplex Resolved */ 14280dbe28b3SPyun YongHyeon #define PHY_M_PS_LINK_UP BIT_10 /* Link Up */ 14290dbe28b3SPyun YongHyeon #define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */ 14300dbe28b3SPyun YongHyeon #define PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */ 14310dbe28b3SPyun YongHyeon #define PHY_M_PS_DOWNS_STAT BIT_5 /* Downshift Status (1=downsh.) */ 14320dbe28b3SPyun YongHyeon #define PHY_M_PS_ENDET_STAT BIT_4 /* Energy Detect Status (1=act) */ 14330dbe28b3SPyun YongHyeon #define PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */ 14340dbe28b3SPyun YongHyeon #define PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */ 14350dbe28b3SPyun YongHyeon #define PHY_M_PS_POL_REV BIT_1 /* Polarity Reversed */ 14360dbe28b3SPyun YongHyeon #define PHY_M_PS_JABBER BIT_0 /* Jabber */ 14370dbe28b3SPyun YongHyeon 14380dbe28b3SPyun YongHyeon #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) 14390dbe28b3SPyun YongHyeon 14400dbe28b3SPyun YongHyeon /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 14410dbe28b3SPyun YongHyeon #define PHY_M_PS_DTE_DETECT BIT_15 /* Data Terminal Equipment (DTE) Detected */ 14420dbe28b3SPyun YongHyeon #define PHY_M_PS_RES_SPEED BIT_14 /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ 14430dbe28b3SPyun YongHyeon 14440dbe28b3SPyun YongHyeon /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ 14450dbe28b3SPyun YongHyeon /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/ 14460dbe28b3SPyun YongHyeon #define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */ 14470dbe28b3SPyun YongHyeon #define PHY_M_IS_LSP_CHANGE BIT_14 /* Link Speed Changed */ 14480dbe28b3SPyun YongHyeon #define PHY_M_IS_DUP_CHANGE BIT_13 /* Duplex Mode Changed */ 14490dbe28b3SPyun YongHyeon #define PHY_M_IS_AN_PR BIT_12 /* Page Received */ 14500dbe28b3SPyun YongHyeon #define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */ 14510dbe28b3SPyun YongHyeon #define PHY_M_IS_LST_CHANGE BIT_10 /* Link Status Changed */ 14520dbe28b3SPyun YongHyeon #define PHY_M_IS_SYMB_ERROR BIT_9 /* Symbol Error */ 14530dbe28b3SPyun YongHyeon #define PHY_M_IS_FALSE_CARR BIT_8 /* False Carrier */ 14540dbe28b3SPyun YongHyeon #define PHY_M_IS_FIFO_ERROR BIT_7 /* FIFO Overflow/Underrun Error */ 14550dbe28b3SPyun YongHyeon #define PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */ 14560dbe28b3SPyun YongHyeon #define PHY_M_IS_DOWNSH_DET BIT_5 /* Downshift Detected */ 14570dbe28b3SPyun YongHyeon #define PHY_M_IS_END_CHANGE BIT_4 /* Energy Detect Changed */ 14580dbe28b3SPyun YongHyeon #define PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */ 14590dbe28b3SPyun YongHyeon #define PHY_M_IS_POL_CHANGE BIT_1 /* Polarity Changed */ 14600dbe28b3SPyun YongHyeon #define PHY_M_IS_JABBER BIT_0 /* Jabber */ 14610dbe28b3SPyun YongHyeon 14620dbe28b3SPyun YongHyeon #define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \ 14630dbe28b3SPyun YongHyeon PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR) 14640dbe28b3SPyun YongHyeon 14650dbe28b3SPyun YongHyeon /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ 14660dbe28b3SPyun YongHyeon #define PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */ 14670dbe28b3SPyun YongHyeon #define PHY_M_EC_ENA_LIN_LB BIT_14 /* Enable Line Loopback (88E1111 only) */ 14680dbe28b3SPyun YongHyeon #define PHY_M_EC_DIS_LINK_P BIT_12 /* Disable Link Pulses (88E1111 only) */ 14690dbe28b3SPyun YongHyeon #define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */ 14700dbe28b3SPyun YongHyeon /* (88E1011 only) */ 14710dbe28b3SPyun YongHyeon #define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */ 14720dbe28b3SPyun YongHyeon /* (88E1011 only) */ 14730dbe28b3SPyun YongHyeon #define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */ 14740dbe28b3SPyun YongHyeon /* (88E1111 only) */ 14750dbe28b3SPyun YongHyeon #define PHY_M_EC_DOWN_S_ENA BIT_8 /* Downshift Enable (88E1111 only) */ 14760dbe28b3SPyun YongHyeon /* !!! Errata in spec. (1 = disable) */ 14770dbe28b3SPyun YongHyeon #define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/ 14780dbe28b3SPyun YongHyeon #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ 14790dbe28b3SPyun YongHyeon #define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */ 14800dbe28b3SPyun YongHyeon #define PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */ 14810dbe28b3SPyun YongHyeon #define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */ 14820dbe28b3SPyun YongHyeon #define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */ 14830dbe28b3SPyun YongHyeon 14840dbe28b3SPyun YongHyeon #define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK) 14850dbe28b3SPyun YongHyeon /* 00=1x; 01=2x; 10=3x; 11=4x */ 14860dbe28b3SPyun YongHyeon #define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK) 14870dbe28b3SPyun YongHyeon /* 00=dis; 01=1x; 10=2x; 11=3x */ 14880dbe28b3SPyun YongHyeon #define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK) 14890dbe28b3SPyun YongHyeon /* 01X=0; 110=2.5; 111=25 (MHz) */ 14900dbe28b3SPyun YongHyeon 14910dbe28b3SPyun YongHyeon #define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2) 14920dbe28b3SPyun YongHyeon /* 000=1x; 001=2x; 010=3x; 011=4x */ 14930dbe28b3SPyun YongHyeon /* 100=5x; 101=6x; 110=7x; 111=8x */ 14940dbe28b3SPyun YongHyeon #define MAC_TX_CLK_0_MHZ 2 14950dbe28b3SPyun YongHyeon #define MAC_TX_CLK_2_5_MHZ 6 14960dbe28b3SPyun YongHyeon #define MAC_TX_CLK_25_MHZ 7 14970dbe28b3SPyun YongHyeon 14980dbe28b3SPyun YongHyeon /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ 14990dbe28b3SPyun YongHyeon #define PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */ 15000dbe28b3SPyun YongHyeon #define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ 15010dbe28b3SPyun YongHyeon #define PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */ 15020dbe28b3SPyun YongHyeon #define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ 15030dbe28b3SPyun YongHyeon #define PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */ 15040dbe28b3SPyun YongHyeon #define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */ 15050dbe28b3SPyun YongHyeon #define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */ 15060dbe28b3SPyun YongHyeon /* (88E1111 only) */ 15070dbe28b3SPyun YongHyeon #define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ 15080dbe28b3SPyun YongHyeon /* (88E1011 only) */ 15090dbe28b3SPyun YongHyeon #define PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */ 15100dbe28b3SPyun YongHyeon #define PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */ 15110dbe28b3SPyun YongHyeon #define PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */ 15120dbe28b3SPyun YongHyeon #define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */ 15130dbe28b3SPyun YongHyeon #define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */ 15140dbe28b3SPyun YongHyeon 15150dbe28b3SPyun YongHyeon #define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK) 15160dbe28b3SPyun YongHyeon 15170dbe28b3SPyun YongHyeon #define PULS_NO_STR 0 /* no pulse stretching */ 15180dbe28b3SPyun YongHyeon #define PULS_21MS 1 /* 21 ms to 42 ms */ 15190dbe28b3SPyun YongHyeon #define PULS_42MS 2 /* 42 ms to 84 ms */ 15200dbe28b3SPyun YongHyeon #define PULS_84MS 3 /* 84 ms to 170 ms */ 15210dbe28b3SPyun YongHyeon #define PULS_170MS 4 /* 170 ms to 340 ms */ 15220dbe28b3SPyun YongHyeon #define PULS_340MS 5 /* 340 ms to 670 ms */ 15230dbe28b3SPyun YongHyeon #define PULS_670MS 6 /* 670 ms to 1.3 s */ 15240dbe28b3SPyun YongHyeon #define PULS_1300MS 7 /* 1.3 s to 2.7 s */ 15250dbe28b3SPyun YongHyeon 15260dbe28b3SPyun YongHyeon #define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK) 15270dbe28b3SPyun YongHyeon 15280dbe28b3SPyun YongHyeon #define BLINK_42MS 0 /* 42 ms */ 15290dbe28b3SPyun YongHyeon #define BLINK_84MS 1 /* 84 ms */ 15300dbe28b3SPyun YongHyeon #define BLINK_170MS 2 /* 170 ms */ 15310dbe28b3SPyun YongHyeon #define BLINK_340MS 3 /* 340 ms */ 15320dbe28b3SPyun YongHyeon #define BLINK_670MS 4 /* 670 ms */ 15330dbe28b3SPyun YongHyeon 15340dbe28b3SPyun YongHyeon /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ 15350dbe28b3SPyun YongHyeon #define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */ 15360dbe28b3SPyun YongHyeon #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ 15370dbe28b3SPyun YongHyeon #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ 15380dbe28b3SPyun YongHyeon #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ 15390dbe28b3SPyun YongHyeon #define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */ 15400dbe28b3SPyun YongHyeon #define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */ 15410dbe28b3SPyun YongHyeon #define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */ 15420dbe28b3SPyun YongHyeon 15430dbe28b3SPyun YongHyeon #define MO_LED_NORM 0 15440dbe28b3SPyun YongHyeon #define MO_LED_BLINK 1 15450dbe28b3SPyun YongHyeon #define MO_LED_OFF 2 15460dbe28b3SPyun YongHyeon #define MO_LED_ON 3 15470dbe28b3SPyun YongHyeon 15480dbe28b3SPyun YongHyeon /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ 15490dbe28b3SPyun YongHyeon #define PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */ 15500dbe28b3SPyun YongHyeon #define PHY_M_EC2_FO_IMPED BIT_5 /* Fiber Output Impedance */ 15510dbe28b3SPyun YongHyeon #define PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */ 15520dbe28b3SPyun YongHyeon #define PHY_M_EC2_FO_BOOST BIT_3 /* Fiber Output Boost */ 15530dbe28b3SPyun YongHyeon #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ 15540dbe28b3SPyun YongHyeon 15550dbe28b3SPyun YongHyeon /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ 15560dbe28b3SPyun YongHyeon #define PHY_M_FC_AUTO_SEL BIT_15 /* Fiber/Copper Auto Sel. Dis. */ 15570dbe28b3SPyun YongHyeon #define PHY_M_FC_AN_REG_ACC BIT_14 /* Fiber/Copper AN Reg. Access */ 15580dbe28b3SPyun YongHyeon #define PHY_M_FC_RESOLUTION BIT_13 /* Fiber/Copper Resolution */ 15590dbe28b3SPyun YongHyeon #define PHY_M_SER_IF_AN_BP BIT_12 /* Ser. IF AN Bypass Enable */ 15600dbe28b3SPyun YongHyeon #define PHY_M_SER_IF_BP_ST BIT_11 /* Ser. IF AN Bypass Status */ 15610dbe28b3SPyun YongHyeon #define PHY_M_IRQ_POLARITY BIT_10 /* IRQ polarity */ 15620dbe28b3SPyun YongHyeon #define PHY_M_DIS_AUT_MED BIT_9 /* Disable Aut. Medium Reg. Selection */ 15630dbe28b3SPyun YongHyeon /* (88E1111 only) */ 15640dbe28b3SPyun YongHyeon #define PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */ 15650dbe28b3SPyun YongHyeon #define PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */ 15660dbe28b3SPyun YongHyeon #define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ 15670dbe28b3SPyun YongHyeon 15680dbe28b3SPyun YongHyeon /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ 15690dbe28b3SPyun YongHyeon #define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */ 15700dbe28b3SPyun YongHyeon #define PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */ 15710dbe28b3SPyun YongHyeon /* (88E1111 only) */ 15720dbe28b3SPyun YongHyeon #define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */ 15730dbe28b3SPyun YongHyeon #define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */ 15740dbe28b3SPyun YongHyeon /* (88E1111 only) */ 15750dbe28b3SPyun YongHyeon #define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */ 15760dbe28b3SPyun YongHyeon 15770dbe28b3SPyun YongHyeon /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ 15780dbe28b3SPyun YongHyeon #define CABD_STAT_NORMAL 0 15790dbe28b3SPyun YongHyeon #define CABD_STAT_SHORT 1 15800dbe28b3SPyun YongHyeon #define CABD_STAT_OPEN 2 15810dbe28b3SPyun YongHyeon #define CABD_STAT_FAIL 3 15820dbe28b3SPyun YongHyeon 15830dbe28b3SPyun YongHyeon /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 15840dbe28b3SPyun YongHyeon /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ 15850dbe28b3SPyun YongHyeon #define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */ 15860dbe28b3SPyun YongHyeon #define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */ 15870dbe28b3SPyun YongHyeon #define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */ 15880dbe28b3SPyun YongHyeon 15890dbe28b3SPyun YongHyeon #define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK) 15900dbe28b3SPyun YongHyeon #define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK) 15910dbe28b3SPyun YongHyeon #define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK) 15920dbe28b3SPyun YongHyeon 15930dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_COLX 0x00 15940dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_ERROR 0x01 15950dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_DUPLEX 0x02 15960dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_DP_COL 0x03 15970dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_SPEED 0x04 15980dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_LINK 0x05 15990dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_TX 0x06 16000dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_RX 0x07 16010dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_ACT 0x08 16020dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_LNK_RX 0x09 16030dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_LNK_AC 0x0a 16040dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_ACT_BL 0x0b 16050dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_TX_BL 0x0c 16060dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_RX_BL 0x0d 16070dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_COL_BL 0x0e 16080dbe28b3SPyun YongHyeon #define LED_PAR_CTRL_INACT 0x0f 16090dbe28b3SPyun YongHyeon 16100dbe28b3SPyun YongHyeon /***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ 16110dbe28b3SPyun YongHyeon #define PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */ 16120dbe28b3SPyun YongHyeon #define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */ 16130dbe28b3SPyun YongHyeon #define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */ 16140dbe28b3SPyun YongHyeon 16150dbe28b3SPyun YongHyeon /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 16160dbe28b3SPyun YongHyeon /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ 16170dbe28b3SPyun YongHyeon #define PHY_M_FIB_FORCE_LNK BIT_10 /* Force Link Good */ 16180dbe28b3SPyun YongHyeon #define PHY_M_FIB_SIGD_POL BIT_9 /* SIGDET Polarity */ 16190dbe28b3SPyun YongHyeon #define PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */ 16200dbe28b3SPyun YongHyeon 16210dbe28b3SPyun YongHyeon /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ 16220dbe28b3SPyun YongHyeon #define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */ 16230dbe28b3SPyun YongHyeon #define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */ 16240dbe28b3SPyun YongHyeon #define PHY_M_MAC_MD_COPPER 5 /* Copper only */ 16250dbe28b3SPyun YongHyeon #define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */ 16260dbe28b3SPyun YongHyeon #define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK) 16270dbe28b3SPyun YongHyeon 16280dbe28b3SPyun YongHyeon /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 16290dbe28b3SPyun YongHyeon #define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */ 16300dbe28b3SPyun YongHyeon #define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */ 16310dbe28b3SPyun YongHyeon #define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */ 16320dbe28b3SPyun YongHyeon #define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ 16330dbe28b3SPyun YongHyeon 16340dbe28b3SPyun YongHyeon #define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK) 16350dbe28b3SPyun YongHyeon #define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK) 16360dbe28b3SPyun YongHyeon #define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK) 16370dbe28b3SPyun YongHyeon #define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK) 16380dbe28b3SPyun YongHyeon 16390dbe28b3SPyun YongHyeon /***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/ 16400dbe28b3SPyun YongHyeon #define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */ 16410dbe28b3SPyun YongHyeon #define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ 16420dbe28b3SPyun YongHyeon #define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ 16430dbe28b3SPyun YongHyeon #define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ 16440dbe28b3SPyun YongHyeon #define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ 16450dbe28b3SPyun YongHyeon #define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ 16460dbe28b3SPyun YongHyeon 16470dbe28b3SPyun YongHyeon #define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK) 16480dbe28b3SPyun YongHyeon #define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK) 16490dbe28b3SPyun YongHyeon #define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK) 16500dbe28b3SPyun YongHyeon #define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK) 16510dbe28b3SPyun YongHyeon #define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK) 16520dbe28b3SPyun YongHyeon #define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK) 16530dbe28b3SPyun YongHyeon 16540dbe28b3SPyun YongHyeon /* 16550dbe28b3SPyun YongHyeon * GMAC registers 16560dbe28b3SPyun YongHyeon * 16570dbe28b3SPyun YongHyeon * The GMAC registers are 16 or 32 bits wide. 16580dbe28b3SPyun YongHyeon * The GMACs host processor interface is 16 bits wide, 16590dbe28b3SPyun YongHyeon * therefore ALL registers will be addressed with 16 bit accesses. 16600dbe28b3SPyun YongHyeon * 16610dbe28b3SPyun YongHyeon * Note: NA reg = Network Address e.g DA, SA etc. 16620dbe28b3SPyun YongHyeon */ 16630dbe28b3SPyun YongHyeon 16640dbe28b3SPyun YongHyeon /* Port Registers */ 16650dbe28b3SPyun YongHyeon #define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */ 16660dbe28b3SPyun YongHyeon #define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ 16670dbe28b3SPyun YongHyeon #define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ 16680dbe28b3SPyun YongHyeon #define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ 16690dbe28b3SPyun YongHyeon #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */ 16700dbe28b3SPyun YongHyeon #define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ 16710dbe28b3SPyun YongHyeon #define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ 16720dbe28b3SPyun YongHyeon 16730dbe28b3SPyun YongHyeon /* Source Address Registers */ 16740dbe28b3SPyun YongHyeon #define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */ 16750dbe28b3SPyun YongHyeon #define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */ 16760dbe28b3SPyun YongHyeon #define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */ 16770dbe28b3SPyun YongHyeon #define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */ 16780dbe28b3SPyun YongHyeon #define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */ 16790dbe28b3SPyun YongHyeon #define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */ 16800dbe28b3SPyun YongHyeon 16810dbe28b3SPyun YongHyeon /* Multicast Address Hash Registers */ 16820dbe28b3SPyun YongHyeon #define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */ 16830dbe28b3SPyun YongHyeon #define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */ 16840dbe28b3SPyun YongHyeon #define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */ 16850dbe28b3SPyun YongHyeon #define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */ 16860dbe28b3SPyun YongHyeon 16870dbe28b3SPyun YongHyeon /* Interrupt Source Registers */ 16880dbe28b3SPyun YongHyeon #define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */ 16890dbe28b3SPyun YongHyeon #define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */ 16900dbe28b3SPyun YongHyeon #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */ 16910dbe28b3SPyun YongHyeon 16920dbe28b3SPyun YongHyeon /* Interrupt Mask Registers */ 16930dbe28b3SPyun YongHyeon #define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */ 16940dbe28b3SPyun YongHyeon #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */ 16950dbe28b3SPyun YongHyeon #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */ 16960dbe28b3SPyun YongHyeon 16970dbe28b3SPyun YongHyeon /* Serial Management Interface (SMI) Registers */ 16980dbe28b3SPyun YongHyeon #define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */ 16990dbe28b3SPyun YongHyeon #define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */ 17000dbe28b3SPyun YongHyeon #define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */ 17010dbe28b3SPyun YongHyeon 17020dbe28b3SPyun YongHyeon /* MIB Counters */ 17030dbe28b3SPyun YongHyeon #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ 17040dbe28b3SPyun YongHyeon #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ 17050dbe28b3SPyun YongHyeon 17060dbe28b3SPyun YongHyeon /* 17070dbe28b3SPyun YongHyeon * MIB Counters base address definitions (low word) - 17080dbe28b3SPyun YongHyeon * use offset 4 for access to high word (32 bit r/o) 17090dbe28b3SPyun YongHyeon */ 17100dbe28b3SPyun YongHyeon #define GM_RXF_UC_OK \ 17110dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */ 17120dbe28b3SPyun YongHyeon #define GM_RXF_BC_OK \ 17130dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */ 17140dbe28b3SPyun YongHyeon #define GM_RXF_MPAUSE \ 17150dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */ 17160dbe28b3SPyun YongHyeon #define GM_RXF_MC_OK \ 17170dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */ 17180dbe28b3SPyun YongHyeon #define GM_RXF_FCS_ERR \ 17190dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */ 17203a91ee71SPyun YongHyeon #define GM_RXF_SPARE1 \ 17213a91ee71SPyun YongHyeon (GM_MIB_CNT_BASE + 40) /* Rx spare 1 */ 17220dbe28b3SPyun YongHyeon #define GM_RXO_OK_LO \ 17230dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */ 17240dbe28b3SPyun YongHyeon #define GM_RXO_OK_HI \ 17250dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */ 17260dbe28b3SPyun YongHyeon #define GM_RXO_ERR_LO \ 17270dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */ 17280dbe28b3SPyun YongHyeon #define GM_RXO_ERR_HI \ 17290dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */ 17300dbe28b3SPyun YongHyeon #define GM_RXF_SHT \ 17310dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ 17320dbe28b3SPyun YongHyeon #define GM_RXE_FRAG \ 17330dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */ 17340dbe28b3SPyun YongHyeon #define GM_RXF_64B \ 17350dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ 17360dbe28b3SPyun YongHyeon #define GM_RXF_127B \ 17370dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */ 17380dbe28b3SPyun YongHyeon #define GM_RXF_255B \ 17390dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */ 17400dbe28b3SPyun YongHyeon #define GM_RXF_511B \ 17410dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */ 17420dbe28b3SPyun YongHyeon #define GM_RXF_1023B \ 17430dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */ 17440dbe28b3SPyun YongHyeon #define GM_RXF_1518B \ 17450dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */ 17460dbe28b3SPyun YongHyeon #define GM_RXF_MAX_SZ \ 17470dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */ 17480dbe28b3SPyun YongHyeon #define GM_RXF_LNG_ERR \ 17490dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */ 17500dbe28b3SPyun YongHyeon #define GM_RXF_JAB_PKT \ 17510dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */ 17523a91ee71SPyun YongHyeon #define GM_RXF_SPARE2 \ 17533a91ee71SPyun YongHyeon (GM_MIB_CNT_BASE + 168) /* Rx spare 2 */ 17540dbe28b3SPyun YongHyeon #define GM_RXE_FIFO_OV \ 17550dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */ 17563a91ee71SPyun YongHyeon #define GM_RXF_SPARE3 \ 17573a91ee71SPyun YongHyeon (GM_MIB_CNT_BASE + 184) /* Rx spare 3 */ 17580dbe28b3SPyun YongHyeon #define GM_TXF_UC_OK \ 17590dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */ 17600dbe28b3SPyun YongHyeon #define GM_TXF_BC_OK \ 17610dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */ 17620dbe28b3SPyun YongHyeon #define GM_TXF_MPAUSE \ 17630dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */ 17640dbe28b3SPyun YongHyeon #define GM_TXF_MC_OK \ 17650dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */ 17660dbe28b3SPyun YongHyeon #define GM_TXO_OK_LO \ 17670dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */ 17680dbe28b3SPyun YongHyeon #define GM_TXO_OK_HI \ 17690dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */ 17700dbe28b3SPyun YongHyeon #define GM_TXF_64B \ 17710dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */ 17720dbe28b3SPyun YongHyeon #define GM_TXF_127B \ 17730dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */ 17740dbe28b3SPyun YongHyeon #define GM_TXF_255B \ 17750dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */ 17760dbe28b3SPyun YongHyeon #define GM_TXF_511B \ 17770dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */ 17780dbe28b3SPyun YongHyeon #define GM_TXF_1023B \ 17790dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */ 17800dbe28b3SPyun YongHyeon #define GM_TXF_1518B \ 17810dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */ 17820dbe28b3SPyun YongHyeon #define GM_TXF_MAX_SZ \ 17830dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */ 17843a91ee71SPyun YongHyeon #define GM_TXF_SPARE1 \ 17853a91ee71SPyun YongHyeon (GM_MIB_CNT_BASE + 296) /* Tx spare 1 */ 17860dbe28b3SPyun YongHyeon #define GM_TXF_COL \ 17870dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 304) /* Tx Collision */ 17880dbe28b3SPyun YongHyeon #define GM_TXF_LAT_COL \ 17890dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */ 17900dbe28b3SPyun YongHyeon #define GM_TXF_ABO_COL \ 17910dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */ 17920dbe28b3SPyun YongHyeon #define GM_TXF_MUL_COL \ 17930dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */ 17940dbe28b3SPyun YongHyeon #define GM_TXF_SNG_COL \ 17950dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */ 17960dbe28b3SPyun YongHyeon #define GM_TXE_FIFO_UR \ 17970dbe28b3SPyun YongHyeon (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */ 17980dbe28b3SPyun YongHyeon 17990dbe28b3SPyun YongHyeon /*----------------------------------------------------------------------------*/ 18000dbe28b3SPyun YongHyeon /* 18010dbe28b3SPyun YongHyeon * GMAC Bit Definitions 18020dbe28b3SPyun YongHyeon * 18030dbe28b3SPyun YongHyeon * If the bit access behaviour differs from the register access behaviour 18040dbe28b3SPyun YongHyeon * (r/w, r/o) this is documented after the bit number. 18050dbe28b3SPyun YongHyeon * The following bit access behaviours are used: 18060dbe28b3SPyun YongHyeon * (sc) self clearing 18070dbe28b3SPyun YongHyeon * (r/o) read only 18080dbe28b3SPyun YongHyeon */ 18090dbe28b3SPyun YongHyeon 18100dbe28b3SPyun YongHyeon /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ 18110dbe28b3SPyun YongHyeon #define GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */ 18120dbe28b3SPyun YongHyeon #define GM_GPSR_DUPLEX BIT_14 /* Duplex Mode (1 = Full) */ 18130dbe28b3SPyun YongHyeon #define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */ 18140dbe28b3SPyun YongHyeon #define GM_GPSR_LINK_UP BIT_12 /* Link Up Status */ 18150dbe28b3SPyun YongHyeon #define GM_GPSR_PAUSE BIT_11 /* Pause State */ 18160dbe28b3SPyun YongHyeon #define GM_GPSR_TX_ACTIVE BIT_10 /* Tx in Progress */ 1817453130d9SPedro F. Giffuni #define GM_GPSR_EXC_COL BIT_9 /* Excessive Collisions Occurred */ 1818453130d9SPedro F. Giffuni #define GM_GPSR_LAT_COL BIT_8 /* Late Collisions Occurred */ 18190dbe28b3SPyun YongHyeon #define GM_GPSR_PHY_ST_CH BIT_5 /* PHY Status Change */ 18200dbe28b3SPyun YongHyeon #define GM_GPSR_GIG_SPEED BIT_4 /* Gigabit Speed (1 = 1000 Mbps) */ 18210dbe28b3SPyun YongHyeon #define GM_GPSR_PART_MODE BIT_3 /* Partition mode */ 18220dbe28b3SPyun YongHyeon #define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */ 18230dbe28b3SPyun YongHyeon 18240dbe28b3SPyun YongHyeon /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ 18250dbe28b3SPyun YongHyeon #define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */ 18260dbe28b3SPyun YongHyeon #define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */ 18270dbe28b3SPyun YongHyeon #define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */ 18280dbe28b3SPyun YongHyeon #define GM_GPCR_TX_ENA BIT_12 /* Enable Transmit */ 18290dbe28b3SPyun YongHyeon #define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */ 18300dbe28b3SPyun YongHyeon #define GM_GPCR_LOOP_ENA BIT_9 /* Enable MAC Loopback Mode */ 18310dbe28b3SPyun YongHyeon #define GM_GPCR_PART_ENA BIT_8 /* Enable Partition Mode */ 18320dbe28b3SPyun YongHyeon #define GM_GPCR_GIGS_ENA BIT_7 /* Gigabit Speed (1000 Mbps) */ 18330dbe28b3SPyun YongHyeon #define GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */ 18340dbe28b3SPyun YongHyeon #define GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */ 18350dbe28b3SPyun YongHyeon #define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */ 18360dbe28b3SPyun YongHyeon #define GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */ 18370dbe28b3SPyun YongHyeon #define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */ 18380dbe28b3SPyun YongHyeon #define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */ 18390dbe28b3SPyun YongHyeon #define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */ 18400dbe28b3SPyun YongHyeon 18410dbe28b3SPyun YongHyeon #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 18420dbe28b3SPyun YongHyeon #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\ 18430dbe28b3SPyun YongHyeon GM_GPCR_AU_SPD_DIS) 18440dbe28b3SPyun YongHyeon 18450dbe28b3SPyun YongHyeon /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ 18460dbe28b3SPyun YongHyeon #define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */ 18470dbe28b3SPyun YongHyeon #define GM_TXCR_CRC_DIS BIT_14 /* Disable insertion of CRC */ 18480dbe28b3SPyun YongHyeon #define GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */ 18490dbe28b3SPyun YongHyeon #define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */ 18500dbe28b3SPyun YongHyeon #define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */ 18510dbe28b3SPyun YongHyeon /* (Yukon-2 only) */ 18520dbe28b3SPyun YongHyeon 18530dbe28b3SPyun YongHyeon #define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK) 18540dbe28b3SPyun YongHyeon #define TX_COL_DEF 0x04 18550dbe28b3SPyun YongHyeon 18560dbe28b3SPyun YongHyeon /* GM_RX_CTRL 16 bit r/w Receive Control Register */ 18570dbe28b3SPyun YongHyeon #define GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */ 18580dbe28b3SPyun YongHyeon #define GM_RXCR_MCF_ENA BIT_14 /* Enable Multicast filtering */ 18590dbe28b3SPyun YongHyeon #define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */ 18600dbe28b3SPyun YongHyeon #define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */ 18610dbe28b3SPyun YongHyeon 18620dbe28b3SPyun YongHyeon /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ 18630dbe28b3SPyun YongHyeon #define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */ 18640dbe28b3SPyun YongHyeon #define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */ 18650dbe28b3SPyun YongHyeon #define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */ 18660dbe28b3SPyun YongHyeon #define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */ 18670dbe28b3SPyun YongHyeon /* (Yukon-2 only) */ 18680dbe28b3SPyun YongHyeon 18690dbe28b3SPyun YongHyeon #define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK) 18700dbe28b3SPyun YongHyeon #define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK) 18710dbe28b3SPyun YongHyeon #define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK) 18720dbe28b3SPyun YongHyeon #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) 18730dbe28b3SPyun YongHyeon 18740dbe28b3SPyun YongHyeon #define TX_JAM_LEN_DEF 0x03 18750dbe28b3SPyun YongHyeon #define TX_JAM_IPG_DEF 0x0b 18760dbe28b3SPyun YongHyeon #define TX_IPG_JAM_DEF 0x1c 18770dbe28b3SPyun YongHyeon #define TX_BOF_LIM_DEF 0x04 18780dbe28b3SPyun YongHyeon 18790dbe28b3SPyun YongHyeon /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ 18800dbe28b3SPyun YongHyeon #define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ 18810dbe28b3SPyun YongHyeon /* r/o on Yukon, r/w on Yukon-EC */ 18820dbe28b3SPyun YongHyeon #define GM_SMOD_LIMIT_4 BIT_10 /* 4 consecutive Tx trials */ 18830dbe28b3SPyun YongHyeon #define GM_SMOD_VLAN_ENA BIT_9 /* Enable VLAN (Max. Frame Len) */ 18840dbe28b3SPyun YongHyeon #define GM_SMOD_JUMBO_ENA BIT_8 /* Enable Jumbo (Max. Frame Len) */ 18850dbe28b3SPyun YongHyeon #define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */ 18860dbe28b3SPyun YongHyeon 18870dbe28b3SPyun YongHyeon #define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK) 18880dbe28b3SPyun YongHyeon #define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK) 18890dbe28b3SPyun YongHyeon 18900dbe28b3SPyun YongHyeon #define DATA_BLIND_DEF 0x04 18910dbe28b3SPyun YongHyeon #define IPG_DATA_DEF 0x1e 18920dbe28b3SPyun YongHyeon 18930dbe28b3SPyun YongHyeon /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ 18940dbe28b3SPyun YongHyeon #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */ 18950dbe28b3SPyun YongHyeon #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */ 18960dbe28b3SPyun YongHyeon #define GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/ 18970dbe28b3SPyun YongHyeon #define GM_SMI_CT_RD_VAL BIT_4 /* Read Valid (Read completed) */ 18980dbe28b3SPyun YongHyeon #define GM_SMI_CT_BUSY BIT_3 /* Busy (Operation in progress) */ 18990dbe28b3SPyun YongHyeon 19000dbe28b3SPyun YongHyeon #define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK) 19010dbe28b3SPyun YongHyeon #define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK) 19020dbe28b3SPyun YongHyeon 19030dbe28b3SPyun YongHyeon /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ 19040dbe28b3SPyun YongHyeon #define GM_PAR_MIB_CLR BIT_5 /* Set MIB Clear Counter Mode */ 19050dbe28b3SPyun YongHyeon #define GM_PAR_MIB_TST BIT_4 /* MIB Load Counter (Test Mode) */ 19060dbe28b3SPyun YongHyeon 19070dbe28b3SPyun YongHyeon /* Receive Frame Status Encoding */ 19080dbe28b3SPyun YongHyeon #define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */ 19090dbe28b3SPyun YongHyeon #define GMR_FS_VLAN BIT_13 /* VLAN Packet */ 19100dbe28b3SPyun YongHyeon #define GMR_FS_JABBER BIT_12 /* Jabber Packet */ 19110dbe28b3SPyun YongHyeon #define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */ 19120dbe28b3SPyun YongHyeon #define GMR_FS_MC BIT_10 /* Multicast Packet */ 19130dbe28b3SPyun YongHyeon #define GMR_FS_BC BIT_9 /* Broadcast Packet */ 19140dbe28b3SPyun YongHyeon #define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */ 19150dbe28b3SPyun YongHyeon #define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */ 19160dbe28b3SPyun YongHyeon #define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */ 19170dbe28b3SPyun YongHyeon #define GMR_FS_MII_ERR BIT_5 /* MII Error */ 19180dbe28b3SPyun YongHyeon #define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */ 19190dbe28b3SPyun YongHyeon #define GMR_FS_FRAGMENT BIT_3 /* Fragment */ 19200dbe28b3SPyun YongHyeon #define GMR_FS_CRC_ERR BIT_1 /* CRC Error */ 19210dbe28b3SPyun YongHyeon #define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */ 19220dbe28b3SPyun YongHyeon 19230dbe28b3SPyun YongHyeon #define GMR_FS_LEN_SHIFT 16 19240dbe28b3SPyun YongHyeon 19250dbe28b3SPyun YongHyeon #define GMR_FS_ANY_ERR ( \ 19260dbe28b3SPyun YongHyeon GMR_FS_RX_FF_OV | \ 19270dbe28b3SPyun YongHyeon GMR_FS_CRC_ERR | \ 19280dbe28b3SPyun YongHyeon GMR_FS_FRAGMENT | \ 19290dbe28b3SPyun YongHyeon GMR_FS_LONG_ERR | \ 19300dbe28b3SPyun YongHyeon GMR_FS_MII_ERR | \ 19310dbe28b3SPyun YongHyeon GMR_FS_BAD_FC | \ 1932d5d60164SPyun YongHyeon GMR_FS_GOOD_FC | \ 19330dbe28b3SPyun YongHyeon GMR_FS_UN_SIZE | \ 19340dbe28b3SPyun YongHyeon GMR_FS_JABBER) 19350dbe28b3SPyun YongHyeon 19360dbe28b3SPyun YongHyeon /* Rx GMAC FIFO Flush Mask (default) */ 19370dbe28b3SPyun YongHyeon #define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR 19380dbe28b3SPyun YongHyeon 19390dbe28b3SPyun YongHyeon /* Receive and Transmit GMAC FIFO Registers (YUKON only) */ 19400dbe28b3SPyun YongHyeon 19410dbe28b3SPyun YongHyeon /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */ 19420dbe28b3SPyun YongHyeon /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */ 19430dbe28b3SPyun YongHyeon /* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ 19440dbe28b3SPyun YongHyeon /* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ 19450dbe28b3SPyun YongHyeon /* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ 19460dbe28b3SPyun YongHyeon /* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ 19470dbe28b3SPyun YongHyeon /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ 19480dbe28b3SPyun YongHyeon /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 19490dbe28b3SPyun YongHyeon /* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ 19500dbe28b3SPyun YongHyeon /* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */ 19510dbe28b3SPyun YongHyeon /* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ 19520dbe28b3SPyun YongHyeon /* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ 19530dbe28b3SPyun YongHyeon /* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ 19540dbe28b3SPyun YongHyeon /* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ 19550dbe28b3SPyun YongHyeon 19560dbe28b3SPyun YongHyeon /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ 19570dbe28b3SPyun YongHyeon #define RX_TRUNC_ON BIT_27 /* enable packet truncation */ 19580dbe28b3SPyun YongHyeon #define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ 19590dbe28b3SPyun YongHyeon #define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ 19600dbe28b3SPyun YongHyeon #define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ 19617c8db6fdSPyun YongHyeon #define GMF_RX_MACSEC_FLUSH_ON BIT_23 19627c8db6fdSPyun YongHyeon #define GMF_RX_MACSEC_FLUSH_OFF BIT_22 196361708f4cSPyun YongHyeon #define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */ 196461708f4cSPyun YongHyeon #define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */ 196561708f4cSPyun YongHyeon #define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */ 196661708f4cSPyun YongHyeon #define GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */ 19670dbe28b3SPyun YongHyeon #define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ 19680dbe28b3SPyun YongHyeon #define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ 19690dbe28b3SPyun YongHyeon #define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ 19700dbe28b3SPyun YongHyeon #define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ 19710dbe28b3SPyun YongHyeon #define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ 19720dbe28b3SPyun YongHyeon #define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ 19730dbe28b3SPyun YongHyeon #define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ 19740dbe28b3SPyun YongHyeon #define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ 19750dbe28b3SPyun YongHyeon #define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ 19760dbe28b3SPyun YongHyeon #define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ 19770dbe28b3SPyun YongHyeon #define GMF_OPER_ON BIT_3 /* Operational Mode On */ 19780dbe28b3SPyun YongHyeon #define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ 19790dbe28b3SPyun YongHyeon #define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ 19800dbe28b3SPyun YongHyeon #define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ 19810dbe28b3SPyun YongHyeon 19820dbe28b3SPyun YongHyeon /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */ 19830dbe28b3SPyun YongHyeon #define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */ 19840dbe28b3SPyun YongHyeon #define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */ 19850dbe28b3SPyun YongHyeon #define TX_VLAN_TAG_ON BIT_25 /* enable VLAN tagging */ 19860dbe28b3SPyun YongHyeon #define TX_VLAN_TAG_OFF BIT_24 /* disable VLAN tagging */ 1987a109c74fSPyun YongHyeon #define TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */ 1988a109c74fSPyun YongHyeon #define TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */ 19890dbe28b3SPyun YongHyeon #define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ 19900dbe28b3SPyun YongHyeon #define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ 19910dbe28b3SPyun YongHyeon #define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ 19920dbe28b3SPyun YongHyeon /* Bits 15..8: same as for RX_GMF_CTRL_T */ 19930dbe28b3SPyun YongHyeon #define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ 19940dbe28b3SPyun YongHyeon #define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ 19950dbe28b3SPyun YongHyeon #define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ 19960dbe28b3SPyun YongHyeon /* Bits 3..0: same as for RX_GMF_CTRL_T */ 19970dbe28b3SPyun YongHyeon 19980dbe28b3SPyun YongHyeon #define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) 19990dbe28b3SPyun YongHyeon #define GMF_TX_CTRL_DEF GMF_OPER_ON 20000dbe28b3SPyun YongHyeon 20010dbe28b3SPyun YongHyeon #define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */ 20020dbe28b3SPyun YongHyeon #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ 20030dbe28b3SPyun YongHyeon 20040dbe28b3SPyun YongHyeon /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ 20050dbe28b3SPyun YongHyeon #define GMT_ST_START BIT_2 /* Start Time Stamp Timer */ 20060dbe28b3SPyun YongHyeon #define GMT_ST_STOP BIT_1 /* Stop Time Stamp Timer */ 20070dbe28b3SPyun YongHyeon #define GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */ 20080dbe28b3SPyun YongHyeon 20090dbe28b3SPyun YongHyeon /* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */ 20100dbe28b3SPyun YongHyeon #define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */ 20110dbe28b3SPyun YongHyeon #define PC_POLL_RQ BIT_4 /* Poll Request Start */ 20120dbe28b3SPyun YongHyeon #define PC_POLL_OP_ON BIT_3 /* Operational Mode On */ 20130dbe28b3SPyun YongHyeon #define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */ 20140dbe28b3SPyun YongHyeon #define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */ 20150dbe28b3SPyun YongHyeon #define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */ 20160dbe28b3SPyun YongHyeon 20170dbe28b3SPyun YongHyeon /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ 20180dbe28b3SPyun YongHyeon /* This register is used by the host driver software */ 20190dbe28b3SPyun YongHyeon #define Y2_ASF_OS_PRES BIT_4 /* ASF operation system present */ 20200dbe28b3SPyun YongHyeon #define Y2_ASF_RESET BIT_3 /* ASF system in reset state */ 20210dbe28b3SPyun YongHyeon #define Y2_ASF_RUNNING BIT_2 /* ASF system operational */ 20220dbe28b3SPyun YongHyeon #define Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */ 20230dbe28b3SPyun YongHyeon #define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */ 20240dbe28b3SPyun YongHyeon 20250dbe28b3SPyun YongHyeon #define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */ 20260dbe28b3SPyun YongHyeon #define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */ 20270dbe28b3SPyun YongHyeon 2028daf29227SPyun YongHyeon /* B28_Y2_ASF_HCU_CCSR 32bit CPU Control and Status Register (Yukon EX) */ 2029daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27 /* SMBALERT pin monitor */ 2030daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_CPU_SLEEP BIT_26 /* CPU sleep status */ 2031daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_CS_TO BIT_25 /* Clock Stretching Timeout */ 2032daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_WDOG BIT_24 /* Watchdog Reset */ 2033daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_CLR_IRQ_HOST BIT_17 /* Clear IRQ_HOST */ 2034daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_SET_IRQ_HCU BIT_16 /* Set IRQ_HCU */ 2035daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_AHB_RST BIT_9 /* Reset AHB bridge */ 2036daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8 /* CPU Reset Mode */ 2037daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5 2038daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4 2039daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3 2040daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */ 2041daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3 2042daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */ 2043daf29227SPyun YongHyeon /* Microcontroller State */ 2044daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_UC_STATE_MSK 3 2045daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0 2046daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_ASF_RESET 0 2047daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1 2048daf29227SPyun YongHyeon #define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0 2049daf29227SPyun YongHyeon 20500dbe28b3SPyun YongHyeon /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ 20510dbe28b3SPyun YongHyeon /* This register is used by the ASF firmware */ 20520dbe28b3SPyun YongHyeon #define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */ 20530dbe28b3SPyun YongHyeon #define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */ 20540dbe28b3SPyun YongHyeon 20550dbe28b3SPyun YongHyeon /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ 20560dbe28b3SPyun YongHyeon #define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */ 20570dbe28b3SPyun YongHyeon #define SC_STAT_OP_ON BIT_3 /* Operational Mode On */ 20580dbe28b3SPyun YongHyeon #define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */ 20590dbe28b3SPyun YongHyeon #define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */ 20600dbe28b3SPyun YongHyeon #define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */ 20610dbe28b3SPyun YongHyeon 20620dbe28b3SPyun YongHyeon /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ 2063daf29227SPyun YongHyeon #define GMC_SEC_RST BIT_15 /* MAC SEC RST */ 2064daf29227SPyun YongHyeon #define GMC_SEC_RST_OFF BIT_14 /* MAC SEC RST Off */ 2065daf29227SPyun YongHyeon #define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */ 2066daf29227SPyun YongHyeon #define GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */ 2067daf29227SPyun YongHyeon #define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */ 2068daf29227SPyun YongHyeon #define GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */ 2069daf29227SPyun YongHyeon #define GMC_BYP_RETR_ON BIT_9 /* Bypass MAC retransmit FIFO On */ 2070daf29227SPyun YongHyeon #define GMC_BYP_RETR_OFF BIT_8 /* Bypass MAC retransmit FIFO Off */ 20710dbe28b3SPyun YongHyeon #define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ 20720dbe28b3SPyun YongHyeon #define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ 20730dbe28b3SPyun YongHyeon #define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ 20740dbe28b3SPyun YongHyeon #define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ 20750dbe28b3SPyun YongHyeon #define GMC_PAUSE_ON BIT_3 /* Pause On */ 20760dbe28b3SPyun YongHyeon #define GMC_PAUSE_OFF BIT_2 /* Pause Off */ 20770dbe28b3SPyun YongHyeon #define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ 20780dbe28b3SPyun YongHyeon #define GMC_RST_SET BIT_0 /* Set GMAC Reset */ 20790dbe28b3SPyun YongHyeon 20800dbe28b3SPyun YongHyeon /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ 20810dbe28b3SPyun YongHyeon #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ 20820dbe28b3SPyun YongHyeon #define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */ 20830dbe28b3SPyun YongHyeon #define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ 20840dbe28b3SPyun YongHyeon #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ 20850dbe28b3SPyun YongHyeon #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ 20860dbe28b3SPyun YongHyeon #define GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */ 20870dbe28b3SPyun YongHyeon #define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */ 20880dbe28b3SPyun YongHyeon #define GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */ 20890dbe28b3SPyun YongHyeon #define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */ 20900dbe28b3SPyun YongHyeon #define GPC_ANEG_0 BIT_19 /* ANEG[0] */ 20910dbe28b3SPyun YongHyeon #define GPC_ENA_XC BIT_18 /* Enable MDI crossover */ 20920dbe28b3SPyun YongHyeon #define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */ 20930dbe28b3SPyun YongHyeon #define GPC_ANEG_3 BIT_16 /* ANEG[3] */ 20940dbe28b3SPyun YongHyeon #define GPC_ANEG_2 BIT_15 /* ANEG[2] */ 20950dbe28b3SPyun YongHyeon #define GPC_ANEG_1 BIT_14 /* ANEG[1] */ 20960dbe28b3SPyun YongHyeon #define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ 20970dbe28b3SPyun YongHyeon #define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */ 20980dbe28b3SPyun YongHyeon #define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */ 20990dbe28b3SPyun YongHyeon #define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */ 21000dbe28b3SPyun YongHyeon #define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */ 21010dbe28b3SPyun YongHyeon #define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */ 21020dbe28b3SPyun YongHyeon #define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */ 21030dbe28b3SPyun YongHyeon #define GPC_RST_SET BIT_0 /* Set GPHY Reset */ 21040dbe28b3SPyun YongHyeon 21050dbe28b3SPyun YongHyeon /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ 21060dbe28b3SPyun YongHyeon /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ 21070dbe28b3SPyun YongHyeon #define GM_IS_RX_CO_OV BIT_5 /* Receive Counter Overflow IRQ */ 21080dbe28b3SPyun YongHyeon #define GM_IS_TX_CO_OV BIT_4 /* Transmit Counter Overflow IRQ */ 21090dbe28b3SPyun YongHyeon #define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ 21100dbe28b3SPyun YongHyeon #define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ 21110dbe28b3SPyun YongHyeon #define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ 21120dbe28b3SPyun YongHyeon #define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ 21130dbe28b3SPyun YongHyeon 21140dbe28b3SPyun YongHyeon #define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR) 21150dbe28b3SPyun YongHyeon 21160dbe28b3SPyun YongHyeon /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ 21170dbe28b3SPyun YongHyeon #define GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */ 21180dbe28b3SPyun YongHyeon #define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */ 21190dbe28b3SPyun YongHyeon 21200dbe28b3SPyun YongHyeon #define MSK_PORT_A 0 21210dbe28b3SPyun YongHyeon #define MSK_PORT_B 1 21220dbe28b3SPyun YongHyeon 21230dbe28b3SPyun YongHyeon /* Register access macros */ 21240dbe28b3SPyun YongHyeon #define CSR_WRITE_4(sc, reg, val) \ 21250dbe28b3SPyun YongHyeon bus_write_4((sc)->msk_res[0], (reg), (val)) 21260dbe28b3SPyun YongHyeon #define CSR_WRITE_2(sc, reg, val) \ 21270dbe28b3SPyun YongHyeon bus_write_2((sc)->msk_res[0], (reg), (val)) 21280dbe28b3SPyun YongHyeon #define CSR_WRITE_1(sc, reg, val) \ 21290dbe28b3SPyun YongHyeon bus_write_1((sc)->msk_res[0], (reg), (val)) 21300dbe28b3SPyun YongHyeon 21310dbe28b3SPyun YongHyeon #define CSR_READ_4(sc, reg) \ 21320dbe28b3SPyun YongHyeon bus_read_4((sc)->msk_res[0], (reg)) 21330dbe28b3SPyun YongHyeon #define CSR_READ_2(sc, reg) \ 21340dbe28b3SPyun YongHyeon bus_read_2((sc)->msk_res[0], (reg)) 21350dbe28b3SPyun YongHyeon #define CSR_READ_1(sc, reg) \ 21360dbe28b3SPyun YongHyeon bus_read_1((sc)->msk_res[0], (reg)) 21370dbe28b3SPyun YongHyeon 21380dbe28b3SPyun YongHyeon #define CSR_PCI_WRITE_4(sc, reg, val) \ 21390dbe28b3SPyun YongHyeon bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 21400dbe28b3SPyun YongHyeon #define CSR_PCI_WRITE_2(sc, reg, val) \ 21410dbe28b3SPyun YongHyeon bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 21420dbe28b3SPyun YongHyeon #define CSR_PCI_WRITE_1(sc, reg, val) \ 21430dbe28b3SPyun YongHyeon bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 21440dbe28b3SPyun YongHyeon 21450dbe28b3SPyun YongHyeon #define CSR_PCI_READ_4(sc, reg) \ 21460dbe28b3SPyun YongHyeon bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 21470dbe28b3SPyun YongHyeon #define CSR_PCI_READ_2(sc, reg) \ 21480dbe28b3SPyun YongHyeon bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 21490dbe28b3SPyun YongHyeon #define CSR_PCI_READ_1(sc, reg) \ 21500dbe28b3SPyun YongHyeon bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 21510dbe28b3SPyun YongHyeon 21520dbe28b3SPyun YongHyeon #define MSK_IF_READ_4(sc_if, reg) \ 21530dbe28b3SPyun YongHyeon CSR_READ_4((sc_if)->msk_softc, (reg)) 21540dbe28b3SPyun YongHyeon #define MSK_IF_READ_2(sc_if, reg) \ 21550dbe28b3SPyun YongHyeon CSR_READ_2((sc_if)->msk_softc, (reg)) 21560dbe28b3SPyun YongHyeon #define MSK_IF_READ_1(sc_if, reg) \ 21570dbe28b3SPyun YongHyeon CSR_READ_1((sc_if)->msk_softc, (reg)) 21580dbe28b3SPyun YongHyeon 21590dbe28b3SPyun YongHyeon #define MSK_IF_WRITE_4(sc_if, reg, val) \ 21600dbe28b3SPyun YongHyeon CSR_WRITE_4((sc_if)->msk_softc, (reg), (val)) 21610dbe28b3SPyun YongHyeon #define MSK_IF_WRITE_2(sc_if, reg, val) \ 21620dbe28b3SPyun YongHyeon CSR_WRITE_2((sc_if)->msk_softc, (reg), (val)) 21630dbe28b3SPyun YongHyeon #define MSK_IF_WRITE_1(sc_if, reg, val) \ 21640dbe28b3SPyun YongHyeon CSR_WRITE_1((sc_if)->msk_softc, (reg), (val)) 21650dbe28b3SPyun YongHyeon 21660dbe28b3SPyun YongHyeon #define GMAC_REG(port, reg) \ 21670dbe28b3SPyun YongHyeon ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg)) 21680dbe28b3SPyun YongHyeon #define GMAC_WRITE_2(sc, port, reg, val) \ 21690dbe28b3SPyun YongHyeon CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val)) 21700dbe28b3SPyun YongHyeon #define GMAC_READ_2(sc, port, reg) \ 21710dbe28b3SPyun YongHyeon CSR_READ_2((sc), GMAC_REG((port), (reg))) 21720dbe28b3SPyun YongHyeon 21730dbe28b3SPyun YongHyeon /* GPHY address (bits 15..11 of SMI control reg) */ 21740dbe28b3SPyun YongHyeon #define PHY_ADDR_MARV 0 21750dbe28b3SPyun YongHyeon 21760dbe28b3SPyun YongHyeon #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 21770dbe28b3SPyun YongHyeon #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 21780dbe28b3SPyun YongHyeon 217997c477f8SPyun YongHyeon #define MSK_RING_ALIGN 32768 218097c477f8SPyun YongHyeon #define MSK_STAT_ALIGN 32768 21810dbe28b3SPyun YongHyeon 21820dbe28b3SPyun YongHyeon /* Rx descriptor data structure */ 21830dbe28b3SPyun YongHyeon struct msk_rx_desc { 21840dbe28b3SPyun YongHyeon uint32_t msk_addr; 21850dbe28b3SPyun YongHyeon uint32_t msk_control; 21860dbe28b3SPyun YongHyeon }; 21870dbe28b3SPyun YongHyeon 21880dbe28b3SPyun YongHyeon /* Tx descriptor data structure */ 21890dbe28b3SPyun YongHyeon struct msk_tx_desc { 21900dbe28b3SPyun YongHyeon uint32_t msk_addr; 21910dbe28b3SPyun YongHyeon uint32_t msk_control; 21920dbe28b3SPyun YongHyeon }; 21930dbe28b3SPyun YongHyeon 21940dbe28b3SPyun YongHyeon /* Status descriptor data structure */ 21950dbe28b3SPyun YongHyeon struct msk_stat_desc { 21960dbe28b3SPyun YongHyeon uint32_t msk_status; 21970dbe28b3SPyun YongHyeon uint32_t msk_control; 21980dbe28b3SPyun YongHyeon }; 21990dbe28b3SPyun YongHyeon 22000dbe28b3SPyun YongHyeon /* mask and shift value to get Tx async queue status for port 1 */ 22010dbe28b3SPyun YongHyeon #define STLE_TXA1_MSKL 0x00000fff 22020dbe28b3SPyun YongHyeon #define STLE_TXA1_SHIFTL 0 22030dbe28b3SPyun YongHyeon 22040dbe28b3SPyun YongHyeon /* mask and shift value to get Tx sync queue status for port 1 */ 22050dbe28b3SPyun YongHyeon #define STLE_TXS1_MSKL 0x00fff000 22060dbe28b3SPyun YongHyeon #define STLE_TXS1_SHIFTL 12 22070dbe28b3SPyun YongHyeon 22080dbe28b3SPyun YongHyeon /* mask and shift value to get Tx async queue status for port 2 */ 22090dbe28b3SPyun YongHyeon #define STLE_TXA2_MSKL 0xff000000 22100dbe28b3SPyun YongHyeon #define STLE_TXA2_SHIFTL 24 22110dbe28b3SPyun YongHyeon #define STLE_TXA2_MSKH 0x000f 22120dbe28b3SPyun YongHyeon /* this one shifts up */ 22130dbe28b3SPyun YongHyeon #define STLE_TXA2_SHIFTH 8 22140dbe28b3SPyun YongHyeon 22150dbe28b3SPyun YongHyeon /* mask and shift value to get Tx sync queue status for port 2 */ 22160dbe28b3SPyun YongHyeon #define STLE_TXS2_MSKL 0x00000000 22170dbe28b3SPyun YongHyeon #define STLE_TXS2_SHIFTL 0 22180dbe28b3SPyun YongHyeon #define STLE_TXS2_MSKH 0xfff0 22190dbe28b3SPyun YongHyeon #define STLE_TXS2_SHIFTH 4 22200dbe28b3SPyun YongHyeon 22210dbe28b3SPyun YongHyeon /* YUKON-2 bit values */ 22220dbe28b3SPyun YongHyeon #define HW_OWNER 0x80000000 22230dbe28b3SPyun YongHyeon #define SW_OWNER 0x00000000 22240dbe28b3SPyun YongHyeon 22250dbe28b3SPyun YongHyeon #define PU_PUTIDX_VALID 0x10000000 22260dbe28b3SPyun YongHyeon 22270dbe28b3SPyun YongHyeon /* YUKON-2 Control flags */ 22280dbe28b3SPyun YongHyeon #define UDPTCP 0x00010000 22290dbe28b3SPyun YongHyeon #define CALSUM 0x00020000 22300dbe28b3SPyun YongHyeon #define WR_SUM 0x00040000 22310dbe28b3SPyun YongHyeon #define INIT_SUM 0x00080000 22320dbe28b3SPyun YongHyeon #define LOCK_SUM 0x00100000 22330dbe28b3SPyun YongHyeon #define INS_VLAN 0x00200000 22340dbe28b3SPyun YongHyeon #define FRC_STAT 0x00400000 22350dbe28b3SPyun YongHyeon #define EOP 0x00800000 22360dbe28b3SPyun YongHyeon 22370dbe28b3SPyun YongHyeon #define TX_LOCK 0x01000000 22380dbe28b3SPyun YongHyeon #define BUF_SEND 0x02000000 22390dbe28b3SPyun YongHyeon #define PACKET_SEND 0x04000000 22400dbe28b3SPyun YongHyeon 22410dbe28b3SPyun YongHyeon #define NO_WARNING 0x40000000 22420dbe28b3SPyun YongHyeon #define NO_UPDATE 0x80000000 22430dbe28b3SPyun YongHyeon 22440dbe28b3SPyun YongHyeon /* YUKON-2 Rx/Tx opcodes defines */ 22450dbe28b3SPyun YongHyeon #define OP_TCPWRITE 0x11000000 22460dbe28b3SPyun YongHyeon #define OP_TCPSTART 0x12000000 22470dbe28b3SPyun YongHyeon #define OP_TCPINIT 0x14000000 22480dbe28b3SPyun YongHyeon #define OP_TCPLCK 0x18000000 22490dbe28b3SPyun YongHyeon #define OP_TCPCHKSUM OP_TCPSTART 22500dbe28b3SPyun YongHyeon #define OP_TCPIS (OP_TCPINIT | OP_TCPSTART) 22510dbe28b3SPyun YongHyeon #define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE) 22520dbe28b3SPyun YongHyeon #define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE) 22530dbe28b3SPyun YongHyeon #define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE) 22540dbe28b3SPyun YongHyeon #define OP_ADDR64 0x21000000 22550dbe28b3SPyun YongHyeon #define OP_VLAN 0x22000000 22560dbe28b3SPyun YongHyeon #define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN) 22570dbe28b3SPyun YongHyeon #define OP_LRGLEN 0x24000000 22580dbe28b3SPyun YongHyeon #define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN) 2259262e9dcfSPyun YongHyeon #define OP_MSS 0x28000000 2260262e9dcfSPyun YongHyeon #define OP_MSSVLAN (OP_MSS | OP_VLAN) 22610dbe28b3SPyun YongHyeon #define OP_BUFFER 0x40000000 22620dbe28b3SPyun YongHyeon #define OP_PACKET 0x41000000 22630dbe28b3SPyun YongHyeon #define OP_LARGESEND 0x43000000 22640dbe28b3SPyun YongHyeon 22650dbe28b3SPyun YongHyeon /* YUKON-2 STATUS opcodes defines */ 22660dbe28b3SPyun YongHyeon #define OP_RXSTAT 0x60000000 22670dbe28b3SPyun YongHyeon #define OP_RXTIMESTAMP 0x61000000 22680dbe28b3SPyun YongHyeon #define OP_RXVLAN 0x62000000 22690dbe28b3SPyun YongHyeon #define OP_RXCHKS 0x64000000 22700dbe28b3SPyun YongHyeon #define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN) 22710dbe28b3SPyun YongHyeon #define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN) 22720dbe28b3SPyun YongHyeon #define OP_RSS_HASH 0x65000000 22730dbe28b3SPyun YongHyeon #define OP_TXINDEXLE 0x68000000 22740dbe28b3SPyun YongHyeon 22750dbe28b3SPyun YongHyeon /* YUKON-2 SPECIAL opcodes defines */ 22760dbe28b3SPyun YongHyeon #define OP_PUTIDX 0x70000000 22770dbe28b3SPyun YongHyeon 22780dbe28b3SPyun YongHyeon #define STLE_OP_MASK 0xff000000 2279efb74172SPyun YongHyeon #define STLE_CSS_MASK 0x00ff0000 22800dbe28b3SPyun YongHyeon #define STLE_LEN_MASK 0x0000ffff 22810dbe28b3SPyun YongHyeon 2282efb74172SPyun YongHyeon /* CSS defined in status LE(valid for descriptor V2 format). */ 2283efb74172SPyun YongHyeon #define CSS_TCPUDP_CSUM_OK 0x00800000 2284efb74172SPyun YongHyeon #define CSS_UDP 0x00400000 2285efb74172SPyun YongHyeon #define CSS_TCP 0x00200000 2286efb74172SPyun YongHyeon #define CSS_IPFRAG 0x00100000 2287efb74172SPyun YongHyeon #define CSS_IPV6 0x00080000 2288efb74172SPyun YongHyeon #define CSS_IPV4_CSUM_OK 0x00040000 2289efb74172SPyun YongHyeon #define CSS_IPV4 0x00020000 2290efb74172SPyun YongHyeon #define CSS_PORT 0x00010000 2291efb74172SPyun YongHyeon 22920dbe28b3SPyun YongHyeon /* Descriptor Bit Definition */ 22930dbe28b3SPyun YongHyeon /* TxCtrl Transmit Buffer Control Field */ 22940dbe28b3SPyun YongHyeon /* RxCtrl Receive Buffer Control Field */ 22950dbe28b3SPyun YongHyeon #define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */ 22960dbe28b3SPyun YongHyeon #define BMU_STF BIT_30 /* Start of Frame */ 22970dbe28b3SPyun YongHyeon #define BMU_EOF BIT_29 /* End of Frame */ 22980dbe28b3SPyun YongHyeon #define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */ 22990dbe28b3SPyun YongHyeon #define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */ 23000dbe28b3SPyun YongHyeon /* TxCtrl specific bits */ 23010dbe28b3SPyun YongHyeon #define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */ 23020dbe28b3SPyun YongHyeon #define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */ 23030dbe28b3SPyun YongHyeon #define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */ 23040dbe28b3SPyun YongHyeon /* RxCtrl specific bits */ 23050dbe28b3SPyun YongHyeon #define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */ 23060dbe28b3SPyun YongHyeon #define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */ 23070dbe28b3SPyun YongHyeon #define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */ 23080dbe28b3SPyun YongHyeon /* Bit 23..16: BMU Check Opcodes */ 23090dbe28b3SPyun YongHyeon #define BMU_CHECK (0x55<<16) /* Default BMU check */ 23100dbe28b3SPyun YongHyeon #define BMU_TCP_CHECK (0x56<<16) /* Descr with TCP ext */ 23110dbe28b3SPyun YongHyeon #define BMU_UDP_CHECK (0x57<<16) /* Descr with UDP ext (YUKON only) */ 23120dbe28b3SPyun YongHyeon #define BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */ 23130dbe28b3SPyun YongHyeon 2314355a415eSPyun YongHyeon /* 2315355a415eSPyun YongHyeon * Controller requires an additional LE op code for 64bit DMA operation. 2316355a415eSPyun YongHyeon * Driver uses fixed number of RX buffers such that this limitation 2317355a415eSPyun YongHyeon * reduces number of available RX buffers with 64bit DMA so double 2318355a415eSPyun YongHyeon * number of RX buffers on platforms that support 64bit DMA. For TX 2319355a415eSPyun YongHyeon * side, controller requires an additional OP_ADDR64 op code if a TX 2320355a415eSPyun YongHyeon * buffer uses different high address value than previously used one. 2321355a415eSPyun YongHyeon * Driver monitors high DMA address change in TX and inserts an 2322355a415eSPyun YongHyeon * OP_ADDR64 op code if the high DMA address is changed. Driver 2323355a415eSPyun YongHyeon * allocates 50% more total TX buffers on platforms that support 64bit 2324355a415eSPyun YongHyeon * DMA. 2325355a415eSPyun YongHyeon */ 2326355a415eSPyun YongHyeon #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 2327355a415eSPyun YongHyeon #define MSK_64BIT_DMA 2328355a415eSPyun YongHyeon #define MSK_TX_RING_CNT 384 2329355a415eSPyun YongHyeon #define MSK_RX_RING_CNT 512 2330355a415eSPyun YongHyeon #else 2331355a415eSPyun YongHyeon #undef MSK_64BIT_DMA 23320dbe28b3SPyun YongHyeon #define MSK_TX_RING_CNT 256 23330dbe28b3SPyun YongHyeon #define MSK_RX_RING_CNT 256 2334355a415eSPyun YongHyeon #endif 233583c04c93SPyun YongHyeon #define MSK_RX_BUF_ALIGN 8 23360dbe28b3SPyun YongHyeon #define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT 233752ee8ac0SPyun YongHyeon #define MSK_MAXTXSEGS 35 23388b51df84SPyun YongHyeon #define MSK_TSO_MAXSGSIZE 4096 2339a272ea16SPyun YongHyeon #define MSK_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 23400dbe28b3SPyun YongHyeon 23410dbe28b3SPyun YongHyeon /* 2342355a415eSPyun YongHyeon * It seems that the hardware requires extra descriptors(LEs) to offload 2343355a415eSPyun YongHyeon * TCP/UDP checksum, VLAN hardware tag insertion and TSO. 23440dbe28b3SPyun YongHyeon * 23450dbe28b3SPyun YongHyeon * 1 descriptor for TCP/UDP checksum offload. 23460dbe28b3SPyun YongHyeon * 1 descriptor VLAN hardware tag insertion. 23470dbe28b3SPyun YongHyeon * 1 descriptor for TSO(TCP Segmentation Offload) 2348355a415eSPyun YongHyeon * 1 descriptor for each 64bits DMA transfers 23490dbe28b3SPyun YongHyeon */ 2350355a415eSPyun YongHyeon #ifdef MSK_64BIT_DMA 2351355a415eSPyun YongHyeon #define MSK_RESERVED_TX_DESC_CNT (MSK_MAXTXSEGS + 3) 2352355a415eSPyun YongHyeon #else 23530dbe28b3SPyun YongHyeon #define MSK_RESERVED_TX_DESC_CNT 3 2354355a415eSPyun YongHyeon #endif 23550dbe28b3SPyun YongHyeon 23560dbe28b3SPyun YongHyeon #define MSK_JUMBO_FRAMELEN 9022 23570dbe28b3SPyun YongHyeon #define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 23580dbe28b3SPyun YongHyeon #define MSK_MAX_FRAMELEN \ 23590dbe28b3SPyun YongHyeon (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) 23600dbe28b3SPyun YongHyeon #define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 23610dbe28b3SPyun YongHyeon 23620dbe28b3SPyun YongHyeon struct msk_txdesc { 23630dbe28b3SPyun YongHyeon struct mbuf *tx_m; 23640dbe28b3SPyun YongHyeon bus_dmamap_t tx_dmamap; 23650dbe28b3SPyun YongHyeon struct msk_tx_desc *tx_le; 23660dbe28b3SPyun YongHyeon }; 23670dbe28b3SPyun YongHyeon 23680dbe28b3SPyun YongHyeon struct msk_rxdesc { 23690dbe28b3SPyun YongHyeon struct mbuf *rx_m; 23700dbe28b3SPyun YongHyeon bus_dmamap_t rx_dmamap; 23710dbe28b3SPyun YongHyeon struct msk_rx_desc *rx_le; 23720dbe28b3SPyun YongHyeon }; 23730dbe28b3SPyun YongHyeon 23740dbe28b3SPyun YongHyeon struct msk_chain_data { 23750dbe28b3SPyun YongHyeon bus_dma_tag_t msk_parent_tag; 23760dbe28b3SPyun YongHyeon bus_dma_tag_t msk_tx_tag; 23770dbe28b3SPyun YongHyeon struct msk_txdesc msk_txdesc[MSK_TX_RING_CNT]; 23780dbe28b3SPyun YongHyeon bus_dma_tag_t msk_rx_tag; 23790dbe28b3SPyun YongHyeon struct msk_rxdesc msk_rxdesc[MSK_RX_RING_CNT]; 23800dbe28b3SPyun YongHyeon bus_dma_tag_t msk_tx_ring_tag; 23810dbe28b3SPyun YongHyeon bus_dma_tag_t msk_rx_ring_tag; 23820dbe28b3SPyun YongHyeon bus_dmamap_t msk_tx_ring_map; 23830dbe28b3SPyun YongHyeon bus_dmamap_t msk_rx_ring_map; 23840dbe28b3SPyun YongHyeon bus_dmamap_t msk_rx_sparemap; 23850dbe28b3SPyun YongHyeon bus_dma_tag_t msk_jumbo_rx_tag; 23860dbe28b3SPyun YongHyeon struct msk_rxdesc msk_jumbo_rxdesc[MSK_JUMBO_RX_RING_CNT]; 23870dbe28b3SPyun YongHyeon bus_dma_tag_t msk_jumbo_rx_ring_tag; 23880dbe28b3SPyun YongHyeon bus_dmamap_t msk_jumbo_rx_ring_map; 23890dbe28b3SPyun YongHyeon bus_dmamap_t msk_jumbo_rx_sparemap; 23900dbe28b3SPyun YongHyeon uint16_t msk_tso_mtu; 23911b7757c0SPyun YongHyeon uint32_t msk_last_csum; 2392355a415eSPyun YongHyeon uint32_t msk_tx_high_addr; 23930dbe28b3SPyun YongHyeon int msk_tx_prod; 23940dbe28b3SPyun YongHyeon int msk_tx_cons; 23950dbe28b3SPyun YongHyeon int msk_tx_cnt; 23960dbe28b3SPyun YongHyeon int msk_tx_put; 23970dbe28b3SPyun YongHyeon int msk_rx_cons; 23980dbe28b3SPyun YongHyeon int msk_rx_prod; 23990dbe28b3SPyun YongHyeon int msk_rx_putwm; 24000dbe28b3SPyun YongHyeon }; 24010dbe28b3SPyun YongHyeon 24020dbe28b3SPyun YongHyeon struct msk_ring_data { 24030dbe28b3SPyun YongHyeon struct msk_tx_desc *msk_tx_ring; 24040dbe28b3SPyun YongHyeon bus_addr_t msk_tx_ring_paddr; 24050dbe28b3SPyun YongHyeon struct msk_rx_desc *msk_rx_ring; 24060dbe28b3SPyun YongHyeon bus_addr_t msk_rx_ring_paddr; 24070dbe28b3SPyun YongHyeon struct msk_rx_desc *msk_jumbo_rx_ring; 24080dbe28b3SPyun YongHyeon bus_addr_t msk_jumbo_rx_ring_paddr; 24090dbe28b3SPyun YongHyeon }; 24100dbe28b3SPyun YongHyeon 24110dbe28b3SPyun YongHyeon #define MSK_TX_RING_ADDR(sc, i) \ 24120dbe28b3SPyun YongHyeon ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i)) 24130dbe28b3SPyun YongHyeon #define MSK_RX_RING_ADDR(sc, i) \ 24140dbe28b3SPyun YongHyeon ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 24150dbe28b3SPyun YongHyeon #define MSK_JUMBO_RX_RING_ADDR(sc, i) \ 24160dbe28b3SPyun YongHyeon ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 24170dbe28b3SPyun YongHyeon 24180dbe28b3SPyun YongHyeon #define MSK_TX_RING_SZ \ 24190dbe28b3SPyun YongHyeon (sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT) 24200dbe28b3SPyun YongHyeon #define MSK_RX_RING_SZ \ 24210dbe28b3SPyun YongHyeon (sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT) 24220dbe28b3SPyun YongHyeon #define MSK_JUMBO_RX_RING_SZ \ 24230dbe28b3SPyun YongHyeon (sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT) 24240dbe28b3SPyun YongHyeon 24250dbe28b3SPyun YongHyeon #define MSK_INC(x, y) (x) = (x + 1) % y 2426355a415eSPyun YongHyeon #ifdef MSK_64BIT_DMA 2427355a415eSPyun YongHyeon #define MSK_RX_INC(x, y) (x) = (x + 2) % y 2428355a415eSPyun YongHyeon #define MSK_RX_BUF_CNT (MSK_RX_RING_CNT / 2) 2429355a415eSPyun YongHyeon #define MSK_JUMBO_RX_BUF_CNT (MSK_JUMBO_RX_RING_CNT / 2) 2430355a415eSPyun YongHyeon #else 2431355a415eSPyun YongHyeon #define MSK_RX_INC(x, y) (x) = (x + 1) % y 2432355a415eSPyun YongHyeon #define MSK_RX_BUF_CNT MSK_RX_RING_CNT 2433355a415eSPyun YongHyeon #define MSK_JUMBO_RX_BUF_CNT MSK_JUMBO_RX_RING_CNT 2434355a415eSPyun YongHyeon #endif 24350dbe28b3SPyun YongHyeon 24360dbe28b3SPyun YongHyeon #define MSK_PCI_BUS 0 24370dbe28b3SPyun YongHyeon #define MSK_PCIX_BUS 1 24380dbe28b3SPyun YongHyeon #define MSK_PEX_BUS 2 24390dbe28b3SPyun YongHyeon 24400dbe28b3SPyun YongHyeon #define MSK_PROC_DEFAULT (MSK_RX_RING_CNT / 2) 24410dbe28b3SPyun YongHyeon #define MSK_PROC_MIN 30 24420dbe28b3SPyun YongHyeon #define MSK_PROC_MAX (MSK_RX_RING_CNT - 1) 24430dbe28b3SPyun YongHyeon 2444cf570c1fSPyun YongHyeon #define MSK_INT_HOLDOFF_DEFAULT 100 2445cf570c1fSPyun YongHyeon 24460dbe28b3SPyun YongHyeon #define MSK_TX_TIMEOUT 5 24470dbe28b3SPyun YongHyeon #define MSK_PUT_WM 10 24480dbe28b3SPyun YongHyeon 2449fcb62a8bSPyun YongHyeon struct msk_mii_data { 2450fcb62a8bSPyun YongHyeon int port; 2451fcb62a8bSPyun YongHyeon uint32_t pmd; 2452fcb62a8bSPyun YongHyeon int mii_flags; 2453fcb62a8bSPyun YongHyeon }; 2454fcb62a8bSPyun YongHyeon 24550dbe28b3SPyun YongHyeon /* Forward decl. */ 24560dbe28b3SPyun YongHyeon struct msk_if_softc; 24570dbe28b3SPyun YongHyeon 24583a91ee71SPyun YongHyeon struct msk_hw_stats { 24593a91ee71SPyun YongHyeon /* Rx stats. */ 24603a91ee71SPyun YongHyeon uint32_t rx_ucast_frames; 24613a91ee71SPyun YongHyeon uint32_t rx_bcast_frames; 24623a91ee71SPyun YongHyeon uint32_t rx_pause_frames; 24633a91ee71SPyun YongHyeon uint32_t rx_mcast_frames; 24643a91ee71SPyun YongHyeon uint32_t rx_crc_errs; 24653a91ee71SPyun YongHyeon uint32_t rx_spare1; 24663a91ee71SPyun YongHyeon uint64_t rx_good_octets; 24673a91ee71SPyun YongHyeon uint64_t rx_bad_octets; 24683a91ee71SPyun YongHyeon uint32_t rx_runts; 24693a91ee71SPyun YongHyeon uint32_t rx_runt_errs; 24703a91ee71SPyun YongHyeon uint32_t rx_pkts_64; 24713a91ee71SPyun YongHyeon uint32_t rx_pkts_65_127; 24723a91ee71SPyun YongHyeon uint32_t rx_pkts_128_255; 24733a91ee71SPyun YongHyeon uint32_t rx_pkts_256_511; 24743a91ee71SPyun YongHyeon uint32_t rx_pkts_512_1023; 24753a91ee71SPyun YongHyeon uint32_t rx_pkts_1024_1518; 24763a91ee71SPyun YongHyeon uint32_t rx_pkts_1519_max; 24773a91ee71SPyun YongHyeon uint32_t rx_pkts_too_long; 24783a91ee71SPyun YongHyeon uint32_t rx_pkts_jabbers; 24793a91ee71SPyun YongHyeon uint32_t rx_spare2; 24803a91ee71SPyun YongHyeon uint32_t rx_fifo_oflows; 24813a91ee71SPyun YongHyeon uint32_t rx_spare3; 24823a91ee71SPyun YongHyeon /* Tx stats. */ 24833a91ee71SPyun YongHyeon uint32_t tx_ucast_frames; 24843a91ee71SPyun YongHyeon uint32_t tx_bcast_frames; 24853a91ee71SPyun YongHyeon uint32_t tx_pause_frames; 24863a91ee71SPyun YongHyeon uint32_t tx_mcast_frames; 24873a91ee71SPyun YongHyeon uint64_t tx_octets; 24883a91ee71SPyun YongHyeon uint32_t tx_pkts_64; 24893a91ee71SPyun YongHyeon uint32_t tx_pkts_65_127; 24903a91ee71SPyun YongHyeon uint32_t tx_pkts_128_255; 24913a91ee71SPyun YongHyeon uint32_t tx_pkts_256_511; 24923a91ee71SPyun YongHyeon uint32_t tx_pkts_512_1023; 24933a91ee71SPyun YongHyeon uint32_t tx_pkts_1024_1518; 24943a91ee71SPyun YongHyeon uint32_t tx_pkts_1519_max; 24953a91ee71SPyun YongHyeon uint32_t tx_spare1; 24963a91ee71SPyun YongHyeon uint32_t tx_colls; 24973a91ee71SPyun YongHyeon uint32_t tx_late_colls; 24983a91ee71SPyun YongHyeon uint32_t tx_excess_colls; 24993a91ee71SPyun YongHyeon uint32_t tx_multi_colls; 25003a91ee71SPyun YongHyeon uint32_t tx_single_colls; 25013a91ee71SPyun YongHyeon uint32_t tx_underflows; 25023a91ee71SPyun YongHyeon }; 25033a91ee71SPyun YongHyeon 25040dbe28b3SPyun YongHyeon /* Softc for the Marvell Yukon II controller. */ 25050dbe28b3SPyun YongHyeon struct msk_softc { 2506298946a9SPyun YongHyeon struct resource *msk_res[1]; /* I/O resource */ 25070dbe28b3SPyun YongHyeon struct resource_spec *msk_res_spec; 2508c72f075aSPyun YongHyeon struct resource *msk_irq[1]; /* IRQ resources */ 2509298946a9SPyun YongHyeon struct resource_spec *msk_irq_spec; 2510c72f075aSPyun YongHyeon void *msk_intrhand; /* irq handler handle */ 25110dbe28b3SPyun YongHyeon device_t msk_dev; 25120dbe28b3SPyun YongHyeon uint8_t msk_hw_id; 25130dbe28b3SPyun YongHyeon uint8_t msk_hw_rev; 25140dbe28b3SPyun YongHyeon uint8_t msk_bustype; 25150dbe28b3SPyun YongHyeon uint8_t msk_num_port; 25167420e9dcSPyun YongHyeon int msk_expcap; 25177420e9dcSPyun YongHyeon int msk_pcixcap; 25180dbe28b3SPyun YongHyeon int msk_ramsize; /* amount of SRAM on NIC */ 25190dbe28b3SPyun YongHyeon uint32_t msk_pmd; /* physical media type */ 25200dbe28b3SPyun YongHyeon uint32_t msk_intrmask; 25210dbe28b3SPyun YongHyeon uint32_t msk_intrhwemask; 252283c04c93SPyun YongHyeon uint32_t msk_pflags; 25230dbe28b3SPyun YongHyeon int msk_clock; 25240dbe28b3SPyun YongHyeon struct msk_if_softc *msk_if[2]; 25250dbe28b3SPyun YongHyeon device_t msk_devs[2]; 25260dbe28b3SPyun YongHyeon int msk_txqsize; 25270dbe28b3SPyun YongHyeon int msk_rxqsize; 25280dbe28b3SPyun YongHyeon int msk_txqstart[2]; 25290dbe28b3SPyun YongHyeon int msk_txqend[2]; 25300dbe28b3SPyun YongHyeon int msk_rxqstart[2]; 25310dbe28b3SPyun YongHyeon int msk_rxqend[2]; 25320dbe28b3SPyun YongHyeon bus_dma_tag_t msk_stat_tag; 25330dbe28b3SPyun YongHyeon bus_dmamap_t msk_stat_map; 25340dbe28b3SPyun YongHyeon struct msk_stat_desc *msk_stat_ring; 25350dbe28b3SPyun YongHyeon bus_addr_t msk_stat_ring_paddr; 2536cf570c1fSPyun YongHyeon int msk_int_holdoff; 25370dbe28b3SPyun YongHyeon int msk_process_limit; 25380dbe28b3SPyun YongHyeon int msk_stat_cons; 2539355a415eSPyun YongHyeon int msk_stat_count; 25400dbe28b3SPyun YongHyeon struct mtx msk_mtx; 25410dbe28b3SPyun YongHyeon }; 25420dbe28b3SPyun YongHyeon 25430dbe28b3SPyun YongHyeon #define MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx) 25440dbe28b3SPyun YongHyeon #define MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx) 25450dbe28b3SPyun YongHyeon #define MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED) 25460dbe28b3SPyun YongHyeon #define MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc) 25470dbe28b3SPyun YongHyeon #define MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc) 25480dbe28b3SPyun YongHyeon #define MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc) 25490dbe28b3SPyun YongHyeon 25500dbe28b3SPyun YongHyeon #define MSK_USECS(sc, us) ((sc)->msk_clock * (us)) 25510dbe28b3SPyun YongHyeon 25520dbe28b3SPyun YongHyeon /* Softc for each logical interface. */ 25530dbe28b3SPyun YongHyeon struct msk_if_softc { 25545ab8c4b8SJustin Hibbits if_t msk_ifp; /* interface info */ 25550dbe28b3SPyun YongHyeon device_t msk_miibus; 25560dbe28b3SPyun YongHyeon device_t msk_if_dev; 25570dbe28b3SPyun YongHyeon int32_t msk_port; /* port # on controller */ 25580dbe28b3SPyun YongHyeon int msk_framesize; 25590dbe28b3SPyun YongHyeon int msk_phytype; 25600dbe28b3SPyun YongHyeon int msk_phyaddr; 256183c04c93SPyun YongHyeon uint32_t msk_flags; 25627a76e8a4SPyun YongHyeon #define MSK_FLAG_MSI 0x0001 2563e2b16603SPyun YongHyeon #define MSK_FLAG_FASTETHER 0x0004 2564e2b16603SPyun YongHyeon #define MSK_FLAG_JUMBO 0x0008 2565e2b16603SPyun YongHyeon #define MSK_FLAG_JUMBO_NOCSUM 0x0010 2566e2b16603SPyun YongHyeon #define MSK_FLAG_RAMBUF 0x0020 2567262e9dcfSPyun YongHyeon #define MSK_FLAG_DESCV2 0x0040 2568ebb25bfaSPyun YongHyeon #define MSK_FLAG_AUTOTX_CSUM 0x0080 2569ebb25bfaSPyun YongHyeon #define MSK_FLAG_NOHWVLAN 0x0100 2570ebb25bfaSPyun YongHyeon #define MSK_FLAG_NORXCHK 0x0200 2571efb74172SPyun YongHyeon #define MSK_FLAG_NORX_CSUM 0x0400 2572ab7df1e4SPyun YongHyeon #define MSK_FLAG_SUSPEND 0x2000 25737a76e8a4SPyun YongHyeon #define MSK_FLAG_DETACH 0x4000 2574ab7df1e4SPyun YongHyeon #define MSK_FLAG_LINK 0x8000 25750dbe28b3SPyun YongHyeon struct callout msk_tick_ch; 25762271eac7SPyun YongHyeon int msk_watchdog_timer; 25770dbe28b3SPyun YongHyeon uint32_t msk_txq; /* Tx. Async Queue offset */ 25780dbe28b3SPyun YongHyeon uint32_t msk_txsq; /* Tx. Syn Queue offset */ 25790dbe28b3SPyun YongHyeon uint32_t msk_rxq; /* Rx. Qeueue offset */ 25800dbe28b3SPyun YongHyeon struct msk_chain_data msk_cdata; 25810dbe28b3SPyun YongHyeon struct msk_ring_data msk_rdata; 25820dbe28b3SPyun YongHyeon struct msk_softc *msk_softc; /* parent controller */ 25833a91ee71SPyun YongHyeon struct msk_hw_stats msk_stats; 25840dbe28b3SPyun YongHyeon int msk_if_flags; 25850dbe28b3SPyun YongHyeon uint16_t msk_vtag; /* VLAN tag id. */ 2586388214e4SPyun YongHyeon uint32_t msk_csum; 25870dbe28b3SPyun YongHyeon }; 25880dbe28b3SPyun YongHyeon 25890dbe28b3SPyun YongHyeon #define MSK_TIMEOUT 1000 25900dbe28b3SPyun YongHyeon #define MSK_PHY_POWERUP 1 25910dbe28b3SPyun YongHyeon #define MSK_PHY_POWERDOWN 0 2592