1 /*- 2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <vm/uma.h> 41 #include <machine/stdarg.h> 42 #include <machine/resource.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <dev/pci/pcivar.h> 46 #include "mvs.h" 47 48 #include <cam/cam.h> 49 #include <cam/cam_ccb.h> 50 #include <cam/cam_sim.h> 51 #include <cam/cam_xpt_sim.h> 52 #include <cam/cam_debug.h> 53 54 /* local prototypes */ 55 static int mvs_ch_init(device_t dev); 56 static int mvs_ch_deinit(device_t dev); 57 static int mvs_ch_suspend(device_t dev); 58 static int mvs_ch_resume(device_t dev); 59 static void mvs_dmainit(device_t dev); 60 static void mvs_dmasetupc_cb(void *xsc, 61 bus_dma_segment_t *segs, int nsegs, int error); 62 static void mvs_dmafini(device_t dev); 63 static void mvs_slotsalloc(device_t dev); 64 static void mvs_slotsfree(device_t dev); 65 static void mvs_setup_edma_queues(device_t dev); 66 static void mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode); 67 static void mvs_ch_pm(void *arg); 68 static void mvs_ch_intr_locked(void *data); 69 static void mvs_ch_intr(void *data); 70 static void mvs_reset(device_t dev); 71 static void mvs_softreset(device_t dev, union ccb *ccb); 72 73 static int mvs_sata_connect(struct mvs_channel *ch); 74 static int mvs_sata_phy_reset(device_t dev); 75 static int mvs_wait(device_t dev, u_int s, u_int c, int t); 76 static void mvs_tfd_read(device_t dev, union ccb *ccb); 77 static void mvs_tfd_write(device_t dev, union ccb *ccb); 78 static void mvs_legacy_intr(device_t dev); 79 static void mvs_crbq_intr(device_t dev); 80 static void mvs_begin_transaction(device_t dev, union ccb *ccb); 81 static void mvs_legacy_execute_transaction(struct mvs_slot *slot); 82 static void mvs_timeout(struct mvs_slot *slot); 83 static void mvs_dmasetprd(void *arg, 84 bus_dma_segment_t *segs, int nsegs, int error); 85 static void mvs_requeue_frozen(device_t dev); 86 static void mvs_execute_transaction(struct mvs_slot *slot); 87 static void mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et); 88 89 static void mvs_issue_read_log(device_t dev); 90 static void mvs_process_read_log(device_t dev, union ccb *ccb); 91 92 static void mvsaction(struct cam_sim *sim, union ccb *ccb); 93 static void mvspoll(struct cam_sim *sim); 94 95 MALLOC_DEFINE(M_MVS, "MVS driver", "MVS driver data buffers"); 96 97 static int 98 mvs_ch_probe(device_t dev) 99 { 100 101 device_set_desc_copy(dev, "Marvell SATA channel"); 102 return (0); 103 } 104 105 static int 106 mvs_ch_attach(device_t dev) 107 { 108 struct mvs_controller *ctlr = device_get_softc(device_get_parent(dev)); 109 struct mvs_channel *ch = device_get_softc(dev); 110 struct cam_devq *devq; 111 int rid, error, i, sata_rev = 0; 112 113 ch->dev = dev; 114 ch->unit = (intptr_t)device_get_ivars(dev); 115 ch->quirks = ctlr->quirks; 116 mtx_init(&ch->mtx, "MVS channel lock", NULL, MTX_DEF); 117 resource_int_value(device_get_name(dev), 118 device_get_unit(dev), "pm_level", &ch->pm_level); 119 if (ch->pm_level > 3) 120 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 121 resource_int_value(device_get_name(dev), 122 device_get_unit(dev), "sata_rev", &sata_rev); 123 for (i = 0; i < 16; i++) { 124 ch->user[i].revision = sata_rev; 125 ch->user[i].mode = 0; 126 ch->user[i].bytecount = (ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048; 127 ch->user[i].tags = MVS_MAX_SLOTS; 128 ch->curr[i] = ch->user[i]; 129 if (ch->pm_level) { 130 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 131 CTS_SATA_CAPS_H_APST | 132 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 133 } 134 } 135 rid = ch->unit; 136 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 137 &rid, RF_ACTIVE))) 138 return (ENXIO); 139 mvs_dmainit(dev); 140 mvs_slotsalloc(dev); 141 mvs_ch_init(dev); 142 mtx_lock(&ch->mtx); 143 rid = ATA_IRQ_RID; 144 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 145 &rid, RF_SHAREABLE | RF_ACTIVE))) { 146 device_printf(dev, "Unable to map interrupt\n"); 147 error = ENXIO; 148 goto err0; 149 } 150 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 151 mvs_ch_intr_locked, dev, &ch->ih))) { 152 device_printf(dev, "Unable to setup interrupt\n"); 153 error = ENXIO; 154 goto err1; 155 } 156 /* Create the device queue for our SIM. */ 157 devq = cam_simq_alloc(MVS_MAX_SLOTS - 1); 158 if (devq == NULL) { 159 device_printf(dev, "Unable to allocate simq\n"); 160 error = ENOMEM; 161 goto err1; 162 } 163 /* Construct SIM entry */ 164 ch->sim = cam_sim_alloc(mvsaction, mvspoll, "mvsch", ch, 165 device_get_unit(dev), &ch->mtx, 166 2, (ch->quirks & MVS_Q_GENI) ? 0 : MVS_MAX_SLOTS - 1, 167 devq); 168 if (ch->sim == NULL) { 169 cam_simq_free(devq); 170 device_printf(dev, "unable to allocate sim\n"); 171 error = ENOMEM; 172 goto err1; 173 } 174 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 175 device_printf(dev, "unable to register xpt bus\n"); 176 error = ENXIO; 177 goto err2; 178 } 179 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 180 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 181 device_printf(dev, "unable to create path\n"); 182 error = ENXIO; 183 goto err3; 184 } 185 if (ch->pm_level > 3) { 186 callout_reset(&ch->pm_timer, 187 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 188 mvs_ch_pm, dev); 189 } 190 mtx_unlock(&ch->mtx); 191 return (0); 192 193 err3: 194 xpt_bus_deregister(cam_sim_path(ch->sim)); 195 err2: 196 cam_sim_free(ch->sim, /*free_devq*/TRUE); 197 err1: 198 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 199 err0: 200 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 201 mtx_unlock(&ch->mtx); 202 mtx_destroy(&ch->mtx); 203 return (error); 204 } 205 206 static int 207 mvs_ch_detach(device_t dev) 208 { 209 struct mvs_channel *ch = device_get_softc(dev); 210 211 mtx_lock(&ch->mtx); 212 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 213 xpt_free_path(ch->path); 214 xpt_bus_deregister(cam_sim_path(ch->sim)); 215 cam_sim_free(ch->sim, /*free_devq*/TRUE); 216 mtx_unlock(&ch->mtx); 217 218 if (ch->pm_level > 3) 219 callout_drain(&ch->pm_timer); 220 bus_teardown_intr(dev, ch->r_irq, ch->ih); 221 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 222 223 mvs_ch_deinit(dev); 224 mvs_slotsfree(dev); 225 mvs_dmafini(dev); 226 227 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 228 mtx_destroy(&ch->mtx); 229 return (0); 230 } 231 232 static int 233 mvs_ch_init(device_t dev) 234 { 235 struct mvs_channel *ch = device_get_softc(dev); 236 uint32_t reg; 237 238 /* Disable port interrupts */ 239 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 240 /* Stop EDMA */ 241 ch->curr_mode = MVS_EDMA_UNKNOWN; 242 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 243 /* Clear and configure FIS interrupts. */ 244 ATA_OUTL(ch->r_mem, SATA_FISIC, 0); 245 reg = ATA_INL(ch->r_mem, SATA_FISC); 246 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1; 247 ATA_OUTL(ch->r_mem, SATA_FISC, reg); 248 reg = ATA_INL(ch->r_mem, SATA_FISIM); 249 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1; 250 ATA_OUTL(ch->r_mem, SATA_FISC, reg); 251 /* Clear SATA error register. */ 252 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 253 /* Clear any outstanding error interrupts. */ 254 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 255 /* Unmask all error interrupts */ 256 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 257 return (0); 258 } 259 260 static int 261 mvs_ch_deinit(device_t dev) 262 { 263 struct mvs_channel *ch = device_get_softc(dev); 264 265 /* Stop EDMA */ 266 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 267 /* Disable port interrupts. */ 268 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 269 return (0); 270 } 271 272 static int 273 mvs_ch_suspend(device_t dev) 274 { 275 struct mvs_channel *ch = device_get_softc(dev); 276 277 mtx_lock(&ch->mtx); 278 xpt_freeze_simq(ch->sim, 1); 279 while (ch->oslots) 280 msleep(ch, &ch->mtx, PRIBIO, "mvssusp", hz/100); 281 mvs_ch_deinit(dev); 282 mtx_unlock(&ch->mtx); 283 return (0); 284 } 285 286 static int 287 mvs_ch_resume(device_t dev) 288 { 289 struct mvs_channel *ch = device_get_softc(dev); 290 291 mtx_lock(&ch->mtx); 292 mvs_ch_init(dev); 293 mvs_reset(dev); 294 xpt_release_simq(ch->sim, TRUE); 295 mtx_unlock(&ch->mtx); 296 return (0); 297 } 298 299 struct mvs_dc_cb_args { 300 bus_addr_t maddr; 301 int error; 302 }; 303 304 static void 305 mvs_dmainit(device_t dev) 306 { 307 struct mvs_channel *ch = device_get_softc(dev); 308 struct mvs_dc_cb_args dcba; 309 310 /* EDMA command request area. */ 311 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 312 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 313 NULL, NULL, MVS_WORKRQ_SIZE, 1, MVS_WORKRQ_SIZE, 314 0, NULL, NULL, &ch->dma.workrq_tag)) 315 goto error; 316 if (bus_dmamem_alloc(ch->dma.workrq_tag, (void **)&ch->dma.workrq, 0, 317 &ch->dma.workrq_map)) 318 goto error; 319 if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map, 320 ch->dma.workrq, MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) || 321 dcba.error) { 322 bus_dmamem_free(ch->dma.workrq_tag, 323 ch->dma.workrq, ch->dma.workrq_map); 324 goto error; 325 } 326 ch->dma.workrq_bus = dcba.maddr; 327 /* EDMA command response area. */ 328 if (bus_dma_tag_create(bus_get_dma_tag(dev), 256, 0, 329 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 330 NULL, NULL, MVS_WORKRP_SIZE, 1, MVS_WORKRP_SIZE, 331 0, NULL, NULL, &ch->dma.workrp_tag)) 332 goto error; 333 if (bus_dmamem_alloc(ch->dma.workrp_tag, (void **)&ch->dma.workrp, 0, 334 &ch->dma.workrp_map)) 335 goto error; 336 if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map, 337 ch->dma.workrp, MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) || 338 dcba.error) { 339 bus_dmamem_free(ch->dma.workrp_tag, 340 ch->dma.workrp, ch->dma.workrp_map); 341 goto error; 342 } 343 ch->dma.workrp_bus = dcba.maddr; 344 /* Data area. */ 345 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, MVS_EPRD_MAX, 346 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 347 NULL, NULL, 348 MVS_SG_ENTRIES * PAGE_SIZE * MVS_MAX_SLOTS, 349 MVS_SG_ENTRIES, MVS_EPRD_MAX, 350 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 351 goto error; 352 } 353 return; 354 355 error: 356 device_printf(dev, "WARNING - DMA initialization failed\n"); 357 mvs_dmafini(dev); 358 } 359 360 static void 361 mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 362 { 363 struct mvs_dc_cb_args *dcba = (struct mvs_dc_cb_args *)xsc; 364 365 if (!(dcba->error = error)) 366 dcba->maddr = segs[0].ds_addr; 367 } 368 369 static void 370 mvs_dmafini(device_t dev) 371 { 372 struct mvs_channel *ch = device_get_softc(dev); 373 374 if (ch->dma.data_tag) { 375 bus_dma_tag_destroy(ch->dma.data_tag); 376 ch->dma.data_tag = NULL; 377 } 378 if (ch->dma.workrp_bus) { 379 bus_dmamap_unload(ch->dma.workrp_tag, ch->dma.workrp_map); 380 bus_dmamem_free(ch->dma.workrp_tag, 381 ch->dma.workrp, ch->dma.workrp_map); 382 ch->dma.workrp_bus = 0; 383 ch->dma.workrp_map = NULL; 384 ch->dma.workrp = NULL; 385 } 386 if (ch->dma.workrp_tag) { 387 bus_dma_tag_destroy(ch->dma.workrp_tag); 388 ch->dma.workrp_tag = NULL; 389 } 390 if (ch->dma.workrq_bus) { 391 bus_dmamap_unload(ch->dma.workrq_tag, ch->dma.workrq_map); 392 bus_dmamem_free(ch->dma.workrq_tag, 393 ch->dma.workrq, ch->dma.workrq_map); 394 ch->dma.workrq_bus = 0; 395 ch->dma.workrq_map = NULL; 396 ch->dma.workrq = NULL; 397 } 398 if (ch->dma.workrq_tag) { 399 bus_dma_tag_destroy(ch->dma.workrq_tag); 400 ch->dma.workrq_tag = NULL; 401 } 402 } 403 404 static void 405 mvs_slotsalloc(device_t dev) 406 { 407 struct mvs_channel *ch = device_get_softc(dev); 408 int i; 409 410 /* Alloc and setup command/dma slots */ 411 bzero(ch->slot, sizeof(ch->slot)); 412 for (i = 0; i < MVS_MAX_SLOTS; i++) { 413 struct mvs_slot *slot = &ch->slot[i]; 414 415 slot->dev = dev; 416 slot->slot = i; 417 slot->state = MVS_SLOT_EMPTY; 418 slot->ccb = NULL; 419 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 420 421 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 422 device_printf(ch->dev, "FAILURE - create data_map\n"); 423 } 424 } 425 426 static void 427 mvs_slotsfree(device_t dev) 428 { 429 struct mvs_channel *ch = device_get_softc(dev); 430 int i; 431 432 /* Free all dma slots */ 433 for (i = 0; i < MVS_MAX_SLOTS; i++) { 434 struct mvs_slot *slot = &ch->slot[i]; 435 436 callout_drain(&slot->timeout); 437 if (slot->dma.data_map) { 438 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 439 slot->dma.data_map = NULL; 440 } 441 } 442 } 443 444 static void 445 mvs_setup_edma_queues(device_t dev) 446 { 447 struct mvs_channel *ch = device_get_softc(dev); 448 uint64_t work; 449 450 /* Requests queue. */ 451 work = ch->dma.workrq_bus; 452 ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32); 453 ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff); 454 ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff); 455 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 456 BUS_DMASYNC_PREWRITE); 457 /* Reponses queue. */ 458 memset(ch->dma.workrp, 0xff, MVS_WORKRP_SIZE); 459 work = ch->dma.workrp_bus; 460 ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32); 461 ATA_OUTL(ch->r_mem, EDMA_RESQIP, work & 0xffffffff); 462 ATA_OUTL(ch->r_mem, EDMA_RESQOP, work & 0xffffffff); 463 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 464 BUS_DMASYNC_PREREAD); 465 ch->out_idx = 0; 466 ch->in_idx = 0; 467 } 468 469 static void 470 mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode) 471 { 472 struct mvs_channel *ch = device_get_softc(dev); 473 int timeout; 474 uint32_t ecfg, fcfg, hc, ltm, unkn; 475 476 if (mode == ch->curr_mode) 477 return; 478 /* If we are running, we should stop first. */ 479 if (ch->curr_mode != MVS_EDMA_OFF) { 480 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EDSEDMA); 481 timeout = 0; 482 while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) { 483 DELAY(1000); 484 if (timeout++ > 1000) { 485 device_printf(dev, "stopping EDMA engine failed\n"); 486 break; 487 } 488 }; 489 } 490 ch->curr_mode = mode; 491 ch->fbs_enabled = 0; 492 ch->fake_busy = 0; 493 /* Report mode to controller. Needed for correct CCC operation. */ 494 MVS_EDMA(device_get_parent(dev), dev, mode); 495 /* Configure new mode. */ 496 ecfg = EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2 | EDMA_CFG_EHOSTQUEUECACHEEN; 497 if (ch->pm_present) { 498 ecfg |= EDMA_CFG_EMASKRXPM; 499 if (ch->quirks & MVS_Q_GENIIE) { 500 ecfg |= EDMA_CFG_EEDMAFBS; 501 ch->fbs_enabled = 1; 502 } 503 } 504 if (ch->quirks & MVS_Q_GENI) 505 ecfg |= EDMA_CFG_ERDBSZ; 506 else if (ch->quirks & MVS_Q_GENII) 507 ecfg |= EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN; 508 if (ch->quirks & MVS_Q_CT) 509 ecfg |= EDMA_CFG_ECUTTHROUGHEN; 510 if (mode != MVS_EDMA_OFF) 511 ecfg |= EDMA_CFG_EEARLYCOMPLETIONEN; 512 if (mode == MVS_EDMA_QUEUED) 513 ecfg |= EDMA_CFG_EQUE; 514 else if (mode == MVS_EDMA_NCQ) 515 ecfg |= EDMA_CFG_ESATANATVCMDQUE; 516 ATA_OUTL(ch->r_mem, EDMA_CFG, ecfg); 517 mvs_setup_edma_queues(dev); 518 if (ch->quirks & MVS_Q_GENIIE) { 519 /* Configure FBS-related registers */ 520 fcfg = ATA_INL(ch->r_mem, SATA_FISC); 521 ltm = ATA_INL(ch->r_mem, SATA_LTM); 522 hc = ATA_INL(ch->r_mem, EDMA_HC); 523 if (ch->fbs_enabled) { 524 fcfg |= SATA_FISC_FISDMAACTIVATESYNCRESP; 525 if (mode == MVS_EDMA_NCQ) { 526 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0; 527 hc &= ~EDMA_IE_EDEVERR; 528 } else { 529 fcfg |= SATA_FISC_FISWAIT4HOSTRDYEN_B0; 530 hc |= EDMA_IE_EDEVERR; 531 } 532 ltm |= (1 << 8); 533 } else { 534 fcfg &= ~SATA_FISC_FISDMAACTIVATESYNCRESP; 535 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0; 536 hc |= EDMA_IE_EDEVERR; 537 ltm &= ~(1 << 8); 538 } 539 ATA_OUTL(ch->r_mem, SATA_FISC, fcfg); 540 ATA_OUTL(ch->r_mem, SATA_LTM, ltm); 541 ATA_OUTL(ch->r_mem, EDMA_HC, hc); 542 /* This is some magic, required to handle several DRQs 543 * with basic DMA. */ 544 unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD); 545 if (mode == MVS_EDMA_OFF) 546 unkn |= 1; 547 else 548 unkn &= ~1; 549 ATA_OUTL(ch->r_mem, EDMA_UNKN_RESD, unkn); 550 } 551 /* Run EDMA. */ 552 if (mode != MVS_EDMA_OFF) 553 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EENEDMA); 554 } 555 556 devclass_t mvs_devclass; 557 devclass_t mvsch_devclass; 558 static device_method_t mvsch_methods[] = { 559 DEVMETHOD(device_probe, mvs_ch_probe), 560 DEVMETHOD(device_attach, mvs_ch_attach), 561 DEVMETHOD(device_detach, mvs_ch_detach), 562 DEVMETHOD(device_suspend, mvs_ch_suspend), 563 DEVMETHOD(device_resume, mvs_ch_resume), 564 { 0, 0 } 565 }; 566 static driver_t mvsch_driver = { 567 "mvsch", 568 mvsch_methods, 569 sizeof(struct mvs_channel) 570 }; 571 DRIVER_MODULE(mvsch, mvs, mvsch_driver, mvsch_devclass, 0, 0); 572 DRIVER_MODULE(mvsch, sata, mvsch_driver, mvsch_devclass, 0, 0); 573 574 static void 575 mvs_phy_check_events(device_t dev, u_int32_t serr) 576 { 577 struct mvs_channel *ch = device_get_softc(dev); 578 579 if (ch->pm_level == 0) { 580 u_int32_t status = ATA_INL(ch->r_mem, SATA_SS); 581 union ccb *ccb; 582 583 if (bootverbose) { 584 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && 585 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && 586 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) { 587 device_printf(dev, "CONNECT requested\n"); 588 } else 589 device_printf(dev, "DISCONNECT requested\n"); 590 } 591 mvs_reset(dev); 592 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 593 return; 594 if (xpt_create_path(&ccb->ccb_h.path, NULL, 595 cam_sim_path(ch->sim), 596 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 597 xpt_free_ccb(ccb); 598 return; 599 } 600 xpt_rescan(ccb); 601 } 602 } 603 604 static void 605 mvs_notify_events(device_t dev) 606 { 607 struct mvs_channel *ch = device_get_softc(dev); 608 struct cam_path *dpath; 609 uint32_t fis; 610 int d; 611 612 /* Try to read PMP field from SDB FIS. Present only for Gen-IIe. */ 613 fis = ATA_INL(ch->r_mem, SATA_FISDW0); 614 if ((fis & 0x80ff) == 0x80a1) 615 d = (fis & 0x0f00) >> 8; 616 else 617 d = ch->pm_present ? 15 : 0; 618 if (bootverbose) 619 device_printf(dev, "SNTF %d\n", d); 620 if (xpt_create_path(&dpath, NULL, 621 xpt_path_path_id(ch->path), d, 0) == CAM_REQ_CMP) { 622 xpt_async(AC_SCSI_AEN, dpath, NULL); 623 xpt_free_path(dpath); 624 } 625 } 626 627 static void 628 mvs_ch_intr_locked(void *data) 629 { 630 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data; 631 device_t dev = (device_t)arg->arg; 632 struct mvs_channel *ch = device_get_softc(dev); 633 634 mtx_lock(&ch->mtx); 635 mvs_ch_intr(data); 636 mtx_unlock(&ch->mtx); 637 } 638 639 static void 640 mvs_ch_pm(void *arg) 641 { 642 device_t dev = (device_t)arg; 643 struct mvs_channel *ch = device_get_softc(dev); 644 uint32_t work; 645 646 if (ch->numrslots != 0) 647 return; 648 /* If we are idle - request power state transition. */ 649 work = ATA_INL(ch->r_mem, SATA_SC); 650 work &= ~SATA_SC_SPM_MASK; 651 if (ch->pm_level == 4) 652 work |= SATA_SC_SPM_PARTIAL; 653 else 654 work |= SATA_SC_SPM_SLUMBER; 655 ATA_OUTL(ch->r_mem, SATA_SC, work); 656 } 657 658 static void 659 mvs_ch_pm_wake(device_t dev) 660 { 661 struct mvs_channel *ch = device_get_softc(dev); 662 uint32_t work; 663 int timeout = 0; 664 665 work = ATA_INL(ch->r_mem, SATA_SS); 666 if (work & SATA_SS_IPM_ACTIVE) 667 return; 668 /* If we are not in active state - request power state transition. */ 669 work = ATA_INL(ch->r_mem, SATA_SC); 670 work &= ~SATA_SC_SPM_MASK; 671 work |= SATA_SC_SPM_ACTIVE; 672 ATA_OUTL(ch->r_mem, SATA_SC, work); 673 /* Wait for transition to happen. */ 674 while ((ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_IPM_ACTIVE) == 0 && 675 timeout++ < 100) { 676 DELAY(100); 677 } 678 } 679 680 static void 681 mvs_ch_intr(void *data) 682 { 683 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data; 684 device_t dev = (device_t)arg->arg; 685 struct mvs_channel *ch = device_get_softc(dev); 686 uint32_t iec, serr = 0, fisic = 0; 687 enum mvs_err_type et; 688 int i, ccs, port = -1, selfdis = 0; 689 int edma = (ch->numtslots != 0 || ch->numdslots != 0); 690 691 /* New item in response queue. */ 692 if ((arg->cause & 2) && edma) 693 mvs_crbq_intr(dev); 694 /* Some error or special event. */ 695 if (arg->cause & 1) { 696 iec = ATA_INL(ch->r_mem, EDMA_IEC); 697 if (iec & EDMA_IE_SERRINT) { 698 serr = ATA_INL(ch->r_mem, SATA_SE); 699 ATA_OUTL(ch->r_mem, SATA_SE, serr); 700 } 701 /* EDMA self-disabled due to error. */ 702 if (iec & EDMA_IE_ESELFDIS) 703 selfdis = 1; 704 /* Transport interrupt. */ 705 if (iec & EDMA_IE_ETRANSINT) { 706 /* For Gen-I this bit means self-disable. */ 707 if (ch->quirks & MVS_Q_GENI) 708 selfdis = 1; 709 /* For Gen-II this bit means SDB-N. */ 710 else if (ch->quirks & MVS_Q_GENII) 711 fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1; 712 else /* For Gen-IIe - read FIS interrupt cause. */ 713 fisic = ATA_INL(ch->r_mem, SATA_FISIC); 714 } 715 if (selfdis) 716 ch->curr_mode = MVS_EDMA_UNKNOWN; 717 ATA_OUTL(ch->r_mem, EDMA_IEC, ~iec); 718 /* Interface errors or Device error. */ 719 if (iec & (0xfc1e9000 | EDMA_IE_EDEVERR)) { 720 port = -1; 721 if (ch->numpslots != 0) { 722 ccs = 0; 723 } else { 724 if (ch->quirks & MVS_Q_GENIIE) 725 ccs = EDMA_S_EIOID(ATA_INL(ch->r_mem, EDMA_S)); 726 else 727 ccs = EDMA_S_EDEVQUETAG(ATA_INL(ch->r_mem, EDMA_S)); 728 /* Check if error is one-PMP-port-specific, */ 729 if (ch->fbs_enabled) { 730 /* Which ports were active. */ 731 for (i = 0; i < 16; i++) { 732 if (ch->numrslotspd[i] == 0) 733 continue; 734 if (port == -1) 735 port = i; 736 else if (port != i) { 737 port = -2; 738 break; 739 } 740 } 741 /* If several ports were active and EDMA still enabled - 742 * other ports are probably unaffected and may continue. 743 */ 744 if (port == -2 && !selfdis) { 745 uint16_t p = ATA_INL(ch->r_mem, SATA_SATAITC) >> 16; 746 port = ffs(p) - 1; 747 if (port != (fls(p) - 1)) 748 port = -2; 749 } 750 } 751 } 752 mvs_requeue_frozen(dev); 753 for (i = 0; i < MVS_MAX_SLOTS; i++) { 754 /* XXX: reqests in loading state. */ 755 if (((ch->rslots >> i) & 1) == 0) 756 continue; 757 if (port >= 0 && 758 ch->slot[i].ccb->ccb_h.target_id != port) 759 continue; 760 if (iec & EDMA_IE_EDEVERR) { /* Device error. */ 761 if (port != -2) { 762 if (ch->numtslots == 0) { 763 /* Untagged operation. */ 764 if (i == ccs) 765 et = MVS_ERR_TFE; 766 else 767 et = MVS_ERR_INNOCENT; 768 } else { 769 /* Tagged operation. */ 770 et = MVS_ERR_NCQ; 771 } 772 } else { 773 et = MVS_ERR_TFE; 774 ch->fatalerr = 1; 775 } 776 } else if (iec & 0xfc1e9000) { 777 if (ch->numtslots == 0 && 778 i != ccs && port != -2) 779 et = MVS_ERR_INNOCENT; 780 else 781 et = MVS_ERR_SATA; 782 } else 783 et = MVS_ERR_INVALID; 784 mvs_end_transaction(&ch->slot[i], et); 785 } 786 } 787 /* Process SDB-N. */ 788 if (fisic & SATA_FISC_FISWAIT4HOSTRDYEN_B1) 789 mvs_notify_events(dev); 790 if (fisic) 791 ATA_OUTL(ch->r_mem, SATA_FISIC, ~fisic); 792 /* Process hot-plug. */ 793 if ((iec & (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) || 794 (serr & SATA_SE_PHY_CHANGED)) 795 mvs_phy_check_events(dev, serr); 796 } 797 /* Legacy mode device interrupt. */ 798 if ((arg->cause & 2) && !edma) 799 mvs_legacy_intr(dev); 800 } 801 802 static uint8_t 803 mvs_getstatus(device_t dev, int clear) 804 { 805 struct mvs_channel *ch = device_get_softc(dev); 806 uint8_t status = ATA_INB(ch->r_mem, clear ? ATA_STATUS : ATA_ALTSTAT); 807 808 if (ch->fake_busy) { 809 if (status & (ATA_S_BUSY | ATA_S_DRQ | ATA_S_ERROR)) 810 ch->fake_busy = 0; 811 else 812 status |= ATA_S_BUSY; 813 } 814 return (status); 815 } 816 817 static void 818 mvs_legacy_intr(device_t dev) 819 { 820 struct mvs_channel *ch = device_get_softc(dev); 821 struct mvs_slot *slot = &ch->slot[0]; /* PIO is always in slot 0. */ 822 union ccb *ccb = slot->ccb; 823 enum mvs_err_type et = MVS_ERR_NONE; 824 int port; 825 u_int length; 826 uint8_t status, ireason; 827 828 /* Clear interrupt and get status. */ 829 status = mvs_getstatus(dev, 1); 830 if (slot->state < MVS_SLOT_RUNNING) 831 return; 832 port = ccb->ccb_h.target_id & 0x0f; 833 /* Wait a bit for late !BUSY status update. */ 834 if (status & ATA_S_BUSY) { 835 DELAY(100); 836 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) { 837 DELAY(1000); 838 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) 839 return; 840 } 841 } 842 /* If we got an error, we are done. */ 843 if (status & ATA_S_ERROR) { 844 et = MVS_ERR_TFE; 845 goto end_finished; 846 } 847 if (ccb->ccb_h.func_code == XPT_ATA_IO) { /* ATA PIO */ 848 ccb->ataio.res.status = status; 849 /* Are we moving data? */ 850 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 851 /* If data read command - get them. */ 852 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 853 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 854 device_printf(dev, "timeout waiting for read DRQ\n"); 855 et = MVS_ERR_TIMEOUT; 856 goto end_finished; 857 } 858 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 859 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 860 ch->transfersize / 2); 861 } 862 /* Update how far we've gotten. */ 863 ch->donecount += ch->transfersize; 864 /* Do we need more? */ 865 if (ccb->ataio.dxfer_len > ch->donecount) { 866 /* Set this transfer size according to HW capabilities */ 867 ch->transfersize = min(ccb->ataio.dxfer_len - ch->donecount, 868 ch->curr[ccb->ccb_h.target_id].bytecount); 869 /* If data write command - put them */ 870 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 871 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 872 device_printf(dev, 873 "timeout waiting for write DRQ\n"); 874 et = MVS_ERR_TIMEOUT; 875 goto end_finished; 876 } 877 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 878 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 879 ch->transfersize / 2); 880 return; 881 } 882 /* If data read command, return & wait for interrupt */ 883 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 884 return; 885 } 886 } 887 } else if (ch->basic_dma) { /* ATAPI DMA */ 888 if (status & ATA_S_DWF) 889 et = MVS_ERR_TFE; 890 else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR) 891 et = MVS_ERR_TFE; 892 /* Stop basic DMA. */ 893 ATA_OUTL(ch->r_mem, DMA_C, 0); 894 goto end_finished; 895 } else { /* ATAPI PIO */ 896 length = ATA_INB(ch->r_mem,ATA_CYL_LSB) | 897 (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8); 898 ireason = ATA_INB(ch->r_mem,ATA_IREASON); 899 switch ((ireason & (ATA_I_CMD | ATA_I_IN)) | 900 (status & ATA_S_DRQ)) { 901 902 case ATAPI_P_CMDOUT: 903 device_printf(dev, "ATAPI CMDOUT\n"); 904 /* Return wait for interrupt */ 905 return; 906 907 case ATAPI_P_WRITE: 908 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 909 device_printf(dev, "trying to write on read buffer\n"); 910 et = MVS_ERR_TFE; 911 goto end_finished; 912 break; 913 } 914 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 915 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 916 length / 2); 917 ch->donecount += length; 918 /* Set next transfer size according to HW capabilities */ 919 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, 920 ch->curr[ccb->ccb_h.target_id].bytecount); 921 /* Return wait for interrupt */ 922 return; 923 924 case ATAPI_P_READ: 925 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 926 device_printf(dev, "trying to read on write buffer\n"); 927 et = MVS_ERR_TFE; 928 goto end_finished; 929 } 930 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 931 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 932 length / 2); 933 ch->donecount += length; 934 /* Set next transfer size according to HW capabilities */ 935 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, 936 ch->curr[ccb->ccb_h.target_id].bytecount); 937 /* Return wait for interrupt */ 938 return; 939 940 case ATAPI_P_DONEDRQ: 941 device_printf(dev, 942 "WARNING - DONEDRQ non conformant device\n"); 943 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 944 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 945 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 946 length / 2); 947 ch->donecount += length; 948 } 949 else if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 950 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 951 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 952 length / 2); 953 ch->donecount += length; 954 } 955 else 956 et = MVS_ERR_TFE; 957 /* FALLTHROUGH */ 958 959 case ATAPI_P_ABORT: 960 case ATAPI_P_DONE: 961 if (status & (ATA_S_ERROR | ATA_S_DWF)) 962 et = MVS_ERR_TFE; 963 goto end_finished; 964 965 default: 966 device_printf(dev, "unknown transfer phase" 967 " (status %02x, ireason %02x)\n", 968 status, ireason); 969 et = MVS_ERR_TFE; 970 } 971 } 972 973 end_finished: 974 mvs_end_transaction(slot, et); 975 } 976 977 static void 978 mvs_crbq_intr(device_t dev) 979 { 980 struct mvs_channel *ch = device_get_softc(dev); 981 struct mvs_crpb *crpb; 982 union ccb *ccb; 983 int in_idx, fin_idx, cin_idx, slot; 984 uint32_t val; 985 uint16_t flags; 986 987 val = ATA_INL(ch->r_mem, EDMA_RESQIP); 988 if (val == 0) 989 val = ATA_INL(ch->r_mem, EDMA_RESQIP); 990 in_idx = (val & EDMA_RESQP_ERPQP_MASK) >> 991 EDMA_RESQP_ERPQP_SHIFT; 992 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 993 BUS_DMASYNC_POSTREAD); 994 fin_idx = cin_idx = ch->in_idx; 995 ch->in_idx = in_idx; 996 while (in_idx != cin_idx) { 997 crpb = (struct mvs_crpb *) 998 (ch->dma.workrp + MVS_CRPB_OFFSET + 999 (MVS_CRPB_SIZE * cin_idx)); 1000 slot = le16toh(crpb->id) & MVS_CRPB_TAG_MASK; 1001 flags = le16toh(crpb->rspflg); 1002 /* 1003 * Handle only successfull completions here. 1004 * Errors will be handled by main intr handler. 1005 */ 1006 if (crpb->id == 0xffff && crpb->rspflg == 0xffff) { 1007 device_printf(dev, "Unfilled CRPB " 1008 "%d (%d->%d) tag %d flags %04x rs %08x\n", 1009 cin_idx, fin_idx, in_idx, slot, flags, ch->rslots); 1010 } else if (ch->numtslots != 0 || 1011 (flags & EDMA_IE_EDEVERR) == 0) { 1012 crpb->id = 0xffff; 1013 crpb->rspflg = 0xffff; 1014 if (ch->slot[slot].state >= MVS_SLOT_RUNNING) { 1015 ccb = ch->slot[slot].ccb; 1016 ccb->ataio.res.status = 1017 (flags & MVS_CRPB_ATASTS_MASK) >> 1018 MVS_CRPB_ATASTS_SHIFT; 1019 mvs_end_transaction(&ch->slot[slot], MVS_ERR_NONE); 1020 } else { 1021 device_printf(dev, "Unused tag in CRPB " 1022 "%d (%d->%d) tag %d flags %04x rs %08x\n", 1023 cin_idx, fin_idx, in_idx, slot, flags, 1024 ch->rslots); 1025 } 1026 } else { 1027 device_printf(dev, 1028 "CRPB with error %d tag %d flags %04x\n", 1029 cin_idx, slot, flags); 1030 } 1031 cin_idx = (cin_idx + 1) & (MVS_MAX_SLOTS - 1); 1032 } 1033 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1034 BUS_DMASYNC_PREREAD); 1035 if (cin_idx == ch->in_idx) { 1036 ATA_OUTL(ch->r_mem, EDMA_RESQOP, 1037 ch->dma.workrp_bus | (cin_idx << EDMA_RESQP_ERPQP_SHIFT)); 1038 } 1039 } 1040 1041 /* Must be called with channel locked. */ 1042 static int 1043 mvs_check_collision(device_t dev, union ccb *ccb) 1044 { 1045 struct mvs_channel *ch = device_get_softc(dev); 1046 1047 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1048 /* NCQ DMA */ 1049 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1050 /* Can't mix NCQ and non-NCQ DMA commands. */ 1051 if (ch->numdslots != 0) 1052 return (1); 1053 /* Can't mix NCQ and PIO commands. */ 1054 if (ch->numpslots != 0) 1055 return (1); 1056 /* If we have no FBS */ 1057 if (!ch->fbs_enabled) { 1058 /* Tagged command while tagged to other target is active. */ 1059 if (ch->numtslots != 0 && 1060 ch->taggedtarget != ccb->ccb_h.target_id) 1061 return (1); 1062 } 1063 /* Non-NCQ DMA */ 1064 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1065 /* Can't mix non-NCQ DMA and NCQ commands. */ 1066 if (ch->numtslots != 0) 1067 return (1); 1068 /* Can't mix non-NCQ DMA and PIO commands. */ 1069 if (ch->numpslots != 0) 1070 return (1); 1071 /* PIO */ 1072 } else { 1073 /* Can't mix PIO with anything. */ 1074 if (ch->numrslots != 0) 1075 return (1); 1076 } 1077 if (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) { 1078 /* Atomic command while anything active. */ 1079 if (ch->numrslots != 0) 1080 return (1); 1081 } 1082 } else { /* ATAPI */ 1083 /* ATAPI goes without EDMA, so can't mix it with anything. */ 1084 if (ch->numrslots != 0) 1085 return (1); 1086 } 1087 /* We have some atomic command running. */ 1088 if (ch->aslots != 0) 1089 return (1); 1090 return (0); 1091 } 1092 1093 static void 1094 mvs_tfd_read(device_t dev, union ccb *ccb) 1095 { 1096 struct mvs_channel *ch = device_get_softc(dev); 1097 struct ata_res *res = &ccb->ataio.res; 1098 1099 res->status = ATA_INB(ch->r_mem, ATA_ALTSTAT); 1100 res->error = ATA_INB(ch->r_mem, ATA_ERROR); 1101 res->device = ATA_INB(ch->r_mem, ATA_DRIVE); 1102 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_HOB); 1103 res->sector_count_exp = ATA_INB(ch->r_mem, ATA_COUNT); 1104 res->lba_low_exp = ATA_INB(ch->r_mem, ATA_SECTOR); 1105 res->lba_mid_exp = ATA_INB(ch->r_mem, ATA_CYL_LSB); 1106 res->lba_high_exp = ATA_INB(ch->r_mem, ATA_CYL_MSB); 1107 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 1108 res->sector_count = ATA_INB(ch->r_mem, ATA_COUNT); 1109 res->lba_low = ATA_INB(ch->r_mem, ATA_SECTOR); 1110 res->lba_mid = ATA_INB(ch->r_mem, ATA_CYL_LSB); 1111 res->lba_high = ATA_INB(ch->r_mem, ATA_CYL_MSB); 1112 } 1113 1114 static void 1115 mvs_tfd_write(device_t dev, union ccb *ccb) 1116 { 1117 struct mvs_channel *ch = device_get_softc(dev); 1118 struct ata_cmd *cmd = &ccb->ataio.cmd; 1119 1120 ATA_OUTB(ch->r_mem, ATA_DRIVE, cmd->device); 1121 ATA_OUTB(ch->r_mem, ATA_CONTROL, cmd->control); 1122 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features_exp); 1123 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features); 1124 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count_exp); 1125 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count); 1126 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low_exp); 1127 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low); 1128 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid_exp); 1129 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid); 1130 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high_exp); 1131 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high); 1132 ATA_OUTB(ch->r_mem, ATA_COMMAND, cmd->command); 1133 } 1134 1135 1136 /* Must be called with channel locked. */ 1137 static void 1138 mvs_begin_transaction(device_t dev, union ccb *ccb) 1139 { 1140 struct mvs_channel *ch = device_get_softc(dev); 1141 struct mvs_slot *slot; 1142 int slotn, tag; 1143 1144 if (ch->pm_level > 0) 1145 mvs_ch_pm_wake(dev); 1146 /* Softreset is a special case. */ 1147 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1148 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1149 mvs_softreset(dev, ccb); 1150 return; 1151 } 1152 /* Choose empty slot. */ 1153 slotn = ffs(~ch->oslots) - 1; 1154 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1155 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1156 if (ch->quirks & MVS_Q_GENIIE) 1157 tag = ffs(~ch->otagspd[ccb->ccb_h.target_id]) - 1; 1158 else 1159 tag = slotn; 1160 } else 1161 tag = 0; 1162 /* Occupy chosen slot. */ 1163 slot = &ch->slot[slotn]; 1164 slot->ccb = ccb; 1165 slot->tag = tag; 1166 /* Stop PM timer. */ 1167 if (ch->numrslots == 0 && ch->pm_level > 3) 1168 callout_stop(&ch->pm_timer); 1169 /* Update channel stats. */ 1170 ch->oslots |= (1 << slot->slot); 1171 ch->numrslots++; 1172 ch->numrslotspd[ccb->ccb_h.target_id]++; 1173 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1174 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1175 ch->otagspd[ccb->ccb_h.target_id] |= (1 << slot->tag); 1176 ch->numtslots++; 1177 ch->numtslotspd[ccb->ccb_h.target_id]++; 1178 ch->taggedtarget = ccb->ccb_h.target_id; 1179 mvs_set_edma_mode(dev, MVS_EDMA_NCQ); 1180 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1181 ch->numdslots++; 1182 mvs_set_edma_mode(dev, MVS_EDMA_ON); 1183 } else { 1184 ch->numpslots++; 1185 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1186 } 1187 if (ccb->ataio.cmd.flags & 1188 (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) { 1189 ch->aslots |= (1 << slot->slot); 1190 } 1191 } else { 1192 uint8_t *cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1193 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes; 1194 ch->numpslots++; 1195 /* Use ATAPI DMA only for commands without under-/overruns. */ 1196 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1197 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA && 1198 (ch->quirks & MVS_Q_SOC) == 0 && 1199 (cdb[0] == 0x08 || 1200 cdb[0] == 0x0a || 1201 cdb[0] == 0x28 || 1202 cdb[0] == 0x2a || 1203 cdb[0] == 0x88 || 1204 cdb[0] == 0x8a || 1205 cdb[0] == 0xa8 || 1206 cdb[0] == 0xaa || 1207 cdb[0] == 0xbe)) { 1208 ch->basic_dma = 1; 1209 } 1210 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1211 } 1212 if (ch->numpslots == 0 || ch->basic_dma) { 1213 void *buf; 1214 bus_size_t size; 1215 1216 slot->state = MVS_SLOT_LOADING; 1217 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1218 buf = ccb->ataio.data_ptr; 1219 size = ccb->ataio.dxfer_len; 1220 } else { 1221 buf = ccb->csio.data_ptr; 1222 size = ccb->csio.dxfer_len; 1223 } 1224 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1225 buf, size, mvs_dmasetprd, slot, 0); 1226 } else 1227 mvs_legacy_execute_transaction(slot); 1228 } 1229 1230 /* Locked by busdma engine. */ 1231 static void 1232 mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1233 { 1234 struct mvs_slot *slot = arg; 1235 struct mvs_channel *ch = device_get_softc(slot->dev); 1236 struct mvs_eprd *eprd; 1237 int i; 1238 1239 if (error) { 1240 device_printf(slot->dev, "DMA load error\n"); 1241 mvs_end_transaction(slot, MVS_ERR_INVALID); 1242 return; 1243 } 1244 KASSERT(nsegs <= MVS_SG_ENTRIES, ("too many DMA segment entries\n")); 1245 /* If there is only one segment - no need to use S/G table on Gen-IIe. */ 1246 if (nsegs == 1 && ch->basic_dma == 0 && (ch->quirks & MVS_Q_GENIIE)) { 1247 slot->dma.addr = segs[0].ds_addr; 1248 slot->dma.len = segs[0].ds_len; 1249 } else { 1250 slot->dma.addr = 0; 1251 /* Get a piece of the workspace for this EPRD */ 1252 eprd = (struct mvs_eprd *) 1253 (ch->dma.workrq + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot)); 1254 /* Fill S/G table */ 1255 for (i = 0; i < nsegs; i++) { 1256 eprd[i].prdbal = htole32(segs[i].ds_addr); 1257 eprd[i].bytecount = htole32(segs[i].ds_len & MVS_EPRD_MASK); 1258 eprd[i].prdbah = htole32((segs[i].ds_addr >> 16) >> 16); 1259 } 1260 eprd[i - 1].bytecount |= htole32(MVS_EPRD_EOF); 1261 } 1262 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1263 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1264 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1265 if (ch->basic_dma) 1266 mvs_legacy_execute_transaction(slot); 1267 else 1268 mvs_execute_transaction(slot); 1269 } 1270 1271 static void 1272 mvs_legacy_execute_transaction(struct mvs_slot *slot) 1273 { 1274 device_t dev = slot->dev; 1275 struct mvs_channel *ch = device_get_softc(dev); 1276 bus_addr_t eprd; 1277 union ccb *ccb = slot->ccb; 1278 int port = ccb->ccb_h.target_id & 0x0f; 1279 int timeout; 1280 1281 slot->state = MVS_SLOT_RUNNING; 1282 ch->rslots |= (1 << slot->slot); 1283 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); 1284 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1285 mvs_tfd_write(dev, ccb); 1286 /* Device reset doesn't interrupt. */ 1287 if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) { 1288 int timeout = 1000000; 1289 do { 1290 DELAY(10); 1291 ccb->ataio.res.status = ATA_INB(ch->r_mem, ATA_STATUS); 1292 } while (ccb->ataio.res.status & ATA_S_BUSY && timeout--); 1293 mvs_legacy_intr(dev); 1294 return; 1295 } 1296 ch->donecount = 0; 1297 ch->transfersize = min(ccb->ataio.dxfer_len, 1298 ch->curr[port].bytecount); 1299 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1300 ch->fake_busy = 1; 1301 /* If data write command - output the data */ 1302 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1303 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 1304 device_printf(dev, 1305 "timeout waiting for write DRQ\n"); 1306 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1307 return; 1308 } 1309 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 1310 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 1311 ch->transfersize / 2); 1312 } 1313 } else { 1314 ch->donecount = 0; 1315 ch->transfersize = min(ccb->csio.dxfer_len, 1316 ch->curr[port].bytecount); 1317 /* Write ATA PACKET command. */ 1318 if (ch->basic_dma) { 1319 ATA_OUTB(ch->r_mem, ATA_FEATURE, ATA_F_DMA); 1320 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0); 1321 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, 0); 1322 } else { 1323 ATA_OUTB(ch->r_mem, ATA_FEATURE, 0); 1324 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, ch->transfersize); 1325 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, ch->transfersize >> 8); 1326 } 1327 ATA_OUTB(ch->r_mem, ATA_COMMAND, ATA_PACKET_CMD); 1328 ch->fake_busy = 1; 1329 /* Wait for ready to write ATAPI command block */ 1330 if (mvs_wait(dev, 0, ATA_S_BUSY, 1000) < 0) { 1331 device_printf(dev, "timeout waiting for ATAPI !BUSY\n"); 1332 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1333 return; 1334 } 1335 timeout = 5000; 1336 while (timeout--) { 1337 int reason = ATA_INB(ch->r_mem, ATA_IREASON); 1338 int status = ATA_INB(ch->r_mem, ATA_STATUS); 1339 1340 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 1341 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 1342 break; 1343 DELAY(20); 1344 } 1345 if (timeout <= 0) { 1346 device_printf(dev, 1347 "timeout waiting for ATAPI command ready\n"); 1348 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1349 return; 1350 } 1351 /* Write ATAPI command. */ 1352 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 1353 (uint16_t *)((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1354 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes), 1355 ch->curr[port].atapi / 2); 1356 DELAY(10); 1357 if (ch->basic_dma) { 1358 /* Start basic DMA. */ 1359 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + 1360 (MVS_EPRD_SIZE * slot->slot); 1361 ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd); 1362 ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16); 1363 ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START | 1364 (((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ? 1365 DMA_C_READ : 0)); 1366 } else if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1367 ch->fake_busy = 1; 1368 } 1369 /* Start command execution timeout */ 1370 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1371 (timeout_t*)mvs_timeout, slot); 1372 } 1373 1374 /* Must be called with channel locked. */ 1375 static void 1376 mvs_execute_transaction(struct mvs_slot *slot) 1377 { 1378 device_t dev = slot->dev; 1379 struct mvs_channel *ch = device_get_softc(dev); 1380 bus_addr_t eprd; 1381 struct mvs_crqb *crqb; 1382 struct mvs_crqb_gen2e *crqb2e; 1383 union ccb *ccb = slot->ccb; 1384 int port = ccb->ccb_h.target_id & 0x0f; 1385 int i; 1386 1387 /* Get address of the prepared EPRD */ 1388 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot); 1389 /* Prepare CRQB. Gen IIe uses different CRQB format. */ 1390 if (ch->quirks & MVS_Q_GENIIE) { 1391 crqb2e = (struct mvs_crqb_gen2e *) 1392 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1393 crqb2e->ctrlflg = htole32( 1394 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB2E_READ : 0) | 1395 (slot->tag << MVS_CRQB2E_DTAG_SHIFT) | 1396 (port << MVS_CRQB2E_PMP_SHIFT) | 1397 (slot->slot << MVS_CRQB2E_HTAG_SHIFT)); 1398 /* If there is only one segment - no need to use S/G table. */ 1399 if (slot->dma.addr != 0) { 1400 eprd = slot->dma.addr; 1401 crqb2e->ctrlflg |= htole32(MVS_CRQB2E_CPRD); 1402 crqb2e->drbc = slot->dma.len; 1403 } 1404 crqb2e->cprdbl = htole32(eprd); 1405 crqb2e->cprdbh = htole32((eprd >> 16) >> 16); 1406 crqb2e->cmd[0] = 0; 1407 crqb2e->cmd[1] = 0; 1408 crqb2e->cmd[2] = ccb->ataio.cmd.command; 1409 crqb2e->cmd[3] = ccb->ataio.cmd.features; 1410 crqb2e->cmd[4] = ccb->ataio.cmd.lba_low; 1411 crqb2e->cmd[5] = ccb->ataio.cmd.lba_mid; 1412 crqb2e->cmd[6] = ccb->ataio.cmd.lba_high; 1413 crqb2e->cmd[7] = ccb->ataio.cmd.device; 1414 crqb2e->cmd[8] = ccb->ataio.cmd.lba_low_exp; 1415 crqb2e->cmd[9] = ccb->ataio.cmd.lba_mid_exp; 1416 crqb2e->cmd[10] = ccb->ataio.cmd.lba_high_exp; 1417 crqb2e->cmd[11] = ccb->ataio.cmd.features_exp; 1418 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1419 crqb2e->cmd[12] = slot->tag << 3; 1420 crqb2e->cmd[13] = 0; 1421 } else { 1422 crqb2e->cmd[12] = ccb->ataio.cmd.sector_count; 1423 crqb2e->cmd[13] = ccb->ataio.cmd.sector_count_exp; 1424 } 1425 crqb2e->cmd[14] = 0; 1426 crqb2e->cmd[15] = 0; 1427 } else { 1428 crqb = (struct mvs_crqb *) 1429 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1430 crqb->cprdbl = htole32(eprd); 1431 crqb->cprdbh = htole32((eprd >> 16) >> 16); 1432 crqb->ctrlflg = htole16( 1433 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB_READ : 0) | 1434 (slot->slot << MVS_CRQB_TAG_SHIFT) | 1435 (port << MVS_CRQB_PMP_SHIFT)); 1436 i = 0; 1437 /* 1438 * Controller can handle only 11 of 12 ATA registers, 1439 * so we have to choose which one to skip. 1440 */ 1441 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1442 crqb->cmd[i++] = ccb->ataio.cmd.features_exp; 1443 crqb->cmd[i++] = 0x11; 1444 } 1445 crqb->cmd[i++] = ccb->ataio.cmd.features; 1446 crqb->cmd[i++] = 0x11; 1447 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1448 crqb->cmd[i++] = slot->tag << 3; 1449 crqb->cmd[i++] = 0x12; 1450 } else { 1451 crqb->cmd[i++] = ccb->ataio.cmd.sector_count_exp; 1452 crqb->cmd[i++] = 0x12; 1453 crqb->cmd[i++] = ccb->ataio.cmd.sector_count; 1454 crqb->cmd[i++] = 0x12; 1455 } 1456 crqb->cmd[i++] = ccb->ataio.cmd.lba_low_exp; 1457 crqb->cmd[i++] = 0x13; 1458 crqb->cmd[i++] = ccb->ataio.cmd.lba_low; 1459 crqb->cmd[i++] = 0x13; 1460 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid_exp; 1461 crqb->cmd[i++] = 0x14; 1462 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid; 1463 crqb->cmd[i++] = 0x14; 1464 crqb->cmd[i++] = ccb->ataio.cmd.lba_high_exp; 1465 crqb->cmd[i++] = 0x15; 1466 crqb->cmd[i++] = ccb->ataio.cmd.lba_high; 1467 crqb->cmd[i++] = 0x15; 1468 crqb->cmd[i++] = ccb->ataio.cmd.device; 1469 crqb->cmd[i++] = 0x16; 1470 crqb->cmd[i++] = ccb->ataio.cmd.command; 1471 crqb->cmd[i++] = 0x97; 1472 } 1473 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 1474 BUS_DMASYNC_PREWRITE); 1475 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1476 BUS_DMASYNC_PREREAD); 1477 slot->state = MVS_SLOT_RUNNING; 1478 ch->rslots |= (1 << slot->slot); 1479 /* Issue command to the controller. */ 1480 ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1); 1481 ATA_OUTL(ch->r_mem, EDMA_REQQIP, 1482 ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1483 /* Start command execution timeout */ 1484 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1485 (timeout_t*)mvs_timeout, slot); 1486 return; 1487 } 1488 1489 /* Must be called with channel locked. */ 1490 static void 1491 mvs_process_timeout(device_t dev) 1492 { 1493 struct mvs_channel *ch = device_get_softc(dev); 1494 int i; 1495 1496 mtx_assert(&ch->mtx, MA_OWNED); 1497 /* Handle the rest of commands. */ 1498 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1499 /* Do we have a running request on slot? */ 1500 if (ch->slot[i].state < MVS_SLOT_RUNNING) 1501 continue; 1502 mvs_end_transaction(&ch->slot[i], MVS_ERR_TIMEOUT); 1503 } 1504 } 1505 1506 /* Must be called with channel locked. */ 1507 static void 1508 mvs_rearm_timeout(device_t dev) 1509 { 1510 struct mvs_channel *ch = device_get_softc(dev); 1511 int i; 1512 1513 mtx_assert(&ch->mtx, MA_OWNED); 1514 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1515 struct mvs_slot *slot = &ch->slot[i]; 1516 1517 /* Do we have a running request on slot? */ 1518 if (slot->state < MVS_SLOT_RUNNING) 1519 continue; 1520 if ((ch->toslots & (1 << i)) == 0) 1521 continue; 1522 callout_reset(&slot->timeout, 1523 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1524 (timeout_t*)mvs_timeout, slot); 1525 } 1526 } 1527 1528 /* Locked by callout mechanism. */ 1529 static void 1530 mvs_timeout(struct mvs_slot *slot) 1531 { 1532 device_t dev = slot->dev; 1533 struct mvs_channel *ch = device_get_softc(dev); 1534 1535 /* Check for stale timeout. */ 1536 if (slot->state < MVS_SLOT_RUNNING) 1537 return; 1538 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1539 device_printf(dev, "iec %08x sstat %08x serr %08x edma_s %08x " 1540 "dma_c %08x dma_s %08x rs %08x status %02x\n", 1541 ATA_INL(ch->r_mem, EDMA_IEC), 1542 ATA_INL(ch->r_mem, SATA_SS), ATA_INL(ch->r_mem, SATA_SE), 1543 ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C), 1544 ATA_INL(ch->r_mem, DMA_S), ch->rslots, 1545 ATA_INB(ch->r_mem, ATA_ALTSTAT)); 1546 /* Handle frozen command. */ 1547 mvs_requeue_frozen(dev); 1548 /* We wait for other commands timeout and pray. */ 1549 if (ch->toslots == 0) 1550 xpt_freeze_simq(ch->sim, 1); 1551 ch->toslots |= (1 << slot->slot); 1552 if ((ch->rslots & ~ch->toslots) == 0) 1553 mvs_process_timeout(dev); 1554 else 1555 device_printf(dev, " ... waiting for slots %08x\n", 1556 ch->rslots & ~ch->toslots); 1557 } 1558 1559 /* Must be called with channel locked. */ 1560 static void 1561 mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et) 1562 { 1563 device_t dev = slot->dev; 1564 struct mvs_channel *ch = device_get_softc(dev); 1565 union ccb *ccb = slot->ccb; 1566 int lastto; 1567 1568 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 1569 BUS_DMASYNC_POSTWRITE); 1570 /* Read result registers to the result struct 1571 * May be incorrect if several commands finished same time, 1572 * so read only when sure or have to. 1573 */ 1574 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1575 struct ata_res *res = &ccb->ataio.res; 1576 1577 if ((et == MVS_ERR_TFE) || 1578 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1579 mvs_tfd_read(dev, ccb); 1580 } else 1581 bzero(res, sizeof(*res)); 1582 } 1583 if (ch->numpslots == 0 || ch->basic_dma) { 1584 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1585 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1586 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1587 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1588 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1589 } 1590 } 1591 if (et != MVS_ERR_NONE) 1592 ch->eslots |= (1 << slot->slot); 1593 /* In case of error, freeze device for proper recovery. */ 1594 if ((et != MVS_ERR_NONE) && (!ch->readlog) && 1595 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1596 xpt_freeze_devq(ccb->ccb_h.path, 1); 1597 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1598 } 1599 /* Set proper result status. */ 1600 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1601 switch (et) { 1602 case MVS_ERR_NONE: 1603 ccb->ccb_h.status |= CAM_REQ_CMP; 1604 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1605 ccb->csio.scsi_status = SCSI_STATUS_OK; 1606 break; 1607 case MVS_ERR_INVALID: 1608 ch->fatalerr = 1; 1609 ccb->ccb_h.status |= CAM_REQ_INVALID; 1610 break; 1611 case MVS_ERR_INNOCENT: 1612 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1613 break; 1614 case MVS_ERR_TFE: 1615 case MVS_ERR_NCQ: 1616 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1617 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1618 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1619 } else { 1620 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1621 } 1622 break; 1623 case MVS_ERR_SATA: 1624 ch->fatalerr = 1; 1625 if (!ch->readlog) { 1626 xpt_freeze_simq(ch->sim, 1); 1627 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1628 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1629 } 1630 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1631 break; 1632 case MVS_ERR_TIMEOUT: 1633 if (!ch->readlog) { 1634 xpt_freeze_simq(ch->sim, 1); 1635 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1636 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1637 } 1638 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1639 break; 1640 default: 1641 ch->fatalerr = 1; 1642 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1643 } 1644 /* Free slot. */ 1645 ch->oslots &= ~(1 << slot->slot); 1646 ch->rslots &= ~(1 << slot->slot); 1647 ch->aslots &= ~(1 << slot->slot); 1648 slot->state = MVS_SLOT_EMPTY; 1649 slot->ccb = NULL; 1650 /* Update channel stats. */ 1651 ch->numrslots--; 1652 ch->numrslotspd[ccb->ccb_h.target_id]--; 1653 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1654 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1655 ch->otagspd[ccb->ccb_h.target_id] &= ~(1 << slot->tag); 1656 ch->numtslots--; 1657 ch->numtslotspd[ccb->ccb_h.target_id]--; 1658 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1659 ch->numdslots--; 1660 } else { 1661 ch->numpslots--; 1662 } 1663 } else { 1664 ch->numpslots--; 1665 ch->basic_dma = 0; 1666 } 1667 /* Cancel timeout state if request completed normally. */ 1668 if (et != MVS_ERR_TIMEOUT) { 1669 lastto = (ch->toslots == (1 << slot->slot)); 1670 ch->toslots &= ~(1 << slot->slot); 1671 if (lastto) 1672 xpt_release_simq(ch->sim, TRUE); 1673 } 1674 /* If it was our READ LOG command - process it. */ 1675 if (ch->readlog) { 1676 mvs_process_read_log(dev, ccb); 1677 /* If it was NCQ command error, put result on hold. */ 1678 } else if (et == MVS_ERR_NCQ) { 1679 ch->hold[slot->slot] = ccb; 1680 ch->holdtag[slot->slot] = slot->tag; 1681 ch->numhslots++; 1682 } else 1683 xpt_done(ccb); 1684 /* Unfreeze frozen command. */ 1685 if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) { 1686 union ccb *fccb = ch->frozen; 1687 ch->frozen = NULL; 1688 mvs_begin_transaction(dev, fccb); 1689 xpt_release_simq(ch->sim, TRUE); 1690 } 1691 /* If we have no other active commands, ... */ 1692 if (ch->rslots == 0) { 1693 /* if there was fatal error - reset port. */ 1694 if (ch->toslots != 0 || ch->fatalerr) { 1695 mvs_reset(dev); 1696 } else { 1697 /* if we have slots in error, we can reinit port. */ 1698 if (ch->eslots != 0) { 1699 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1700 ch->eslots = 0; 1701 } 1702 /* if there commands on hold, we can do READ LOG. */ 1703 if (!ch->readlog && ch->numhslots) 1704 mvs_issue_read_log(dev); 1705 } 1706 /* If all the rest of commands are in timeout - give them chance. */ 1707 } else if ((ch->rslots & ~ch->toslots) == 0 && 1708 et != MVS_ERR_TIMEOUT) 1709 mvs_rearm_timeout(dev); 1710 /* Start PM timer. */ 1711 if (ch->numrslots == 0 && ch->pm_level > 3 && 1712 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 1713 callout_schedule(&ch->pm_timer, 1714 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1715 } 1716 } 1717 1718 static void 1719 mvs_issue_read_log(device_t dev) 1720 { 1721 struct mvs_channel *ch = device_get_softc(dev); 1722 union ccb *ccb; 1723 struct ccb_ataio *ataio; 1724 int i; 1725 1726 ch->readlog = 1; 1727 /* Find some holden command. */ 1728 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1729 if (ch->hold[i]) 1730 break; 1731 } 1732 ccb = xpt_alloc_ccb_nowait(); 1733 if (ccb == NULL) { 1734 device_printf(dev, "Unable allocate READ LOG command"); 1735 return; /* XXX */ 1736 } 1737 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1738 ccb->ccb_h.func_code = XPT_ATA_IO; 1739 ccb->ccb_h.flags = CAM_DIR_IN; 1740 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1741 ataio = &ccb->ataio; 1742 ataio->data_ptr = malloc(512, M_MVS, M_NOWAIT); 1743 if (ataio->data_ptr == NULL) { 1744 xpt_free_ccb(ccb); 1745 device_printf(dev, "Unable allocate memory for READ LOG command"); 1746 return; /* XXX */ 1747 } 1748 ataio->dxfer_len = 512; 1749 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1750 ataio->cmd.flags = CAM_ATAIO_48BIT; 1751 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1752 ataio->cmd.sector_count = 1; 1753 ataio->cmd.sector_count_exp = 0; 1754 ataio->cmd.lba_low = 0x10; 1755 ataio->cmd.lba_mid = 0; 1756 ataio->cmd.lba_mid_exp = 0; 1757 /* Freeze SIM while doing READ LOG EXT. */ 1758 xpt_freeze_simq(ch->sim, 1); 1759 mvs_begin_transaction(dev, ccb); 1760 } 1761 1762 static void 1763 mvs_process_read_log(device_t dev, union ccb *ccb) 1764 { 1765 struct mvs_channel *ch = device_get_softc(dev); 1766 uint8_t *data; 1767 struct ata_res *res; 1768 int i; 1769 1770 ch->readlog = 0; 1771 1772 data = ccb->ataio.data_ptr; 1773 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1774 (data[0] & 0x80) == 0) { 1775 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1776 if (!ch->hold[i]) 1777 continue; 1778 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id) 1779 continue; 1780 if ((data[0] & 0x1F) == ch->holdtag[i]) { 1781 res = &ch->hold[i]->ataio.res; 1782 res->status = data[2]; 1783 res->error = data[3]; 1784 res->lba_low = data[4]; 1785 res->lba_mid = data[5]; 1786 res->lba_high = data[6]; 1787 res->device = data[7]; 1788 res->lba_low_exp = data[8]; 1789 res->lba_mid_exp = data[9]; 1790 res->lba_high_exp = data[10]; 1791 res->sector_count = data[12]; 1792 res->sector_count_exp = data[13]; 1793 } else { 1794 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1795 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1796 } 1797 xpt_done(ch->hold[i]); 1798 ch->hold[i] = NULL; 1799 ch->numhslots--; 1800 } 1801 } else { 1802 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1803 device_printf(dev, "Error while READ LOG EXT\n"); 1804 else if ((data[0] & 0x80) == 0) { 1805 device_printf(dev, 1806 "Non-queued command error in READ LOG EXT\n"); 1807 } 1808 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1809 if (!ch->hold[i]) 1810 continue; 1811 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id) 1812 continue; 1813 xpt_done(ch->hold[i]); 1814 ch->hold[i] = NULL; 1815 ch->numhslots--; 1816 } 1817 } 1818 free(ccb->ataio.data_ptr, M_MVS); 1819 xpt_free_ccb(ccb); 1820 xpt_release_simq(ch->sim, TRUE); 1821 } 1822 1823 static int 1824 mvs_wait(device_t dev, u_int s, u_int c, int t) 1825 { 1826 int timeout = 0; 1827 uint8_t st; 1828 1829 while (((st = mvs_getstatus(dev, 0)) & (s | c)) != s) { 1830 DELAY(1000); 1831 if (timeout++ > t) { 1832 device_printf(dev, "Wait status %02x\n", st); 1833 return (-1); 1834 } 1835 } 1836 return (timeout); 1837 } 1838 1839 static void 1840 mvs_requeue_frozen(device_t dev) 1841 { 1842 struct mvs_channel *ch = device_get_softc(dev); 1843 union ccb *fccb = ch->frozen; 1844 1845 if (fccb) { 1846 ch->frozen = NULL; 1847 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1848 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1849 xpt_freeze_devq(fccb->ccb_h.path, 1); 1850 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1851 } 1852 xpt_done(fccb); 1853 } 1854 } 1855 1856 static void 1857 mvs_reset(device_t dev) 1858 { 1859 struct mvs_channel *ch = device_get_softc(dev); 1860 int i; 1861 1862 xpt_freeze_simq(ch->sim, 1); 1863 if (bootverbose) 1864 device_printf(dev, "MVS reset...\n"); 1865 /* Requeue freezed command. */ 1866 mvs_requeue_frozen(dev); 1867 /* Kill the engine and requeue all running commands. */ 1868 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1869 ATA_OUTL(ch->r_mem, DMA_C, 0); 1870 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1871 /* Do we have a running request on slot? */ 1872 if (ch->slot[i].state < MVS_SLOT_RUNNING) 1873 continue; 1874 /* XXX; Commands in loading state. */ 1875 mvs_end_transaction(&ch->slot[i], MVS_ERR_INNOCENT); 1876 } 1877 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1878 if (!ch->hold[i]) 1879 continue; 1880 xpt_done(ch->hold[i]); 1881 ch->hold[i] = NULL; 1882 ch->numhslots--; 1883 } 1884 if (ch->toslots != 0) 1885 xpt_release_simq(ch->sim, TRUE); 1886 ch->eslots = 0; 1887 ch->toslots = 0; 1888 ch->fatalerr = 0; 1889 /* Tell the XPT about the event */ 1890 xpt_async(AC_BUS_RESET, ch->path, NULL); 1891 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 1892 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EATARST); 1893 DELAY(25); 1894 ATA_OUTL(ch->r_mem, EDMA_CMD, 0); 1895 /* Reset and reconnect PHY, */ 1896 if (!mvs_sata_phy_reset(dev)) { 1897 if (bootverbose) 1898 device_printf(dev, 1899 "MVS reset done: phy reset found no device\n"); 1900 ch->devices = 0; 1901 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 1902 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 1903 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 1904 xpt_release_simq(ch->sim, TRUE); 1905 return; 1906 } 1907 /* Wait for clearing busy status. */ 1908 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 15000)) < 0) 1909 device_printf(dev, "device is not ready\n"); 1910 else if (bootverbose) 1911 device_printf(dev, "ready wait time=%dms\n", i); 1912 ch->devices = 1; 1913 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 1914 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 1915 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 1916 if (bootverbose) 1917 device_printf(dev, "MVS reset done: device found\n"); 1918 xpt_release_simq(ch->sim, TRUE); 1919 } 1920 1921 static void 1922 mvs_softreset(device_t dev, union ccb *ccb) 1923 { 1924 struct mvs_channel *ch = device_get_softc(dev); 1925 int port = ccb->ccb_h.target_id & 0x0f; 1926 int i; 1927 1928 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1929 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); 1930 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET); 1931 DELAY(10000); 1932 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 1933 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1934 /* Wait for clearing busy status. */ 1935 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout)) < 0) { 1936 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1937 } else { 1938 ccb->ccb_h.status |= CAM_REQ_CMP; 1939 } 1940 mvs_tfd_read(dev, ccb); 1941 xpt_done(ccb); 1942 } 1943 1944 static int 1945 mvs_sata_connect(struct mvs_channel *ch) 1946 { 1947 u_int32_t status; 1948 int timeout; 1949 1950 /* Wait up to 100ms for "connect well" */ 1951 for (timeout = 0; timeout < 100 ; timeout++) { 1952 status = ATA_INL(ch->r_mem, SATA_SS); 1953 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && 1954 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && 1955 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) 1956 break; 1957 if ((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_OFFLINE) { 1958 if (bootverbose) { 1959 device_printf(ch->dev, "SATA offline status=%08x\n", 1960 status); 1961 } 1962 return (0); 1963 } 1964 DELAY(1000); 1965 } 1966 if (timeout >= 100) { 1967 if (bootverbose) { 1968 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 1969 status); 1970 } 1971 return (0); 1972 } 1973 if (bootverbose) { 1974 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 1975 timeout, status); 1976 } 1977 /* Clear SATA error register */ 1978 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 1979 return (1); 1980 } 1981 1982 static int 1983 mvs_sata_phy_reset(device_t dev) 1984 { 1985 struct mvs_channel *ch = device_get_softc(dev); 1986 int sata_rev; 1987 uint32_t val; 1988 1989 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 1990 if (sata_rev == 1) 1991 val = SATA_SC_SPD_SPEED_GEN1; 1992 else if (sata_rev == 2) 1993 val = SATA_SC_SPD_SPEED_GEN2; 1994 else if (sata_rev == 3) 1995 val = SATA_SC_SPD_SPEED_GEN3; 1996 else 1997 val = 0; 1998 ATA_OUTL(ch->r_mem, SATA_SC, 1999 SATA_SC_DET_RESET | val | 2000 SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER); 2001 DELAY(5000); 2002 ATA_OUTL(ch->r_mem, SATA_SC, 2003 SATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2004 (SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER))); 2005 DELAY(5000); 2006 if (!mvs_sata_connect(ch)) { 2007 if (ch->pm_level > 0) 2008 ATA_OUTL(ch->r_mem, SATA_SC, SATA_SC_DET_DISABLE); 2009 return (0); 2010 } 2011 return (1); 2012 } 2013 2014 static int 2015 mvs_check_ids(device_t dev, union ccb *ccb) 2016 { 2017 struct mvs_channel *ch = device_get_softc(dev); 2018 2019 if (ccb->ccb_h.target_id > ((ch->quirks & MVS_Q_GENI) ? 0 : 15)) { 2020 ccb->ccb_h.status = CAM_TID_INVALID; 2021 xpt_done(ccb); 2022 return (-1); 2023 } 2024 if (ccb->ccb_h.target_lun != 0) { 2025 ccb->ccb_h.status = CAM_LUN_INVALID; 2026 xpt_done(ccb); 2027 return (-1); 2028 } 2029 return (0); 2030 } 2031 2032 static void 2033 mvsaction(struct cam_sim *sim, union ccb *ccb) 2034 { 2035 device_t dev, parent; 2036 struct mvs_channel *ch; 2037 2038 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mvsaction func_code=%x\n", 2039 ccb->ccb_h.func_code)); 2040 2041 ch = (struct mvs_channel *)cam_sim_softc(sim); 2042 dev = ch->dev; 2043 switch (ccb->ccb_h.func_code) { 2044 /* Common cases first */ 2045 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2046 case XPT_SCSI_IO: 2047 if (mvs_check_ids(dev, ccb)) 2048 return; 2049 if (ch->devices == 0 || 2050 (ch->pm_present == 0 && 2051 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2052 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2053 break; 2054 } 2055 /* Check for command collision. */ 2056 if (mvs_check_collision(dev, ccb)) { 2057 /* Freeze command. */ 2058 ch->frozen = ccb; 2059 /* We have only one frozen slot, so freeze simq also. */ 2060 xpt_freeze_simq(ch->sim, 1); 2061 return; 2062 } 2063 mvs_begin_transaction(dev, ccb); 2064 return; 2065 case XPT_EN_LUN: /* Enable LUN as a target */ 2066 case XPT_TARGET_IO: /* Execute target I/O request */ 2067 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2068 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2069 case XPT_ABORT: /* Abort the specified CCB */ 2070 /* XXX Implement */ 2071 ccb->ccb_h.status = CAM_REQ_INVALID; 2072 break; 2073 case XPT_SET_TRAN_SETTINGS: 2074 { 2075 struct ccb_trans_settings *cts = &ccb->cts; 2076 struct mvs_device *d; 2077 2078 if (mvs_check_ids(dev, ccb)) 2079 return; 2080 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2081 d = &ch->curr[ccb->ccb_h.target_id]; 2082 else 2083 d = &ch->user[ccb->ccb_h.target_id]; 2084 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2085 d->revision = cts->xport_specific.sata.revision; 2086 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2087 d->mode = cts->xport_specific.sata.mode; 2088 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) { 2089 d->bytecount = min((ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048, 2090 cts->xport_specific.sata.bytecount); 2091 } 2092 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2093 d->tags = min(MVS_MAX_SLOTS, cts->xport_specific.sata.tags); 2094 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2095 ch->pm_present = cts->xport_specific.sata.pm_present; 2096 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2097 d->atapi = cts->xport_specific.sata.atapi; 2098 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2099 d->caps = cts->xport_specific.sata.caps; 2100 ccb->ccb_h.status = CAM_REQ_CMP; 2101 break; 2102 } 2103 case XPT_GET_TRAN_SETTINGS: 2104 /* Get default/user set transfer settings for the target */ 2105 { 2106 struct ccb_trans_settings *cts = &ccb->cts; 2107 struct mvs_device *d; 2108 uint32_t status; 2109 2110 if (mvs_check_ids(dev, ccb)) 2111 return; 2112 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2113 d = &ch->curr[ccb->ccb_h.target_id]; 2114 else 2115 d = &ch->user[ccb->ccb_h.target_id]; 2116 cts->protocol = PROTO_ATA; 2117 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2118 cts->transport = XPORT_SATA; 2119 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2120 cts->proto_specific.valid = 0; 2121 cts->xport_specific.sata.valid = 0; 2122 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2123 (ccb->ccb_h.target_id == 15 || 2124 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2125 status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK; 2126 if (status & 0x0f0) { 2127 cts->xport_specific.sata.revision = 2128 (status & 0x0f0) >> 4; 2129 cts->xport_specific.sata.valid |= 2130 CTS_SATA_VALID_REVISION; 2131 } 2132 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2133 // if (ch->pm_level) 2134 // cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2135 cts->xport_specific.sata.caps &= 2136 ch->user[ccb->ccb_h.target_id].caps; 2137 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2138 } else { 2139 cts->xport_specific.sata.revision = d->revision; 2140 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2141 cts->xport_specific.sata.caps = d->caps; 2142 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2143 } 2144 cts->xport_specific.sata.mode = d->mode; 2145 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2146 cts->xport_specific.sata.bytecount = d->bytecount; 2147 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2148 cts->xport_specific.sata.pm_present = ch->pm_present; 2149 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2150 cts->xport_specific.sata.tags = d->tags; 2151 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2152 cts->xport_specific.sata.atapi = d->atapi; 2153 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2154 ccb->ccb_h.status = CAM_REQ_CMP; 2155 break; 2156 } 2157 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2158 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2159 mvs_reset(dev); 2160 ccb->ccb_h.status = CAM_REQ_CMP; 2161 break; 2162 case XPT_TERM_IO: /* Terminate the I/O process */ 2163 /* XXX Implement */ 2164 ccb->ccb_h.status = CAM_REQ_INVALID; 2165 break; 2166 case XPT_PATH_INQ: /* Path routing inquiry */ 2167 { 2168 struct ccb_pathinq *cpi = &ccb->cpi; 2169 2170 parent = device_get_parent(dev); 2171 cpi->version_num = 1; /* XXX??? */ 2172 cpi->hba_inquiry = PI_SDTR_ABLE; 2173 if (!(ch->quirks & MVS_Q_GENI)) { 2174 cpi->hba_inquiry |= PI_SATAPM; 2175 /* Gen-II is extremely slow with NCQ on PMP. */ 2176 if ((ch->quirks & MVS_Q_GENIIE) || ch->pm_present == 0) 2177 cpi->hba_inquiry |= PI_TAG_ABLE; 2178 } 2179 cpi->target_sprt = 0; 2180 cpi->hba_misc = PIM_SEQSCAN; 2181 cpi->hba_eng_cnt = 0; 2182 if (!(ch->quirks & MVS_Q_GENI)) 2183 cpi->max_target = 15; 2184 else 2185 cpi->max_target = 0; 2186 cpi->max_lun = 0; 2187 cpi->initiator_id = 0; 2188 cpi->bus_id = cam_sim_bus(sim); 2189 cpi->base_transfer_speed = 150000; 2190 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2191 strncpy(cpi->hba_vid, "Marvell", HBA_IDLEN); 2192 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2193 cpi->unit_number = cam_sim_unit(sim); 2194 cpi->transport = XPORT_SATA; 2195 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2196 cpi->protocol = PROTO_ATA; 2197 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2198 cpi->maxio = MAXPHYS; 2199 if ((ch->quirks & MVS_Q_SOC) == 0) { 2200 cpi->hba_vendor = pci_get_vendor(parent); 2201 cpi->hba_device = pci_get_device(parent); 2202 cpi->hba_subvendor = pci_get_subvendor(parent); 2203 cpi->hba_subdevice = pci_get_subdevice(parent); 2204 } 2205 cpi->ccb_h.status = CAM_REQ_CMP; 2206 break; 2207 } 2208 default: 2209 ccb->ccb_h.status = CAM_REQ_INVALID; 2210 break; 2211 } 2212 xpt_done(ccb); 2213 } 2214 2215 static void 2216 mvspoll(struct cam_sim *sim) 2217 { 2218 struct mvs_channel *ch = (struct mvs_channel *)cam_sim_softc(sim); 2219 struct mvs_intr_arg arg; 2220 2221 arg.arg = ch->dev; 2222 arg.cause = 2; /* XXX */ 2223 mvs_ch_intr(&arg); 2224 } 2225 2226