1 /*- 2 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Definitions for the Marvell 88W8363 Wireless LAN controller. 35 */ 36 #ifndef _DEV_MWL_MVVAR_H 37 #define _DEV_MWL_MVVAR_H 38 39 #include <sys/endian.h> 40 #include <net80211/ieee80211_radiotap.h> 41 #include <dev/mwl/mwlhal.h> 42 #include <dev/mwl/mwlreg.h> 43 #include <dev/mwl/if_mwlioctl.h> 44 45 #ifndef MWL_TXBUF 46 #define MWL_TXBUF 256 /* number of TX descriptors/buffers */ 47 #endif 48 #ifndef MWL_TXACKBUF 49 #define MWL_TXACKBUF (MWL_TXBUF/2) /* number of TX ACK desc's/buffers */ 50 #endif 51 #ifndef MWL_RXDESC 52 #define MWL_RXDESC 256 /* number of RX descriptors */ 53 #endif 54 #ifndef MWL_RXBUF 55 #define MWL_RXBUF ((5*MWL_RXDESC)/2)/* number of RX dma buffers */ 56 #endif 57 #ifndef MWL_MAXBA 58 #define MWL_MAXBA 2 /* max BA streams/sta */ 59 #endif 60 61 #ifdef MWL_SGDMA_SUPPORT 62 #define MWL_TXDESC 6 /* max tx descriptors/segments */ 63 #else 64 #define MWL_TXDESC 1 /* max tx descriptors/segments */ 65 #endif 66 #ifndef MWL_AGGR_SIZE 67 #define MWL_AGGR_SIZE 3839 /* max tx agregation size */ 68 #endif 69 #define MWL_AGEINTERVAL 1 /* poke f/w every sec to age q's */ 70 #define MWL_MAXSTAID 64 /* max of 64 stations */ 71 72 /* 73 * DMA state for tx/rx descriptors. 74 */ 75 76 /* 77 * Software backed version of tx/rx descriptors. We keep 78 * the software state out of the h/w descriptor structure 79 * so that may be allocated in uncached memory w/o paying 80 * performance hit. 81 */ 82 struct mwl_txbuf { 83 STAILQ_ENTRY(mwl_txbuf) bf_list; 84 void *bf_desc; /* h/w descriptor */ 85 bus_addr_t bf_daddr; /* physical addr of desc */ 86 bus_dmamap_t bf_dmamap; /* DMA map for descriptors */ 87 int bf_nseg; 88 bus_dma_segment_t bf_segs[MWL_TXDESC]; 89 struct mbuf *bf_m; 90 struct ieee80211_node *bf_node; 91 struct mwl_txq *bf_txq; /* backpointer to tx q/ring */ 92 }; 93 typedef STAILQ_HEAD(, mwl_txbuf) mwl_txbufhead; 94 95 /* 96 * Common "base class" for tx/rx descriptor resources 97 * allocated using the bus dma api. 98 */ 99 struct mwl_descdma { 100 const char* dd_name; 101 void *dd_desc; /* descriptors */ 102 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 103 bus_size_t dd_desc_len; /* size of dd_desc */ 104 bus_dma_segment_t dd_dseg; 105 int dd_dnseg; /* number of segments */ 106 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 107 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 108 void *dd_bufptr; /* associated buffers */ 109 }; 110 111 /* 112 * TX/RX ring definitions. There are 4 tx rings, one 113 * per AC, and 1 rx ring. Note carefully that transmit 114 * descriptors are treated as a contiguous chunk and the 115 * firmware pre-fetches descriptors. This means that we 116 * must preserve order when moving descriptors between 117 * the active+free lists; otherwise we may stall transmit. 118 */ 119 struct mwl_txq { 120 struct mwl_descdma dma; /* bus dma resources */ 121 struct mtx lock; /* tx q lock */ 122 char name[12]; /* e.g. "mwl0_txq4" */ 123 int qnum; /* f/w q number */ 124 int txpri; /* f/w tx priority */ 125 int nfree; /* # buffers on free list */ 126 mwl_txbufhead free; /* queue of free buffers */ 127 mwl_txbufhead active; /* queue of active buffers */ 128 }; 129 130 #define MWL_TXQ_LOCK_INIT(_sc, _tq) do { \ 131 snprintf((_tq)->name, sizeof((_tq)->name), "%s_txq%u", \ 132 device_get_nameunit((_sc)->sc_dev), (_tq)->qnum); \ 133 mtx_init(&(_tq)->lock, (_tq)->name, NULL, MTX_DEF); \ 134 } while (0) 135 #define MWL_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->lock) 136 #define MWL_TXQ_LOCK(_tq) mtx_lock(&(_tq)->lock) 137 #define MWL_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->lock) 138 #define MWL_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->lock, MA_OWNED) 139 140 #define MWL_TXDESC_SYNC(txq, ds, how) do { \ 141 bus_dmamap_sync((txq)->dma.dd_dmat, (txq)->dma.dd_dmamap, how); \ 142 } while(0) 143 144 /* 145 * RX dma buffers that are not in use are kept on a list. 146 */ 147 struct mwl_jumbo { 148 SLIST_ENTRY(mwl_jumbo) next; 149 }; 150 typedef SLIST_HEAD(, mwl_jumbo) mwl_jumbohead; 151 152 #define MWL_JUMBO_DATA2BUF(_data) ((struct mwl_jumbo *)(_data)) 153 #define MWL_JUMBO_BUF2DATA(_buf) ((uint8_t *)(_buf)) 154 #define MWL_JUMBO_OFFSET(_sc, _data) \ 155 (((const uint8_t *)(_data)) - (const uint8_t *)((_sc)->sc_rxmem)) 156 #define MWL_JUMBO_DMA_ADDR(_sc, _data) \ 157 ((_sc)->sc_rxmem_paddr + MWL_JUMBO_OFFSET(_sc, _data)) 158 159 struct mwl_rxbuf { 160 STAILQ_ENTRY(mwl_rxbuf) bf_list; 161 void *bf_desc; /* h/w descriptor */ 162 bus_addr_t bf_daddr; /* physical addr of desc */ 163 uint8_t *bf_data; /* rx data area */ 164 }; 165 typedef STAILQ_HEAD(, mwl_rxbuf) mwl_rxbufhead; 166 167 #define MWL_RXDESC_SYNC(sc, ds, how) do { \ 168 bus_dmamap_sync((sc)->sc_rxdma.dd_dmat, (sc)->sc_rxdma.dd_dmamap, how);\ 169 } while (0) 170 171 /* 172 * BA stream state. One of these is setup for each stream 173 * allocated/created for use. We pre-allocate the h/w stream 174 * before sending ADDBA request then complete the setup when 175 * get ADDBA response (success). The completed state is setup 176 * to optimize the fast path in mwl_txstart--we precalculate 177 * the QoS control bits in the outbound frame and use those 178 * to identify which BA stream to use (assigning the h/w q to 179 * the TxPriority field of the descriptor). 180 * 181 * NB: Each station may have at most MWL_MAXBA streams at one time. 182 */ 183 struct mwl_bastate { 184 uint16_t qos; /* QoS ctl for BA stream */ 185 uint8_t txq; /* h/w q for BA stream */ 186 const MWL_HAL_BASTREAM *bastream; /* A-MPDU BA stream */ 187 }; 188 189 static __inline__ void 190 mwl_bastream_setup(struct mwl_bastate *bas, int ac, int txq) 191 { 192 bas->txq = txq; 193 bas->qos = htole16(WME_AC_TO_TID(ac) | IEEE80211_QOS_ACKPOLICY_BA); 194 } 195 196 static __inline__ void 197 mwl_bastream_free(struct mwl_bastate *bas) 198 { 199 bas->qos = 0; 200 bas->bastream = NULL; 201 /* NB: don't need to clear txq */ 202 } 203 204 /* 205 * Check the QoS control bits from an outbound frame against the 206 * value calculated when a BA stream is setup (above). We need 207 * to match the TID and also the ACK policy so we only match AMPDU 208 * frames. The bits from the frame are assumed in network byte 209 * order, hence the potential byte swap. 210 */ 211 static __inline__ int 212 mwl_bastream_match(const struct mwl_bastate *bas, uint16_t qos) 213 { 214 return (qos & htole16(IEEE80211_QOS_TID|IEEE80211_QOS_ACKPOLICY)) == 215 bas->qos; 216 } 217 218 /* driver-specific node state */ 219 struct mwl_node { 220 struct ieee80211_node mn_node; /* base class */ 221 struct mwl_ant_info mn_ai; /* antenna info */ 222 uint32_t mn_avgrssi; /* average rssi over all rx frames */ 223 uint16_t mn_staid; /* firmware station id */ 224 struct mwl_bastate mn_ba[MWL_MAXBA]; 225 struct mwl_hal_vap *mn_hvap; /* hal vap handle */ 226 }; 227 #define MWL_NODE(ni) ((struct mwl_node *)(ni)) 228 #define MWL_NODE_CONST(ni) ((const struct mwl_node *)(ni)) 229 230 /* 231 * Driver-specific vap state. 232 */ 233 struct mwl_vap { 234 struct ieee80211vap mv_vap; /* base class */ 235 struct mwl_hal_vap *mv_hvap; /* hal vap handle */ 236 struct mwl_hal_vap *mv_ap_hvap; /* ap hal vap handle for wds */ 237 uint16_t mv_last_ps_sta; /* last count of ps sta's */ 238 uint16_t mv_eapolformat; /* fixed tx rate for EAPOL */ 239 int (*mv_newstate)(struct ieee80211vap *, 240 enum ieee80211_state, int); 241 int (*mv_set_tim)(struct ieee80211_node *, int); 242 }; 243 #define MWL_VAP(vap) ((struct mwl_vap *)(vap)) 244 #define MWL_VAP_CONST(vap) ((const struct mwl_vap *)(vap)) 245 246 struct mwl_softc { 247 struct ifnet *sc_ifp; /* interface common */ 248 struct mwl_stats sc_stats; /* interface statistics */ 249 int sc_debug; 250 device_t sc_dev; 251 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 252 bus_space_handle_t sc_io0h; /* BAR 0 */ 253 bus_space_tag_t sc_io0t; 254 bus_space_handle_t sc_io1h; /* BAR 1 */ 255 bus_space_tag_t sc_io1t; 256 struct mtx sc_mtx; /* master lock (recursive) */ 257 struct taskqueue *sc_tq; /* private task queue */ 258 struct callout sc_watchdog; 259 int sc_tx_timer; 260 unsigned int sc_invalid : 1, /* disable hardware accesses */ 261 sc_recvsetup:1, /* recv setup */ 262 sc_csapending:1,/* 11h channel switch pending */ 263 sc_radarena : 1,/* radar detection enabled */ 264 sc_rxblocked: 1;/* rx waiting for dma buffers */ 265 266 struct mwl_hal *sc_mh; /* h/w access layer */ 267 struct mwl_hal_vap *sc_hvap; /* hal vap handle */ 268 struct mwl_hal_hwspec sc_hwspecs; /* h/w capabilities */ 269 uint32_t sc_fwrelease; /* release # of loaded f/w */ 270 struct mwl_hal_txrxdma sc_hwdma; /* h/w dma setup */ 271 uint32_t sc_imask; /* interrupt mask copy */ 272 enum ieee80211_phymode sc_curmode; 273 u_int16_t sc_curaid; /* current association id */ 274 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 275 MWL_HAL_CHANNEL sc_curchan; 276 MWL_HAL_TXRATE_HANDLING sc_txratehandling; 277 u_int16_t sc_rxantenna; /* rx antenna */ 278 u_int16_t sc_txantenna; /* tx antenna */ 279 uint8_t sc_napvaps; /* # ap mode vaps */ 280 uint8_t sc_nwdsvaps; /* # wds mode vaps */ 281 uint8_t sc_nstavaps; /* # sta mode vaps */ 282 uint8_t sc_ndwdsvaps; /* # sta mode dwds vaps */ 283 uint8_t sc_nbssid0; /* # vap's using base mac */ 284 uint32_t sc_bssidmask; /* bssid mask */ 285 286 void (*sc_recv_mgmt)(struct ieee80211com *, 287 struct mbuf *, 288 struct ieee80211_node *, 289 int, int, int, u_int32_t); 290 int (*sc_newstate)(struct ieee80211com *, 291 enum ieee80211_state, int); 292 void (*sc_node_cleanup)(struct ieee80211_node *); 293 void (*sc_node_drain)(struct ieee80211_node *); 294 int (*sc_recv_action)(struct ieee80211_node *, 295 const struct ieee80211_frame *, 296 const uint8_t *, const uint8_t *); 297 int (*sc_addba_request)(struct ieee80211_node *, 298 struct ieee80211_tx_ampdu *, 299 int dialogtoken, int baparamset, 300 int batimeout); 301 int (*sc_addba_response)(struct ieee80211_node *, 302 struct ieee80211_tx_ampdu *, 303 int status, int baparamset, 304 int batimeout); 305 void (*sc_addba_stop)(struct ieee80211_node *, 306 struct ieee80211_tx_ampdu *); 307 308 struct mwl_descdma sc_rxdma; /* rx bus dma resources */ 309 mwl_rxbufhead sc_rxbuf; /* rx buffers */ 310 struct mwl_rxbuf *sc_rxnext; /* next rx buffer to process */ 311 struct task sc_rxtask; /* rx int processing */ 312 void *sc_rxmem; /* rx dma buffer pool */ 313 bus_dma_tag_t sc_rxdmat; /* rx bus DMA tag */ 314 bus_size_t sc_rxmemsize; /* rx dma buffer pool size */ 315 bus_dmamap_t sc_rxmap; /* map for rx dma buffers */ 316 bus_addr_t sc_rxmem_paddr; /* physical addr of sc_rxmem */ 317 mwl_jumbohead sc_rxfree; /* list of free dma buffers */ 318 int sc_nrxfree; /* # buffers on rx free list */ 319 struct mtx sc_rxlock; /* lock on sc_rxfree */ 320 321 struct mwl_txq sc_txq[MWL_NUM_TX_QUEUES]; 322 struct mwl_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 323 struct mbuf *sc_aggrq; /* aggregation q */ 324 struct task sc_txtask; /* tx int processing */ 325 struct task sc_bawatchdogtask;/* BA watchdog processing */ 326 327 struct task sc_radartask; /* radar detect processing */ 328 struct task sc_chanswitchtask;/* chan switch processing */ 329 330 uint8_t sc_staid[MWL_MAXSTAID/NBBY]; 331 int sc_ageinterval; 332 struct callout sc_timer; /* periodic work */ 333 334 struct mwl_tx_radiotap_header sc_tx_th; 335 struct mwl_rx_radiotap_header sc_rx_th; 336 }; 337 338 #define MWL_LOCK_INIT(_sc) \ 339 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 340 NULL, MTX_DEF | MTX_RECURSE) 341 #define MWL_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 342 #define MWL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 343 #define MWL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 344 #define MWL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 345 346 #define MWL_RXFREE_INIT(_sc) \ 347 mtx_init(&(_sc)->sc_rxlock, device_get_nameunit((_sc)->sc_dev), \ 348 NULL, MTX_DEF) 349 #define MWL_RXFREE_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rxlock) 350 #define MWL_RXFREE_LOCK(_sc) mtx_lock(&(_sc)->sc_rxlock) 351 #define MWL_RXFREE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rxlock) 352 #define MWL_RXFREE_ASSERT(_sc) mtx_assert(&(_sc)->sc_rxlock, MA_OWNED) 353 354 int mwl_attach(u_int16_t, struct mwl_softc *); 355 int mwl_detach(struct mwl_softc *); 356 void mwl_resume(struct mwl_softc *); 357 void mwl_suspend(struct mwl_softc *); 358 void mwl_shutdown(void *); 359 void mwl_intr(void *); 360 361 #endif /* _DEV_MWL_MVVAR_H */ 362