1b2fc195eSAndrew Gallatin /******************************************************************************* 24d846d26SWarner Losh SPDX-License-Identifier: BSD-2-Clause 3b2fc195eSAndrew Gallatin 401638550SAndrew Gallatin Copyright (c) 2006-2009, Myricom Inc. 5b2fc195eSAndrew Gallatin All rights reserved. 6b2fc195eSAndrew Gallatin 7b2fc195eSAndrew Gallatin Redistribution and use in source and binary forms, with or without 8b2fc195eSAndrew Gallatin modification, are permitted provided that the following conditions are met: 9b2fc195eSAndrew Gallatin 10b2fc195eSAndrew Gallatin 1. Redistributions of source code must retain the above copyright notice, 11b2fc195eSAndrew Gallatin this list of conditions and the following disclaimer. 12b2fc195eSAndrew Gallatin 13eb8e82f5SAndrew Gallatin 2. Neither the name of the Myricom Inc, nor the names of its 14b2fc195eSAndrew Gallatin contributors may be used to endorse or promote products derived from 15b2fc195eSAndrew Gallatin this software without specific prior written permission. 16b2fc195eSAndrew Gallatin 17b2fc195eSAndrew Gallatin THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18b2fc195eSAndrew Gallatin AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19b2fc195eSAndrew Gallatin IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20b2fc195eSAndrew Gallatin ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21b2fc195eSAndrew Gallatin LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22b2fc195eSAndrew Gallatin CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23b2fc195eSAndrew Gallatin SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24b2fc195eSAndrew Gallatin INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25b2fc195eSAndrew Gallatin CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26b2fc195eSAndrew Gallatin ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27b2fc195eSAndrew Gallatin POSSIBILITY OF SUCH DAMAGE. 28b2fc195eSAndrew Gallatin ***************************************************************************/ 29b2fc195eSAndrew Gallatin 305e7d8541SAndrew Gallatin #ifndef _myri10ge_mcp_h 315e7d8541SAndrew Gallatin #define _myri10ge_mcp_h 32b2fc195eSAndrew Gallatin 335e7d8541SAndrew Gallatin #define MXGEFW_VERSION_MAJOR 1 345e7d8541SAndrew Gallatin #define MXGEFW_VERSION_MINOR 4 355e7d8541SAndrew Gallatin 3601638550SAndrew Gallatin #if defined MXGEFW && !defined _stdint_h_ 37b2fc195eSAndrew Gallatin typedef signed char int8_t; 38b2fc195eSAndrew Gallatin typedef signed short int16_t; 39b2fc195eSAndrew Gallatin typedef signed int int32_t; 40b2fc195eSAndrew Gallatin typedef signed long long int64_t; 41b2fc195eSAndrew Gallatin typedef unsigned char uint8_t; 42b2fc195eSAndrew Gallatin typedef unsigned short uint16_t; 43b2fc195eSAndrew Gallatin typedef unsigned int uint32_t; 44b2fc195eSAndrew Gallatin typedef unsigned long long uint64_t; 45b2fc195eSAndrew Gallatin #endif 46b2fc195eSAndrew Gallatin 47b2fc195eSAndrew Gallatin /* 8 Bytes */ 485e7d8541SAndrew Gallatin struct mcp_dma_addr { 49b2fc195eSAndrew Gallatin uint32_t high; 50b2fc195eSAndrew Gallatin uint32_t low; 515e7d8541SAndrew Gallatin }; 525e7d8541SAndrew Gallatin typedef struct mcp_dma_addr mcp_dma_addr_t; 53b2fc195eSAndrew Gallatin 541e413cf9SAndrew Gallatin /* 4 Bytes */ 555e7d8541SAndrew Gallatin struct mcp_slot { 565e7d8541SAndrew Gallatin uint16_t checksum; 575e7d8541SAndrew Gallatin uint16_t length; 585e7d8541SAndrew Gallatin }; 595e7d8541SAndrew Gallatin typedef struct mcp_slot mcp_slot_t; 60b2fc195eSAndrew Gallatin 61c587e59fSAndrew Gallatin #ifdef MXGEFW_NDIS 621e413cf9SAndrew Gallatin /* 8-byte descriptor, exclusively used by NDIS drivers. */ 631e413cf9SAndrew Gallatin struct mcp_slot_8 { 641e413cf9SAndrew Gallatin /* Place hash value at the top so it gets written before length. 651e413cf9SAndrew Gallatin * The driver polls length. 661e413cf9SAndrew Gallatin */ 671e413cf9SAndrew Gallatin uint32_t hash; 681e413cf9SAndrew Gallatin uint16_t checksum; 691e413cf9SAndrew Gallatin uint16_t length; 701e413cf9SAndrew Gallatin }; 711e413cf9SAndrew Gallatin typedef struct mcp_slot_8 mcp_slot_8_t; 721e413cf9SAndrew Gallatin 73c587e59fSAndrew Gallatin /* Two bits of length in mcp_slot are used to indicate hash type. */ 74c587e59fSAndrew Gallatin #define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 75c587e59fSAndrew Gallatin #define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 76c587e59fSAndrew Gallatin #define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 77c587e59fSAndrew Gallatin #define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 78c587e59fSAndrew Gallatin #endif 79c587e59fSAndrew Gallatin 80b2fc195eSAndrew Gallatin /* 64 Bytes */ 815e7d8541SAndrew Gallatin struct mcp_cmd { 82b2fc195eSAndrew Gallatin uint32_t cmd; 83b2fc195eSAndrew Gallatin uint32_t data0; /* will be low portion if data > 32 bits */ 84b2fc195eSAndrew Gallatin /* 8 */ 85b2fc195eSAndrew Gallatin uint32_t data1; /* will be high portion if data > 32 bits */ 86b2fc195eSAndrew Gallatin uint32_t data2; /* currently unused.. */ 87b2fc195eSAndrew Gallatin /* 16 */ 885e7d8541SAndrew Gallatin struct mcp_dma_addr response_addr; 89b2fc195eSAndrew Gallatin /* 24 */ 90b2fc195eSAndrew Gallatin uint8_t pad[40]; 915e7d8541SAndrew Gallatin }; 925e7d8541SAndrew Gallatin typedef struct mcp_cmd mcp_cmd_t; 93b2fc195eSAndrew Gallatin 94b2fc195eSAndrew Gallatin /* 8 Bytes */ 955e7d8541SAndrew Gallatin struct mcp_cmd_response { 96b2fc195eSAndrew Gallatin uint32_t data; 97b2fc195eSAndrew Gallatin uint32_t result; 985e7d8541SAndrew Gallatin }; 995e7d8541SAndrew Gallatin typedef struct mcp_cmd_response mcp_cmd_response_t; 100b2fc195eSAndrew Gallatin 101b2fc195eSAndrew Gallatin /* 102b2fc195eSAndrew Gallatin flags used in mcp_kreq_ether_send_t: 103b2fc195eSAndrew Gallatin 104b2fc195eSAndrew Gallatin The SMALL flag is only needed in the first segment. It is raised 105b2fc195eSAndrew Gallatin for packets that are total less or equal 512 bytes. 106b2fc195eSAndrew Gallatin 107b2fc195eSAndrew Gallatin The CKSUM flag must be set in all segments. 108b2fc195eSAndrew Gallatin 109b2fc195eSAndrew Gallatin The PADDED flags is set if the packet needs to be padded, and it 110b2fc195eSAndrew Gallatin must be set for all segments. 111b2fc195eSAndrew Gallatin 1125e7d8541SAndrew Gallatin The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 113b2fc195eSAndrew Gallatin length of all previous segments was odd. 114b2fc195eSAndrew Gallatin */ 115b2fc195eSAndrew Gallatin 1165e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_SMALL 0x1 1175e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_TSO_HDR 0x1 1185e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_FIRST 0x2 1195e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_ALIGN_ODD 0x4 1205e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_CKSUM 0x8 1215e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_TSO_LAST 0x8 1225e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_NO_TSO 0x10 1235e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_TSO_CHOP 0x10 1245e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_TSO_PLD 0x20 125b2fc195eSAndrew Gallatin 1265e7d8541SAndrew Gallatin #define MXGEFW_SEND_SMALL_SIZE 1520 1275e7d8541SAndrew Gallatin #define MXGEFW_MAX_MTU 9400 128b2fc195eSAndrew Gallatin 1295e7d8541SAndrew Gallatin union mcp_pso_or_cumlen { 130b2fc195eSAndrew Gallatin uint16_t pseudo_hdr_offset; 131b2fc195eSAndrew Gallatin uint16_t cum_len; 1325e7d8541SAndrew Gallatin }; 1335e7d8541SAndrew Gallatin typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 134b2fc195eSAndrew Gallatin 1355e7d8541SAndrew Gallatin #define MXGEFW_MAX_SEND_DESC 12 1365e7d8541SAndrew Gallatin #define MXGEFW_PAD 2 137b2fc195eSAndrew Gallatin 138b2fc195eSAndrew Gallatin /* 16 Bytes */ 1395e7d8541SAndrew Gallatin struct mcp_kreq_ether_send { 140b2fc195eSAndrew Gallatin uint32_t addr_high; 141b2fc195eSAndrew Gallatin uint32_t addr_low; 1425e7d8541SAndrew Gallatin uint16_t pseudo_hdr_offset; 143b2fc195eSAndrew Gallatin uint16_t length; 144b2fc195eSAndrew Gallatin uint8_t pad; 1455e7d8541SAndrew Gallatin uint8_t rdma_count; 146b2fc195eSAndrew Gallatin uint8_t cksum_offset; /* where to start computing cksum */ 1475e7d8541SAndrew Gallatin uint8_t flags; /* as defined above */ 1485e7d8541SAndrew Gallatin }; 1495e7d8541SAndrew Gallatin typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 150b2fc195eSAndrew Gallatin 151b2fc195eSAndrew Gallatin /* 8 Bytes */ 1525e7d8541SAndrew Gallatin struct mcp_kreq_ether_recv { 153b2fc195eSAndrew Gallatin uint32_t addr_high; 154b2fc195eSAndrew Gallatin uint32_t addr_low; 1555e7d8541SAndrew Gallatin }; 1565e7d8541SAndrew Gallatin typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 157b2fc195eSAndrew Gallatin 158b2fc195eSAndrew Gallatin /* Commands */ 159b2fc195eSAndrew Gallatin 1600fa7f681SAndrew Gallatin #define MXGEFW_BOOT_HANDOFF 0xfc0000 1610fa7f681SAndrew Gallatin #define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 1620fa7f681SAndrew Gallatin 1630fa7f681SAndrew Gallatin #define MXGEFW_ETH_CMD 0xf80000 1640fa7f681SAndrew Gallatin #define MXGEFW_ETH_SEND_4 0x200000 1650fa7f681SAndrew Gallatin #define MXGEFW_ETH_SEND_1 0x240000 1660fa7f681SAndrew Gallatin #define MXGEFW_ETH_SEND_2 0x280000 1670fa7f681SAndrew Gallatin #define MXGEFW_ETH_SEND_3 0x2c0000 1680fa7f681SAndrew Gallatin #define MXGEFW_ETH_RECV_SMALL 0x300000 1690fa7f681SAndrew Gallatin #define MXGEFW_ETH_RECV_BIG 0x340000 17088843c54SAndrew Gallatin #define MXGEFW_ETH_SEND_GO 0x380000 17188843c54SAndrew Gallatin #define MXGEFW_ETH_SEND_STOP 0x3C0000 1720fa7f681SAndrew Gallatin 1730fa7f681SAndrew Gallatin #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 1740fa7f681SAndrew Gallatin #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 175b2fc195eSAndrew Gallatin 1765e7d8541SAndrew Gallatin enum myri10ge_mcp_cmd_type { 1775e7d8541SAndrew Gallatin MXGEFW_CMD_NONE = 0, 178b2fc195eSAndrew Gallatin /* Reset the mcp, it is left in a safe state, waiting 179b2fc195eSAndrew Gallatin for the driver to set all its parameters */ 18001638550SAndrew Gallatin MXGEFW_CMD_RESET = 1, 181b2fc195eSAndrew Gallatin 182b2fc195eSAndrew Gallatin /* get the version number of the current firmware.. 183b2fc195eSAndrew Gallatin (may be available in the eeprom strings..? */ 18401638550SAndrew Gallatin MXGEFW_GET_MCP_VERSION = 2, 185b2fc195eSAndrew Gallatin 186b2fc195eSAndrew Gallatin /* Parameters which must be set by the driver before it can 1875e7d8541SAndrew Gallatin issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 1885e7d8541SAndrew Gallatin MXGEFW_CMD_RESET is issued */ 189b2fc195eSAndrew Gallatin 19001638550SAndrew Gallatin MXGEFW_CMD_SET_INTRQ_DMA = 3, 19188843c54SAndrew Gallatin /* data0 = LSW of the host address 19288843c54SAndrew Gallatin * data1 = MSW of the host address 19388843c54SAndrew Gallatin * data2 = slice number if multiple slices are used 19488843c54SAndrew Gallatin */ 19588843c54SAndrew Gallatin 19601638550SAndrew Gallatin MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */ 19701638550SAndrew Gallatin MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */ 198b2fc195eSAndrew Gallatin 199b2fc195eSAndrew Gallatin 200b2fc195eSAndrew Gallatin /* Parameters which refer to lanai SRAM addresses where the 201b2fc195eSAndrew Gallatin driver must issue PIO writes for various things */ 202b2fc195eSAndrew Gallatin 20301638550SAndrew Gallatin MXGEFW_CMD_GET_SEND_OFFSET = 6, 20401638550SAndrew Gallatin MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7, 20501638550SAndrew Gallatin MXGEFW_CMD_GET_BIG_RX_OFFSET = 8, 20688843c54SAndrew Gallatin /* data0 = slice number if multiple slices are used */ 20788843c54SAndrew Gallatin 20801638550SAndrew Gallatin MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9, 20901638550SAndrew Gallatin MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10, 210b2fc195eSAndrew Gallatin 211b2fc195eSAndrew Gallatin /* Parameters which refer to rings stored on the MCP, 212b2fc195eSAndrew Gallatin and whose size is controlled by the mcp */ 213b2fc195eSAndrew Gallatin 21401638550SAndrew Gallatin MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */ 21501638550SAndrew Gallatin MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */ 216b2fc195eSAndrew Gallatin 217b2fc195eSAndrew Gallatin /* Parameters which refer to rings stored in the host, 218b2fc195eSAndrew Gallatin and whose size is controlled by the host. Note that 219b2fc195eSAndrew Gallatin all must be physically contiguous and must contain 220b2fc195eSAndrew Gallatin a power of 2 number of entries. */ 221b2fc195eSAndrew Gallatin 22201638550SAndrew Gallatin MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ 2237a22215cSEitan Adler #define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1U << 31) 224b2fc195eSAndrew Gallatin 225b2fc195eSAndrew Gallatin /* command to bring ethernet interface up. Above parameters 226b2fc195eSAndrew Gallatin (plus mtu & mac address) must have been exchanged prior 227b2fc195eSAndrew Gallatin to issuing this command */ 22801638550SAndrew Gallatin MXGEFW_CMD_ETHERNET_UP = 14, 229b2fc195eSAndrew Gallatin 230b2fc195eSAndrew Gallatin /* command to bring ethernet interface down. No further sends 2315e7d8541SAndrew Gallatin or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 232b2fc195eSAndrew Gallatin is issued, and all interrupt queues must be flushed prior 233b2fc195eSAndrew Gallatin to ack'ing this command */ 234b2fc195eSAndrew Gallatin 23501638550SAndrew Gallatin MXGEFW_CMD_ETHERNET_DOWN = 15, 236b2fc195eSAndrew Gallatin 237b2fc195eSAndrew Gallatin /* commands the driver may issue live, without resetting 238b2fc195eSAndrew Gallatin the nic. Note that increasing the mtu "live" should 239b2fc195eSAndrew Gallatin only be done if the driver has already supplied buffers 240b2fc195eSAndrew Gallatin sufficiently large to handle the new mtu. Decreasing 241b2fc195eSAndrew Gallatin the mtu live is safe */ 242b2fc195eSAndrew Gallatin 24301638550SAndrew Gallatin MXGEFW_CMD_SET_MTU = 16, 24401638550SAndrew Gallatin MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */ 24501638550SAndrew Gallatin MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */ 24601638550SAndrew Gallatin MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */ 247b2fc195eSAndrew Gallatin 24801638550SAndrew Gallatin MXGEFW_ENABLE_PROMISC = 20, 24901638550SAndrew Gallatin MXGEFW_DISABLE_PROMISC = 21, 25001638550SAndrew Gallatin MXGEFW_SET_MAC_ADDRESS = 22, 251b2fc195eSAndrew Gallatin 25201638550SAndrew Gallatin MXGEFW_ENABLE_FLOW_CONTROL = 23, 25301638550SAndrew Gallatin MXGEFW_DISABLE_FLOW_CONTROL = 24, 2545e7d8541SAndrew Gallatin 2555e7d8541SAndrew Gallatin /* do a DMA test 2565e7d8541SAndrew Gallatin data0,data1 = DMA address 2575e7d8541SAndrew Gallatin data2 = RDMA length (MSH), WDMA length (LSH) 2585e7d8541SAndrew Gallatin command return data = repetitions (MSH), 0.5-ms ticks (LSH) 2595e7d8541SAndrew Gallatin */ 26001638550SAndrew Gallatin MXGEFW_DMA_TEST = 25, 2610fa7f681SAndrew Gallatin 26201638550SAndrew Gallatin MXGEFW_ENABLE_ALLMULTI = 26, 26301638550SAndrew Gallatin MXGEFW_DISABLE_ALLMULTI = 27, 2640fa7f681SAndrew Gallatin 2650fa7f681SAndrew Gallatin /* returns MXGEFW_CMD_ERROR_MULTICAST 2660fa7f681SAndrew Gallatin if there is no room in the cache 2670fa7f681SAndrew Gallatin data0,MSH(data1) = multicast group address */ 26801638550SAndrew Gallatin MXGEFW_JOIN_MULTICAST_GROUP = 28, 2690fa7f681SAndrew Gallatin /* returns MXGEFW_CMD_ERROR_MULTICAST 2700fa7f681SAndrew Gallatin if the address is not in the cache, 2710fa7f681SAndrew Gallatin or is equal to FF-FF-FF-FF-FF-FF 2720fa7f681SAndrew Gallatin data0,MSH(data1) = multicast group address */ 27301638550SAndrew Gallatin MXGEFW_LEAVE_MULTICAST_GROUP = 29, 27401638550SAndrew Gallatin MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30, 2750fa7f681SAndrew Gallatin 27601638550SAndrew Gallatin MXGEFW_CMD_SET_STATS_DMA_V2 = 31, 2770fa7f681SAndrew Gallatin /* data0, data1 = bus addr, 27888843c54SAndrew Gallatin * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 27988843c54SAndrew Gallatin * adding new stuff to mcp_irq_data without changing the ABI 28088843c54SAndrew Gallatin * 28188843c54SAndrew Gallatin * If multiple slices are used, data2 contains both the size of the 28288843c54SAndrew Gallatin * structure (in the lower 16 bits) and the slice number 28388843c54SAndrew Gallatin * (in the upper 16 bits). 28488843c54SAndrew Gallatin */ 2858fe615baSAndrew Gallatin 28601638550SAndrew Gallatin MXGEFW_CMD_UNALIGNED_TEST = 32, 2878fe615baSAndrew Gallatin /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 2888fe615baSAndrew Gallatin chipset */ 2898fe615baSAndrew Gallatin 29001638550SAndrew Gallatin MXGEFW_CMD_UNALIGNED_STATUS = 33, 2918fe615baSAndrew Gallatin /* return data = boolean, true if the chipset is known to be unaligned */ 292053e637fSAndrew Gallatin 29301638550SAndrew Gallatin MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 294053e637fSAndrew Gallatin /* data0 = number of big buffers to use. It must be 0 or a power of 2. 295053e637fSAndrew Gallatin * 0 indicates that the NIC consumes as many buffers as they are required 296053e637fSAndrew Gallatin * for packet. This is the default behavior. 297053e637fSAndrew Gallatin * A power of 2 number indicates that the NIC always uses the specified 298053e637fSAndrew Gallatin * number of buffers for each big receive packet. 299053e637fSAndrew Gallatin * It is up to the driver to ensure that this value is big enough for 300053e637fSAndrew Gallatin * the NIC to be able to receive maximum-sized packets. 301053e637fSAndrew Gallatin */ 302c587e59fSAndrew Gallatin 30301638550SAndrew Gallatin MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35, 30401638550SAndrew Gallatin MXGEFW_CMD_ENABLE_RSS_QUEUES = 36, 305c587e59fSAndrew Gallatin /* data0 = number of slices n (0, 1, ..., n-1) to enable 30688843c54SAndrew Gallatin * data1 = interrupt mode | use of multiple transmit queues. 30788843c54SAndrew Gallatin * 0=share one INTx/MSI. 30888843c54SAndrew Gallatin * 1=use one MSI-X per queue. 309c587e59fSAndrew Gallatin * If all queues share one interrupt, the driver must have set 310c587e59fSAndrew Gallatin * RSS_SHARED_INTERRUPT_DMA before enabling queues. 31188843c54SAndrew Gallatin * 2=enable both receive and send queues. 31288843c54SAndrew Gallatin * Without this bit set, only one send queue (slice 0's send queue) 31388843c54SAndrew Gallatin * is enabled. The receive queues are always enabled. 314c587e59fSAndrew Gallatin */ 31588843c54SAndrew Gallatin #define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 31688843c54SAndrew Gallatin #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 31788843c54SAndrew Gallatin #define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 3181e413cf9SAndrew Gallatin 31901638550SAndrew Gallatin MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37, 32001638550SAndrew Gallatin MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38, 321c587e59fSAndrew Gallatin /* data0, data1 = bus address lsw, msw */ 32201638550SAndrew Gallatin MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39, 323c587e59fSAndrew Gallatin /* get the offset of the indirection table */ 32401638550SAndrew Gallatin MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40, 325c587e59fSAndrew Gallatin /* set the size of the indirection table */ 32601638550SAndrew Gallatin MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41, 327c587e59fSAndrew Gallatin /* get the offset of the secret key */ 32801638550SAndrew Gallatin MXGEFW_CMD_RSS_KEY_UPDATED = 42, 329c587e59fSAndrew Gallatin /* tell nic that the secret key's been updated */ 33001638550SAndrew Gallatin MXGEFW_CMD_SET_RSS_ENABLE = 43, 331c587e59fSAndrew Gallatin /* data0 = enable/disable rss 332c587e59fSAndrew Gallatin * 0: disable rss. nic does not distribute receive packets. 333c587e59fSAndrew Gallatin * 1: enable rss. nic distributes receive packets among queues. 334c587e59fSAndrew Gallatin * data1 = hash type 3351e413cf9SAndrew Gallatin * 1: IPV4 (required by RSS) 3361e413cf9SAndrew Gallatin * 2: TCP_IPV4 (required by RSS) 3371e413cf9SAndrew Gallatin * 3: IPV4 | TCP_IPV4 (required by RSS) 3381e413cf9SAndrew Gallatin * 4: source port 33988843c54SAndrew Gallatin * 5: source port + destination port 340c587e59fSAndrew Gallatin */ 3411e413cf9SAndrew Gallatin #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 3421e413cf9SAndrew Gallatin #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 3431e413cf9SAndrew Gallatin #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 34488843c54SAndrew Gallatin #define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 34588843c54SAndrew Gallatin #define MXGEFW_RSS_HASH_TYPE_MAX 0x5 346c587e59fSAndrew Gallatin 34701638550SAndrew Gallatin MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44, 348c587e59fSAndrew Gallatin /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 349c587e59fSAndrew Gallatin * If the header size of a IPv6 TSO packet is larger than the specified 350c587e59fSAndrew Gallatin * value, then the driver must not use TSO. 351c587e59fSAndrew Gallatin * This size restriction only applies to IPv6 TSO. 352c587e59fSAndrew Gallatin * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 353c587e59fSAndrew Gallatin * always has enough header buffer to store maximum-sized headers. 354c587e59fSAndrew Gallatin */ 355c587e59fSAndrew Gallatin 35601638550SAndrew Gallatin MXGEFW_CMD_SET_TSO_MODE = 45, 357c587e59fSAndrew Gallatin /* data0 = TSO mode. 358c587e59fSAndrew Gallatin * 0: Linux/FreeBSD style (NIC default) 359c587e59fSAndrew Gallatin * 1: NDIS/NetBSD style 360c587e59fSAndrew Gallatin */ 3611e413cf9SAndrew Gallatin #define MXGEFW_TSO_MODE_LINUX 0 3621e413cf9SAndrew Gallatin #define MXGEFW_TSO_MODE_NDIS 1 363c587e59fSAndrew Gallatin 36401638550SAndrew Gallatin MXGEFW_CMD_MDIO_READ = 46, 365c587e59fSAndrew Gallatin /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 36601638550SAndrew Gallatin MXGEFW_CMD_MDIO_WRITE = 47, 367c587e59fSAndrew Gallatin /* data0 = dev_addr, data1 = register/addr, data2 = value */ 368c587e59fSAndrew Gallatin 36901638550SAndrew Gallatin MXGEFW_CMD_I2C_READ = 48, 37001638550SAndrew Gallatin /* Starts to get a fresh copy of one byte or of the module i2c table, the 371c587e59fSAndrew Gallatin * obtained data is cached inside the xaui-xfi chip : 37201638550SAndrew Gallatin * data0 : 0 => get one byte, 1=> get 256 bytes 37301638550SAndrew Gallatin * data1 : If data0 == 0: location to refresh 37401638550SAndrew Gallatin * bit 7:0 register location 37501638550SAndrew Gallatin * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1) 37601638550SAndrew Gallatin * bit 23:16 is the i2c bus number (for multi-port NICs) 37701638550SAndrew Gallatin * If data0 == 1: unused 378c587e59fSAndrew Gallatin * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 37901638550SAndrew Gallatin * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts 380c587e59fSAndrew Gallatin * will return MXGEFW_CMD_ERROR_BUSY 381c587e59fSAndrew Gallatin */ 38201638550SAndrew Gallatin MXGEFW_CMD_I2C_BYTE = 49, 383c587e59fSAndrew Gallatin /* Return the last obtained copy of a given byte in the xfp i2c table 38401638550SAndrew Gallatin * (copy cached during the last relevant MXGEFW_CMD_I2C_READ) 385c587e59fSAndrew Gallatin * data0 : index of the desired table entry 386c587e59fSAndrew Gallatin * Return data = the byte stored at the requested index in the table 387c587e59fSAndrew Gallatin */ 3881e413cf9SAndrew Gallatin 38901638550SAndrew Gallatin MXGEFW_CMD_GET_VPUMP_OFFSET = 50, 3901e413cf9SAndrew Gallatin /* Return data = NIC memory offset of mcp_vpump_public_global */ 39101638550SAndrew Gallatin MXGEFW_CMD_RESET_VPUMP = 51, 3921e413cf9SAndrew Gallatin /* Resets the VPUMP state */ 3931e413cf9SAndrew Gallatin 39401638550SAndrew Gallatin MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52, 3951e413cf9SAndrew Gallatin /* data0 = mcp_slot type to use. 3961e413cf9SAndrew Gallatin * 0 = the default 4B mcp_slot 3971e413cf9SAndrew Gallatin * 1 = 8B mcp_slot_8 3981e413cf9SAndrew Gallatin */ 3991e413cf9SAndrew Gallatin #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 4001e413cf9SAndrew Gallatin #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 4011e413cf9SAndrew Gallatin 40201638550SAndrew Gallatin MXGEFW_CMD_SET_THROTTLE_FACTOR = 53, 4031e413cf9SAndrew Gallatin /* set the throttle factor for ethp_z8e 4041e413cf9SAndrew Gallatin data0 = throttle_factor 4051e413cf9SAndrew Gallatin throttle_factor = 256 * pcie-raw-speed / tx_speed 4061e413cf9SAndrew Gallatin tx_speed = 256 * pcie-raw-speed / throttle_factor 4071e413cf9SAndrew Gallatin 4081e413cf9SAndrew Gallatin For PCI-E x8: pcie-raw-speed == 16Gb/s 4091e413cf9SAndrew Gallatin For PCI-E x4: pcie-raw-speed == 8Gb/s 4101e413cf9SAndrew Gallatin 4111e413cf9SAndrew Gallatin ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 4121e413cf9SAndrew Gallatin ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 4131e413cf9SAndrew Gallatin 4141e413cf9SAndrew Gallatin with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 4151e413cf9SAndrew Gallatin with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 4161e413cf9SAndrew Gallatin */ 4171e413cf9SAndrew Gallatin 41801638550SAndrew Gallatin MXGEFW_CMD_VPUMP_UP = 54, 4191e413cf9SAndrew Gallatin /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 42001638550SAndrew Gallatin MXGEFW_CMD_GET_VPUMP_CLK = 55, 42188843c54SAndrew Gallatin /* Get the lanai clock */ 42288843c54SAndrew Gallatin 42301638550SAndrew Gallatin MXGEFW_CMD_GET_DCA_OFFSET = 56, 42488843c54SAndrew Gallatin /* offset of dca control for WDMAs */ 42588843c54SAndrew Gallatin 42688843c54SAndrew Gallatin /* VMWare NetQueue commands */ 42701638550SAndrew Gallatin MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57, 42801638550SAndrew Gallatin MXGEFW_CMD_NETQ_ADD_FILTER = 58, 42988843c54SAndrew Gallatin /* data0 = filter_id << 16 | queue << 8 | type */ 43088843c54SAndrew Gallatin /* data1 = MS4 of MAC Addr */ 43188843c54SAndrew Gallatin /* data2 = LS2_MAC << 16 | VLAN_tag */ 43201638550SAndrew Gallatin MXGEFW_CMD_NETQ_DEL_FILTER = 59, 43388843c54SAndrew Gallatin /* data0 = filter_id */ 43401638550SAndrew Gallatin MXGEFW_CMD_NETQ_QUERY1 = 60, 43501638550SAndrew Gallatin MXGEFW_CMD_NETQ_QUERY2 = 61, 43601638550SAndrew Gallatin MXGEFW_CMD_NETQ_QUERY3 = 62, 43701638550SAndrew Gallatin MXGEFW_CMD_NETQ_QUERY4 = 63, 4381e413cf9SAndrew Gallatin 43901638550SAndrew Gallatin MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64, 44001638550SAndrew Gallatin /* When set, small receive buffers can cross page boundaries. 44101638550SAndrew Gallatin * Both small and big receive buffers may start at any address. 44201638550SAndrew Gallatin * This option has performance implications, so use with caution. 44301638550SAndrew Gallatin */ 4445e7d8541SAndrew Gallatin }; 4455e7d8541SAndrew Gallatin typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 446b2fc195eSAndrew Gallatin 4475e7d8541SAndrew Gallatin enum myri10ge_mcp_cmd_status { 4485e7d8541SAndrew Gallatin MXGEFW_CMD_OK = 0, 44901638550SAndrew Gallatin MXGEFW_CMD_UNKNOWN = 1, 45001638550SAndrew Gallatin MXGEFW_CMD_ERROR_RANGE = 2, 45101638550SAndrew Gallatin MXGEFW_CMD_ERROR_BUSY = 3, 45201638550SAndrew Gallatin MXGEFW_CMD_ERROR_EMPTY = 4, 45301638550SAndrew Gallatin MXGEFW_CMD_ERROR_CLOSED = 5, 45401638550SAndrew Gallatin MXGEFW_CMD_ERROR_HASH_ERROR = 6, 45501638550SAndrew Gallatin MXGEFW_CMD_ERROR_BAD_PORT = 7, 45601638550SAndrew Gallatin MXGEFW_CMD_ERROR_RESOURCES = 8, 45701638550SAndrew Gallatin MXGEFW_CMD_ERROR_MULTICAST = 9, 45801638550SAndrew Gallatin MXGEFW_CMD_ERROR_UNALIGNED = 10, 45901638550SAndrew Gallatin MXGEFW_CMD_ERROR_NO_MDIO = 11, 46001638550SAndrew Gallatin MXGEFW_CMD_ERROR_I2C_FAILURE = 12, 46101638550SAndrew Gallatin MXGEFW_CMD_ERROR_I2C_ABSENT = 13, 46201638550SAndrew Gallatin MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14 4635e7d8541SAndrew Gallatin }; 4645e7d8541SAndrew Gallatin typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 465b2fc195eSAndrew Gallatin 4660fa7f681SAndrew Gallatin #define MXGEFW_OLD_IRQ_DATA_LEN 40 4670fa7f681SAndrew Gallatin 4685e7d8541SAndrew Gallatin struct mcp_irq_data { 4690fa7f681SAndrew Gallatin /* add new counters at the beginning */ 4708fe615baSAndrew Gallatin uint32_t future_use[1]; 4718fe615baSAndrew Gallatin uint32_t dropped_pause; 4728fe615baSAndrew Gallatin uint32_t dropped_unicast_filtered; 4738fe615baSAndrew Gallatin uint32_t dropped_bad_crc32; 4748fe615baSAndrew Gallatin uint32_t dropped_bad_phy; 4750fa7f681SAndrew Gallatin uint32_t dropped_multicast_filtered; 4760fa7f681SAndrew Gallatin /* 40 Bytes */ 4775e7d8541SAndrew Gallatin uint32_t send_done_count; 4785e7d8541SAndrew Gallatin 4798fe615baSAndrew Gallatin #define MXGEFW_LINK_DOWN 0 4808fe615baSAndrew Gallatin #define MXGEFW_LINK_UP 1 4818fe615baSAndrew Gallatin #define MXGEFW_LINK_MYRINET 2 4828fe615baSAndrew Gallatin #define MXGEFW_LINK_UNKNOWN 3 483b2fc195eSAndrew Gallatin uint32_t link_up; 484b2fc195eSAndrew Gallatin uint32_t dropped_link_overflow; 485b2fc195eSAndrew Gallatin uint32_t dropped_link_error_or_filtered; 486b2fc195eSAndrew Gallatin uint32_t dropped_runt; 487b2fc195eSAndrew Gallatin uint32_t dropped_overrun; 488b2fc195eSAndrew Gallatin uint32_t dropped_no_small_buffer; 489b2fc195eSAndrew Gallatin uint32_t dropped_no_big_buffer; 490b2fc195eSAndrew Gallatin uint32_t rdma_tags_available; 4915e7d8541SAndrew Gallatin 4925e7d8541SAndrew Gallatin uint8_t tx_stopped; 4935e7d8541SAndrew Gallatin uint8_t link_down; 4945e7d8541SAndrew Gallatin uint8_t stats_updated; 4955e7d8541SAndrew Gallatin uint8_t valid; 4965e7d8541SAndrew Gallatin }; 4975e7d8541SAndrew Gallatin typedef struct mcp_irq_data mcp_irq_data_t; 498b2fc195eSAndrew Gallatin 499c587e59fSAndrew Gallatin #ifdef MXGEFW_NDIS 5001e413cf9SAndrew Gallatin /* Exclusively used by NDIS drivers */ 501c587e59fSAndrew Gallatin struct mcp_rss_shared_interrupt { 502c587e59fSAndrew Gallatin uint8_t pad[2]; 503c587e59fSAndrew Gallatin uint8_t queue; 504c587e59fSAndrew Gallatin uint8_t valid; 505c587e59fSAndrew Gallatin }; 506c587e59fSAndrew Gallatin #endif 507b2fc195eSAndrew Gallatin 50888843c54SAndrew Gallatin /* definitions for NETQ filter type */ 50988843c54SAndrew Gallatin #define MXGEFW_NETQ_FILTERTYPE_NONE 0 51088843c54SAndrew Gallatin #define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 51188843c54SAndrew Gallatin #define MXGEFW_NETQ_FILTERTYPE_VLAN 2 51288843c54SAndrew Gallatin #define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 51388843c54SAndrew Gallatin 5145e7d8541SAndrew Gallatin #endif /* _myri10ge_mcp_h */ 515