1b2fc195eSAndrew Gallatin /******************************************************************************* 2b2fc195eSAndrew Gallatin 31e413cf9SAndrew Gallatin Copyright (c) 2006-2008, Myricom Inc. 4b2fc195eSAndrew Gallatin All rights reserved. 5b2fc195eSAndrew Gallatin 6b2fc195eSAndrew Gallatin Redistribution and use in source and binary forms, with or without 7b2fc195eSAndrew Gallatin modification, are permitted provided that the following conditions are met: 8b2fc195eSAndrew Gallatin 9b2fc195eSAndrew Gallatin 1. Redistributions of source code must retain the above copyright notice, 10b2fc195eSAndrew Gallatin this list of conditions and the following disclaimer. 11b2fc195eSAndrew Gallatin 12eb8e82f5SAndrew Gallatin 2. Neither the name of the Myricom Inc, nor the names of its 13b2fc195eSAndrew Gallatin contributors may be used to endorse or promote products derived from 14b2fc195eSAndrew Gallatin this software without specific prior written permission. 15b2fc195eSAndrew Gallatin 16b2fc195eSAndrew Gallatin THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17b2fc195eSAndrew Gallatin AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18b2fc195eSAndrew Gallatin IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19b2fc195eSAndrew Gallatin ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20b2fc195eSAndrew Gallatin LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21b2fc195eSAndrew Gallatin CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22b2fc195eSAndrew Gallatin SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23b2fc195eSAndrew Gallatin INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24b2fc195eSAndrew Gallatin CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25b2fc195eSAndrew Gallatin ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26b2fc195eSAndrew Gallatin POSSIBILITY OF SUCH DAMAGE. 27b2fc195eSAndrew Gallatin 28b2fc195eSAndrew Gallatin $FreeBSD$ 29b2fc195eSAndrew Gallatin ***************************************************************************/ 30b2fc195eSAndrew Gallatin 315e7d8541SAndrew Gallatin #ifndef _myri10ge_mcp_h 325e7d8541SAndrew Gallatin #define _myri10ge_mcp_h 33b2fc195eSAndrew Gallatin 345e7d8541SAndrew Gallatin #define MXGEFW_VERSION_MAJOR 1 355e7d8541SAndrew Gallatin #define MXGEFW_VERSION_MINOR 4 365e7d8541SAndrew Gallatin 375e7d8541SAndrew Gallatin #ifdef MXGEFW 38b2fc195eSAndrew Gallatin typedef signed char int8_t; 39b2fc195eSAndrew Gallatin typedef signed short int16_t; 40b2fc195eSAndrew Gallatin typedef signed int int32_t; 41b2fc195eSAndrew Gallatin typedef signed long long int64_t; 42b2fc195eSAndrew Gallatin typedef unsigned char uint8_t; 43b2fc195eSAndrew Gallatin typedef unsigned short uint16_t; 44b2fc195eSAndrew Gallatin typedef unsigned int uint32_t; 45b2fc195eSAndrew Gallatin typedef unsigned long long uint64_t; 46b2fc195eSAndrew Gallatin #endif 47b2fc195eSAndrew Gallatin 48b2fc195eSAndrew Gallatin /* 8 Bytes */ 495e7d8541SAndrew Gallatin struct mcp_dma_addr { 50b2fc195eSAndrew Gallatin uint32_t high; 51b2fc195eSAndrew Gallatin uint32_t low; 525e7d8541SAndrew Gallatin }; 535e7d8541SAndrew Gallatin typedef struct mcp_dma_addr mcp_dma_addr_t; 54b2fc195eSAndrew Gallatin 551e413cf9SAndrew Gallatin /* 4 Bytes */ 565e7d8541SAndrew Gallatin struct mcp_slot { 575e7d8541SAndrew Gallatin uint16_t checksum; 585e7d8541SAndrew Gallatin uint16_t length; 595e7d8541SAndrew Gallatin }; 605e7d8541SAndrew Gallatin typedef struct mcp_slot mcp_slot_t; 61b2fc195eSAndrew Gallatin 62c587e59fSAndrew Gallatin #ifdef MXGEFW_NDIS 631e413cf9SAndrew Gallatin /* 8-byte descriptor, exclusively used by NDIS drivers. */ 641e413cf9SAndrew Gallatin struct mcp_slot_8 { 651e413cf9SAndrew Gallatin /* Place hash value at the top so it gets written before length. 661e413cf9SAndrew Gallatin * The driver polls length. 671e413cf9SAndrew Gallatin */ 681e413cf9SAndrew Gallatin uint32_t hash; 691e413cf9SAndrew Gallatin uint16_t checksum; 701e413cf9SAndrew Gallatin uint16_t length; 711e413cf9SAndrew Gallatin }; 721e413cf9SAndrew Gallatin typedef struct mcp_slot_8 mcp_slot_8_t; 731e413cf9SAndrew Gallatin 74c587e59fSAndrew Gallatin /* Two bits of length in mcp_slot are used to indicate hash type. */ 75c587e59fSAndrew Gallatin #define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 76c587e59fSAndrew Gallatin #define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 77c587e59fSAndrew Gallatin #define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 78c587e59fSAndrew Gallatin #define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 79c587e59fSAndrew Gallatin #endif 80c587e59fSAndrew Gallatin 81b2fc195eSAndrew Gallatin /* 64 Bytes */ 825e7d8541SAndrew Gallatin struct mcp_cmd { 83b2fc195eSAndrew Gallatin uint32_t cmd; 84b2fc195eSAndrew Gallatin uint32_t data0; /* will be low portion if data > 32 bits */ 85b2fc195eSAndrew Gallatin /* 8 */ 86b2fc195eSAndrew Gallatin uint32_t data1; /* will be high portion if data > 32 bits */ 87b2fc195eSAndrew Gallatin uint32_t data2; /* currently unused.. */ 88b2fc195eSAndrew Gallatin /* 16 */ 895e7d8541SAndrew Gallatin struct mcp_dma_addr response_addr; 90b2fc195eSAndrew Gallatin /* 24 */ 91b2fc195eSAndrew Gallatin uint8_t pad[40]; 925e7d8541SAndrew Gallatin }; 935e7d8541SAndrew Gallatin typedef struct mcp_cmd mcp_cmd_t; 94b2fc195eSAndrew Gallatin 95b2fc195eSAndrew Gallatin /* 8 Bytes */ 965e7d8541SAndrew Gallatin struct mcp_cmd_response { 97b2fc195eSAndrew Gallatin uint32_t data; 98b2fc195eSAndrew Gallatin uint32_t result; 995e7d8541SAndrew Gallatin }; 1005e7d8541SAndrew Gallatin typedef struct mcp_cmd_response mcp_cmd_response_t; 101b2fc195eSAndrew Gallatin 102b2fc195eSAndrew Gallatin 103b2fc195eSAndrew Gallatin 104b2fc195eSAndrew Gallatin /* 105b2fc195eSAndrew Gallatin flags used in mcp_kreq_ether_send_t: 106b2fc195eSAndrew Gallatin 107b2fc195eSAndrew Gallatin The SMALL flag is only needed in the first segment. It is raised 108b2fc195eSAndrew Gallatin for packets that are total less or equal 512 bytes. 109b2fc195eSAndrew Gallatin 110b2fc195eSAndrew Gallatin The CKSUM flag must be set in all segments. 111b2fc195eSAndrew Gallatin 112b2fc195eSAndrew Gallatin The PADDED flags is set if the packet needs to be padded, and it 113b2fc195eSAndrew Gallatin must be set for all segments. 114b2fc195eSAndrew Gallatin 1155e7d8541SAndrew Gallatin The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 116b2fc195eSAndrew Gallatin length of all previous segments was odd. 117b2fc195eSAndrew Gallatin */ 118b2fc195eSAndrew Gallatin 119b2fc195eSAndrew Gallatin 1205e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_SMALL 0x1 1215e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_TSO_HDR 0x1 1225e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_FIRST 0x2 1235e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_ALIGN_ODD 0x4 1245e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_CKSUM 0x8 1255e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_TSO_LAST 0x8 1265e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_NO_TSO 0x10 1275e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_TSO_CHOP 0x10 1285e7d8541SAndrew Gallatin #define MXGEFW_FLAGS_TSO_PLD 0x20 129b2fc195eSAndrew Gallatin 1305e7d8541SAndrew Gallatin #define MXGEFW_SEND_SMALL_SIZE 1520 1315e7d8541SAndrew Gallatin #define MXGEFW_MAX_MTU 9400 132b2fc195eSAndrew Gallatin 1335e7d8541SAndrew Gallatin union mcp_pso_or_cumlen { 134b2fc195eSAndrew Gallatin uint16_t pseudo_hdr_offset; 135b2fc195eSAndrew Gallatin uint16_t cum_len; 1365e7d8541SAndrew Gallatin }; 1375e7d8541SAndrew Gallatin typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 138b2fc195eSAndrew Gallatin 1395e7d8541SAndrew Gallatin #define MXGEFW_MAX_SEND_DESC 12 1405e7d8541SAndrew Gallatin #define MXGEFW_PAD 2 141b2fc195eSAndrew Gallatin 142b2fc195eSAndrew Gallatin /* 16 Bytes */ 1435e7d8541SAndrew Gallatin struct mcp_kreq_ether_send { 144b2fc195eSAndrew Gallatin uint32_t addr_high; 145b2fc195eSAndrew Gallatin uint32_t addr_low; 1465e7d8541SAndrew Gallatin uint16_t pseudo_hdr_offset; 147b2fc195eSAndrew Gallatin uint16_t length; 148b2fc195eSAndrew Gallatin uint8_t pad; 1495e7d8541SAndrew Gallatin uint8_t rdma_count; 150b2fc195eSAndrew Gallatin uint8_t cksum_offset; /* where to start computing cksum */ 1515e7d8541SAndrew Gallatin uint8_t flags; /* as defined above */ 1525e7d8541SAndrew Gallatin }; 1535e7d8541SAndrew Gallatin typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 154b2fc195eSAndrew Gallatin 155b2fc195eSAndrew Gallatin /* 8 Bytes */ 1565e7d8541SAndrew Gallatin struct mcp_kreq_ether_recv { 157b2fc195eSAndrew Gallatin uint32_t addr_high; 158b2fc195eSAndrew Gallatin uint32_t addr_low; 1595e7d8541SAndrew Gallatin }; 1605e7d8541SAndrew Gallatin typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 161b2fc195eSAndrew Gallatin 162b2fc195eSAndrew Gallatin 163b2fc195eSAndrew Gallatin /* Commands */ 164b2fc195eSAndrew Gallatin 1650fa7f681SAndrew Gallatin #define MXGEFW_BOOT_HANDOFF 0xfc0000 1660fa7f681SAndrew Gallatin #define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 1670fa7f681SAndrew Gallatin 1680fa7f681SAndrew Gallatin #define MXGEFW_ETH_CMD 0xf80000 1690fa7f681SAndrew Gallatin #define MXGEFW_ETH_SEND_4 0x200000 1700fa7f681SAndrew Gallatin #define MXGEFW_ETH_SEND_1 0x240000 1710fa7f681SAndrew Gallatin #define MXGEFW_ETH_SEND_2 0x280000 1720fa7f681SAndrew Gallatin #define MXGEFW_ETH_SEND_3 0x2c0000 1730fa7f681SAndrew Gallatin #define MXGEFW_ETH_RECV_SMALL 0x300000 1740fa7f681SAndrew Gallatin #define MXGEFW_ETH_RECV_BIG 0x340000 1750fa7f681SAndrew Gallatin 1760fa7f681SAndrew Gallatin #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 1770fa7f681SAndrew Gallatin #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 178b2fc195eSAndrew Gallatin 1795e7d8541SAndrew Gallatin enum myri10ge_mcp_cmd_type { 1805e7d8541SAndrew Gallatin MXGEFW_CMD_NONE = 0, 181b2fc195eSAndrew Gallatin /* Reset the mcp, it is left in a safe state, waiting 182b2fc195eSAndrew Gallatin for the driver to set all its parameters */ 1835e7d8541SAndrew Gallatin MXGEFW_CMD_RESET, 184b2fc195eSAndrew Gallatin 185b2fc195eSAndrew Gallatin /* get the version number of the current firmware.. 186b2fc195eSAndrew Gallatin (may be available in the eeprom strings..? */ 1875e7d8541SAndrew Gallatin MXGEFW_GET_MCP_VERSION, 188b2fc195eSAndrew Gallatin 189b2fc195eSAndrew Gallatin 190b2fc195eSAndrew Gallatin /* Parameters which must be set by the driver before it can 1915e7d8541SAndrew Gallatin issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 1925e7d8541SAndrew Gallatin MXGEFW_CMD_RESET is issued */ 193b2fc195eSAndrew Gallatin 1945e7d8541SAndrew Gallatin MXGEFW_CMD_SET_INTRQ_DMA, 1955e7d8541SAndrew Gallatin MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */ 1965e7d8541SAndrew Gallatin MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */ 197b2fc195eSAndrew Gallatin 198b2fc195eSAndrew Gallatin 199b2fc195eSAndrew Gallatin /* Parameters which refer to lanai SRAM addresses where the 200b2fc195eSAndrew Gallatin driver must issue PIO writes for various things */ 201b2fc195eSAndrew Gallatin 2025e7d8541SAndrew Gallatin MXGEFW_CMD_GET_SEND_OFFSET, 2035e7d8541SAndrew Gallatin MXGEFW_CMD_GET_SMALL_RX_OFFSET, 2045e7d8541SAndrew Gallatin MXGEFW_CMD_GET_BIG_RX_OFFSET, 2055e7d8541SAndrew Gallatin MXGEFW_CMD_GET_IRQ_ACK_OFFSET, 2065e7d8541SAndrew Gallatin MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, 207b2fc195eSAndrew Gallatin 208b2fc195eSAndrew Gallatin /* Parameters which refer to rings stored on the MCP, 209b2fc195eSAndrew Gallatin and whose size is controlled by the mcp */ 210b2fc195eSAndrew Gallatin 2115e7d8541SAndrew Gallatin MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */ 2125e7d8541SAndrew Gallatin MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */ 213b2fc195eSAndrew Gallatin 214b2fc195eSAndrew Gallatin /* Parameters which refer to rings stored in the host, 215b2fc195eSAndrew Gallatin and whose size is controlled by the host. Note that 216b2fc195eSAndrew Gallatin all must be physically contiguous and must contain 217b2fc195eSAndrew Gallatin a power of 2 number of entries. */ 218b2fc195eSAndrew Gallatin 2195e7d8541SAndrew Gallatin MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */ 220b2fc195eSAndrew Gallatin 221b2fc195eSAndrew Gallatin /* command to bring ethernet interface up. Above parameters 222b2fc195eSAndrew Gallatin (plus mtu & mac address) must have been exchanged prior 223b2fc195eSAndrew Gallatin to issuing this command */ 2245e7d8541SAndrew Gallatin MXGEFW_CMD_ETHERNET_UP, 225b2fc195eSAndrew Gallatin 226b2fc195eSAndrew Gallatin /* command to bring ethernet interface down. No further sends 2275e7d8541SAndrew Gallatin or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 228b2fc195eSAndrew Gallatin is issued, and all interrupt queues must be flushed prior 229b2fc195eSAndrew Gallatin to ack'ing this command */ 230b2fc195eSAndrew Gallatin 2315e7d8541SAndrew Gallatin MXGEFW_CMD_ETHERNET_DOWN, 232b2fc195eSAndrew Gallatin 233b2fc195eSAndrew Gallatin /* commands the driver may issue live, without resetting 234b2fc195eSAndrew Gallatin the nic. Note that increasing the mtu "live" should 235b2fc195eSAndrew Gallatin only be done if the driver has already supplied buffers 236b2fc195eSAndrew Gallatin sufficiently large to handle the new mtu. Decreasing 237b2fc195eSAndrew Gallatin the mtu live is safe */ 238b2fc195eSAndrew Gallatin 2395e7d8541SAndrew Gallatin MXGEFW_CMD_SET_MTU, 2405e7d8541SAndrew Gallatin MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */ 2415e7d8541SAndrew Gallatin MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */ 2420fa7f681SAndrew Gallatin MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, /* replaced by SET_STATS_DMA_V2 */ 243b2fc195eSAndrew Gallatin 2445e7d8541SAndrew Gallatin MXGEFW_ENABLE_PROMISC, 2455e7d8541SAndrew Gallatin MXGEFW_DISABLE_PROMISC, 2465e7d8541SAndrew Gallatin MXGEFW_SET_MAC_ADDRESS, 247b2fc195eSAndrew Gallatin 2485e7d8541SAndrew Gallatin MXGEFW_ENABLE_FLOW_CONTROL, 2495e7d8541SAndrew Gallatin MXGEFW_DISABLE_FLOW_CONTROL, 2505e7d8541SAndrew Gallatin 2515e7d8541SAndrew Gallatin /* do a DMA test 2525e7d8541SAndrew Gallatin data0,data1 = DMA address 2535e7d8541SAndrew Gallatin data2 = RDMA length (MSH), WDMA length (LSH) 2545e7d8541SAndrew Gallatin command return data = repetitions (MSH), 0.5-ms ticks (LSH) 2555e7d8541SAndrew Gallatin */ 2560fa7f681SAndrew Gallatin MXGEFW_DMA_TEST, 2570fa7f681SAndrew Gallatin 2580fa7f681SAndrew Gallatin MXGEFW_ENABLE_ALLMULTI, 2590fa7f681SAndrew Gallatin MXGEFW_DISABLE_ALLMULTI, 2600fa7f681SAndrew Gallatin 2610fa7f681SAndrew Gallatin /* returns MXGEFW_CMD_ERROR_MULTICAST 2620fa7f681SAndrew Gallatin if there is no room in the cache 2630fa7f681SAndrew Gallatin data0,MSH(data1) = multicast group address */ 2640fa7f681SAndrew Gallatin MXGEFW_JOIN_MULTICAST_GROUP, 2650fa7f681SAndrew Gallatin /* returns MXGEFW_CMD_ERROR_MULTICAST 2660fa7f681SAndrew Gallatin if the address is not in the cache, 2670fa7f681SAndrew Gallatin or is equal to FF-FF-FF-FF-FF-FF 2680fa7f681SAndrew Gallatin data0,MSH(data1) = multicast group address */ 2690fa7f681SAndrew Gallatin MXGEFW_LEAVE_MULTICAST_GROUP, 2700fa7f681SAndrew Gallatin MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, 2710fa7f681SAndrew Gallatin 2720fa7f681SAndrew Gallatin MXGEFW_CMD_SET_STATS_DMA_V2, 2730fa7f681SAndrew Gallatin /* data0, data1 = bus addr, 2740fa7f681SAndrew Gallatin data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 2750fa7f681SAndrew Gallatin adding new stuff to mcp_irq_data without changing the ABI */ 2768fe615baSAndrew Gallatin 2778fe615baSAndrew Gallatin MXGEFW_CMD_UNALIGNED_TEST, 2788fe615baSAndrew Gallatin /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 2798fe615baSAndrew Gallatin chipset */ 2808fe615baSAndrew Gallatin 281053e637fSAndrew Gallatin MXGEFW_CMD_UNALIGNED_STATUS, 2828fe615baSAndrew Gallatin /* return data = boolean, true if the chipset is known to be unaligned */ 283053e637fSAndrew Gallatin 284053e637fSAndrew Gallatin MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS, 285053e637fSAndrew Gallatin /* data0 = number of big buffers to use. It must be 0 or a power of 2. 286053e637fSAndrew Gallatin * 0 indicates that the NIC consumes as many buffers as they are required 287053e637fSAndrew Gallatin * for packet. This is the default behavior. 288053e637fSAndrew Gallatin * A power of 2 number indicates that the NIC always uses the specified 289053e637fSAndrew Gallatin * number of buffers for each big receive packet. 290053e637fSAndrew Gallatin * It is up to the driver to ensure that this value is big enough for 291053e637fSAndrew Gallatin * the NIC to be able to receive maximum-sized packets. 292053e637fSAndrew Gallatin */ 293c587e59fSAndrew Gallatin 294c587e59fSAndrew Gallatin MXGEFW_CMD_GET_MAX_RSS_QUEUES, 295c587e59fSAndrew Gallatin MXGEFW_CMD_ENABLE_RSS_QUEUES, 296c587e59fSAndrew Gallatin /* data0 = number of slices n (0, 1, ..., n-1) to enable 2971e413cf9SAndrew Gallatin * data1 = interrupt mode. 2981e413cf9SAndrew Gallatin * 0=share one INTx/MSI, 1=use one MSI-X per queue. 299c587e59fSAndrew Gallatin * If all queues share one interrupt, the driver must have set 300c587e59fSAndrew Gallatin * RSS_SHARED_INTERRUPT_DMA before enabling queues. 301c587e59fSAndrew Gallatin */ 3021e413cf9SAndrew Gallatin #define MXGEFW_SLICE_INTR_MODE_SHARED 0 3031e413cf9SAndrew Gallatin #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 1 3041e413cf9SAndrew Gallatin 305c587e59fSAndrew Gallatin MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET, 306c587e59fSAndrew Gallatin MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA, 307c587e59fSAndrew Gallatin /* data0, data1 = bus address lsw, msw */ 308c587e59fSAndrew Gallatin MXGEFW_CMD_GET_RSS_TABLE_OFFSET, 309c587e59fSAndrew Gallatin /* get the offset of the indirection table */ 310c587e59fSAndrew Gallatin MXGEFW_CMD_SET_RSS_TABLE_SIZE, 311c587e59fSAndrew Gallatin /* set the size of the indirection table */ 312c587e59fSAndrew Gallatin MXGEFW_CMD_GET_RSS_KEY_OFFSET, 313c587e59fSAndrew Gallatin /* get the offset of the secret key */ 314c587e59fSAndrew Gallatin MXGEFW_CMD_RSS_KEY_UPDATED, 315c587e59fSAndrew Gallatin /* tell nic that the secret key's been updated */ 316c587e59fSAndrew Gallatin MXGEFW_CMD_SET_RSS_ENABLE, 317c587e59fSAndrew Gallatin /* data0 = enable/disable rss 318c587e59fSAndrew Gallatin * 0: disable rss. nic does not distribute receive packets. 319c587e59fSAndrew Gallatin * 1: enable rss. nic distributes receive packets among queues. 320c587e59fSAndrew Gallatin * data1 = hash type 3211e413cf9SAndrew Gallatin * 1: IPV4 (required by RSS) 3221e413cf9SAndrew Gallatin * 2: TCP_IPV4 (required by RSS) 3231e413cf9SAndrew Gallatin * 3: IPV4 | TCP_IPV4 (required by RSS) 3241e413cf9SAndrew Gallatin * 4: source port 325c587e59fSAndrew Gallatin */ 3261e413cf9SAndrew Gallatin #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 3271e413cf9SAndrew Gallatin #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 3281e413cf9SAndrew Gallatin #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 329c587e59fSAndrew Gallatin 330c587e59fSAndrew Gallatin MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE, 331c587e59fSAndrew Gallatin /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 332c587e59fSAndrew Gallatin * If the header size of a IPv6 TSO packet is larger than the specified 333c587e59fSAndrew Gallatin * value, then the driver must not use TSO. 334c587e59fSAndrew Gallatin * This size restriction only applies to IPv6 TSO. 335c587e59fSAndrew Gallatin * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 336c587e59fSAndrew Gallatin * always has enough header buffer to store maximum-sized headers. 337c587e59fSAndrew Gallatin */ 338c587e59fSAndrew Gallatin 339c587e59fSAndrew Gallatin MXGEFW_CMD_SET_TSO_MODE, 340c587e59fSAndrew Gallatin /* data0 = TSO mode. 341c587e59fSAndrew Gallatin * 0: Linux/FreeBSD style (NIC default) 342c587e59fSAndrew Gallatin * 1: NDIS/NetBSD style 343c587e59fSAndrew Gallatin */ 3441e413cf9SAndrew Gallatin #define MXGEFW_TSO_MODE_LINUX 0 3451e413cf9SAndrew Gallatin #define MXGEFW_TSO_MODE_NDIS 1 346c587e59fSAndrew Gallatin 347c587e59fSAndrew Gallatin MXGEFW_CMD_MDIO_READ, 348c587e59fSAndrew Gallatin /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 349c587e59fSAndrew Gallatin MXGEFW_CMD_MDIO_WRITE, 350c587e59fSAndrew Gallatin /* data0 = dev_addr, data1 = register/addr, data2 = value */ 351c587e59fSAndrew Gallatin 352c587e59fSAndrew Gallatin MXGEFW_CMD_XFP_I2C_READ, 353c587e59fSAndrew Gallatin /* Starts to get a fresh copy of one byte or of the whole xfp i2c table, the 354c587e59fSAndrew Gallatin * obtained data is cached inside the xaui-xfi chip : 355c587e59fSAndrew Gallatin * data0 : "all" flag : 0 => get one byte, 1=> get 256 bytes, 356c587e59fSAndrew Gallatin * data1 : if (data0 == 0): index of byte to refresh [ not used otherwise ] 357c587e59fSAndrew Gallatin * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 358c587e59fSAndrew Gallatin * During the i2c operation, MXGEFW_CMD_XFP_I2C_READ or MXGEFW_CMD_XFP_BYTE attempts 359c587e59fSAndrew Gallatin * will return MXGEFW_CMD_ERROR_BUSY 360c587e59fSAndrew Gallatin */ 3611e413cf9SAndrew Gallatin MXGEFW_CMD_XFP_BYTE, 362c587e59fSAndrew Gallatin /* Return the last obtained copy of a given byte in the xfp i2c table 363c587e59fSAndrew Gallatin * (copy cached during the last relevant MXGEFW_CMD_XFP_I2C_READ) 364c587e59fSAndrew Gallatin * data0 : index of the desired table entry 365c587e59fSAndrew Gallatin * Return data = the byte stored at the requested index in the table 366c587e59fSAndrew Gallatin */ 3671e413cf9SAndrew Gallatin 3681e413cf9SAndrew Gallatin MXGEFW_CMD_GET_VPUMP_OFFSET, 3691e413cf9SAndrew Gallatin /* Return data = NIC memory offset of mcp_vpump_public_global */ 3701e413cf9SAndrew Gallatin MXGEFW_CMD_RESET_VPUMP, 3711e413cf9SAndrew Gallatin /* Resets the VPUMP state */ 3721e413cf9SAndrew Gallatin 3731e413cf9SAndrew Gallatin MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, 3741e413cf9SAndrew Gallatin /* data0 = mcp_slot type to use. 3751e413cf9SAndrew Gallatin * 0 = the default 4B mcp_slot 3761e413cf9SAndrew Gallatin * 1 = 8B mcp_slot_8 3771e413cf9SAndrew Gallatin */ 3781e413cf9SAndrew Gallatin #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 3791e413cf9SAndrew Gallatin #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 3801e413cf9SAndrew Gallatin 3811e413cf9SAndrew Gallatin MXGEFW_CMD_SET_THROTTLE_FACTOR, 3821e413cf9SAndrew Gallatin /* set the throttle factor for ethp_z8e 3831e413cf9SAndrew Gallatin data0 = throttle_factor 3841e413cf9SAndrew Gallatin throttle_factor = 256 * pcie-raw-speed / tx_speed 3851e413cf9SAndrew Gallatin tx_speed = 256 * pcie-raw-speed / throttle_factor 3861e413cf9SAndrew Gallatin 3871e413cf9SAndrew Gallatin For PCI-E x8: pcie-raw-speed == 16Gb/s 3881e413cf9SAndrew Gallatin For PCI-E x4: pcie-raw-speed == 8Gb/s 3891e413cf9SAndrew Gallatin 3901e413cf9SAndrew Gallatin ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 3911e413cf9SAndrew Gallatin ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 3921e413cf9SAndrew Gallatin 3931e413cf9SAndrew Gallatin with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 3941e413cf9SAndrew Gallatin with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 3951e413cf9SAndrew Gallatin */ 3961e413cf9SAndrew Gallatin 3971e413cf9SAndrew Gallatin MXGEFW_CMD_VPUMP_UP 3981e413cf9SAndrew Gallatin /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 3991e413cf9SAndrew Gallatin 4005e7d8541SAndrew Gallatin }; 4015e7d8541SAndrew Gallatin typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 402b2fc195eSAndrew Gallatin 403b2fc195eSAndrew Gallatin 4045e7d8541SAndrew Gallatin enum myri10ge_mcp_cmd_status { 4055e7d8541SAndrew Gallatin MXGEFW_CMD_OK = 0, 4065e7d8541SAndrew Gallatin MXGEFW_CMD_UNKNOWN, 4075e7d8541SAndrew Gallatin MXGEFW_CMD_ERROR_RANGE, 4085e7d8541SAndrew Gallatin MXGEFW_CMD_ERROR_BUSY, 4095e7d8541SAndrew Gallatin MXGEFW_CMD_ERROR_EMPTY, 4105e7d8541SAndrew Gallatin MXGEFW_CMD_ERROR_CLOSED, 4115e7d8541SAndrew Gallatin MXGEFW_CMD_ERROR_HASH_ERROR, 4125e7d8541SAndrew Gallatin MXGEFW_CMD_ERROR_BAD_PORT, 4130fa7f681SAndrew Gallatin MXGEFW_CMD_ERROR_RESOURCES, 4148fe615baSAndrew Gallatin MXGEFW_CMD_ERROR_MULTICAST, 415c587e59fSAndrew Gallatin MXGEFW_CMD_ERROR_UNALIGNED, 416c587e59fSAndrew Gallatin MXGEFW_CMD_ERROR_NO_MDIO, 417c587e59fSAndrew Gallatin MXGEFW_CMD_ERROR_XFP_FAILURE, 418c587e59fSAndrew Gallatin MXGEFW_CMD_ERROR_XFP_ABSENT 4195e7d8541SAndrew Gallatin }; 4205e7d8541SAndrew Gallatin typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 421b2fc195eSAndrew Gallatin 422b2fc195eSAndrew Gallatin 4230fa7f681SAndrew Gallatin #define MXGEFW_OLD_IRQ_DATA_LEN 40 4240fa7f681SAndrew Gallatin 4255e7d8541SAndrew Gallatin struct mcp_irq_data { 4260fa7f681SAndrew Gallatin /* add new counters at the beginning */ 4278fe615baSAndrew Gallatin uint32_t future_use[1]; 4288fe615baSAndrew Gallatin uint32_t dropped_pause; 4298fe615baSAndrew Gallatin uint32_t dropped_unicast_filtered; 4308fe615baSAndrew Gallatin uint32_t dropped_bad_crc32; 4318fe615baSAndrew Gallatin uint32_t dropped_bad_phy; 4320fa7f681SAndrew Gallatin uint32_t dropped_multicast_filtered; 4330fa7f681SAndrew Gallatin /* 40 Bytes */ 4345e7d8541SAndrew Gallatin uint32_t send_done_count; 4355e7d8541SAndrew Gallatin 4368fe615baSAndrew Gallatin #define MXGEFW_LINK_DOWN 0 4378fe615baSAndrew Gallatin #define MXGEFW_LINK_UP 1 4388fe615baSAndrew Gallatin #define MXGEFW_LINK_MYRINET 2 4398fe615baSAndrew Gallatin #define MXGEFW_LINK_UNKNOWN 3 440b2fc195eSAndrew Gallatin uint32_t link_up; 441b2fc195eSAndrew Gallatin uint32_t dropped_link_overflow; 442b2fc195eSAndrew Gallatin uint32_t dropped_link_error_or_filtered; 443b2fc195eSAndrew Gallatin uint32_t dropped_runt; 444b2fc195eSAndrew Gallatin uint32_t dropped_overrun; 445b2fc195eSAndrew Gallatin uint32_t dropped_no_small_buffer; 446b2fc195eSAndrew Gallatin uint32_t dropped_no_big_buffer; 447b2fc195eSAndrew Gallatin uint32_t rdma_tags_available; 4485e7d8541SAndrew Gallatin 4495e7d8541SAndrew Gallatin uint8_t tx_stopped; 4505e7d8541SAndrew Gallatin uint8_t link_down; 4515e7d8541SAndrew Gallatin uint8_t stats_updated; 4525e7d8541SAndrew Gallatin uint8_t valid; 4535e7d8541SAndrew Gallatin }; 4545e7d8541SAndrew Gallatin typedef struct mcp_irq_data mcp_irq_data_t; 455b2fc195eSAndrew Gallatin 456c587e59fSAndrew Gallatin #ifdef MXGEFW_NDIS 4571e413cf9SAndrew Gallatin /* Exclusively used by NDIS drivers */ 458c587e59fSAndrew Gallatin struct mcp_rss_shared_interrupt { 459c587e59fSAndrew Gallatin uint8_t pad[2]; 460c587e59fSAndrew Gallatin uint8_t queue; 461c587e59fSAndrew Gallatin uint8_t valid; 462c587e59fSAndrew Gallatin }; 463c587e59fSAndrew Gallatin #endif 464b2fc195eSAndrew Gallatin 4655e7d8541SAndrew Gallatin #endif /* _myri10ge_mcp_h */ 466