1 /* 2 * Copyright (c) 2017 Stormshield. 3 * Copyright (c) 2017 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "opt_platform.h" 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/endian.h> 35 #include <sys/mbuf.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/socket.h> 41 #include <sys/sysctl.h> 42 #include <sys/smp.h> 43 #include <sys/taskqueue.h> 44 #ifdef MVNETA_KTR 45 #include <sys/ktr.h> 46 #endif 47 48 #include <net/ethernet.h> 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp_lro.h> 61 62 #include <sys/sockio.h> 63 #include <sys/bus.h> 64 #include <machine/bus.h> 65 #include <sys/rman.h> 66 #include <machine/resource.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/mdio/mdio.h> 72 73 #include <arm/mv/mvvar.h> 74 75 #if !defined(__aarch64__) 76 #include <arm/mv/mvreg.h> 77 #include <arm/mv/mvwin.h> 78 #endif 79 80 #include "if_mvnetareg.h" 81 #include "if_mvnetavar.h" 82 83 #include "miibus_if.h" 84 #include "mdio_if.h" 85 86 #ifdef MVNETA_DEBUG 87 #define STATIC /* nothing */ 88 #else 89 #define STATIC static 90 #endif 91 92 #define DASSERT(x) KASSERT((x), (#x)) 93 94 #define A3700_TCLK_250MHZ 250000000 95 96 /* Device Register Initialization */ 97 STATIC int mvneta_initreg(struct ifnet *); 98 99 /* Descriptor Ring Control for each of queues */ 100 STATIC int mvneta_ring_alloc_rx_queue(struct mvneta_softc *, int); 101 STATIC int mvneta_ring_alloc_tx_queue(struct mvneta_softc *, int); 102 STATIC void mvneta_ring_dealloc_rx_queue(struct mvneta_softc *, int); 103 STATIC void mvneta_ring_dealloc_tx_queue(struct mvneta_softc *, int); 104 STATIC int mvneta_ring_init_rx_queue(struct mvneta_softc *, int); 105 STATIC int mvneta_ring_init_tx_queue(struct mvneta_softc *, int); 106 STATIC void mvneta_ring_flush_rx_queue(struct mvneta_softc *, int); 107 STATIC void mvneta_ring_flush_tx_queue(struct mvneta_softc *, int); 108 STATIC void mvneta_dmamap_cb(void *, bus_dma_segment_t *, int, int); 109 STATIC int mvneta_dma_create(struct mvneta_softc *); 110 111 /* Rx/Tx Queue Control */ 112 STATIC int mvneta_rx_queue_init(struct ifnet *, int); 113 STATIC int mvneta_tx_queue_init(struct ifnet *, int); 114 STATIC int mvneta_rx_queue_enable(struct ifnet *, int); 115 STATIC int mvneta_tx_queue_enable(struct ifnet *, int); 116 STATIC void mvneta_rx_lockq(struct mvneta_softc *, int); 117 STATIC void mvneta_rx_unlockq(struct mvneta_softc *, int); 118 STATIC void mvneta_tx_lockq(struct mvneta_softc *, int); 119 STATIC void mvneta_tx_unlockq(struct mvneta_softc *, int); 120 121 /* Interrupt Handlers */ 122 STATIC void mvneta_disable_intr(struct mvneta_softc *); 123 STATIC void mvneta_enable_intr(struct mvneta_softc *); 124 STATIC void mvneta_rxtxth_intr(void *); 125 STATIC int mvneta_misc_intr(struct mvneta_softc *); 126 STATIC void mvneta_tick(void *); 127 /* struct ifnet and mii callbacks*/ 128 STATIC int mvneta_xmitfast_locked(struct mvneta_softc *, int, struct mbuf **); 129 STATIC int mvneta_xmit_locked(struct mvneta_softc *, int); 130 #ifdef MVNETA_MULTIQUEUE 131 STATIC int mvneta_transmit(struct ifnet *, struct mbuf *); 132 #else /* !MVNETA_MULTIQUEUE */ 133 STATIC void mvneta_start(struct ifnet *); 134 #endif 135 STATIC void mvneta_qflush(struct ifnet *); 136 STATIC void mvneta_tx_task(void *, int); 137 STATIC int mvneta_ioctl(struct ifnet *, u_long, caddr_t); 138 STATIC void mvneta_init(void *); 139 STATIC void mvneta_init_locked(void *); 140 STATIC void mvneta_stop(struct mvneta_softc *); 141 STATIC void mvneta_stop_locked(struct mvneta_softc *); 142 STATIC int mvneta_mediachange(struct ifnet *); 143 STATIC void mvneta_mediastatus(struct ifnet *, struct ifmediareq *); 144 STATIC void mvneta_portup(struct mvneta_softc *); 145 STATIC void mvneta_portdown(struct mvneta_softc *); 146 147 /* Link State Notify */ 148 STATIC void mvneta_update_autoneg(struct mvneta_softc *, int); 149 STATIC int mvneta_update_media(struct mvneta_softc *, int); 150 STATIC void mvneta_adjust_link(struct mvneta_softc *); 151 STATIC void mvneta_update_eee(struct mvneta_softc *); 152 STATIC void mvneta_update_fc(struct mvneta_softc *); 153 STATIC void mvneta_link_isr(struct mvneta_softc *); 154 STATIC void mvneta_linkupdate(struct mvneta_softc *, boolean_t); 155 STATIC void mvneta_linkup(struct mvneta_softc *); 156 STATIC void mvneta_linkdown(struct mvneta_softc *); 157 STATIC void mvneta_linkreset(struct mvneta_softc *); 158 159 /* Tx Subroutines */ 160 STATIC int mvneta_tx_queue(struct mvneta_softc *, struct mbuf **, int); 161 STATIC void mvneta_tx_set_csumflag(struct ifnet *, 162 struct mvneta_tx_desc *, struct mbuf *); 163 STATIC void mvneta_tx_queue_complete(struct mvneta_softc *, int); 164 STATIC void mvneta_tx_drain(struct mvneta_softc *); 165 166 /* Rx Subroutines */ 167 STATIC int mvneta_rx(struct mvneta_softc *, int, int); 168 STATIC void mvneta_rx_queue(struct mvneta_softc *, int, int); 169 STATIC void mvneta_rx_queue_refill(struct mvneta_softc *, int); 170 STATIC void mvneta_rx_set_csumflag(struct ifnet *, 171 struct mvneta_rx_desc *, struct mbuf *); 172 STATIC void mvneta_rx_buf_free(struct mvneta_softc *, struct mvneta_buf *); 173 174 /* MAC address filter */ 175 STATIC void mvneta_filter_setup(struct mvneta_softc *); 176 177 /* sysctl(9) */ 178 STATIC int sysctl_read_mib(SYSCTL_HANDLER_ARGS); 179 STATIC int sysctl_clear_mib(SYSCTL_HANDLER_ARGS); 180 STATIC int sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS); 181 STATIC void sysctl_mvneta_init(struct mvneta_softc *); 182 183 /* MIB */ 184 STATIC void mvneta_clear_mib(struct mvneta_softc *); 185 STATIC uint64_t mvneta_read_mib(struct mvneta_softc *, int); 186 STATIC void mvneta_update_mib(struct mvneta_softc *); 187 188 /* Switch */ 189 STATIC boolean_t mvneta_has_switch(device_t); 190 191 #define mvneta_sc_lock(sc) mtx_lock(&sc->mtx) 192 #define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx) 193 194 STATIC struct mtx mii_mutex; 195 STATIC int mii_init = 0; 196 197 /* Device */ 198 STATIC int mvneta_detach(device_t); 199 /* MII */ 200 STATIC int mvneta_miibus_readreg(device_t, int, int); 201 STATIC int mvneta_miibus_writereg(device_t, int, int, int); 202 203 /* Clock */ 204 STATIC uint32_t mvneta_get_clk(void); 205 206 static device_method_t mvneta_methods[] = { 207 /* Device interface */ 208 DEVMETHOD(device_detach, mvneta_detach), 209 /* MII interface */ 210 DEVMETHOD(miibus_readreg, mvneta_miibus_readreg), 211 DEVMETHOD(miibus_writereg, mvneta_miibus_writereg), 212 /* MDIO interface */ 213 DEVMETHOD(mdio_readreg, mvneta_miibus_readreg), 214 DEVMETHOD(mdio_writereg, mvneta_miibus_writereg), 215 216 /* End */ 217 DEVMETHOD_END 218 }; 219 220 DEFINE_CLASS_0(mvneta, mvneta_driver, mvneta_methods, sizeof(struct mvneta_softc)); 221 222 DRIVER_MODULE(miibus, mvneta, miibus_driver, miibus_devclass, 0, 0); 223 DRIVER_MODULE(mdio, mvneta, mdio_driver, mdio_devclass, 0, 0); 224 MODULE_DEPEND(mvneta, mdio, 1, 1, 1); 225 MODULE_DEPEND(mvneta, ether, 1, 1, 1); 226 MODULE_DEPEND(mvneta, miibus, 1, 1, 1); 227 MODULE_DEPEND(mvneta, mvxpbm, 1, 1, 1); 228 229 /* 230 * List of MIB register and names 231 */ 232 enum mvneta_mib_idx 233 { 234 MVNETA_MIB_RX_GOOD_OCT_IDX, 235 MVNETA_MIB_RX_BAD_OCT_IDX, 236 MVNETA_MIB_TX_MAC_TRNS_ERR_IDX, 237 MVNETA_MIB_RX_GOOD_FRAME_IDX, 238 MVNETA_MIB_RX_BAD_FRAME_IDX, 239 MVNETA_MIB_RX_BCAST_FRAME_IDX, 240 MVNETA_MIB_RX_MCAST_FRAME_IDX, 241 MVNETA_MIB_RX_FRAME64_OCT_IDX, 242 MVNETA_MIB_RX_FRAME127_OCT_IDX, 243 MVNETA_MIB_RX_FRAME255_OCT_IDX, 244 MVNETA_MIB_RX_FRAME511_OCT_IDX, 245 MVNETA_MIB_RX_FRAME1023_OCT_IDX, 246 MVNETA_MIB_RX_FRAMEMAX_OCT_IDX, 247 MVNETA_MIB_TX_GOOD_OCT_IDX, 248 MVNETA_MIB_TX_GOOD_FRAME_IDX, 249 MVNETA_MIB_TX_EXCES_COL_IDX, 250 MVNETA_MIB_TX_MCAST_FRAME_IDX, 251 MVNETA_MIB_TX_BCAST_FRAME_IDX, 252 MVNETA_MIB_TX_MAC_CTL_ERR_IDX, 253 MVNETA_MIB_FC_SENT_IDX, 254 MVNETA_MIB_FC_GOOD_IDX, 255 MVNETA_MIB_FC_BAD_IDX, 256 MVNETA_MIB_PKT_UNDERSIZE_IDX, 257 MVNETA_MIB_PKT_FRAGMENT_IDX, 258 MVNETA_MIB_PKT_OVERSIZE_IDX, 259 MVNETA_MIB_PKT_JABBER_IDX, 260 MVNETA_MIB_MAC_RX_ERR_IDX, 261 MVNETA_MIB_MAC_CRC_ERR_IDX, 262 MVNETA_MIB_MAC_COL_IDX, 263 MVNETA_MIB_MAC_LATE_COL_IDX, 264 }; 265 266 STATIC struct mvneta_mib_def { 267 uint32_t regnum; 268 int reg64; 269 const char *sysctl_name; 270 const char *desc; 271 } mvneta_mib_list[] = { 272 [MVNETA_MIB_RX_GOOD_OCT_IDX] = {MVNETA_MIB_RX_GOOD_OCT, 1, 273 "rx_good_oct", "Good Octets Rx"}, 274 [MVNETA_MIB_RX_BAD_OCT_IDX] = {MVNETA_MIB_RX_BAD_OCT, 0, 275 "rx_bad_oct", "Bad Octets Rx"}, 276 [MVNETA_MIB_TX_MAC_TRNS_ERR_IDX] = {MVNETA_MIB_TX_MAC_TRNS_ERR, 0, 277 "tx_mac_err", "MAC Transmit Error"}, 278 [MVNETA_MIB_RX_GOOD_FRAME_IDX] = {MVNETA_MIB_RX_GOOD_FRAME, 0, 279 "rx_good_frame", "Good Frames Rx"}, 280 [MVNETA_MIB_RX_BAD_FRAME_IDX] = {MVNETA_MIB_RX_BAD_FRAME, 0, 281 "rx_bad_frame", "Bad Frames Rx"}, 282 [MVNETA_MIB_RX_BCAST_FRAME_IDX] = {MVNETA_MIB_RX_BCAST_FRAME, 0, 283 "rx_bcast_frame", "Broadcast Frames Rx"}, 284 [MVNETA_MIB_RX_MCAST_FRAME_IDX] = {MVNETA_MIB_RX_MCAST_FRAME, 0, 285 "rx_mcast_frame", "Multicast Frames Rx"}, 286 [MVNETA_MIB_RX_FRAME64_OCT_IDX] = {MVNETA_MIB_RX_FRAME64_OCT, 0, 287 "rx_frame_1_64", "Frame Size 1 - 64"}, 288 [MVNETA_MIB_RX_FRAME127_OCT_IDX] = {MVNETA_MIB_RX_FRAME127_OCT, 0, 289 "rx_frame_65_127", "Frame Size 65 - 127"}, 290 [MVNETA_MIB_RX_FRAME255_OCT_IDX] = {MVNETA_MIB_RX_FRAME255_OCT, 0, 291 "rx_frame_128_255", "Frame Size 128 - 255"}, 292 [MVNETA_MIB_RX_FRAME511_OCT_IDX] = {MVNETA_MIB_RX_FRAME511_OCT, 0, 293 "rx_frame_256_511", "Frame Size 256 - 511"}, 294 [MVNETA_MIB_RX_FRAME1023_OCT_IDX] = {MVNETA_MIB_RX_FRAME1023_OCT, 0, 295 "rx_frame_512_1023", "Frame Size 512 - 1023"}, 296 [MVNETA_MIB_RX_FRAMEMAX_OCT_IDX] = {MVNETA_MIB_RX_FRAMEMAX_OCT, 0, 297 "rx_fame_1024_max", "Frame Size 1024 - Max"}, 298 [MVNETA_MIB_TX_GOOD_OCT_IDX] = {MVNETA_MIB_TX_GOOD_OCT, 1, 299 "tx_good_oct", "Good Octets Tx"}, 300 [MVNETA_MIB_TX_GOOD_FRAME_IDX] = {MVNETA_MIB_TX_GOOD_FRAME, 0, 301 "tx_good_frame", "Good Frames Tx"}, 302 [MVNETA_MIB_TX_EXCES_COL_IDX] = {MVNETA_MIB_TX_EXCES_COL, 0, 303 "tx_exces_collision", "Excessive Collision"}, 304 [MVNETA_MIB_TX_MCAST_FRAME_IDX] = {MVNETA_MIB_TX_MCAST_FRAME, 0, 305 "tx_mcast_frame", "Multicast Frames Tx"}, 306 [MVNETA_MIB_TX_BCAST_FRAME_IDX] = {MVNETA_MIB_TX_BCAST_FRAME, 0, 307 "tx_bcast_frame", "Broadcast Frames Tx"}, 308 [MVNETA_MIB_TX_MAC_CTL_ERR_IDX] = {MVNETA_MIB_TX_MAC_CTL_ERR, 0, 309 "tx_mac_ctl_err", "Unknown MAC Control"}, 310 [MVNETA_MIB_FC_SENT_IDX] = {MVNETA_MIB_FC_SENT, 0, 311 "fc_tx", "Flow Control Tx"}, 312 [MVNETA_MIB_FC_GOOD_IDX] = {MVNETA_MIB_FC_GOOD, 0, 313 "fc_rx_good", "Good Flow Control Rx"}, 314 [MVNETA_MIB_FC_BAD_IDX] = {MVNETA_MIB_FC_BAD, 0, 315 "fc_rx_bad", "Bad Flow Control Rx"}, 316 [MVNETA_MIB_PKT_UNDERSIZE_IDX] = {MVNETA_MIB_PKT_UNDERSIZE, 0, 317 "pkt_undersize", "Undersized Packets Rx"}, 318 [MVNETA_MIB_PKT_FRAGMENT_IDX] = {MVNETA_MIB_PKT_FRAGMENT, 0, 319 "pkt_fragment", "Fragmented Packets Rx"}, 320 [MVNETA_MIB_PKT_OVERSIZE_IDX] = {MVNETA_MIB_PKT_OVERSIZE, 0, 321 "pkt_oversize", "Oversized Packets Rx"}, 322 [MVNETA_MIB_PKT_JABBER_IDX] = {MVNETA_MIB_PKT_JABBER, 0, 323 "pkt_jabber", "Jabber Packets Rx"}, 324 [MVNETA_MIB_MAC_RX_ERR_IDX] = {MVNETA_MIB_MAC_RX_ERR, 0, 325 "mac_rx_err", "MAC Rx Errors"}, 326 [MVNETA_MIB_MAC_CRC_ERR_IDX] = {MVNETA_MIB_MAC_CRC_ERR, 0, 327 "mac_crc_err", "MAC CRC Errors"}, 328 [MVNETA_MIB_MAC_COL_IDX] = {MVNETA_MIB_MAC_COL, 0, 329 "mac_collision", "MAC Collision"}, 330 [MVNETA_MIB_MAC_LATE_COL_IDX] = {MVNETA_MIB_MAC_LATE_COL, 0, 331 "mac_late_collision", "MAC Late Collision"}, 332 }; 333 334 static struct resource_spec res_spec[] = { 335 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 336 { SYS_RES_IRQ, 0, RF_ACTIVE }, 337 { -1, 0} 338 }; 339 340 static struct { 341 driver_intr_t *handler; 342 char * description; 343 } mvneta_intrs[] = { 344 { mvneta_rxtxth_intr, "MVNETA aggregated interrupt" }, 345 }; 346 347 STATIC uint32_t 348 mvneta_get_clk() 349 { 350 #if defined(__aarch64__) 351 return (A3700_TCLK_250MHZ); 352 #else 353 return (get_tclk()); 354 #endif 355 } 356 357 static int 358 mvneta_set_mac_address(struct mvneta_softc *sc, uint8_t *addr) 359 { 360 unsigned int mac_h; 361 unsigned int mac_l; 362 363 mac_l = (addr[4] << 8) | (addr[5]); 364 mac_h = (addr[0] << 24) | (addr[1] << 16) | 365 (addr[2] << 8) | (addr[3] << 0); 366 367 MVNETA_WRITE(sc, MVNETA_MACAL, mac_l); 368 MVNETA_WRITE(sc, MVNETA_MACAH, mac_h); 369 return (0); 370 } 371 372 static int 373 mvneta_get_mac_address(struct mvneta_softc *sc, uint8_t *addr) 374 { 375 uint32_t mac_l, mac_h; 376 377 #ifdef FDT 378 if (mvneta_fdt_mac_address(sc, addr) == 0) 379 return (0); 380 #endif 381 /* 382 * Fall back -- use the currently programmed address. 383 */ 384 mac_l = MVNETA_READ(sc, MVNETA_MACAL); 385 mac_h = MVNETA_READ(sc, MVNETA_MACAH); 386 if (mac_l == 0 && mac_h == 0) { 387 /* 388 * Generate pseudo-random MAC. 389 * Set lower part to random number | unit number. 390 */ 391 mac_l = arc4random() & ~0xff; 392 mac_l |= device_get_unit(sc->dev) & 0xff; 393 mac_h = arc4random(); 394 mac_h &= ~(3 << 24); /* Clear multicast and LAA bits */ 395 if (bootverbose) { 396 device_printf(sc->dev, 397 "Could not acquire MAC address. " 398 "Using randomized one.\n"); 399 } 400 } 401 402 addr[0] = (mac_h & 0xff000000) >> 24; 403 addr[1] = (mac_h & 0x00ff0000) >> 16; 404 addr[2] = (mac_h & 0x0000ff00) >> 8; 405 addr[3] = (mac_h & 0x000000ff); 406 addr[4] = (mac_l & 0x0000ff00) >> 8; 407 addr[5] = (mac_l & 0x000000ff); 408 return (0); 409 } 410 411 STATIC boolean_t 412 mvneta_has_switch(device_t self) 413 { 414 #ifdef FDT 415 return (mvneta_has_switch_fdt(self)); 416 #endif 417 418 return (false); 419 } 420 421 STATIC int 422 mvneta_dma_create(struct mvneta_softc *sc) 423 { 424 size_t maxsize, maxsegsz; 425 size_t q; 426 int error; 427 428 /* 429 * Create Tx DMA 430 */ 431 maxsize = maxsegsz = sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT; 432 433 error = bus_dma_tag_create( 434 bus_get_dma_tag(sc->dev), /* parent */ 435 16, 0, /* alignment, boundary */ 436 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 437 BUS_SPACE_MAXADDR, /* highaddr */ 438 NULL, NULL, /* filtfunc, filtfuncarg */ 439 maxsize, /* maxsize */ 440 1, /* nsegments */ 441 maxsegsz, /* maxsegsz */ 442 0, /* flags */ 443 NULL, NULL, /* lockfunc, lockfuncarg */ 444 &sc->tx_dtag); /* dmat */ 445 if (error != 0) { 446 device_printf(sc->dev, 447 "Failed to create DMA tag for Tx descriptors.\n"); 448 goto fail; 449 } 450 error = bus_dma_tag_create( 451 bus_get_dma_tag(sc->dev), /* parent */ 452 1, 0, /* alignment, boundary */ 453 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 454 BUS_SPACE_MAXADDR, /* highaddr */ 455 NULL, NULL, /* filtfunc, filtfuncarg */ 456 MVNETA_MAX_FRAME, /* maxsize */ 457 MVNETA_TX_SEGLIMIT, /* nsegments */ 458 MVNETA_MAX_FRAME, /* maxsegsz */ 459 BUS_DMA_ALLOCNOW, /* flags */ 460 NULL, NULL, /* lockfunc, lockfuncarg */ 461 &sc->txmbuf_dtag); 462 if (error != 0) { 463 device_printf(sc->dev, 464 "Failed to create DMA tag for Tx mbufs.\n"); 465 goto fail; 466 } 467 468 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 469 error = mvneta_ring_alloc_tx_queue(sc, q); 470 if (error != 0) { 471 device_printf(sc->dev, 472 "Failed to allocate DMA safe memory for TxQ: %zu\n", q); 473 goto fail; 474 } 475 } 476 477 /* 478 * Create Rx DMA. 479 */ 480 /* Create tag for Rx descripors */ 481 error = bus_dma_tag_create( 482 bus_get_dma_tag(sc->dev), /* parent */ 483 32, 0, /* alignment, boundary */ 484 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 485 BUS_SPACE_MAXADDR, /* highaddr */ 486 NULL, NULL, /* filtfunc, filtfuncarg */ 487 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsize */ 488 1, /* nsegments */ 489 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsegsz */ 490 0, /* flags */ 491 NULL, NULL, /* lockfunc, lockfuncarg */ 492 &sc->rx_dtag); /* dmat */ 493 if (error != 0) { 494 device_printf(sc->dev, 495 "Failed to create DMA tag for Rx descriptors.\n"); 496 goto fail; 497 } 498 499 /* Create tag for Rx buffers */ 500 error = bus_dma_tag_create( 501 bus_get_dma_tag(sc->dev), /* parent */ 502 32, 0, /* alignment, boundary */ 503 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 504 BUS_SPACE_MAXADDR, /* highaddr */ 505 NULL, NULL, /* filtfunc, filtfuncarg */ 506 MVNETA_MAX_FRAME, 1, /* maxsize, nsegments */ 507 MVNETA_MAX_FRAME, /* maxsegsz */ 508 0, /* flags */ 509 NULL, NULL, /* lockfunc, lockfuncarg */ 510 &sc->rxbuf_dtag); /* dmat */ 511 if (error != 0) { 512 device_printf(sc->dev, 513 "Failed to create DMA tag for Rx buffers.\n"); 514 goto fail; 515 } 516 517 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 518 if (mvneta_ring_alloc_rx_queue(sc, q) != 0) { 519 device_printf(sc->dev, 520 "Failed to allocate DMA safe memory for RxQ: %zu\n", q); 521 goto fail; 522 } 523 } 524 525 return (0); 526 fail: 527 mvneta_detach(sc->dev); 528 529 return (error); 530 } 531 532 /* ARGSUSED */ 533 int 534 mvneta_attach(device_t self) 535 { 536 struct mvneta_softc *sc; 537 struct ifnet *ifp; 538 device_t child; 539 int ifm_target; 540 int q, error; 541 #if !defined(__aarch64__) 542 uint32_t reg; 543 #endif 544 545 sc = device_get_softc(self); 546 sc->dev = self; 547 548 mtx_init(&sc->mtx, "mvneta_sc", NULL, MTX_DEF); 549 550 error = bus_alloc_resources(self, res_spec, sc->res); 551 if (error) { 552 device_printf(self, "could not allocate resources\n"); 553 return (ENXIO); 554 } 555 556 sc->version = MVNETA_READ(sc, MVNETA_PV); 557 device_printf(self, "version is %x\n", sc->version); 558 callout_init(&sc->tick_ch, 0); 559 560 /* 561 * make sure DMA engines are in reset state 562 */ 563 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 564 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 565 566 #if !defined(__aarch64__) 567 /* 568 * Disable port snoop for buffers and descriptors 569 * to avoid L2 caching of both without DRAM copy. 570 * Obtain coherency settings from the first MBUS 571 * window attribute. 572 */ 573 if ((MVNETA_READ(sc, MV_WIN_NETA_BASE(0)) & IO_WIN_COH_ATTR_MASK) == 0) { 574 reg = MVNETA_READ(sc, MVNETA_PSNPCFG); 575 reg &= ~MVNETA_PSNPCFG_DESCSNP_MASK; 576 reg &= ~MVNETA_PSNPCFG_BUFSNP_MASK; 577 MVNETA_WRITE(sc, MVNETA_PSNPCFG, reg); 578 } 579 #endif 580 581 error = bus_setup_intr(self, sc->res[1], 582 INTR_TYPE_NET | INTR_MPSAFE, NULL, mvneta_intrs[0].handler, sc, 583 &sc->ih_cookie[0]); 584 if (error) { 585 device_printf(self, "could not setup %s\n", 586 mvneta_intrs[0].description); 587 mvneta_detach(self); 588 return (error); 589 } 590 591 /* 592 * MAC address 593 */ 594 if (mvneta_get_mac_address(sc, sc->enaddr)) { 595 device_printf(self, "no mac address.\n"); 596 return (ENXIO); 597 } 598 mvneta_set_mac_address(sc, sc->enaddr); 599 600 mvneta_disable_intr(sc); 601 602 /* Allocate network interface */ 603 ifp = sc->ifp = if_alloc(IFT_ETHER); 604 if (ifp == NULL) { 605 device_printf(self, "if_alloc() failed\n"); 606 mvneta_detach(self); 607 return (ENOMEM); 608 } 609 if_initname(ifp, device_get_name(self), device_get_unit(self)); 610 611 /* 612 * We can support 802.1Q VLAN-sized frames and jumbo 613 * Ethernet frames. 614 */ 615 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU; 616 617 ifp->if_softc = sc; 618 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 619 #ifdef MVNETA_MULTIQUEUE 620 ifp->if_transmit = mvneta_transmit; 621 ifp->if_qflush = mvneta_qflush; 622 #else /* !MVNETA_MULTIQUEUE */ 623 ifp->if_start = mvneta_start; 624 ifp->if_snd.ifq_drv_maxlen = MVNETA_TX_RING_CNT - 1; 625 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 626 IFQ_SET_READY(&ifp->if_snd); 627 #endif 628 ifp->if_init = mvneta_init; 629 ifp->if_ioctl = mvneta_ioctl; 630 631 /* 632 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 633 */ 634 ifp->if_capabilities |= IFCAP_HWCSUM; 635 636 /* 637 * As VLAN hardware tagging is not supported 638 * but is necessary to perform VLAN hardware checksums, 639 * it is done in the driver 640 */ 641 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 642 643 /* 644 * Currently IPv6 HW checksum is broken, so make sure it is disabled. 645 */ 646 ifp->if_capabilities &= ~IFCAP_HWCSUM_IPV6; 647 ifp->if_capenable = ifp->if_capabilities; 648 649 /* 650 * Disabled option(s): 651 * - Support for Large Receive Offload 652 */ 653 ifp->if_capabilities |= IFCAP_LRO; 654 655 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 656 657 sc->rx_frame_size = MCLBYTES; /* ether_ifattach() always sets normal mtu */ 658 659 /* 660 * Device DMA Buffer allocation. 661 * Handles resource deallocation in case of failure. 662 */ 663 error = mvneta_dma_create(sc); 664 if (error != 0) { 665 mvneta_detach(self); 666 return (error); 667 } 668 669 /* Initialize queues */ 670 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 671 error = mvneta_ring_init_tx_queue(sc, q); 672 if (error != 0) { 673 mvneta_detach(self); 674 return (error); 675 } 676 } 677 678 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 679 error = mvneta_ring_init_rx_queue(sc, q); 680 if (error != 0) { 681 mvneta_detach(self); 682 return (error); 683 } 684 } 685 686 /* 687 * Enable DMA engines and Initialize Device Registers. 688 */ 689 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 690 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 691 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 692 mvneta_sc_lock(sc); 693 mvneta_filter_setup(sc); 694 mvneta_sc_unlock(sc); 695 mvneta_initreg(ifp); 696 697 /* 698 * Now MAC is working, setup MII. 699 */ 700 if (mii_init == 0) { 701 /* 702 * MII bus is shared by all MACs and all PHYs in SoC. 703 * serializing the bus access should be safe. 704 */ 705 mtx_init(&mii_mutex, "mvneta_mii", NULL, MTX_DEF); 706 mii_init = 1; 707 } 708 709 /* Attach PHY(s) */ 710 if ((sc->phy_addr != MII_PHY_ANY) && (!sc->use_inband_status)) { 711 error = mii_attach(self, &sc->miibus, ifp, mvneta_mediachange, 712 mvneta_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, 713 MII_OFFSET_ANY, 0); 714 if (error != 0) { 715 if (bootverbose) { 716 device_printf(self, 717 "MII attach failed, error: %d\n", error); 718 } 719 ether_ifdetach(sc->ifp); 720 mvneta_detach(self); 721 return (error); 722 } 723 sc->mii = device_get_softc(sc->miibus); 724 sc->phy_attached = 1; 725 726 /* Disable auto-negotiation in MAC - rely on PHY layer */ 727 mvneta_update_autoneg(sc, FALSE); 728 } else if (sc->use_inband_status == TRUE) { 729 /* In-band link status */ 730 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 731 mvneta_mediastatus); 732 733 /* Configure media */ 734 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 735 0, NULL); 736 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 737 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 738 0, NULL); 739 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 740 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 741 0, NULL); 742 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 743 ifmedia_set(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO); 744 745 /* Enable auto-negotiation */ 746 mvneta_update_autoneg(sc, TRUE); 747 748 mvneta_sc_lock(sc); 749 if (MVNETA_IS_LINKUP(sc)) 750 mvneta_linkup(sc); 751 else 752 mvneta_linkdown(sc); 753 mvneta_sc_unlock(sc); 754 755 } else { 756 /* Fixed-link, use predefined values */ 757 mvneta_update_autoneg(sc, FALSE); 758 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 759 mvneta_mediastatus); 760 761 ifm_target = IFM_ETHER; 762 switch (sc->phy_speed) { 763 case 2500: 764 if (sc->phy_mode != MVNETA_PHY_SGMII && 765 sc->phy_mode != MVNETA_PHY_QSGMII) { 766 device_printf(self, 767 "2.5G speed can work only in (Q)SGMII mode\n"); 768 ether_ifdetach(sc->ifp); 769 mvneta_detach(self); 770 return (ENXIO); 771 } 772 ifm_target |= IFM_2500_T; 773 break; 774 case 1000: 775 ifm_target |= IFM_1000_T; 776 break; 777 case 100: 778 ifm_target |= IFM_100_TX; 779 break; 780 case 10: 781 ifm_target |= IFM_10_T; 782 break; 783 default: 784 ether_ifdetach(sc->ifp); 785 mvneta_detach(self); 786 return (ENXIO); 787 } 788 789 if (sc->phy_fdx) 790 ifm_target |= IFM_FDX; 791 else 792 ifm_target |= IFM_HDX; 793 794 ifmedia_add(&sc->mvneta_ifmedia, ifm_target, 0, NULL); 795 ifmedia_set(&sc->mvneta_ifmedia, ifm_target); 796 if_link_state_change(sc->ifp, LINK_STATE_UP); 797 798 if (mvneta_has_switch(self)) { 799 if (bootverbose) 800 device_printf(self, "This device is attached to a switch\n"); 801 child = device_add_child(sc->dev, "mdio", -1); 802 if (child == NULL) { 803 ether_ifdetach(sc->ifp); 804 mvneta_detach(self); 805 return (ENXIO); 806 } 807 bus_generic_attach(sc->dev); 808 bus_generic_attach(child); 809 } 810 811 /* Configure MAC media */ 812 mvneta_update_media(sc, ifm_target); 813 } 814 815 ether_ifattach(ifp, sc->enaddr); 816 817 callout_reset(&sc->tick_ch, 0, mvneta_tick, sc); 818 819 sysctl_mvneta_init(sc); 820 821 return (0); 822 } 823 824 STATIC int 825 mvneta_detach(device_t dev) 826 { 827 struct mvneta_softc *sc; 828 struct ifnet *ifp; 829 int q; 830 831 sc = device_get_softc(dev); 832 ifp = sc->ifp; 833 834 if (device_is_attached(dev)) { 835 mvneta_stop(sc); 836 callout_drain(&sc->tick_ch); 837 ether_ifdetach(sc->ifp); 838 } 839 840 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) 841 mvneta_ring_dealloc_rx_queue(sc, q); 842 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) 843 mvneta_ring_dealloc_tx_queue(sc, q); 844 845 device_delete_children(dev); 846 847 if (sc->ih_cookie[0] != NULL) 848 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie[0]); 849 850 if (sc->tx_dtag != NULL) 851 bus_dma_tag_destroy(sc->tx_dtag); 852 if (sc->rx_dtag != NULL) 853 bus_dma_tag_destroy(sc->rx_dtag); 854 if (sc->txmbuf_dtag != NULL) 855 bus_dma_tag_destroy(sc->txmbuf_dtag); 856 if (sc->rxbuf_dtag != NULL) 857 bus_dma_tag_destroy(sc->rxbuf_dtag); 858 859 bus_release_resources(dev, res_spec, sc->res); 860 861 if (sc->ifp) 862 if_free(sc->ifp); 863 864 if (mtx_initialized(&sc->mtx)) 865 mtx_destroy(&sc->mtx); 866 867 return (0); 868 } 869 870 /* 871 * MII 872 */ 873 STATIC int 874 mvneta_miibus_readreg(device_t dev, int phy, int reg) 875 { 876 struct mvneta_softc *sc; 877 struct ifnet *ifp; 878 uint32_t smi, val; 879 int i; 880 881 sc = device_get_softc(dev); 882 ifp = sc->ifp; 883 884 mtx_lock(&mii_mutex); 885 886 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 887 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 888 break; 889 DELAY(1); 890 } 891 if (i == MVNETA_PHY_TIMEOUT) { 892 if_printf(ifp, "SMI busy timeout\n"); 893 mtx_unlock(&mii_mutex); 894 return (-1); 895 } 896 897 smi = MVNETA_SMI_PHYAD(phy) | 898 MVNETA_SMI_REGAD(reg) | MVNETA_SMI_OPCODE_READ; 899 MVNETA_WRITE(sc, MVNETA_SMI, smi); 900 901 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 902 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 903 break; 904 DELAY(1); 905 } 906 907 if (i == MVNETA_PHY_TIMEOUT) { 908 if_printf(ifp, "SMI busy timeout\n"); 909 mtx_unlock(&mii_mutex); 910 return (-1); 911 } 912 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 913 smi = MVNETA_READ(sc, MVNETA_SMI); 914 if (smi & MVNETA_SMI_READVALID) 915 break; 916 DELAY(1); 917 } 918 919 if (i == MVNETA_PHY_TIMEOUT) { 920 if_printf(ifp, "SMI busy timeout\n"); 921 mtx_unlock(&mii_mutex); 922 return (-1); 923 } 924 925 mtx_unlock(&mii_mutex); 926 927 #ifdef MVNETA_KTR 928 CTR3(KTR_SPARE2, "%s i=%d, timeout=%d\n", ifp->if_xname, i, 929 MVNETA_PHY_TIMEOUT); 930 #endif 931 932 val = smi & MVNETA_SMI_DATA_MASK; 933 934 #ifdef MVNETA_KTR 935 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, phy, 936 reg, val); 937 #endif 938 return (val); 939 } 940 941 STATIC int 942 mvneta_miibus_writereg(device_t dev, int phy, int reg, int val) 943 { 944 struct mvneta_softc *sc; 945 struct ifnet *ifp; 946 uint32_t smi; 947 int i; 948 949 sc = device_get_softc(dev); 950 ifp = sc->ifp; 951 #ifdef MVNETA_KTR 952 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, 953 phy, reg, val); 954 #endif 955 956 mtx_lock(&mii_mutex); 957 958 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 959 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 960 break; 961 DELAY(1); 962 } 963 if (i == MVNETA_PHY_TIMEOUT) { 964 if_printf(ifp, "SMI busy timeout\n"); 965 mtx_unlock(&mii_mutex); 966 return (0); 967 } 968 969 smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) | 970 MVNETA_SMI_OPCODE_WRITE | (val & MVNETA_SMI_DATA_MASK); 971 MVNETA_WRITE(sc, MVNETA_SMI, smi); 972 973 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 974 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 975 break; 976 DELAY(1); 977 } 978 979 mtx_unlock(&mii_mutex); 980 981 if (i == MVNETA_PHY_TIMEOUT) 982 if_printf(ifp, "phy write timed out\n"); 983 984 return (0); 985 } 986 987 STATIC void 988 mvneta_portup(struct mvneta_softc *sc) 989 { 990 int q; 991 992 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 993 mvneta_rx_lockq(sc, q); 994 mvneta_rx_queue_enable(sc->ifp, q); 995 mvneta_rx_unlockq(sc, q); 996 } 997 998 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 999 mvneta_tx_lockq(sc, q); 1000 mvneta_tx_queue_enable(sc->ifp, q); 1001 mvneta_tx_unlockq(sc, q); 1002 } 1003 1004 } 1005 1006 STATIC void 1007 mvneta_portdown(struct mvneta_softc *sc) 1008 { 1009 struct mvneta_rx_ring *rx; 1010 struct mvneta_tx_ring *tx; 1011 int q, cnt; 1012 uint32_t reg; 1013 1014 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1015 rx = MVNETA_RX_RING(sc, q); 1016 mvneta_rx_lockq(sc, q); 1017 rx->queue_status = MVNETA_QUEUE_DISABLED; 1018 mvneta_rx_unlockq(sc, q); 1019 } 1020 1021 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1022 tx = MVNETA_TX_RING(sc, q); 1023 mvneta_tx_lockq(sc, q); 1024 tx->queue_status = MVNETA_QUEUE_DISABLED; 1025 mvneta_tx_unlockq(sc, q); 1026 } 1027 1028 /* Wait for all Rx activity to terminate. */ 1029 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1030 reg = MVNETA_RQC_DIS(reg); 1031 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1032 cnt = 0; 1033 do { 1034 if (cnt >= RX_DISABLE_TIMEOUT) { 1035 if_printf(sc->ifp, 1036 "timeout for RX stopped. rqc 0x%x\n", reg); 1037 break; 1038 } 1039 cnt++; 1040 reg = MVNETA_READ(sc, MVNETA_RQC); 1041 } while ((reg & MVNETA_RQC_EN_MASK) != 0); 1042 1043 /* Wait for all Tx activity to terminate. */ 1044 reg = MVNETA_READ(sc, MVNETA_PIE); 1045 reg &= ~MVNETA_PIE_TXPKTINTRPTENB_MASK; 1046 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1047 1048 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1049 reg &= ~MVNETA_PRXTXTI_TBTCQ_MASK; 1050 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1051 1052 reg = MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_EN_MASK; 1053 reg = MVNETA_TQC_DIS(reg); 1054 MVNETA_WRITE(sc, MVNETA_TQC, reg); 1055 cnt = 0; 1056 do { 1057 if (cnt >= TX_DISABLE_TIMEOUT) { 1058 if_printf(sc->ifp, 1059 "timeout for TX stopped. tqc 0x%x\n", reg); 1060 break; 1061 } 1062 cnt++; 1063 reg = MVNETA_READ(sc, MVNETA_TQC); 1064 } while ((reg & MVNETA_TQC_EN_MASK) != 0); 1065 1066 /* Wait for all Tx FIFO is empty */ 1067 cnt = 0; 1068 do { 1069 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1070 if_printf(sc->ifp, 1071 "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1072 break; 1073 } 1074 cnt++; 1075 reg = MVNETA_READ(sc, MVNETA_PS0); 1076 } while (((reg & MVNETA_PS0_TXFIFOEMP) == 0) && 1077 ((reg & MVNETA_PS0_TXINPROG) != 0)); 1078 } 1079 1080 /* 1081 * Device Register Initialization 1082 * reset device registers to device driver default value. 1083 * the device is not enabled here. 1084 */ 1085 STATIC int 1086 mvneta_initreg(struct ifnet *ifp) 1087 { 1088 struct mvneta_softc *sc; 1089 int q; 1090 uint32_t reg; 1091 1092 sc = ifp->if_softc; 1093 #ifdef MVNETA_KTR 1094 CTR1(KTR_SPARE2, "%s initializing device register", ifp->if_xname); 1095 #endif 1096 1097 /* Disable Legacy WRR, Disable EJP, Release from reset. */ 1098 MVNETA_WRITE(sc, MVNETA_TQC_1, 0); 1099 /* Enable mbus retry. */ 1100 MVNETA_WRITE(sc, MVNETA_MBUS_CONF, MVNETA_MBUS_RETRY_EN); 1101 1102 /* Init TX/RX Queue Registers */ 1103 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1104 mvneta_rx_lockq(sc, q); 1105 if (mvneta_rx_queue_init(ifp, q) != 0) { 1106 device_printf(sc->dev, 1107 "initialization failed: cannot initialize queue\n"); 1108 mvneta_rx_unlockq(sc, q); 1109 return (ENOBUFS); 1110 } 1111 mvneta_rx_unlockq(sc, q); 1112 } 1113 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1114 mvneta_tx_lockq(sc, q); 1115 if (mvneta_tx_queue_init(ifp, q) != 0) { 1116 device_printf(sc->dev, 1117 "initialization failed: cannot initialize queue\n"); 1118 mvneta_tx_unlockq(sc, q); 1119 return (ENOBUFS); 1120 } 1121 mvneta_tx_unlockq(sc, q); 1122 } 1123 1124 /* 1125 * Ethernet Unit Control - disable automatic PHY management by HW. 1126 * In case the port uses SMI-controlled PHY, poll its status with 1127 * mii_tick() and update MAC settings accordingly. 1128 */ 1129 reg = MVNETA_READ(sc, MVNETA_EUC); 1130 reg &= ~MVNETA_EUC_POLLING; 1131 MVNETA_WRITE(sc, MVNETA_EUC, reg); 1132 1133 /* EEE: Low Power Idle */ 1134 reg = MVNETA_LPIC0_LILIMIT(MVNETA_LPI_LI); 1135 reg |= MVNETA_LPIC0_TSLIMIT(MVNETA_LPI_TS); 1136 MVNETA_WRITE(sc, MVNETA_LPIC0, reg); 1137 1138 reg = MVNETA_LPIC1_TWLIMIT(MVNETA_LPI_TW); 1139 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 1140 1141 reg = MVNETA_LPIC2_MUSTSET; 1142 MVNETA_WRITE(sc, MVNETA_LPIC2, reg); 1143 1144 /* Port MAC Control set 0 */ 1145 reg = MVNETA_PMACC0_MUSTSET; /* must write 0x1 */ 1146 reg &= ~MVNETA_PMACC0_PORTEN; /* port is still disabled */ 1147 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 1148 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 1149 1150 /* Port MAC Control set 2 */ 1151 reg = MVNETA_READ(sc, MVNETA_PMACC2); 1152 switch (sc->phy_mode) { 1153 case MVNETA_PHY_QSGMII: 1154 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1155 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_QSGMII); 1156 break; 1157 case MVNETA_PHY_SGMII: 1158 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1159 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_SGMII); 1160 break; 1161 case MVNETA_PHY_RGMII: 1162 case MVNETA_PHY_RGMII_ID: 1163 reg |= MVNETA_PMACC2_RGMIIEN; 1164 break; 1165 } 1166 reg |= MVNETA_PMACC2_MUSTSET; 1167 reg &= ~MVNETA_PMACC2_PORTMACRESET; 1168 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 1169 1170 /* Port Configuration Extended: enable Tx CRC generation */ 1171 reg = MVNETA_READ(sc, MVNETA_PXCX); 1172 reg &= ~MVNETA_PXCX_TXCRCDIS; 1173 MVNETA_WRITE(sc, MVNETA_PXCX, reg); 1174 1175 /* clear MIB counter registers(clear by read) */ 1176 mvneta_sc_lock(sc); 1177 mvneta_clear_mib(sc); 1178 mvneta_sc_unlock(sc); 1179 1180 /* Set SDC register except IPGINT bits */ 1181 reg = MVNETA_SDC_RXBSZ_16_64BITWORDS; 1182 reg |= MVNETA_SDC_TXBSZ_16_64BITWORDS; 1183 reg |= MVNETA_SDC_BLMR; 1184 reg |= MVNETA_SDC_BLMT; 1185 MVNETA_WRITE(sc, MVNETA_SDC, reg); 1186 1187 return (0); 1188 } 1189 1190 STATIC void 1191 mvneta_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error) 1192 { 1193 1194 if (error != 0) 1195 return; 1196 *(bus_addr_t *)arg = segs->ds_addr; 1197 } 1198 1199 STATIC int 1200 mvneta_ring_alloc_rx_queue(struct mvneta_softc *sc, int q) 1201 { 1202 struct mvneta_rx_ring *rx; 1203 struct mvneta_buf *rxbuf; 1204 bus_dmamap_t dmap; 1205 int i, error; 1206 1207 if (q >= MVNETA_RX_QNUM_MAX) 1208 return (EINVAL); 1209 1210 rx = MVNETA_RX_RING(sc, q); 1211 mtx_init(&rx->ring_mtx, "mvneta_rx", NULL, MTX_DEF); 1212 /* Allocate DMA memory for Rx descriptors */ 1213 error = bus_dmamem_alloc(sc->rx_dtag, 1214 (void**)&(rx->desc), 1215 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1216 &rx->desc_map); 1217 if (error != 0 || rx->desc == NULL) 1218 goto fail; 1219 error = bus_dmamap_load(sc->rx_dtag, rx->desc_map, 1220 rx->desc, 1221 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, 1222 mvneta_dmamap_cb, &rx->desc_pa, BUS_DMA_NOWAIT); 1223 if (error != 0) 1224 goto fail; 1225 1226 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1227 error = bus_dmamap_create(sc->rxbuf_dtag, 0, &dmap); 1228 if (error != 0) { 1229 device_printf(sc->dev, 1230 "Failed to create DMA map for Rx buffer num: %d\n", i); 1231 goto fail; 1232 } 1233 rxbuf = &rx->rxbuf[i]; 1234 rxbuf->dmap = dmap; 1235 rxbuf->m = NULL; 1236 } 1237 1238 return (0); 1239 fail: 1240 mvneta_rx_lockq(sc, q); 1241 mvneta_ring_flush_rx_queue(sc, q); 1242 mvneta_rx_unlockq(sc, q); 1243 mvneta_ring_dealloc_rx_queue(sc, q); 1244 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1245 return (error); 1246 } 1247 1248 STATIC int 1249 mvneta_ring_alloc_tx_queue(struct mvneta_softc *sc, int q) 1250 { 1251 struct mvneta_tx_ring *tx; 1252 int error; 1253 1254 if (q >= MVNETA_TX_QNUM_MAX) 1255 return (EINVAL); 1256 tx = MVNETA_TX_RING(sc, q); 1257 mtx_init(&tx->ring_mtx, "mvneta_tx", NULL, MTX_DEF); 1258 error = bus_dmamem_alloc(sc->tx_dtag, 1259 (void**)&(tx->desc), 1260 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1261 &tx->desc_map); 1262 if (error != 0 || tx->desc == NULL) 1263 goto fail; 1264 error = bus_dmamap_load(sc->tx_dtag, tx->desc_map, 1265 tx->desc, 1266 sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT, 1267 mvneta_dmamap_cb, &tx->desc_pa, BUS_DMA_NOWAIT); 1268 if (error != 0) 1269 goto fail; 1270 1271 #ifdef MVNETA_MULTIQUEUE 1272 tx->br = buf_ring_alloc(MVNETA_BUFRING_SIZE, M_DEVBUF, M_NOWAIT, 1273 &tx->ring_mtx); 1274 if (tx->br == NULL) { 1275 device_printf(sc->dev, 1276 "Could not setup buffer ring for TxQ(%d)\n", q); 1277 error = ENOMEM; 1278 goto fail; 1279 } 1280 #endif 1281 1282 return (0); 1283 fail: 1284 mvneta_tx_lockq(sc, q); 1285 mvneta_ring_flush_tx_queue(sc, q); 1286 mvneta_tx_unlockq(sc, q); 1287 mvneta_ring_dealloc_tx_queue(sc, q); 1288 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1289 return (error); 1290 } 1291 1292 STATIC void 1293 mvneta_ring_dealloc_tx_queue(struct mvneta_softc *sc, int q) 1294 { 1295 struct mvneta_tx_ring *tx; 1296 struct mvneta_buf *txbuf; 1297 void *kva; 1298 int error; 1299 int i; 1300 1301 if (q >= MVNETA_TX_QNUM_MAX) 1302 return; 1303 tx = MVNETA_TX_RING(sc, q); 1304 1305 if (tx->taskq != NULL) { 1306 /* Remove task */ 1307 while (taskqueue_cancel(tx->taskq, &tx->task, NULL) != 0) 1308 taskqueue_drain(tx->taskq, &tx->task); 1309 } 1310 #ifdef MVNETA_MULTIQUEUE 1311 if (tx->br != NULL) 1312 drbr_free(tx->br, M_DEVBUF); 1313 #endif 1314 1315 if (sc->txmbuf_dtag != NULL) { 1316 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1317 txbuf = &tx->txbuf[i]; 1318 if (txbuf->dmap != NULL) { 1319 error = bus_dmamap_destroy(sc->txmbuf_dtag, 1320 txbuf->dmap); 1321 if (error != 0) { 1322 panic("%s: map busy for Tx descriptor (Q%d, %d)", 1323 __func__, q, i); 1324 } 1325 } 1326 } 1327 } 1328 1329 if (tx->desc_pa != 0) 1330 bus_dmamap_unload(sc->tx_dtag, tx->desc_map); 1331 1332 kva = (void *)tx->desc; 1333 if (kva != NULL) 1334 bus_dmamem_free(sc->tx_dtag, tx->desc, tx->desc_map); 1335 1336 if (mtx_name(&tx->ring_mtx) != NULL) 1337 mtx_destroy(&tx->ring_mtx); 1338 1339 memset(tx, 0, sizeof(*tx)); 1340 } 1341 1342 STATIC void 1343 mvneta_ring_dealloc_rx_queue(struct mvneta_softc *sc, int q) 1344 { 1345 struct mvneta_rx_ring *rx; 1346 struct lro_ctrl *lro; 1347 void *kva; 1348 1349 if (q >= MVNETA_RX_QNUM_MAX) 1350 return; 1351 1352 rx = MVNETA_RX_RING(sc, q); 1353 1354 if (rx->desc_pa != 0) 1355 bus_dmamap_unload(sc->rx_dtag, rx->desc_map); 1356 1357 kva = (void *)rx->desc; 1358 if (kva != NULL) 1359 bus_dmamem_free(sc->rx_dtag, rx->desc, rx->desc_map); 1360 1361 lro = &rx->lro; 1362 tcp_lro_free(lro); 1363 1364 if (mtx_name(&rx->ring_mtx) != NULL) 1365 mtx_destroy(&rx->ring_mtx); 1366 1367 memset(rx, 0, sizeof(*rx)); 1368 } 1369 1370 STATIC int 1371 mvneta_ring_init_rx_queue(struct mvneta_softc *sc, int q) 1372 { 1373 struct mvneta_rx_ring *rx; 1374 struct lro_ctrl *lro; 1375 int error; 1376 1377 if (q >= MVNETA_RX_QNUM_MAX) 1378 return (0); 1379 1380 rx = MVNETA_RX_RING(sc, q); 1381 rx->dma = rx->cpu = 0; 1382 rx->queue_th_received = MVNETA_RXTH_COUNT; 1383 rx->queue_th_time = (mvneta_get_clk() / 1000) / 10; /* 0.1 [ms] */ 1384 1385 /* Initialize LRO */ 1386 rx->lro_enabled = FALSE; 1387 if ((sc->ifp->if_capenable & IFCAP_LRO) != 0) { 1388 lro = &rx->lro; 1389 error = tcp_lro_init(lro); 1390 if (error != 0) 1391 device_printf(sc->dev, "LRO Initialization failed!\n"); 1392 else { 1393 rx->lro_enabled = TRUE; 1394 lro->ifp = sc->ifp; 1395 } 1396 } 1397 1398 return (0); 1399 } 1400 1401 STATIC int 1402 mvneta_ring_init_tx_queue(struct mvneta_softc *sc, int q) 1403 { 1404 struct mvneta_tx_ring *tx; 1405 struct mvneta_buf *txbuf; 1406 int i, error; 1407 1408 if (q >= MVNETA_TX_QNUM_MAX) 1409 return (0); 1410 1411 tx = MVNETA_TX_RING(sc, q); 1412 1413 /* Tx handle */ 1414 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1415 txbuf = &tx->txbuf[i]; 1416 txbuf->m = NULL; 1417 /* Tx handle needs DMA map for busdma_load_mbuf() */ 1418 error = bus_dmamap_create(sc->txmbuf_dtag, 0, 1419 &txbuf->dmap); 1420 if (error != 0) { 1421 device_printf(sc->dev, 1422 "can't create dma map (tx ring %d)\n", i); 1423 return (error); 1424 } 1425 } 1426 tx->dma = tx->cpu = 0; 1427 tx->used = 0; 1428 tx->drv_error = 0; 1429 tx->queue_status = MVNETA_QUEUE_DISABLED; 1430 tx->queue_hung = FALSE; 1431 1432 tx->ifp = sc->ifp; 1433 tx->qidx = q; 1434 TASK_INIT(&tx->task, 0, mvneta_tx_task, tx); 1435 tx->taskq = taskqueue_create_fast("mvneta_tx_taskq", M_WAITOK, 1436 taskqueue_thread_enqueue, &tx->taskq); 1437 taskqueue_start_threads(&tx->taskq, 1, PI_NET, "%s: tx_taskq(%d)", 1438 device_get_nameunit(sc->dev), q); 1439 1440 return (0); 1441 } 1442 1443 STATIC void 1444 mvneta_ring_flush_tx_queue(struct mvneta_softc *sc, int q) 1445 { 1446 struct mvneta_tx_ring *tx; 1447 struct mvneta_buf *txbuf; 1448 int i; 1449 1450 tx = MVNETA_TX_RING(sc, q); 1451 KASSERT_TX_MTX(sc, q); 1452 1453 /* Tx handle */ 1454 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1455 txbuf = &tx->txbuf[i]; 1456 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 1457 if (txbuf->m != NULL) { 1458 m_freem(txbuf->m); 1459 txbuf->m = NULL; 1460 } 1461 } 1462 tx->dma = tx->cpu = 0; 1463 tx->used = 0; 1464 } 1465 1466 STATIC void 1467 mvneta_ring_flush_rx_queue(struct mvneta_softc *sc, int q) 1468 { 1469 struct mvneta_rx_ring *rx; 1470 struct mvneta_buf *rxbuf; 1471 int i; 1472 1473 rx = MVNETA_RX_RING(sc, q); 1474 KASSERT_RX_MTX(sc, q); 1475 1476 /* Rx handle */ 1477 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1478 rxbuf = &rx->rxbuf[i]; 1479 mvneta_rx_buf_free(sc, rxbuf); 1480 } 1481 rx->dma = rx->cpu = 0; 1482 } 1483 1484 /* 1485 * Rx/Tx Queue Control 1486 */ 1487 STATIC int 1488 mvneta_rx_queue_init(struct ifnet *ifp, int q) 1489 { 1490 struct mvneta_softc *sc; 1491 struct mvneta_rx_ring *rx; 1492 uint32_t reg; 1493 1494 sc = ifp->if_softc; 1495 KASSERT_RX_MTX(sc, q); 1496 rx = MVNETA_RX_RING(sc, q); 1497 DASSERT(rx->desc_pa != 0); 1498 1499 /* descriptor address */ 1500 MVNETA_WRITE(sc, MVNETA_PRXDQA(q), rx->desc_pa); 1501 1502 /* Rx buffer size and descriptor ring size */ 1503 reg = MVNETA_PRXDQS_BUFFERSIZE(sc->rx_frame_size >> 3); 1504 reg |= MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(MVNETA_RX_RING_CNT); 1505 MVNETA_WRITE(sc, MVNETA_PRXDQS(q), reg); 1506 #ifdef MVNETA_KTR 1507 CTR3(KTR_SPARE2, "%s PRXDQS(%d): %#x", ifp->if_xname, q, 1508 MVNETA_READ(sc, MVNETA_PRXDQS(q))); 1509 #endif 1510 /* Rx packet offset address */ 1511 reg = MVNETA_PRXC_PACKETOFFSET(MVNETA_PACKET_OFFSET >> 3); 1512 MVNETA_WRITE(sc, MVNETA_PRXC(q), reg); 1513 #ifdef MVNETA_KTR 1514 CTR3(KTR_SPARE2, "%s PRXC(%d): %#x", ifp->if_xname, q, 1515 MVNETA_READ(sc, MVNETA_PRXC(q))); 1516 #endif 1517 1518 /* if DMA is not working, register is not updated */ 1519 DASSERT(MVNETA_READ(sc, MVNETA_PRXDQA(q)) == rx->desc_pa); 1520 return (0); 1521 } 1522 1523 STATIC int 1524 mvneta_tx_queue_init(struct ifnet *ifp, int q) 1525 { 1526 struct mvneta_softc *sc; 1527 struct mvneta_tx_ring *tx; 1528 uint32_t reg; 1529 1530 sc = ifp->if_softc; 1531 KASSERT_TX_MTX(sc, q); 1532 tx = MVNETA_TX_RING(sc, q); 1533 DASSERT(tx->desc_pa != 0); 1534 1535 /* descriptor address */ 1536 MVNETA_WRITE(sc, MVNETA_PTXDQA(q), tx->desc_pa); 1537 1538 /* descriptor ring size */ 1539 reg = MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT); 1540 MVNETA_WRITE(sc, MVNETA_PTXDQS(q), reg); 1541 1542 /* if DMA is not working, register is not updated */ 1543 DASSERT(MVNETA_READ(sc, MVNETA_PTXDQA(q)) == tx->desc_pa); 1544 return (0); 1545 } 1546 1547 STATIC int 1548 mvneta_rx_queue_enable(struct ifnet *ifp, int q) 1549 { 1550 struct mvneta_softc *sc; 1551 struct mvneta_rx_ring *rx; 1552 uint32_t reg; 1553 1554 sc = ifp->if_softc; 1555 rx = MVNETA_RX_RING(sc, q); 1556 KASSERT_RX_MTX(sc, q); 1557 1558 /* Set Rx interrupt threshold */ 1559 reg = MVNETA_PRXDQTH_ODT(rx->queue_th_received); 1560 MVNETA_WRITE(sc, MVNETA_PRXDQTH(q), reg); 1561 1562 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 1563 MVNETA_WRITE(sc, MVNETA_PRXITTH(q), reg); 1564 1565 /* Unmask RXTX_TH Intr. */ 1566 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1567 reg |= MVNETA_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1568 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1569 1570 /* Enable Rx queue */ 1571 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1572 reg |= MVNETA_RQC_ENQ(q); 1573 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1574 1575 rx->queue_status = MVNETA_QUEUE_WORKING; 1576 return (0); 1577 } 1578 1579 STATIC int 1580 mvneta_tx_queue_enable(struct ifnet *ifp, int q) 1581 { 1582 struct mvneta_softc *sc; 1583 struct mvneta_tx_ring *tx; 1584 1585 sc = ifp->if_softc; 1586 tx = MVNETA_TX_RING(sc, q); 1587 KASSERT_TX_MTX(sc, q); 1588 1589 /* Enable Tx queue */ 1590 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(q)); 1591 1592 tx->queue_status = MVNETA_QUEUE_IDLE; 1593 tx->queue_hung = FALSE; 1594 return (0); 1595 } 1596 1597 STATIC __inline void 1598 mvneta_rx_lockq(struct mvneta_softc *sc, int q) 1599 { 1600 1601 DASSERT(q >= 0); 1602 DASSERT(q < MVNETA_RX_QNUM_MAX); 1603 mtx_lock(&sc->rx_ring[q].ring_mtx); 1604 } 1605 1606 STATIC __inline void 1607 mvneta_rx_unlockq(struct mvneta_softc *sc, int q) 1608 { 1609 1610 DASSERT(q >= 0); 1611 DASSERT(q < MVNETA_RX_QNUM_MAX); 1612 mtx_unlock(&sc->rx_ring[q].ring_mtx); 1613 } 1614 1615 STATIC __inline int __unused 1616 mvneta_tx_trylockq(struct mvneta_softc *sc, int q) 1617 { 1618 1619 DASSERT(q >= 0); 1620 DASSERT(q < MVNETA_TX_QNUM_MAX); 1621 return (mtx_trylock(&sc->tx_ring[q].ring_mtx)); 1622 } 1623 1624 STATIC __inline void 1625 mvneta_tx_lockq(struct mvneta_softc *sc, int q) 1626 { 1627 1628 DASSERT(q >= 0); 1629 DASSERT(q < MVNETA_TX_QNUM_MAX); 1630 mtx_lock(&sc->tx_ring[q].ring_mtx); 1631 } 1632 1633 STATIC __inline void 1634 mvneta_tx_unlockq(struct mvneta_softc *sc, int q) 1635 { 1636 1637 DASSERT(q >= 0); 1638 DASSERT(q < MVNETA_TX_QNUM_MAX); 1639 mtx_unlock(&sc->tx_ring[q].ring_mtx); 1640 } 1641 1642 /* 1643 * Interrupt Handlers 1644 */ 1645 STATIC void 1646 mvneta_disable_intr(struct mvneta_softc *sc) 1647 { 1648 1649 MVNETA_WRITE(sc, MVNETA_EUIM, 0); 1650 MVNETA_WRITE(sc, MVNETA_EUIC, 0); 1651 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, 0); 1652 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 1653 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 1654 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 1655 MVNETA_WRITE(sc, MVNETA_PMIM, 0); 1656 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 1657 MVNETA_WRITE(sc, MVNETA_PIE, 0); 1658 } 1659 1660 STATIC void 1661 mvneta_enable_intr(struct mvneta_softc *sc) 1662 { 1663 uint32_t reg; 1664 1665 /* Enable Summary Bit to check all interrupt cause. */ 1666 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1667 reg |= MVNETA_PRXTXTI_PMISCICSUMMARY; 1668 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1669 1670 if (sc->use_inband_status) { 1671 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1672 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 1673 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE); 1674 } 1675 1676 /* Enable All Queue Interrupt */ 1677 reg = MVNETA_READ(sc, MVNETA_PIE); 1678 reg |= MVNETA_PIE_RXPKTINTRPTENB_MASK; 1679 reg |= MVNETA_PIE_TXPKTINTRPTENB_MASK; 1680 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1681 } 1682 1683 STATIC void 1684 mvneta_rxtxth_intr(void *arg) 1685 { 1686 struct mvneta_softc *sc; 1687 struct ifnet *ifp; 1688 uint32_t ic, queues; 1689 1690 sc = arg; 1691 ifp = sc->ifp; 1692 #ifdef MVNETA_KTR 1693 CTR1(KTR_SPARE2, "%s got RXTX_TH_Intr", ifp->if_xname); 1694 #endif 1695 ic = MVNETA_READ(sc, MVNETA_PRXTXTIC); 1696 if (ic == 0) 1697 return; 1698 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, ~ic); 1699 1700 /* Ack maintance interrupt first */ 1701 if (__predict_false((ic & MVNETA_PRXTXTI_PMISCICSUMMARY) && 1702 sc->use_inband_status)) { 1703 mvneta_sc_lock(sc); 1704 mvneta_misc_intr(sc); 1705 mvneta_sc_unlock(sc); 1706 } 1707 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 1708 return; 1709 /* RxTxTH interrupt */ 1710 queues = MVNETA_PRXTXTI_GET_RBICTAPQ(ic); 1711 if (__predict_true(queues)) { 1712 #ifdef MVNETA_KTR 1713 CTR1(KTR_SPARE2, "%s got PRXTXTIC: +RXEOF", ifp->if_xname); 1714 #endif 1715 /* At the moment the driver support only one RX queue. */ 1716 DASSERT(MVNETA_IS_QUEUE_SET(queues, 0)); 1717 mvneta_rx(sc, 0, 0); 1718 } 1719 } 1720 1721 STATIC int 1722 mvneta_misc_intr(struct mvneta_softc *sc) 1723 { 1724 uint32_t ic; 1725 int claimed = 0; 1726 1727 #ifdef MVNETA_KTR 1728 CTR1(KTR_SPARE2, "%s got MISC_INTR", sc->ifp->if_xname); 1729 #endif 1730 KASSERT_SC_MTX(sc); 1731 1732 for (;;) { 1733 ic = MVNETA_READ(sc, MVNETA_PMIC); 1734 ic &= MVNETA_READ(sc, MVNETA_PMIM); 1735 if (ic == 0) 1736 break; 1737 MVNETA_WRITE(sc, MVNETA_PMIC, ~ic); 1738 claimed = 1; 1739 1740 if (ic & (MVNETA_PMI_PHYSTATUSCHNG | 1741 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE)) 1742 mvneta_link_isr(sc); 1743 } 1744 return (claimed); 1745 } 1746 1747 STATIC void 1748 mvneta_tick(void *arg) 1749 { 1750 struct mvneta_softc *sc; 1751 struct mvneta_tx_ring *tx; 1752 struct mvneta_rx_ring *rx; 1753 int q; 1754 uint32_t fc_prev, fc_curr; 1755 1756 sc = arg; 1757 1758 /* 1759 * This is done before mib update to get the right stats 1760 * for this tick. 1761 */ 1762 mvneta_tx_drain(sc); 1763 1764 /* Extract previous flow-control frame received counter. */ 1765 fc_prev = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1766 /* Read mib registers (clear by read). */ 1767 mvneta_update_mib(sc); 1768 /* Extract current flow-control frame received counter. */ 1769 fc_curr = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1770 1771 1772 if (sc->phy_attached && sc->ifp->if_flags & IFF_UP) { 1773 mvneta_sc_lock(sc); 1774 mii_tick(sc->mii); 1775 1776 /* Adjust MAC settings */ 1777 mvneta_adjust_link(sc); 1778 mvneta_sc_unlock(sc); 1779 } 1780 1781 /* 1782 * We were unable to refill the rx queue and left the rx func, leaving 1783 * the ring without mbuf and no way to call the refill func. 1784 */ 1785 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1786 rx = MVNETA_RX_RING(sc, q); 1787 if (rx->needs_refill == TRUE) { 1788 mvneta_rx_lockq(sc, q); 1789 mvneta_rx_queue_refill(sc, q); 1790 mvneta_rx_unlockq(sc, q); 1791 } 1792 } 1793 1794 /* 1795 * Watchdog: 1796 * - check if queue is mark as hung. 1797 * - ignore hung status if we received some pause frame 1798 * as hardware may have paused packet transmit. 1799 */ 1800 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1801 /* 1802 * We should take queue lock, but as we only read 1803 * queue status we can do it without lock, we may 1804 * only missdetect queue status for one tick. 1805 */ 1806 tx = MVNETA_TX_RING(sc, q); 1807 1808 if (tx->queue_hung && (fc_curr - fc_prev) == 0) 1809 goto timeout; 1810 } 1811 1812 callout_schedule(&sc->tick_ch, hz); 1813 return; 1814 1815 timeout: 1816 if_printf(sc->ifp, "watchdog timeout\n"); 1817 1818 mvneta_sc_lock(sc); 1819 sc->counter_watchdog++; 1820 sc->counter_watchdog_mib++; 1821 /* Trigger reinitialize sequence. */ 1822 mvneta_stop_locked(sc); 1823 mvneta_init_locked(sc); 1824 mvneta_sc_unlock(sc); 1825 } 1826 1827 STATIC void 1828 mvneta_qflush(struct ifnet *ifp) 1829 { 1830 #ifdef MVNETA_MULTIQUEUE 1831 struct mvneta_softc *sc; 1832 struct mvneta_tx_ring *tx; 1833 struct mbuf *m; 1834 size_t q; 1835 1836 sc = ifp->if_softc; 1837 1838 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1839 tx = MVNETA_TX_RING(sc, q); 1840 mvneta_tx_lockq(sc, q); 1841 while ((m = buf_ring_dequeue_sc(tx->br)) != NULL) 1842 m_freem(m); 1843 mvneta_tx_unlockq(sc, q); 1844 } 1845 #endif 1846 if_qflush(ifp); 1847 } 1848 1849 STATIC void 1850 mvneta_tx_task(void *arg, int pending) 1851 { 1852 struct mvneta_softc *sc; 1853 struct mvneta_tx_ring *tx; 1854 struct ifnet *ifp; 1855 int error; 1856 1857 tx = arg; 1858 ifp = tx->ifp; 1859 sc = ifp->if_softc; 1860 1861 mvneta_tx_lockq(sc, tx->qidx); 1862 error = mvneta_xmit_locked(sc, tx->qidx); 1863 mvneta_tx_unlockq(sc, tx->qidx); 1864 1865 /* Try again */ 1866 if (__predict_false(error != 0 && error != ENETDOWN)) { 1867 pause("mvneta_tx_task_sleep", 1); 1868 taskqueue_enqueue(tx->taskq, &tx->task); 1869 } 1870 } 1871 1872 STATIC int 1873 mvneta_xmitfast_locked(struct mvneta_softc *sc, int q, struct mbuf **m) 1874 { 1875 struct mvneta_tx_ring *tx; 1876 struct ifnet *ifp; 1877 int error; 1878 1879 KASSERT_TX_MTX(sc, q); 1880 tx = MVNETA_TX_RING(sc, q); 1881 error = 0; 1882 1883 ifp = sc->ifp; 1884 1885 /* Dont enqueue packet if the queue is disabled. */ 1886 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) { 1887 m_freem(*m); 1888 *m = NULL; 1889 return (ENETDOWN); 1890 } 1891 1892 /* Reclaim mbuf if above threshold. */ 1893 if (__predict_true(tx->used > MVNETA_TX_RECLAIM_COUNT)) 1894 mvneta_tx_queue_complete(sc, q); 1895 1896 /* Do not call transmit path if queue is already too full. */ 1897 if (__predict_false(tx->used > 1898 MVNETA_TX_RING_CNT - MVNETA_TX_SEGLIMIT)) 1899 return (ENOBUFS); 1900 1901 error = mvneta_tx_queue(sc, m, q); 1902 if (__predict_false(error != 0)) 1903 return (error); 1904 1905 /* Send a copy of the frame to the BPF listener */ 1906 ETHER_BPF_MTAP(ifp, *m); 1907 1908 /* Set watchdog on */ 1909 tx->watchdog_time = ticks; 1910 tx->queue_status = MVNETA_QUEUE_WORKING; 1911 1912 return (error); 1913 } 1914 1915 #ifdef MVNETA_MULTIQUEUE 1916 STATIC int 1917 mvneta_transmit(struct ifnet *ifp, struct mbuf *m) 1918 { 1919 struct mvneta_softc *sc; 1920 struct mvneta_tx_ring *tx; 1921 int error; 1922 int q; 1923 1924 sc = ifp->if_softc; 1925 1926 /* Use default queue if there is no flow id as thread can migrate. */ 1927 if (__predict_true(M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)) 1928 q = m->m_pkthdr.flowid % MVNETA_TX_QNUM_MAX; 1929 else 1930 q = 0; 1931 1932 tx = MVNETA_TX_RING(sc, q); 1933 1934 /* If buf_ring is full start transmit immediatly. */ 1935 if (buf_ring_full(tx->br)) { 1936 mvneta_tx_lockq(sc, q); 1937 mvneta_xmit_locked(sc, q); 1938 mvneta_tx_unlockq(sc, q); 1939 } 1940 1941 /* 1942 * If the buf_ring is empty we will not reorder packets. 1943 * If the lock is available transmit without using buf_ring. 1944 */ 1945 if (buf_ring_empty(tx->br) && mvneta_tx_trylockq(sc, q) != 0) { 1946 error = mvneta_xmitfast_locked(sc, q, &m); 1947 mvneta_tx_unlockq(sc, q); 1948 if (__predict_true(error == 0)) 1949 return (0); 1950 1951 /* Transmit can fail in fastpath. */ 1952 if (__predict_false(m == NULL)) 1953 return (error); 1954 } 1955 1956 /* Enqueue then schedule taskqueue. */ 1957 error = drbr_enqueue(ifp, tx->br, m); 1958 if (__predict_false(error != 0)) 1959 return (error); 1960 1961 taskqueue_enqueue(tx->taskq, &tx->task); 1962 return (0); 1963 } 1964 1965 STATIC int 1966 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 1967 { 1968 struct ifnet *ifp; 1969 struct mvneta_tx_ring *tx; 1970 struct mbuf *m; 1971 int error; 1972 1973 KASSERT_TX_MTX(sc, q); 1974 ifp = sc->ifp; 1975 tx = MVNETA_TX_RING(sc, q); 1976 error = 0; 1977 1978 while ((m = drbr_peek(ifp, tx->br)) != NULL) { 1979 error = mvneta_xmitfast_locked(sc, q, &m); 1980 if (__predict_false(error != 0)) { 1981 if (m != NULL) 1982 drbr_putback(ifp, tx->br, m); 1983 else 1984 drbr_advance(ifp, tx->br); 1985 break; 1986 } 1987 drbr_advance(ifp, tx->br); 1988 } 1989 1990 return (error); 1991 } 1992 #else /* !MVNETA_MULTIQUEUE */ 1993 STATIC void 1994 mvneta_start(struct ifnet *ifp) 1995 { 1996 struct mvneta_softc *sc; 1997 struct mvneta_tx_ring *tx; 1998 int error; 1999 2000 sc = ifp->if_softc; 2001 tx = MVNETA_TX_RING(sc, 0); 2002 2003 mvneta_tx_lockq(sc, 0); 2004 error = mvneta_xmit_locked(sc, 0); 2005 mvneta_tx_unlockq(sc, 0); 2006 /* Handle retransmit in the background taskq. */ 2007 if (__predict_false(error != 0 && error != ENETDOWN)) 2008 taskqueue_enqueue(tx->taskq, &tx->task); 2009 } 2010 2011 STATIC int 2012 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 2013 { 2014 struct ifnet *ifp; 2015 struct mvneta_tx_ring *tx; 2016 struct mbuf *m; 2017 int error; 2018 2019 KASSERT_TX_MTX(sc, q); 2020 ifp = sc->ifp; 2021 tx = MVNETA_TX_RING(sc, 0); 2022 error = 0; 2023 2024 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2025 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 2026 if (m == NULL) 2027 break; 2028 2029 error = mvneta_xmitfast_locked(sc, q, &m); 2030 if (__predict_false(error != 0)) { 2031 if (m != NULL) 2032 IFQ_DRV_PREPEND(&ifp->if_snd, m); 2033 break; 2034 } 2035 } 2036 2037 return (error); 2038 } 2039 #endif 2040 2041 STATIC int 2042 mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2043 { 2044 struct mvneta_softc *sc; 2045 struct mvneta_rx_ring *rx; 2046 struct ifreq *ifr; 2047 int error, mask; 2048 uint32_t flags; 2049 int q; 2050 2051 error = 0; 2052 sc = ifp->if_softc; 2053 ifr = (struct ifreq *)data; 2054 switch (cmd) { 2055 case SIOCSIFFLAGS: 2056 mvneta_sc_lock(sc); 2057 if (ifp->if_flags & IFF_UP) { 2058 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2059 flags = ifp->if_flags ^ sc->mvneta_if_flags; 2060 2061 if (flags != 0) 2062 sc->mvneta_if_flags = ifp->if_flags; 2063 2064 if ((flags & IFF_PROMISC) != 0) 2065 mvneta_filter_setup(sc); 2066 } else { 2067 mvneta_init_locked(sc); 2068 sc->mvneta_if_flags = ifp->if_flags; 2069 if (sc->phy_attached) 2070 mii_mediachg(sc->mii); 2071 mvneta_sc_unlock(sc); 2072 break; 2073 } 2074 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2075 mvneta_stop_locked(sc); 2076 2077 sc->mvneta_if_flags = ifp->if_flags; 2078 mvneta_sc_unlock(sc); 2079 break; 2080 case SIOCSIFCAP: 2081 if (ifp->if_mtu > sc->tx_csum_limit && 2082 ifr->ifr_reqcap & IFCAP_TXCSUM) 2083 ifr->ifr_reqcap &= ~IFCAP_TXCSUM; 2084 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2085 if (mask & IFCAP_HWCSUM) { 2086 ifp->if_capenable &= ~IFCAP_HWCSUM; 2087 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 2088 if (ifp->if_capenable & IFCAP_TXCSUM) 2089 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2090 CSUM_UDP; 2091 else 2092 ifp->if_hwassist = 0; 2093 } 2094 if (mask & IFCAP_LRO) { 2095 mvneta_sc_lock(sc); 2096 ifp->if_capenable ^= IFCAP_LRO; 2097 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2098 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2099 rx = MVNETA_RX_RING(sc, q); 2100 rx->lro_enabled = !rx->lro_enabled; 2101 } 2102 } 2103 mvneta_sc_unlock(sc); 2104 } 2105 VLAN_CAPABILITIES(ifp); 2106 break; 2107 case SIOCSIFMEDIA: 2108 if ((IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T || 2109 IFM_SUBTYPE(ifr->ifr_media) == IFM_2500_T) && 2110 (ifr->ifr_media & IFM_FDX) == 0) { 2111 device_printf(sc->dev, 2112 "%s half-duplex unsupported\n", 2113 IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T ? 2114 "1000Base-T" : 2115 "2500Base-T"); 2116 error = EINVAL; 2117 break; 2118 } 2119 case SIOCGIFMEDIA: /* FALLTHROUGH */ 2120 case SIOCGIFXMEDIA: 2121 if (!sc->phy_attached) 2122 error = ifmedia_ioctl(ifp, ifr, &sc->mvneta_ifmedia, 2123 cmd); 2124 else 2125 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, 2126 cmd); 2127 break; 2128 case SIOCSIFMTU: 2129 if (ifr->ifr_mtu < 68 || ifr->ifr_mtu > MVNETA_MAX_FRAME - 2130 MVNETA_ETHER_SIZE) { 2131 error = EINVAL; 2132 } else { 2133 ifp->if_mtu = ifr->ifr_mtu; 2134 mvneta_sc_lock(sc); 2135 if (ifp->if_mtu + MVNETA_ETHER_SIZE <= MCLBYTES) { 2136 sc->rx_frame_size = MCLBYTES; 2137 } else { 2138 sc->rx_frame_size = MJUM9BYTES; 2139 } 2140 if (ifp->if_mtu > sc->tx_csum_limit) { 2141 ifp->if_capenable &= ~IFCAP_TXCSUM; 2142 ifp->if_hwassist = 0; 2143 } else { 2144 ifp->if_capenable |= IFCAP_TXCSUM; 2145 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2146 CSUM_UDP; 2147 } 2148 /* 2149 * Reinitialize RX queues. 2150 * We need to update RX descriptor size. 2151 */ 2152 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2153 mvneta_stop_locked(sc); 2154 2155 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2156 mvneta_rx_lockq(sc, q); 2157 if (mvneta_rx_queue_init(ifp, q) != 0) { 2158 device_printf(sc->dev, 2159 "initialization failed:" 2160 " cannot initialize queue\n"); 2161 mvneta_rx_unlockq(sc, q); 2162 error = ENOBUFS; 2163 break; 2164 } 2165 mvneta_rx_unlockq(sc, q); 2166 } 2167 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2168 mvneta_init_locked(sc); 2169 2170 mvneta_sc_unlock(sc); 2171 } 2172 break; 2173 2174 default: 2175 error = ether_ioctl(ifp, cmd, data); 2176 break; 2177 } 2178 2179 return (error); 2180 } 2181 2182 STATIC void 2183 mvneta_init_locked(void *arg) 2184 { 2185 struct mvneta_softc *sc; 2186 struct ifnet *ifp; 2187 uint32_t reg; 2188 int q, cpu; 2189 2190 sc = arg; 2191 ifp = sc->ifp; 2192 2193 if (!device_is_attached(sc->dev) || 2194 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2195 return; 2196 2197 mvneta_disable_intr(sc); 2198 callout_stop(&sc->tick_ch); 2199 2200 /* Get the latest mac address */ 2201 bcopy(IF_LLADDR(ifp), sc->enaddr, ETHER_ADDR_LEN); 2202 mvneta_set_mac_address(sc, sc->enaddr); 2203 mvneta_filter_setup(sc); 2204 2205 /* Start DMA Engine */ 2206 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 2207 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 2208 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 2209 2210 /* Enable port */ 2211 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2212 reg |= MVNETA_PMACC0_PORTEN; 2213 reg &= ~MVNETA_PMACC0_FRAMESIZELIMIT_MASK; 2214 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 2215 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2216 2217 /* Allow access to each TXQ/RXQ from both CPU's */ 2218 for (cpu = 0; cpu < mp_ncpus; ++cpu) 2219 MVNETA_WRITE(sc, MVNETA_PCP2Q(cpu), 2220 MVNETA_PCP2Q_TXQEN_MASK | MVNETA_PCP2Q_RXQEN_MASK); 2221 2222 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2223 mvneta_rx_lockq(sc, q); 2224 mvneta_rx_queue_refill(sc, q); 2225 mvneta_rx_unlockq(sc, q); 2226 } 2227 2228 if (!sc->phy_attached) 2229 mvneta_linkup(sc); 2230 2231 /* Enable interrupt */ 2232 mvneta_enable_intr(sc); 2233 2234 /* Set Counter */ 2235 callout_schedule(&sc->tick_ch, hz); 2236 2237 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2238 } 2239 2240 STATIC void 2241 mvneta_init(void *arg) 2242 { 2243 struct mvneta_softc *sc; 2244 2245 sc = arg; 2246 mvneta_sc_lock(sc); 2247 mvneta_init_locked(sc); 2248 if (sc->phy_attached) 2249 mii_mediachg(sc->mii); 2250 mvneta_sc_unlock(sc); 2251 } 2252 2253 /* ARGSUSED */ 2254 STATIC void 2255 mvneta_stop_locked(struct mvneta_softc *sc) 2256 { 2257 struct ifnet *ifp; 2258 struct mvneta_rx_ring *rx; 2259 struct mvneta_tx_ring *tx; 2260 uint32_t reg; 2261 int q; 2262 2263 ifp = sc->ifp; 2264 if (ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2265 return; 2266 2267 mvneta_disable_intr(sc); 2268 2269 callout_stop(&sc->tick_ch); 2270 2271 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2272 2273 /* Link down */ 2274 if (sc->linkup == TRUE) 2275 mvneta_linkdown(sc); 2276 2277 /* Reset the MAC Port Enable bit */ 2278 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2279 reg &= ~MVNETA_PMACC0_PORTEN; 2280 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2281 2282 /* Disable each of queue */ 2283 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2284 rx = MVNETA_RX_RING(sc, q); 2285 2286 mvneta_rx_lockq(sc, q); 2287 mvneta_ring_flush_rx_queue(sc, q); 2288 mvneta_rx_unlockq(sc, q); 2289 } 2290 2291 /* 2292 * Hold Reset state of DMA Engine 2293 * (must write 0x0 to restart it) 2294 */ 2295 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 2296 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 2297 2298 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2299 tx = MVNETA_TX_RING(sc, q); 2300 2301 mvneta_tx_lockq(sc, q); 2302 mvneta_ring_flush_tx_queue(sc, q); 2303 mvneta_tx_unlockq(sc, q); 2304 } 2305 } 2306 2307 STATIC void 2308 mvneta_stop(struct mvneta_softc *sc) 2309 { 2310 2311 mvneta_sc_lock(sc); 2312 mvneta_stop_locked(sc); 2313 mvneta_sc_unlock(sc); 2314 } 2315 2316 STATIC int 2317 mvneta_mediachange(struct ifnet *ifp) 2318 { 2319 struct mvneta_softc *sc; 2320 2321 sc = ifp->if_softc; 2322 2323 if (!sc->phy_attached && !sc->use_inband_status) { 2324 /* We shouldn't be here */ 2325 if_printf(ifp, "Cannot change media in fixed-link mode!\n"); 2326 return (0); 2327 } 2328 2329 if (sc->use_inband_status) { 2330 mvneta_update_media(sc, sc->mvneta_ifmedia.ifm_media); 2331 return (0); 2332 } 2333 2334 mvneta_sc_lock(sc); 2335 2336 /* Update PHY */ 2337 mii_mediachg(sc->mii); 2338 2339 mvneta_sc_unlock(sc); 2340 2341 return (0); 2342 } 2343 2344 STATIC void 2345 mvneta_get_media(struct mvneta_softc *sc, struct ifmediareq *ifmr) 2346 { 2347 uint32_t psr; 2348 2349 psr = MVNETA_READ(sc, MVNETA_PSR); 2350 2351 /* Speed */ 2352 if (psr & MVNETA_PSR_GMIISPEED) 2353 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_1000_T); 2354 else if (psr & MVNETA_PSR_MIISPEED) 2355 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_100_TX); 2356 else if (psr & MVNETA_PSR_LINKUP) 2357 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_10_T); 2358 2359 /* Duplex */ 2360 if (psr & MVNETA_PSR_FULLDX) 2361 ifmr->ifm_active |= IFM_FDX; 2362 2363 /* Link */ 2364 ifmr->ifm_status = IFM_AVALID; 2365 if (psr & MVNETA_PSR_LINKUP) 2366 ifmr->ifm_status |= IFM_ACTIVE; 2367 } 2368 2369 STATIC void 2370 mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2371 { 2372 struct mvneta_softc *sc; 2373 struct mii_data *mii; 2374 2375 sc = ifp->if_softc; 2376 2377 if (!sc->phy_attached && !sc->use_inband_status) { 2378 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 2379 return; 2380 } 2381 2382 mvneta_sc_lock(sc); 2383 2384 if (sc->use_inband_status) { 2385 mvneta_get_media(sc, ifmr); 2386 mvneta_sc_unlock(sc); 2387 return; 2388 } 2389 2390 mii = sc->mii; 2391 mii_pollstat(mii); 2392 2393 ifmr->ifm_active = mii->mii_media_active; 2394 ifmr->ifm_status = mii->mii_media_status; 2395 2396 mvneta_sc_unlock(sc); 2397 } 2398 2399 /* 2400 * Link State Notify 2401 */ 2402 STATIC void 2403 mvneta_update_autoneg(struct mvneta_softc *sc, int enable) 2404 { 2405 int reg; 2406 2407 if (enable) { 2408 reg = MVNETA_READ(sc, MVNETA_PANC); 2409 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2410 MVNETA_PANC_ANFCEN); 2411 reg |= MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2412 MVNETA_PANC_INBANDANEN; 2413 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2414 2415 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2416 reg |= MVNETA_PMACC2_INBANDANMODE; 2417 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2418 2419 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2420 reg |= MVNETA_PSOMSCD_ENABLE; 2421 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2422 } else { 2423 reg = MVNETA_READ(sc, MVNETA_PANC); 2424 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2425 MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2426 MVNETA_PANC_INBANDANEN); 2427 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2428 2429 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2430 reg &= ~MVNETA_PMACC2_INBANDANMODE; 2431 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2432 2433 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2434 reg &= ~MVNETA_PSOMSCD_ENABLE; 2435 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2436 } 2437 } 2438 2439 STATIC int 2440 mvneta_update_media(struct mvneta_softc *sc, int media) 2441 { 2442 int reg, err; 2443 boolean_t running; 2444 2445 err = 0; 2446 2447 mvneta_sc_lock(sc); 2448 2449 mvneta_linkreset(sc); 2450 2451 running = (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2452 if (running) 2453 mvneta_stop_locked(sc); 2454 2455 sc->autoneg = (IFM_SUBTYPE(media) == IFM_AUTO); 2456 2457 if (sc->use_inband_status) 2458 mvneta_update_autoneg(sc, IFM_SUBTYPE(media) == IFM_AUTO); 2459 2460 mvneta_update_eee(sc); 2461 mvneta_update_fc(sc); 2462 2463 if (IFM_SUBTYPE(media) != IFM_AUTO) { 2464 reg = MVNETA_READ(sc, MVNETA_PANC); 2465 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2466 MVNETA_PANC_SETMIISPEED | 2467 MVNETA_PANC_SETFULLDX); 2468 if (IFM_SUBTYPE(media) == IFM_1000_T || 2469 IFM_SUBTYPE(media) == IFM_2500_T) { 2470 if ((media & IFM_FDX) == 0) { 2471 device_printf(sc->dev, 2472 "%s half-duplex unsupported\n", 2473 IFM_SUBTYPE(media) == IFM_1000_T ? 2474 "1000Base-T" : 2475 "2500Base-T"); 2476 err = EINVAL; 2477 goto out; 2478 } 2479 reg |= MVNETA_PANC_SETGMIISPEED; 2480 } else if (IFM_SUBTYPE(media) == IFM_100_TX) 2481 reg |= MVNETA_PANC_SETMIISPEED; 2482 2483 if (media & IFM_FDX) 2484 reg |= MVNETA_PANC_SETFULLDX; 2485 2486 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2487 } 2488 out: 2489 if (running) 2490 mvneta_init_locked(sc); 2491 mvneta_sc_unlock(sc); 2492 return (err); 2493 } 2494 2495 STATIC void 2496 mvneta_adjust_link(struct mvneta_softc *sc) 2497 { 2498 boolean_t phy_linkup; 2499 int reg; 2500 2501 /* Update eee/fc */ 2502 mvneta_update_eee(sc); 2503 mvneta_update_fc(sc); 2504 2505 /* Check for link change */ 2506 phy_linkup = (sc->mii->mii_media_status & 2507 (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE); 2508 2509 if (sc->linkup != phy_linkup) 2510 mvneta_linkupdate(sc, phy_linkup); 2511 2512 /* Don't update media on disabled link */ 2513 if (!phy_linkup) 2514 return; 2515 2516 /* Check for media type change */ 2517 if (sc->mvneta_media != sc->mii->mii_media_active) { 2518 sc->mvneta_media = sc->mii->mii_media_active; 2519 2520 reg = MVNETA_READ(sc, MVNETA_PANC); 2521 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2522 MVNETA_PANC_SETMIISPEED | 2523 MVNETA_PANC_SETFULLDX); 2524 if (IFM_SUBTYPE(sc->mvneta_media) == IFM_1000_T || 2525 IFM_SUBTYPE(sc->mvneta_media) == IFM_2500_T) { 2526 reg |= MVNETA_PANC_SETGMIISPEED; 2527 } else if (IFM_SUBTYPE(sc->mvneta_media) == IFM_100_TX) 2528 reg |= MVNETA_PANC_SETMIISPEED; 2529 2530 if (sc->mvneta_media & IFM_FDX) 2531 reg |= MVNETA_PANC_SETFULLDX; 2532 2533 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2534 } 2535 } 2536 2537 STATIC void 2538 mvneta_link_isr(struct mvneta_softc *sc) 2539 { 2540 int linkup; 2541 2542 KASSERT_SC_MTX(sc); 2543 2544 linkup = MVNETA_IS_LINKUP(sc) ? TRUE : FALSE; 2545 if (sc->linkup == linkup) 2546 return; 2547 2548 if (linkup == TRUE) 2549 mvneta_linkup(sc); 2550 else 2551 mvneta_linkdown(sc); 2552 2553 #ifdef DEBUG 2554 device_printf(sc->dev, 2555 "%s: link %s\n", sc->ifp->if_xname, linkup ? "up" : "down"); 2556 #endif 2557 } 2558 2559 STATIC void 2560 mvneta_linkupdate(struct mvneta_softc *sc, boolean_t linkup) 2561 { 2562 2563 KASSERT_SC_MTX(sc); 2564 2565 if (linkup == TRUE) 2566 mvneta_linkup(sc); 2567 else 2568 mvneta_linkdown(sc); 2569 2570 #ifdef DEBUG 2571 device_printf(sc->dev, 2572 "%s: link %s\n", sc->ifp->if_xname, linkup ? "up" : "down"); 2573 #endif 2574 } 2575 2576 STATIC void 2577 mvneta_update_eee(struct mvneta_softc *sc) 2578 { 2579 uint32_t reg; 2580 2581 KASSERT_SC_MTX(sc); 2582 2583 /* set EEE parameters */ 2584 reg = MVNETA_READ(sc, MVNETA_LPIC1); 2585 if (sc->cf_lpi) 2586 reg |= MVNETA_LPIC1_LPIRE; 2587 else 2588 reg &= ~MVNETA_LPIC1_LPIRE; 2589 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 2590 } 2591 2592 STATIC void 2593 mvneta_update_fc(struct mvneta_softc *sc) 2594 { 2595 uint32_t reg; 2596 2597 KASSERT_SC_MTX(sc); 2598 2599 reg = MVNETA_READ(sc, MVNETA_PANC); 2600 if (sc->cf_fc) { 2601 /* Flow control negotiation */ 2602 reg |= MVNETA_PANC_PAUSEADV; 2603 reg |= MVNETA_PANC_ANFCEN; 2604 } else { 2605 /* Disable flow control negotiation */ 2606 reg &= ~MVNETA_PANC_PAUSEADV; 2607 reg &= ~MVNETA_PANC_ANFCEN; 2608 } 2609 2610 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2611 } 2612 2613 STATIC void 2614 mvneta_linkup(struct mvneta_softc *sc) 2615 { 2616 uint32_t reg; 2617 2618 KASSERT_SC_MTX(sc); 2619 2620 if (!sc->use_inband_status) { 2621 reg = MVNETA_READ(sc, MVNETA_PANC); 2622 reg |= MVNETA_PANC_FORCELINKPASS; 2623 reg &= ~MVNETA_PANC_FORCELINKFAIL; 2624 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2625 } 2626 2627 mvneta_qflush(sc->ifp); 2628 mvneta_portup(sc); 2629 sc->linkup = TRUE; 2630 if_link_state_change(sc->ifp, LINK_STATE_UP); 2631 } 2632 2633 STATIC void 2634 mvneta_linkdown(struct mvneta_softc *sc) 2635 { 2636 uint32_t reg; 2637 2638 KASSERT_SC_MTX(sc); 2639 2640 if (!sc->use_inband_status) { 2641 reg = MVNETA_READ(sc, MVNETA_PANC); 2642 reg &= ~MVNETA_PANC_FORCELINKPASS; 2643 reg |= MVNETA_PANC_FORCELINKFAIL; 2644 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2645 } 2646 2647 mvneta_portdown(sc); 2648 mvneta_qflush(sc->ifp); 2649 sc->linkup = FALSE; 2650 if_link_state_change(sc->ifp, LINK_STATE_DOWN); 2651 } 2652 2653 STATIC void 2654 mvneta_linkreset(struct mvneta_softc *sc) 2655 { 2656 struct mii_softc *mii; 2657 2658 if (sc->phy_attached) { 2659 /* Force reset PHY */ 2660 mii = LIST_FIRST(&sc->mii->mii_phys); 2661 if (mii) 2662 mii_phy_reset(mii); 2663 } 2664 } 2665 2666 /* 2667 * Tx Subroutines 2668 */ 2669 STATIC int 2670 mvneta_tx_queue(struct mvneta_softc *sc, struct mbuf **mbufp, int q) 2671 { 2672 struct ifnet *ifp; 2673 bus_dma_segment_t txsegs[MVNETA_TX_SEGLIMIT]; 2674 struct mbuf *mtmp, *mbuf; 2675 struct mvneta_tx_ring *tx; 2676 struct mvneta_buf *txbuf; 2677 struct mvneta_tx_desc *t; 2678 uint32_t ptxsu; 2679 int start, used, error, i, txnsegs; 2680 2681 mbuf = *mbufp; 2682 tx = MVNETA_TX_RING(sc, q); 2683 DASSERT(tx->used >= 0); 2684 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2685 t = NULL; 2686 ifp = sc->ifp; 2687 2688 if (__predict_false(mbuf->m_flags & M_VLANTAG)) { 2689 mbuf = ether_vlanencap(mbuf, mbuf->m_pkthdr.ether_vtag); 2690 if (mbuf == NULL) { 2691 tx->drv_error++; 2692 *mbufp = NULL; 2693 return (ENOBUFS); 2694 } 2695 mbuf->m_flags &= ~M_VLANTAG; 2696 *mbufp = mbuf; 2697 } 2698 2699 if (__predict_false(mbuf->m_next != NULL && 2700 (mbuf->m_pkthdr.csum_flags & 2701 (CSUM_IP | CSUM_TCP | CSUM_UDP)) != 0)) { 2702 if (M_WRITABLE(mbuf) == 0) { 2703 mtmp = m_dup(mbuf, M_NOWAIT); 2704 m_freem(mbuf); 2705 if (mtmp == NULL) { 2706 tx->drv_error++; 2707 *mbufp = NULL; 2708 return (ENOBUFS); 2709 } 2710 *mbufp = mbuf = mtmp; 2711 } 2712 } 2713 2714 /* load mbuf using dmamap of 1st descriptor */ 2715 txbuf = &tx->txbuf[tx->cpu]; 2716 error = bus_dmamap_load_mbuf_sg(sc->txmbuf_dtag, 2717 txbuf->dmap, mbuf, txsegs, &txnsegs, 2718 BUS_DMA_NOWAIT); 2719 if (__predict_false(error != 0)) { 2720 #ifdef MVNETA_KTR 2721 CTR3(KTR_SPARE2, "%s:%u bus_dmamap_load_mbuf_sg error=%d", ifp->if_xname, q, error); 2722 #endif 2723 /* This is the only recoverable error (except EFBIG). */ 2724 if (error != ENOMEM) { 2725 tx->drv_error++; 2726 m_freem(mbuf); 2727 *mbufp = NULL; 2728 return (ENOBUFS); 2729 } 2730 return (error); 2731 } 2732 2733 if (__predict_false(txnsegs <= 0 2734 || (txnsegs + tx->used) > MVNETA_TX_RING_CNT)) { 2735 /* we have no enough descriptors or mbuf is broken */ 2736 #ifdef MVNETA_KTR 2737 CTR3(KTR_SPARE2, "%s:%u not enough descriptors txnsegs=%d", 2738 ifp->if_xname, q, txnsegs); 2739 #endif 2740 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2741 return (ENOBUFS); 2742 } 2743 DASSERT(txbuf->m == NULL); 2744 2745 /* remember mbuf using 1st descriptor */ 2746 txbuf->m = mbuf; 2747 bus_dmamap_sync(sc->txmbuf_dtag, txbuf->dmap, 2748 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2749 2750 /* load to tx descriptors */ 2751 start = tx->cpu; 2752 used = 0; 2753 for (i = 0; i < txnsegs; i++) { 2754 t = &tx->desc[tx->cpu]; 2755 t->command = 0; 2756 t->l4ichk = 0; 2757 t->flags = 0; 2758 if (__predict_true(i == 0)) { 2759 /* 1st descriptor */ 2760 t->command |= MVNETA_TX_CMD_W_PACKET_OFFSET(0); 2761 t->command |= MVNETA_TX_CMD_F; 2762 mvneta_tx_set_csumflag(ifp, t, mbuf); 2763 } 2764 t->bufptr_pa = txsegs[i].ds_addr; 2765 t->bytecnt = txsegs[i].ds_len; 2766 tx->cpu = tx_counter_adv(tx->cpu, 1); 2767 2768 tx->used++; 2769 used++; 2770 } 2771 /* t is last descriptor here */ 2772 DASSERT(t != NULL); 2773 t->command |= MVNETA_TX_CMD_L|MVNETA_TX_CMD_PADDING; 2774 2775 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2776 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2777 2778 while (__predict_false(used > 255)) { 2779 ptxsu = MVNETA_PTXSU_NOWD(255); 2780 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2781 used -= 255; 2782 } 2783 if (__predict_true(used > 0)) { 2784 ptxsu = MVNETA_PTXSU_NOWD(used); 2785 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2786 } 2787 return (0); 2788 } 2789 2790 STATIC void 2791 mvneta_tx_set_csumflag(struct ifnet *ifp, 2792 struct mvneta_tx_desc *t, struct mbuf *m) 2793 { 2794 struct ether_header *eh; 2795 struct ether_vlan_header *evh; 2796 int csum_flags; 2797 uint32_t iphl, ipoff; 2798 struct ip *ip; 2799 2800 iphl = ipoff = 0; 2801 csum_flags = ifp->if_hwassist & m->m_pkthdr.csum_flags; 2802 eh = mtod(m, struct ether_header *); 2803 2804 switch (ntohs(eh->ether_type)) { 2805 case ETHERTYPE_IP: 2806 ipoff = ETHER_HDR_LEN; 2807 break; 2808 case ETHERTYPE_VLAN: 2809 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2810 evh = mtod(m, struct ether_vlan_header *); 2811 if (ntohs(evh->evl_proto) == ETHERTYPE_VLAN) 2812 ipoff += ETHER_VLAN_ENCAP_LEN; 2813 break; 2814 default: 2815 csum_flags = 0; 2816 } 2817 2818 if (__predict_true(csum_flags & (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP))) { 2819 ip = (struct ip *)(m->m_data + ipoff); 2820 iphl = ip->ip_hl<<2; 2821 t->command |= MVNETA_TX_CMD_L3_IP4; 2822 } else { 2823 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2824 return; 2825 } 2826 2827 2828 /* L3 */ 2829 if (csum_flags & CSUM_IP) { 2830 t->command |= MVNETA_TX_CMD_IP4_CHECKSUM; 2831 } 2832 2833 /* L4 */ 2834 if (csum_flags & CSUM_IP_TCP) { 2835 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2836 t->command |= MVNETA_TX_CMD_L4_TCP; 2837 } else if (csum_flags & CSUM_IP_UDP) { 2838 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2839 t->command |= MVNETA_TX_CMD_L4_UDP; 2840 } else 2841 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2842 2843 t->l4ichk = 0; 2844 t->command |= MVNETA_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2845 t->command |= MVNETA_TX_CMD_L3_OFFSET(ipoff); 2846 } 2847 2848 STATIC void 2849 mvneta_tx_queue_complete(struct mvneta_softc *sc, int q) 2850 { 2851 struct mvneta_tx_ring *tx; 2852 struct mvneta_buf *txbuf; 2853 struct mvneta_tx_desc *t; 2854 uint32_t ptxs, ptxsu, ndesc; 2855 int i; 2856 2857 KASSERT_TX_MTX(sc, q); 2858 2859 tx = MVNETA_TX_RING(sc, q); 2860 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) 2861 return; 2862 2863 ptxs = MVNETA_READ(sc, MVNETA_PTXS(q)); 2864 ndesc = MVNETA_PTXS_GET_TBC(ptxs); 2865 2866 if (__predict_false(ndesc == 0)) { 2867 if (tx->used == 0) 2868 tx->queue_status = MVNETA_QUEUE_IDLE; 2869 else if (tx->queue_status == MVNETA_QUEUE_WORKING && 2870 ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG)) 2871 tx->queue_hung = TRUE; 2872 return; 2873 } 2874 2875 #ifdef MVNETA_KTR 2876 CTR3(KTR_SPARE2, "%s:%u tx_complete begin ndesc=%u", 2877 sc->ifp->if_xname, q, ndesc); 2878 #endif 2879 2880 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2881 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2882 2883 for (i = 0; i < ndesc; i++) { 2884 t = &tx->desc[tx->dma]; 2885 #ifdef MVNETA_KTR 2886 if (t->flags & MVNETA_TX_F_ES) 2887 CTR3(KTR_SPARE2, "%s tx error queue %d desc %d", 2888 sc->ifp->if_xname, q, tx->dma); 2889 #endif 2890 txbuf = &tx->txbuf[tx->dma]; 2891 if (__predict_true(txbuf->m != NULL)) { 2892 DASSERT((t->command & MVNETA_TX_CMD_F) != 0); 2893 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2894 m_freem(txbuf->m); 2895 txbuf->m = NULL; 2896 } 2897 else 2898 DASSERT((t->flags & MVNETA_TX_CMD_F) == 0); 2899 tx->dma = tx_counter_adv(tx->dma, 1); 2900 tx->used--; 2901 } 2902 DASSERT(tx->used >= 0); 2903 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2904 while (__predict_false(ndesc > 255)) { 2905 ptxsu = MVNETA_PTXSU_NORB(255); 2906 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2907 ndesc -= 255; 2908 } 2909 if (__predict_true(ndesc > 0)) { 2910 ptxsu = MVNETA_PTXSU_NORB(ndesc); 2911 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2912 } 2913 #ifdef MVNETA_KTR 2914 CTR5(KTR_SPARE2, "%s:%u tx_complete tx_cpu=%d tx_dma=%d tx_used=%d", 2915 sc->ifp->if_xname, q, tx->cpu, tx->dma, tx->used); 2916 #endif 2917 2918 tx->watchdog_time = ticks; 2919 2920 if (tx->used == 0) 2921 tx->queue_status = MVNETA_QUEUE_IDLE; 2922 } 2923 2924 /* 2925 * Do a final TX complete when TX is idle. 2926 */ 2927 STATIC void 2928 mvneta_tx_drain(struct mvneta_softc *sc) 2929 { 2930 struct mvneta_tx_ring *tx; 2931 int q; 2932 2933 /* 2934 * Handle trailing mbuf on TX queue. 2935 * Check is done lockess to avoid TX path contention. 2936 */ 2937 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2938 tx = MVNETA_TX_RING(sc, q); 2939 if ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG_TXCOMP && 2940 tx->used > 0) { 2941 mvneta_tx_lockq(sc, q); 2942 mvneta_tx_queue_complete(sc, q); 2943 mvneta_tx_unlockq(sc, q); 2944 } 2945 } 2946 } 2947 2948 /* 2949 * Rx Subroutines 2950 */ 2951 STATIC int 2952 mvneta_rx(struct mvneta_softc *sc, int q, int count) 2953 { 2954 uint32_t prxs, npkt; 2955 int more; 2956 2957 more = 0; 2958 mvneta_rx_lockq(sc, q); 2959 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 2960 npkt = MVNETA_PRXS_GET_ODC(prxs); 2961 if (__predict_false(npkt == 0)) 2962 goto out; 2963 2964 if (count > 0 && npkt > count) { 2965 more = 1; 2966 npkt = count; 2967 } 2968 mvneta_rx_queue(sc, q, npkt); 2969 out: 2970 mvneta_rx_unlockq(sc, q); 2971 return more; 2972 } 2973 2974 /* 2975 * Helper routine for updating PRXSU register of a given queue. 2976 * Handles number of processed descriptors bigger than maximum acceptable value. 2977 */ 2978 STATIC __inline void 2979 mvneta_prxsu_update(struct mvneta_softc *sc, int q, int processed) 2980 { 2981 uint32_t prxsu; 2982 2983 while (__predict_false(processed > 255)) { 2984 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 2985 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 2986 processed -= 255; 2987 } 2988 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(processed); 2989 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 2990 } 2991 2992 static __inline void 2993 mvneta_prefetch(void *p) 2994 { 2995 2996 __builtin_prefetch(p); 2997 } 2998 2999 STATIC void 3000 mvneta_rx_queue(struct mvneta_softc *sc, int q, int npkt) 3001 { 3002 struct ifnet *ifp; 3003 struct mvneta_rx_ring *rx; 3004 struct mvneta_rx_desc *r; 3005 struct mvneta_buf *rxbuf; 3006 struct mbuf *m; 3007 struct lro_ctrl *lro; 3008 struct lro_entry *queued; 3009 void *pktbuf; 3010 int i, pktlen, processed, ndma; 3011 3012 KASSERT_RX_MTX(sc, q); 3013 3014 ifp = sc->ifp; 3015 rx = MVNETA_RX_RING(sc, q); 3016 processed = 0; 3017 3018 if (__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3019 return; 3020 3021 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, 3022 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3023 3024 for (i = 0; i < npkt; i++) { 3025 /* Prefetch next desc, rxbuf. */ 3026 ndma = rx_counter_adv(rx->dma, 1); 3027 mvneta_prefetch(&rx->desc[ndma]); 3028 mvneta_prefetch(&rx->rxbuf[ndma]); 3029 3030 /* get descriptor and packet */ 3031 r = &rx->desc[rx->dma]; 3032 rxbuf = &rx->rxbuf[rx->dma]; 3033 m = rxbuf->m; 3034 rxbuf->m = NULL; 3035 DASSERT(m != NULL); 3036 bus_dmamap_sync(sc->rxbuf_dtag, rxbuf->dmap, 3037 BUS_DMASYNC_POSTREAD); 3038 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3039 /* Prefetch mbuf header. */ 3040 mvneta_prefetch(m); 3041 3042 processed++; 3043 /* Drop desc with error status or not in a single buffer. */ 3044 DASSERT((r->status & (MVNETA_RX_F|MVNETA_RX_L)) == 3045 (MVNETA_RX_F|MVNETA_RX_L)); 3046 if (__predict_false((r->status & MVNETA_RX_ES) || 3047 (r->status & (MVNETA_RX_F|MVNETA_RX_L)) != 3048 (MVNETA_RX_F|MVNETA_RX_L))) 3049 goto rx_error; 3050 3051 /* 3052 * [ OFF | MH | PKT | CRC ] 3053 * bytecnt cover MH, PKT, CRC 3054 */ 3055 pktlen = r->bytecnt - ETHER_CRC_LEN - MVNETA_HWHEADER_SIZE; 3056 pktbuf = (uint8_t *)rx->rxbuf_virt_addr[rx->dma] + MVNETA_PACKET_OFFSET + 3057 MVNETA_HWHEADER_SIZE; 3058 3059 /* Prefetch mbuf data. */ 3060 mvneta_prefetch(pktbuf); 3061 3062 /* Write value to mbuf (avoid read). */ 3063 m->m_data = pktbuf; 3064 m->m_len = m->m_pkthdr.len = pktlen; 3065 m->m_pkthdr.rcvif = ifp; 3066 mvneta_rx_set_csumflag(ifp, r, m); 3067 3068 /* Increase rx_dma before releasing the lock. */ 3069 rx->dma = ndma; 3070 3071 if (__predict_false(rx->lro_enabled && 3072 ((r->status & MVNETA_RX_L3_IP) != 0) && 3073 ((r->status & MVNETA_RX_L4_MASK) == MVNETA_RX_L4_TCP) && 3074 (m->m_pkthdr.csum_flags & 3075 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) == 3076 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR))) { 3077 if (rx->lro.lro_cnt != 0) { 3078 if (tcp_lro_rx(&rx->lro, m, 0) == 0) 3079 goto rx_done; 3080 } 3081 } 3082 3083 mvneta_rx_unlockq(sc, q); 3084 (*ifp->if_input)(ifp, m); 3085 mvneta_rx_lockq(sc, q); 3086 /* 3087 * Check whether this queue has been disabled in the 3088 * meantime. If yes, then clear LRO and exit. 3089 */ 3090 if(__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3091 goto rx_lro; 3092 rx_done: 3093 /* Refresh receive ring to avoid stall and minimize jitter. */ 3094 if (processed >= MVNETA_RX_REFILL_COUNT) { 3095 mvneta_prxsu_update(sc, q, processed); 3096 mvneta_rx_queue_refill(sc, q); 3097 processed = 0; 3098 } 3099 continue; 3100 rx_error: 3101 m_freem(m); 3102 rx->dma = ndma; 3103 /* Refresh receive ring to avoid stall and minimize jitter. */ 3104 if (processed >= MVNETA_RX_REFILL_COUNT) { 3105 mvneta_prxsu_update(sc, q, processed); 3106 mvneta_rx_queue_refill(sc, q); 3107 processed = 0; 3108 } 3109 } 3110 #ifdef MVNETA_KTR 3111 CTR3(KTR_SPARE2, "%s:%u %u packets received", ifp->if_xname, q, npkt); 3112 #endif 3113 /* DMA status update */ 3114 mvneta_prxsu_update(sc, q, processed); 3115 /* Refill the rest of buffers if there are any to refill */ 3116 mvneta_rx_queue_refill(sc, q); 3117 3118 rx_lro: 3119 /* 3120 * Flush any outstanding LRO work 3121 */ 3122 lro = &rx->lro; 3123 while (__predict_false((queued = LIST_FIRST(&lro->lro_active)) != NULL)) { 3124 LIST_REMOVE(LIST_FIRST((&lro->lro_active)), next); 3125 tcp_lro_flush(lro, queued); 3126 } 3127 } 3128 3129 STATIC void 3130 mvneta_rx_buf_free(struct mvneta_softc *sc, struct mvneta_buf *rxbuf) 3131 { 3132 3133 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3134 /* This will remove all data at once */ 3135 m_freem(rxbuf->m); 3136 } 3137 3138 STATIC void 3139 mvneta_rx_queue_refill(struct mvneta_softc *sc, int q) 3140 { 3141 struct mvneta_rx_ring *rx; 3142 struct mvneta_rx_desc *r; 3143 struct mvneta_buf *rxbuf; 3144 bus_dma_segment_t segs; 3145 struct mbuf *m; 3146 uint32_t prxs, prxsu, ndesc; 3147 int npkt, refill, nsegs, error; 3148 3149 KASSERT_RX_MTX(sc, q); 3150 3151 rx = MVNETA_RX_RING(sc, q); 3152 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 3153 ndesc = MVNETA_PRXS_GET_NODC(prxs) + MVNETA_PRXS_GET_ODC(prxs); 3154 refill = MVNETA_RX_RING_CNT - ndesc; 3155 #ifdef MVNETA_KTR 3156 CTR3(KTR_SPARE2, "%s:%u refill %u packets", sc->ifp->if_xname, q, 3157 refill); 3158 #endif 3159 if (__predict_false(refill <= 0)) 3160 return; 3161 3162 for (npkt = 0; npkt < refill; npkt++) { 3163 rxbuf = &rx->rxbuf[rx->cpu]; 3164 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, sc->rx_frame_size); 3165 if (__predict_false(m == NULL)) { 3166 error = ENOBUFS; 3167 break; 3168 } 3169 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3170 3171 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_dtag, rxbuf->dmap, 3172 m, &segs, &nsegs, BUS_DMA_NOWAIT); 3173 if (__predict_false(error != 0 || nsegs != 1)) { 3174 KASSERT(1, ("Failed to load Rx mbuf DMA map")); 3175 m_freem(m); 3176 break; 3177 } 3178 3179 /* Add the packet to the ring */ 3180 rxbuf->m = m; 3181 r = &rx->desc[rx->cpu]; 3182 r->bufptr_pa = segs.ds_addr; 3183 rx->rxbuf_virt_addr[rx->cpu] = m->m_data; 3184 3185 rx->cpu = rx_counter_adv(rx->cpu, 1); 3186 } 3187 if (npkt == 0) { 3188 if (refill == MVNETA_RX_RING_CNT) 3189 rx->needs_refill = TRUE; 3190 return; 3191 } 3192 3193 rx->needs_refill = FALSE; 3194 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3195 3196 while (__predict_false(npkt > 255)) { 3197 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(255); 3198 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3199 npkt -= 255; 3200 } 3201 if (__predict_true(npkt > 0)) { 3202 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(npkt); 3203 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3204 } 3205 } 3206 3207 STATIC __inline void 3208 mvneta_rx_set_csumflag(struct ifnet *ifp, 3209 struct mvneta_rx_desc *r, struct mbuf *m) 3210 { 3211 uint32_t csum_flags; 3212 3213 csum_flags = 0; 3214 if (__predict_false((r->status & 3215 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 0)) 3216 return; /* not a IP packet */ 3217 3218 /* L3 */ 3219 if (__predict_true((r->status & MVNETA_RX_IP_HEADER_OK) == 3220 MVNETA_RX_IP_HEADER_OK)) 3221 csum_flags |= CSUM_L3_CALC|CSUM_L3_VALID; 3222 3223 if (__predict_true((r->status & (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 3224 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP))) { 3225 /* L4 */ 3226 switch (r->status & MVNETA_RX_L4_MASK) { 3227 case MVNETA_RX_L4_TCP: 3228 case MVNETA_RX_L4_UDP: 3229 csum_flags |= CSUM_L4_CALC; 3230 if (__predict_true((r->status & 3231 MVNETA_RX_L4_CHECKSUM_OK) == MVNETA_RX_L4_CHECKSUM_OK)) { 3232 csum_flags |= CSUM_L4_VALID; 3233 m->m_pkthdr.csum_data = htons(0xffff); 3234 } 3235 break; 3236 case MVNETA_RX_L4_OTH: 3237 default: 3238 break; 3239 } 3240 } 3241 m->m_pkthdr.csum_flags = csum_flags; 3242 } 3243 3244 /* 3245 * MAC address filter 3246 */ 3247 STATIC void 3248 mvneta_filter_setup(struct mvneta_softc *sc) 3249 { 3250 struct ifnet *ifp; 3251 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 3252 uint32_t pxc; 3253 int i; 3254 3255 KASSERT_SC_MTX(sc); 3256 3257 memset(dfut, 0, sizeof(dfut)); 3258 memset(dfsmt, 0, sizeof(dfsmt)); 3259 memset(dfomt, 0, sizeof(dfomt)); 3260 3261 ifp = sc->ifp; 3262 ifp->if_flags |= IFF_ALLMULTI; 3263 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 3264 for (i = 0; i < MVNETA_NDFSMT; i++) { 3265 dfsmt[i] = dfomt[i] = 3266 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3267 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3268 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3269 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3270 } 3271 } 3272 3273 pxc = MVNETA_READ(sc, MVNETA_PXC); 3274 pxc &= ~(MVNETA_PXC_UPM | MVNETA_PXC_RXQ_MASK | MVNETA_PXC_RXQARP_MASK | 3275 MVNETA_PXC_TCPQ_MASK | MVNETA_PXC_UDPQ_MASK | MVNETA_PXC_BPDUQ_MASK); 3276 pxc |= MVNETA_PXC_RXQ(MVNETA_RX_QNUM_MAX-1); 3277 pxc |= MVNETA_PXC_RXQARP(MVNETA_RX_QNUM_MAX-1); 3278 pxc |= MVNETA_PXC_TCPQ(MVNETA_RX_QNUM_MAX-1); 3279 pxc |= MVNETA_PXC_UDPQ(MVNETA_RX_QNUM_MAX-1); 3280 pxc |= MVNETA_PXC_BPDUQ(MVNETA_RX_QNUM_MAX-1); 3281 pxc |= MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP; 3282 if (ifp->if_flags & IFF_BROADCAST) { 3283 pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP); 3284 } 3285 if (ifp->if_flags & IFF_PROMISC) { 3286 pxc |= MVNETA_PXC_UPM; 3287 } 3288 MVNETA_WRITE(sc, MVNETA_PXC, pxc); 3289 3290 /* Set Destination Address Filter Unicast Table */ 3291 if (ifp->if_flags & IFF_PROMISC) { 3292 /* pass all unicast addresses */ 3293 for (i = 0; i < MVNETA_NDFUT; i++) { 3294 dfut[i] = 3295 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3296 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3297 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3298 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3299 } 3300 } else { 3301 i = sc->enaddr[5] & 0xf; /* last nibble */ 3302 dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3303 } 3304 MVNETA_WRITE_REGION(sc, MVNETA_DFUT(0), dfut, MVNETA_NDFUT); 3305 3306 /* Set Destination Address Filter Multicast Tables */ 3307 MVNETA_WRITE_REGION(sc, MVNETA_DFSMT(0), dfsmt, MVNETA_NDFSMT); 3308 MVNETA_WRITE_REGION(sc, MVNETA_DFOMT(0), dfomt, MVNETA_NDFOMT); 3309 } 3310 3311 /* 3312 * sysctl(9) 3313 */ 3314 STATIC int 3315 sysctl_read_mib(SYSCTL_HANDLER_ARGS) 3316 { 3317 struct mvneta_sysctl_mib *arg; 3318 struct mvneta_softc *sc; 3319 uint64_t val; 3320 3321 arg = (struct mvneta_sysctl_mib *)arg1; 3322 if (arg == NULL) 3323 return (EINVAL); 3324 3325 sc = arg->sc; 3326 if (sc == NULL) 3327 return (EINVAL); 3328 if (arg->index < 0 || arg->index > MVNETA_PORTMIB_NOCOUNTER) 3329 return (EINVAL); 3330 3331 mvneta_sc_lock(sc); 3332 val = arg->counter; 3333 mvneta_sc_unlock(sc); 3334 return sysctl_handle_64(oidp, &val, 0, req); 3335 } 3336 3337 3338 STATIC int 3339 sysctl_clear_mib(SYSCTL_HANDLER_ARGS) 3340 { 3341 struct mvneta_softc *sc; 3342 int err, val; 3343 3344 val = 0; 3345 sc = (struct mvneta_softc *)arg1; 3346 if (sc == NULL) 3347 return (EINVAL); 3348 3349 err = sysctl_handle_int(oidp, &val, 0, req); 3350 if (err != 0) 3351 return (err); 3352 3353 if (val < 0 || val > 1) 3354 return (EINVAL); 3355 3356 if (val == 1) { 3357 mvneta_sc_lock(sc); 3358 mvneta_clear_mib(sc); 3359 mvneta_sc_unlock(sc); 3360 } 3361 3362 return (0); 3363 } 3364 3365 STATIC int 3366 sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS) 3367 { 3368 struct mvneta_sysctl_queue *arg; 3369 struct mvneta_rx_ring *rx; 3370 struct mvneta_softc *sc; 3371 uint32_t reg, time_mvtclk; 3372 int err, time_us; 3373 3374 rx = NULL; 3375 arg = (struct mvneta_sysctl_queue *)arg1; 3376 if (arg == NULL) 3377 return (EINVAL); 3378 if (arg->queue < 0 || arg->queue > MVNETA_RX_RING_CNT) 3379 return (EINVAL); 3380 if (arg->rxtx != MVNETA_SYSCTL_RX) 3381 return (EINVAL); 3382 3383 sc = arg->sc; 3384 if (sc == NULL) 3385 return (EINVAL); 3386 3387 /* read queue length */ 3388 mvneta_sc_lock(sc); 3389 mvneta_rx_lockq(sc, arg->queue); 3390 rx = MVNETA_RX_RING(sc, arg->queue); 3391 time_mvtclk = rx->queue_th_time; 3392 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / mvneta_get_clk(); 3393 mvneta_rx_unlockq(sc, arg->queue); 3394 mvneta_sc_unlock(sc); 3395 3396 err = sysctl_handle_int(oidp, &time_us, 0, req); 3397 if (err != 0) 3398 return (err); 3399 3400 mvneta_sc_lock(sc); 3401 mvneta_rx_lockq(sc, arg->queue); 3402 3403 /* update queue length (0[sec] - 1[sec]) */ 3404 if (time_us < 0 || time_us > (1000 * 1000)) { 3405 mvneta_rx_unlockq(sc, arg->queue); 3406 mvneta_sc_unlock(sc); 3407 return (EINVAL); 3408 } 3409 time_mvtclk = 3410 (uint64_t)mvneta_get_clk() * (uint64_t)time_us / (1000ULL * 1000ULL); 3411 rx->queue_th_time = time_mvtclk; 3412 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 3413 MVNETA_WRITE(sc, MVNETA_PRXITTH(arg->queue), reg); 3414 mvneta_rx_unlockq(sc, arg->queue); 3415 mvneta_sc_unlock(sc); 3416 3417 return (0); 3418 } 3419 3420 STATIC void 3421 sysctl_mvneta_init(struct mvneta_softc *sc) 3422 { 3423 struct sysctl_ctx_list *ctx; 3424 struct sysctl_oid_list *children; 3425 struct sysctl_oid_list *rxchildren; 3426 struct sysctl_oid_list *qchildren, *mchildren; 3427 struct sysctl_oid *tree; 3428 int i, q; 3429 struct mvneta_sysctl_queue *rxarg; 3430 #define MVNETA_SYSCTL_NAME(num) "queue" # num 3431 static const char *sysctl_queue_names[] = { 3432 MVNETA_SYSCTL_NAME(0), MVNETA_SYSCTL_NAME(1), 3433 MVNETA_SYSCTL_NAME(2), MVNETA_SYSCTL_NAME(3), 3434 MVNETA_SYSCTL_NAME(4), MVNETA_SYSCTL_NAME(5), 3435 MVNETA_SYSCTL_NAME(6), MVNETA_SYSCTL_NAME(7), 3436 }; 3437 #undef MVNETA_SYSCTL_NAME 3438 3439 #ifndef NO_SYSCTL_DESCR 3440 #define MVNETA_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3441 static const char *sysctl_queue_descrs[] = { 3442 MVNETA_SYSCTL_DESCR(0), MVNETA_SYSCTL_DESCR(1), 3443 MVNETA_SYSCTL_DESCR(2), MVNETA_SYSCTL_DESCR(3), 3444 MVNETA_SYSCTL_DESCR(4), MVNETA_SYSCTL_DESCR(5), 3445 MVNETA_SYSCTL_DESCR(6), MVNETA_SYSCTL_DESCR(7), 3446 }; 3447 #undef MVNETA_SYSCTL_DESCR 3448 #endif 3449 3450 3451 ctx = device_get_sysctl_ctx(sc->dev); 3452 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3453 3454 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rx", 3455 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA RX"); 3456 rxchildren = SYSCTL_CHILDREN(tree); 3457 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "mib", 3458 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA MIB"); 3459 mchildren = SYSCTL_CHILDREN(tree); 3460 3461 3462 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "flow_control", 3463 CTLFLAG_RW, &sc->cf_fc, 0, "flow control"); 3464 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpi", 3465 CTLFLAG_RW, &sc->cf_lpi, 0, "Low Power Idle"); 3466 3467 /* 3468 * MIB access 3469 */ 3470 /* dev.mvneta.[unit].mib.<mibs> */ 3471 for (i = 0; i < MVNETA_PORTMIB_NOCOUNTER; i++) { 3472 struct mvneta_sysctl_mib *mib_arg = &sc->sysctl_mib[i]; 3473 3474 mib_arg->sc = sc; 3475 mib_arg->index = i; 3476 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, 3477 mvneta_mib_list[i].sysctl_name, 3478 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 3479 (void *)mib_arg, 0, sysctl_read_mib, "I", 3480 mvneta_mib_list[i].desc); 3481 } 3482 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "rx_discard", 3483 CTLFLAG_RD, &sc->counter_pdfc, "Port Rx Discard Frame Counter"); 3484 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "overrun", 3485 CTLFLAG_RD, &sc->counter_pofc, "Port Overrun Frame Counter"); 3486 SYSCTL_ADD_UINT(ctx, mchildren, OID_AUTO, "watchdog", 3487 CTLFLAG_RD, &sc->counter_watchdog, 0, "TX Watchdog Counter"); 3488 3489 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, "reset", 3490 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3491 (void *)sc, 0, sysctl_clear_mib, "I", "Reset MIB counters"); 3492 3493 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 3494 rxarg = &sc->sysctl_rx_queue[q]; 3495 3496 rxarg->sc = sc; 3497 rxarg->queue = q; 3498 rxarg->rxtx = MVNETA_SYSCTL_RX; 3499 3500 /* hw.mvneta.mvneta[unit].rx.[queue] */ 3501 tree = SYSCTL_ADD_NODE(ctx, rxchildren, OID_AUTO, 3502 sysctl_queue_names[q], CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 3503 sysctl_queue_descrs[q]); 3504 qchildren = SYSCTL_CHILDREN(tree); 3505 3506 /* hw.mvneta.mvneta[unit].rx.[queue].threshold_timer_us */ 3507 SYSCTL_ADD_PROC(ctx, qchildren, OID_AUTO, "threshold_timer_us", 3508 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, rxarg, 0, 3509 sysctl_set_queue_rxthtime, "I", 3510 "interrupt coalescing threshold timer [us]"); 3511 } 3512 } 3513 3514 /* 3515 * MIB 3516 */ 3517 STATIC uint64_t 3518 mvneta_read_mib(struct mvneta_softc *sc, int index) 3519 { 3520 struct mvneta_mib_def *mib; 3521 uint64_t val; 3522 3523 mib = &mvneta_mib_list[index]; 3524 val = MVNETA_READ_MIB(sc, mib->regnum); 3525 if (mib->reg64) 3526 val |= (uint64_t)MVNETA_READ_MIB(sc, mib->regnum + 4) << 32; 3527 return (val); 3528 } 3529 3530 STATIC void 3531 mvneta_clear_mib(struct mvneta_softc *sc) 3532 { 3533 int i; 3534 3535 KASSERT_SC_MTX(sc); 3536 3537 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3538 (void)mvneta_read_mib(sc, i); 3539 sc->sysctl_mib[i].counter = 0; 3540 } 3541 MVNETA_READ(sc, MVNETA_PDFC); 3542 sc->counter_pdfc = 0; 3543 MVNETA_READ(sc, MVNETA_POFC); 3544 sc->counter_pofc = 0; 3545 sc->counter_watchdog = 0; 3546 } 3547 3548 STATIC void 3549 mvneta_update_mib(struct mvneta_softc *sc) 3550 { 3551 struct mvneta_tx_ring *tx; 3552 int i; 3553 uint64_t val; 3554 uint32_t reg; 3555 3556 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3557 3558 val = mvneta_read_mib(sc, i); 3559 if (val == 0) 3560 continue; 3561 3562 sc->sysctl_mib[i].counter += val; 3563 switch (mvneta_mib_list[i].regnum) { 3564 case MVNETA_MIB_RX_GOOD_OCT: 3565 if_inc_counter(sc->ifp, IFCOUNTER_IBYTES, val); 3566 break; 3567 case MVNETA_MIB_RX_BAD_FRAME: 3568 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, val); 3569 break; 3570 case MVNETA_MIB_RX_GOOD_FRAME: 3571 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, val); 3572 break; 3573 case MVNETA_MIB_RX_MCAST_FRAME: 3574 if_inc_counter(sc->ifp, IFCOUNTER_IMCASTS, val); 3575 break; 3576 case MVNETA_MIB_TX_GOOD_OCT: 3577 if_inc_counter(sc->ifp, IFCOUNTER_OBYTES, val); 3578 break; 3579 case MVNETA_MIB_TX_GOOD_FRAME: 3580 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, val); 3581 break; 3582 case MVNETA_MIB_TX_MCAST_FRAME: 3583 if_inc_counter(sc->ifp, IFCOUNTER_OMCASTS, val); 3584 break; 3585 case MVNETA_MIB_MAC_COL: 3586 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, val); 3587 break; 3588 case MVNETA_MIB_TX_MAC_TRNS_ERR: 3589 case MVNETA_MIB_TX_EXCES_COL: 3590 case MVNETA_MIB_MAC_LATE_COL: 3591 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, val); 3592 break; 3593 } 3594 } 3595 3596 reg = MVNETA_READ(sc, MVNETA_PDFC); 3597 sc->counter_pdfc += reg; 3598 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3599 reg = MVNETA_READ(sc, MVNETA_POFC); 3600 sc->counter_pofc += reg; 3601 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3602 3603 /* TX watchdog. */ 3604 if (sc->counter_watchdog_mib > 0) { 3605 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, sc->counter_watchdog_mib); 3606 sc->counter_watchdog_mib = 0; 3607 } 3608 /* 3609 * TX driver errors: 3610 * We do not take queue locks to not disrupt TX path. 3611 * We may only miss one drv error which will be fixed at 3612 * next mib update. We may also clear counter when TX path 3613 * is incrementing it but we only do it if counter was not zero 3614 * thus we may only loose one error. 3615 */ 3616 for (i = 0; i < MVNETA_TX_QNUM_MAX; i++) { 3617 tx = MVNETA_TX_RING(sc, i); 3618 3619 if (tx->drv_error > 0) { 3620 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, tx->drv_error); 3621 tx->drv_error = 0; 3622 } 3623 } 3624 } 3625