1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __NVME_PRIVATE_H__ 32 #define __NVME_PRIVATE_H__ 33 34 #include <sys/param.h> 35 #include <sys/bio.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/systm.h> 44 #include <sys/taskqueue.h> 45 46 #include <vm/uma.h> 47 48 #include <machine/bus.h> 49 50 #include "nvme.h" 51 52 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 53 54 MALLOC_DECLARE(M_NVME); 55 56 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 57 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 58 59 #define NVME_ADMIN_TRACKERS (16) 60 #define NVME_ADMIN_ENTRIES (128) 61 /* min and max are defined in admin queue attributes section of spec */ 62 #define NVME_MIN_ADMIN_ENTRIES (2) 63 #define NVME_MAX_ADMIN_ENTRIES (4096) 64 65 /* 66 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 67 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 68 * will allow outstanding on an I/O qpair at any time. The only advantage in 69 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 70 * the contents of the submission and completion queues, it will show a longer 71 * history of data. 72 */ 73 #define NVME_IO_ENTRIES (256) 74 #define NVME_IO_TRACKERS (128) 75 #define NVME_MIN_IO_TRACKERS (4) 76 #define NVME_MAX_IO_TRACKERS (1024) 77 78 /* 79 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 80 * for each controller. 81 */ 82 83 #define NVME_INT_COAL_TIME (0) /* disabled */ 84 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 85 86 #define NVME_MAX_NAMESPACES (16) 87 #define NVME_MAX_CONSUMERS (2) 88 #define NVME_MAX_ASYNC_EVENTS (8) 89 90 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 91 #define NVME_MIN_TIMEOUT_PERIOD (5) 92 #define NVME_MAX_TIMEOUT_PERIOD (120) 93 94 #define NVME_DEFAULT_RETRY_COUNT (4) 95 96 /* Maximum log page size to fetch for AERs. */ 97 #define NVME_MAX_AER_LOG_SIZE (4096) 98 99 /* 100 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 101 * it. 102 */ 103 #ifndef CACHE_LINE_SIZE 104 #define CACHE_LINE_SIZE (64) 105 #endif 106 107 #define NVME_GONE 0xfffffffful 108 109 extern int32_t nvme_retry_count; 110 extern bool nvme_verbose_cmd_dump; 111 112 struct nvme_completion_poll_status { 113 struct nvme_completion cpl; 114 int done; 115 }; 116 117 extern devclass_t nvme_devclass; 118 119 #define NVME_REQUEST_VADDR 1 120 #define NVME_REQUEST_NULL 2 /* For requests with no payload. */ 121 #define NVME_REQUEST_UIO 3 122 #define NVME_REQUEST_BIO 4 123 #define NVME_REQUEST_CCB 5 124 125 struct nvme_request { 126 struct nvme_command cmd; 127 struct nvme_qpair *qpair; 128 union { 129 void *payload; 130 struct bio *bio; 131 } u; 132 uint32_t type; 133 uint32_t payload_size; 134 bool timeout; 135 nvme_cb_fn_t cb_fn; 136 void *cb_arg; 137 int32_t retries; 138 STAILQ_ENTRY(nvme_request) stailq; 139 }; 140 141 struct nvme_async_event_request { 142 struct nvme_controller *ctrlr; 143 struct nvme_request *req; 144 struct nvme_completion cpl; 145 uint32_t log_page_id; 146 uint32_t log_page_size; 147 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 148 }; 149 150 struct nvme_tracker { 151 TAILQ_ENTRY(nvme_tracker) tailq; 152 struct nvme_request *req; 153 struct nvme_qpair *qpair; 154 sbintime_t deadline; 155 bus_dmamap_t payload_dma_map; 156 uint16_t cid; 157 158 uint64_t *prp; 159 bus_addr_t prp_bus_addr; 160 }; 161 162 enum nvme_recovery { 163 RECOVERY_NONE = 0, /* Normal operations */ 164 RECOVERY_START, /* Deadline has passed, start recovering */ 165 RECOVERY_RESET, /* This pass, initiate reset of controller */ 166 RECOVERY_WAITING, /* waiting for the reset to complete */ 167 }; 168 struct nvme_qpair { 169 struct nvme_controller *ctrlr; 170 uint32_t id; 171 int domain; 172 int cpu; 173 174 uint16_t vector; 175 int rid; 176 struct resource *res; 177 void *tag; 178 179 struct callout timer; 180 sbintime_t deadline; 181 bool timer_armed; 182 enum nvme_recovery recovery_state; 183 184 uint32_t num_entries; 185 uint32_t num_trackers; 186 uint32_t sq_tdbl_off; 187 uint32_t cq_hdbl_off; 188 189 uint32_t phase; 190 uint32_t sq_head; 191 uint32_t sq_tail; 192 uint32_t cq_head; 193 194 int64_t num_cmds; 195 int64_t num_intr_handler_calls; 196 int64_t num_retries; 197 int64_t num_failures; 198 int64_t num_ignored; 199 200 struct nvme_command *cmd; 201 struct nvme_completion *cpl; 202 203 bus_dma_tag_t dma_tag; 204 bus_dma_tag_t dma_tag_payload; 205 206 bus_dmamap_t queuemem_map; 207 uint64_t cmd_bus_addr; 208 uint64_t cpl_bus_addr; 209 210 TAILQ_HEAD(, nvme_tracker) free_tr; 211 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 212 STAILQ_HEAD(, nvme_request) queued_req; 213 214 struct nvme_tracker **act_tr; 215 216 struct mtx lock __aligned(CACHE_LINE_SIZE); 217 218 } __aligned(CACHE_LINE_SIZE); 219 220 struct nvme_namespace { 221 struct nvme_controller *ctrlr; 222 struct nvme_namespace_data data; 223 uint32_t id; 224 uint32_t flags; 225 struct cdev *cdev; 226 void *cons_cookie[NVME_MAX_CONSUMERS]; 227 uint32_t boundary; 228 struct mtx lock; 229 }; 230 231 /* 232 * One of these per allocated PCI device. 233 */ 234 struct nvme_controller { 235 device_t dev; 236 237 struct mtx lock; 238 int domain; 239 uint32_t ready_timeout_in_ms; 240 uint32_t quirks; 241 #define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */ 242 #define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */ 243 #define QUIRK_INTEL_ALIGNMENT 4 /* Pre NVMe 1.3 performance alignment */ 244 245 bus_space_tag_t bus_tag; 246 bus_space_handle_t bus_handle; 247 int resource_id; 248 struct resource *resource; 249 250 /* 251 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 252 * separate from the control registers which are in BAR 0/1. These 253 * members track the mapping of BAR 4/5 for that reason. 254 */ 255 int bar4_resource_id; 256 struct resource *bar4_resource; 257 258 int msi_count; 259 uint32_t enable_aborts; 260 261 uint32_t num_io_queues; 262 uint32_t max_hw_pend_io; 263 264 /* Fields for tracking progress during controller initialization. */ 265 struct intr_config_hook config_hook; 266 uint32_t ns_identified; 267 uint32_t queues_created; 268 269 struct task reset_task; 270 struct task fail_req_task; 271 struct taskqueue *taskqueue; 272 273 /* For shared legacy interrupt. */ 274 int rid; 275 struct resource *res; 276 void *tag; 277 278 /** maximum i/o size in bytes */ 279 uint32_t max_xfer_size; 280 281 /** minimum page size supported by this controller in bytes */ 282 uint32_t min_page_size; 283 284 /** interrupt coalescing time period (in microseconds) */ 285 uint32_t int_coal_time; 286 287 /** interrupt coalescing threshold */ 288 uint32_t int_coal_threshold; 289 290 /** timeout period in seconds */ 291 uint32_t timeout_period; 292 293 /** doorbell stride */ 294 uint32_t dstrd; 295 296 struct nvme_qpair adminq; 297 struct nvme_qpair *ioq; 298 299 struct nvme_registers *regs; 300 301 struct nvme_controller_data cdata; 302 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 303 304 struct cdev *cdev; 305 306 /** bit mask of event types currently enabled for async events */ 307 uint32_t async_event_config; 308 309 uint32_t num_aers; 310 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 311 312 void *cons_cookie[NVME_MAX_CONSUMERS]; 313 314 uint32_t is_resetting; 315 uint32_t is_initialized; 316 uint32_t notification_sent; 317 318 bool is_failed; 319 bool is_dying; 320 STAILQ_HEAD(, nvme_request) fail_req; 321 322 /* Host Memory Buffer */ 323 int hmb_nchunks; 324 size_t hmb_chunk; 325 bus_dma_tag_t hmb_tag; 326 struct nvme_hmb_chunk { 327 bus_dmamap_t hmbc_map; 328 void *hmbc_vaddr; 329 uint64_t hmbc_paddr; 330 } *hmb_chunks; 331 bus_dma_tag_t hmb_desc_tag; 332 bus_dmamap_t hmb_desc_map; 333 struct nvme_hmb_desc *hmb_desc_vaddr; 334 uint64_t hmb_desc_paddr; 335 }; 336 337 #define nvme_mmio_offsetof(reg) \ 338 offsetof(struct nvme_registers, reg) 339 340 #define nvme_mmio_read_4(sc, reg) \ 341 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 342 nvme_mmio_offsetof(reg)) 343 344 #define nvme_mmio_write_4(sc, reg, val) \ 345 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 346 nvme_mmio_offsetof(reg), val) 347 348 #define nvme_mmio_write_8(sc, reg, val) \ 349 do { \ 350 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 351 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 352 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 353 nvme_mmio_offsetof(reg)+4, \ 354 (val & 0xFFFFFFFF00000000ULL) >> 32); \ 355 } while (0); 356 357 #define nvme_printf(ctrlr, fmt, args...) \ 358 device_printf(ctrlr->dev, fmt, ##args) 359 360 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 361 362 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 363 void *payload, 364 nvme_cb_fn_t cb_fn, void *cb_arg); 365 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 366 uint32_t nsid, void *payload, 367 nvme_cb_fn_t cb_fn, void *cb_arg); 368 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 369 uint32_t microseconds, 370 uint32_t threshold, 371 nvme_cb_fn_t cb_fn, 372 void *cb_arg); 373 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 374 struct nvme_error_information_entry *payload, 375 uint32_t num_entries, /* 0 = max */ 376 nvme_cb_fn_t cb_fn, 377 void *cb_arg); 378 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 379 uint32_t nsid, 380 struct nvme_health_information_page *payload, 381 nvme_cb_fn_t cb_fn, 382 void *cb_arg); 383 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 384 struct nvme_firmware_page *payload, 385 nvme_cb_fn_t cb_fn, 386 void *cb_arg); 387 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 388 struct nvme_qpair *io_que, 389 nvme_cb_fn_t cb_fn, void *cb_arg); 390 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 391 struct nvme_qpair *io_que, 392 nvme_cb_fn_t cb_fn, void *cb_arg); 393 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 394 struct nvme_qpair *io_que, 395 nvme_cb_fn_t cb_fn, void *cb_arg); 396 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 397 struct nvme_qpair *io_que, 398 nvme_cb_fn_t cb_fn, void *cb_arg); 399 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 400 uint32_t num_queues, nvme_cb_fn_t cb_fn, 401 void *cb_arg); 402 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 403 uint32_t state, 404 nvme_cb_fn_t cb_fn, void *cb_arg); 405 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 406 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 407 408 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 409 410 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 411 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 412 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 413 void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 414 /* ctrlr defined as void * to allow use with config_intrhook. */ 415 void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 416 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 417 struct nvme_request *req); 418 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 419 struct nvme_request *req); 420 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 421 struct nvme_request *req); 422 423 int nvme_qpair_construct(struct nvme_qpair *qpair, 424 uint32_t num_entries, uint32_t num_trackers, 425 struct nvme_controller *ctrlr); 426 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 427 struct nvme_tracker *tr); 428 bool nvme_qpair_process_completions(struct nvme_qpair *qpair); 429 void nvme_qpair_submit_request(struct nvme_qpair *qpair, 430 struct nvme_request *req); 431 void nvme_qpair_reset(struct nvme_qpair *qpair); 432 void nvme_qpair_fail(struct nvme_qpair *qpair); 433 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 434 struct nvme_request *req, 435 uint32_t sct, uint32_t sc); 436 437 void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 438 void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 439 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 440 441 void nvme_io_qpair_enable(struct nvme_qpair *qpair); 442 void nvme_io_qpair_disable(struct nvme_qpair *qpair); 443 void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 444 445 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id, 446 struct nvme_controller *ctrlr); 447 void nvme_ns_destruct(struct nvme_namespace *ns); 448 449 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 450 451 void nvme_dump_command(struct nvme_command *cmd); 452 void nvme_dump_completion(struct nvme_completion *cpl); 453 454 int nvme_attach(device_t dev); 455 int nvme_shutdown(device_t dev); 456 int nvme_detach(device_t dev); 457 458 /* 459 * Wait for a command to complete using the nvme_completion_poll_cb. Used in 460 * limited contexts where the caller knows it's OK to block briefly while the 461 * command runs. The ISR will run the callback which will set status->done to 462 * true, usually within microseconds. If not, then after one second timeout 463 * handler should reset the controller and abort all outstanding requests 464 * including this polled one. If still not after ten seconds, then something is 465 * wrong with the driver, and panic is the only way to recover. 466 * 467 * Most commands using this interface aren't actual I/O to the drive's media so 468 * complete within a few microseconds. Adaptively spin for one tick to catch the 469 * vast majority of these without waiting for a tick plus scheduling delays. Since 470 * these are on startup, this drastically reduces startup time. 471 */ 472 static __inline 473 void 474 nvme_completion_poll(struct nvme_completion_poll_status *status) 475 { 476 int timeout = ticks + 10 * hz; 477 sbintime_t delta_t = SBT_1US; 478 479 while (!atomic_load_acq_int(&status->done)) { 480 if (timeout - ticks < 0) 481 panic("NVME polled command failed to complete within 10s."); 482 pause_sbt("nvme", delta_t, 0, C_PREL(1)); 483 delta_t = min(SBT_1MS, delta_t * 3 / 2); 484 } 485 } 486 487 static __inline void 488 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 489 { 490 uint64_t *bus_addr = (uint64_t *)arg; 491 492 KASSERT(nseg == 1, ("number of segments (%d) is not 1", nseg)); 493 if (error != 0) 494 printf("nvme_single_map err %d\n", error); 495 *bus_addr = seg[0].ds_addr; 496 } 497 498 static __inline struct nvme_request * 499 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 500 { 501 struct nvme_request *req; 502 503 req = malloc(sizeof(*req), M_NVME, M_NOWAIT | M_ZERO); 504 if (req != NULL) { 505 req->cb_fn = cb_fn; 506 req->cb_arg = cb_arg; 507 req->timeout = true; 508 } 509 return (req); 510 } 511 512 static __inline struct nvme_request * 513 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 514 nvme_cb_fn_t cb_fn, void *cb_arg) 515 { 516 struct nvme_request *req; 517 518 req = _nvme_allocate_request(cb_fn, cb_arg); 519 if (req != NULL) { 520 req->type = NVME_REQUEST_VADDR; 521 req->u.payload = payload; 522 req->payload_size = payload_size; 523 } 524 return (req); 525 } 526 527 static __inline struct nvme_request * 528 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 529 { 530 struct nvme_request *req; 531 532 req = _nvme_allocate_request(cb_fn, cb_arg); 533 if (req != NULL) 534 req->type = NVME_REQUEST_NULL; 535 return (req); 536 } 537 538 static __inline struct nvme_request * 539 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 540 { 541 struct nvme_request *req; 542 543 req = _nvme_allocate_request(cb_fn, cb_arg); 544 if (req != NULL) { 545 req->type = NVME_REQUEST_BIO; 546 req->u.bio = bio; 547 } 548 return (req); 549 } 550 551 static __inline struct nvme_request * 552 nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg) 553 { 554 struct nvme_request *req; 555 556 req = _nvme_allocate_request(cb_fn, cb_arg); 557 if (req != NULL) { 558 req->type = NVME_REQUEST_CCB; 559 req->u.payload = ccb; 560 } 561 562 return (req); 563 } 564 565 #define nvme_free_request(req) free(req, M_NVME) 566 567 void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 568 const struct nvme_completion *async_cpl, 569 uint32_t log_page_id, void *log_page_buffer, 570 uint32_t log_page_size); 571 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 572 void nvme_notify_new_controller(struct nvme_controller *ctrlr); 573 void nvme_notify_ns(struct nvme_controller *ctrlr, int nsid); 574 575 void nvme_ctrlr_shared_handler(void *arg); 576 void nvme_ctrlr_poll(struct nvme_controller *ctrlr); 577 578 int nvme_ctrlr_suspend(struct nvme_controller *ctrlr); 579 int nvme_ctrlr_resume(struct nvme_controller *ctrlr); 580 581 #endif /* __NVME_PRIVATE_H__ */ 582