1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __NVME_PRIVATE_H__ 32 #define __NVME_PRIVATE_H__ 33 34 #include <sys/param.h> 35 #include <sys/bio.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/memdesc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/systm.h> 45 #include <sys/taskqueue.h> 46 47 #include <vm/uma.h> 48 49 #include <machine/bus.h> 50 51 #include "nvme.h" 52 53 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 54 55 MALLOC_DECLARE(M_NVME); 56 57 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 58 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 59 60 #define NVME_ADMIN_TRACKERS (16) 61 #define NVME_ADMIN_ENTRIES (128) 62 /* min and max are defined in admin queue attributes section of spec */ 63 #define NVME_MIN_ADMIN_ENTRIES (2) 64 #define NVME_MAX_ADMIN_ENTRIES (4096) 65 66 /* 67 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 68 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 69 * will allow outstanding on an I/O qpair at any time. The only advantage in 70 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 71 * the contents of the submission and completion queues, it will show a longer 72 * history of data. 73 */ 74 #define NVME_IO_ENTRIES (256) 75 #define NVME_IO_TRACKERS (128) 76 #define NVME_MIN_IO_TRACKERS (4) 77 #define NVME_MAX_IO_TRACKERS (1024) 78 79 /* 80 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 81 * for each controller. 82 */ 83 84 #define NVME_INT_COAL_TIME (0) /* disabled */ 85 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 86 87 #define NVME_MAX_NAMESPACES (16) 88 #define NVME_MAX_CONSUMERS (2) 89 #define NVME_MAX_ASYNC_EVENTS (8) 90 91 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 92 #define NVME_MIN_TIMEOUT_PERIOD (5) 93 #define NVME_MAX_TIMEOUT_PERIOD (120) 94 95 #define NVME_DEFAULT_RETRY_COUNT (4) 96 97 /* Maximum log page size to fetch for AERs. */ 98 #define NVME_MAX_AER_LOG_SIZE (4096) 99 100 /* 101 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 102 * it. 103 */ 104 #ifndef CACHE_LINE_SIZE 105 #define CACHE_LINE_SIZE (64) 106 #endif 107 108 #define NVME_GONE 0xfffffffful 109 110 extern int32_t nvme_retry_count; 111 extern bool nvme_verbose_cmd_dump; 112 113 struct nvme_completion_poll_status { 114 struct nvme_completion cpl; 115 int done; 116 }; 117 118 struct nvme_request { 119 struct nvme_command cmd; 120 struct nvme_qpair *qpair; 121 struct memdesc payload; 122 nvme_cb_fn_t cb_fn; 123 void *cb_arg; 124 int32_t retries; 125 bool payload_valid; 126 bool timeout; 127 bool spare[2]; /* Future use */ 128 STAILQ_ENTRY(nvme_request) stailq; 129 }; 130 131 struct nvme_async_event_request { 132 struct nvme_controller *ctrlr; 133 struct nvme_request *req; 134 struct nvme_completion cpl; 135 uint32_t log_page_id; 136 uint32_t log_page_size; 137 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 138 }; 139 140 struct nvme_tracker { 141 TAILQ_ENTRY(nvme_tracker) tailq; 142 struct nvme_request *req; 143 struct nvme_qpair *qpair; 144 sbintime_t deadline; 145 bus_dmamap_t payload_dma_map; 146 uint16_t cid; 147 148 uint64_t *prp; 149 bus_addr_t prp_bus_addr; 150 }; 151 152 enum nvme_recovery { 153 RECOVERY_NONE = 0, /* Normal operations */ 154 RECOVERY_START, /* Deadline has passed, start recovering */ 155 RECOVERY_RESET, /* This pass, initiate reset of controller */ 156 RECOVERY_WAITING, /* waiting for the reset to complete */ 157 }; 158 struct nvme_qpair { 159 struct nvme_controller *ctrlr; 160 uint32_t id; 161 int domain; 162 int cpu; 163 164 uint16_t vector; 165 int rid; 166 struct resource *res; 167 void *tag; 168 169 struct callout timer; 170 sbintime_t deadline; 171 bool timer_armed; 172 enum nvme_recovery recovery_state; 173 174 uint32_t num_entries; 175 uint32_t num_trackers; 176 uint32_t sq_tdbl_off; 177 uint32_t cq_hdbl_off; 178 179 uint32_t phase; 180 uint32_t sq_head; 181 uint32_t sq_tail; 182 uint32_t cq_head; 183 184 int64_t num_cmds; 185 int64_t num_intr_handler_calls; 186 int64_t num_retries; 187 int64_t num_failures; 188 int64_t num_ignored; 189 190 struct nvme_command *cmd; 191 struct nvme_completion *cpl; 192 193 bus_dma_tag_t dma_tag; 194 bus_dma_tag_t dma_tag_payload; 195 196 bus_dmamap_t queuemem_map; 197 uint64_t cmd_bus_addr; 198 uint64_t cpl_bus_addr; 199 200 TAILQ_HEAD(, nvme_tracker) free_tr; 201 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 202 STAILQ_HEAD(, nvme_request) queued_req; 203 204 struct nvme_tracker **act_tr; 205 206 struct mtx_padalign lock; 207 208 } __aligned(CACHE_LINE_SIZE); 209 210 struct nvme_namespace { 211 struct nvme_controller *ctrlr; 212 struct nvme_namespace_data data; 213 uint32_t id; 214 uint32_t flags; 215 struct cdev *cdev; 216 void *cons_cookie[NVME_MAX_CONSUMERS]; 217 uint32_t boundary; 218 struct mtx lock; 219 }; 220 221 /* 222 * One of these per allocated PCI device. 223 */ 224 struct nvme_controller { 225 device_t dev; 226 227 struct mtx lock; 228 int domain; 229 uint32_t ready_timeout_in_ms; 230 uint32_t quirks; 231 #define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */ 232 #define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */ 233 #define QUIRK_INTEL_ALIGNMENT 4 /* Pre NVMe 1.3 performance alignment */ 234 #define QUIRK_AHCI 8 /* Attached via AHCI redirect */ 235 236 bus_space_tag_t bus_tag; 237 bus_space_handle_t bus_handle; 238 int resource_id; 239 struct resource *resource; 240 241 /* 242 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 243 * separate from the control registers which are in BAR 0/1. These 244 * members track the mapping of BAR 4/5 for that reason. 245 */ 246 int bar4_resource_id; 247 struct resource *bar4_resource; 248 249 int msi_count; 250 uint32_t enable_aborts; 251 252 uint32_t num_io_queues; 253 uint32_t max_hw_pend_io; 254 255 /* Fields for tracking progress during controller initialization. */ 256 struct intr_config_hook config_hook; 257 uint32_t ns_identified; 258 uint32_t queues_created; 259 260 struct task reset_task; 261 struct task fail_req_task; 262 struct taskqueue *taskqueue; 263 264 /* For shared legacy interrupt. */ 265 int rid; 266 struct resource *res; 267 void *tag; 268 269 /** maximum i/o size in bytes */ 270 uint32_t max_xfer_size; 271 272 /** LO and HI capacity mask */ 273 uint32_t cap_lo; 274 uint32_t cap_hi; 275 276 /** Page size and log2(page_size) - 12 that we're currently using */ 277 uint32_t page_size; 278 uint32_t mps; 279 280 /** interrupt coalescing time period (in microseconds) */ 281 uint32_t int_coal_time; 282 283 /** interrupt coalescing threshold */ 284 uint32_t int_coal_threshold; 285 286 /** timeout period in seconds */ 287 uint32_t timeout_period; 288 289 /** doorbell stride */ 290 uint32_t dstrd; 291 292 struct nvme_qpair adminq; 293 struct nvme_qpair *ioq; 294 295 struct nvme_registers *regs; 296 297 struct nvme_controller_data cdata; 298 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 299 300 struct cdev *cdev; 301 302 /** bit mask of event types currently enabled for async events */ 303 uint32_t async_event_config; 304 305 uint32_t num_aers; 306 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 307 308 void *cons_cookie[NVME_MAX_CONSUMERS]; 309 310 uint32_t is_resetting; 311 uint32_t is_initialized; 312 uint32_t notification_sent; 313 314 bool is_failed; 315 bool is_dying; 316 STAILQ_HEAD(, nvme_request) fail_req; 317 318 /* Host Memory Buffer */ 319 int hmb_nchunks; 320 size_t hmb_chunk; 321 bus_dma_tag_t hmb_tag; 322 struct nvme_hmb_chunk { 323 bus_dmamap_t hmbc_map; 324 void *hmbc_vaddr; 325 uint64_t hmbc_paddr; 326 } *hmb_chunks; 327 bus_dma_tag_t hmb_desc_tag; 328 bus_dmamap_t hmb_desc_map; 329 struct nvme_hmb_desc *hmb_desc_vaddr; 330 uint64_t hmb_desc_paddr; 331 }; 332 333 #define nvme_mmio_offsetof(reg) \ 334 offsetof(struct nvme_registers, reg) 335 336 #define nvme_mmio_read_4(sc, reg) \ 337 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 338 nvme_mmio_offsetof(reg)) 339 340 #define nvme_mmio_write_4(sc, reg, val) \ 341 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 342 nvme_mmio_offsetof(reg), val) 343 344 #define nvme_mmio_write_8(sc, reg, val) \ 345 do { \ 346 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 347 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 348 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 349 nvme_mmio_offsetof(reg)+4, \ 350 (val & 0xFFFFFFFF00000000ULL) >> 32); \ 351 } while (0); 352 353 #define nvme_printf(ctrlr, fmt, args...) \ 354 device_printf(ctrlr->dev, fmt, ##args) 355 356 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 357 358 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 359 void *payload, 360 nvme_cb_fn_t cb_fn, void *cb_arg); 361 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 362 uint32_t nsid, void *payload, 363 nvme_cb_fn_t cb_fn, void *cb_arg); 364 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 365 uint32_t microseconds, 366 uint32_t threshold, 367 nvme_cb_fn_t cb_fn, 368 void *cb_arg); 369 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 370 struct nvme_error_information_entry *payload, 371 uint32_t num_entries, /* 0 = max */ 372 nvme_cb_fn_t cb_fn, 373 void *cb_arg); 374 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 375 uint32_t nsid, 376 struct nvme_health_information_page *payload, 377 nvme_cb_fn_t cb_fn, 378 void *cb_arg); 379 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 380 struct nvme_firmware_page *payload, 381 nvme_cb_fn_t cb_fn, 382 void *cb_arg); 383 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 384 struct nvme_qpair *io_que, 385 nvme_cb_fn_t cb_fn, void *cb_arg); 386 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 387 struct nvme_qpair *io_que, 388 nvme_cb_fn_t cb_fn, void *cb_arg); 389 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 390 struct nvme_qpair *io_que, 391 nvme_cb_fn_t cb_fn, void *cb_arg); 392 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 393 struct nvme_qpair *io_que, 394 nvme_cb_fn_t cb_fn, void *cb_arg); 395 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 396 uint32_t num_queues, nvme_cb_fn_t cb_fn, 397 void *cb_arg); 398 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 399 uint32_t state, 400 nvme_cb_fn_t cb_fn, void *cb_arg); 401 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 402 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 403 404 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 405 406 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 407 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 408 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 409 void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 410 /* ctrlr defined as void * to allow use with config_intrhook. */ 411 void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 412 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 413 struct nvme_request *req); 414 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 415 struct nvme_request *req); 416 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 417 struct nvme_request *req); 418 419 int nvme_qpair_construct(struct nvme_qpair *qpair, 420 uint32_t num_entries, uint32_t num_trackers, 421 struct nvme_controller *ctrlr); 422 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 423 struct nvme_tracker *tr); 424 bool nvme_qpair_process_completions(struct nvme_qpair *qpair); 425 void nvme_qpair_submit_request(struct nvme_qpair *qpair, 426 struct nvme_request *req); 427 void nvme_qpair_reset(struct nvme_qpair *qpair); 428 void nvme_qpair_fail(struct nvme_qpair *qpair); 429 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 430 struct nvme_request *req, 431 uint32_t sct, uint32_t sc); 432 433 void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 434 void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 435 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 436 437 void nvme_io_qpair_enable(struct nvme_qpair *qpair); 438 void nvme_io_qpair_disable(struct nvme_qpair *qpair); 439 void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 440 441 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id, 442 struct nvme_controller *ctrlr); 443 void nvme_ns_destruct(struct nvme_namespace *ns); 444 445 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 446 447 void nvme_qpair_print_command(struct nvme_qpair *qpair, 448 struct nvme_command *cmd); 449 void nvme_qpair_print_completion(struct nvme_qpair *qpair, 450 struct nvme_completion *cpl); 451 452 int nvme_attach(device_t dev); 453 int nvme_shutdown(device_t dev); 454 int nvme_detach(device_t dev); 455 456 /* 457 * Wait for a command to complete using the nvme_completion_poll_cb. Used in 458 * limited contexts where the caller knows it's OK to block briefly while the 459 * command runs. The ISR will run the callback which will set status->done to 460 * true, usually within microseconds. If not, then after one second timeout 461 * handler should reset the controller and abort all outstanding requests 462 * including this polled one. If still not after ten seconds, then something is 463 * wrong with the driver, and panic is the only way to recover. 464 * 465 * Most commands using this interface aren't actual I/O to the drive's media so 466 * complete within a few microseconds. Adaptively spin for one tick to catch the 467 * vast majority of these without waiting for a tick plus scheduling delays. Since 468 * these are on startup, this drastically reduces startup time. 469 */ 470 static __inline 471 void 472 nvme_completion_poll(struct nvme_completion_poll_status *status) 473 { 474 int timeout = ticks + 10 * hz; 475 sbintime_t delta_t = SBT_1US; 476 477 while (!atomic_load_acq_int(&status->done)) { 478 if (timeout - ticks < 0) 479 panic("NVME polled command failed to complete within 10s."); 480 pause_sbt("nvme", delta_t, 0, C_PREL(1)); 481 delta_t = min(SBT_1MS, delta_t * 3 / 2); 482 } 483 } 484 485 static __inline void 486 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 487 { 488 uint64_t *bus_addr = (uint64_t *)arg; 489 490 KASSERT(nseg == 1, ("number of segments (%d) is not 1", nseg)); 491 if (error != 0) 492 printf("nvme_single_map err %d\n", error); 493 *bus_addr = seg[0].ds_addr; 494 } 495 496 static __inline struct nvme_request * 497 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 498 { 499 struct nvme_request *req; 500 501 req = malloc(sizeof(*req), M_NVME, M_NOWAIT | M_ZERO); 502 if (req != NULL) { 503 req->cb_fn = cb_fn; 504 req->cb_arg = cb_arg; 505 req->timeout = true; 506 } 507 return (req); 508 } 509 510 static __inline struct nvme_request * 511 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 512 nvme_cb_fn_t cb_fn, void *cb_arg) 513 { 514 struct nvme_request *req; 515 516 req = _nvme_allocate_request(cb_fn, cb_arg); 517 if (req != NULL) { 518 req->payload = memdesc_vaddr(payload, payload_size); 519 req->payload_valid = true; 520 } 521 return (req); 522 } 523 524 static __inline struct nvme_request * 525 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 526 { 527 struct nvme_request *req; 528 529 req = _nvme_allocate_request(cb_fn, cb_arg); 530 return (req); 531 } 532 533 static __inline struct nvme_request * 534 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 535 { 536 struct nvme_request *req; 537 538 req = _nvme_allocate_request(cb_fn, cb_arg); 539 if (req != NULL) { 540 req->payload = memdesc_bio(bio); 541 req->payload_valid = true; 542 } 543 return (req); 544 } 545 546 static __inline struct nvme_request * 547 nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg) 548 { 549 struct nvme_request *req; 550 551 req = _nvme_allocate_request(cb_fn, cb_arg); 552 if (req != NULL) { 553 req->payload = memdesc_ccb(ccb); 554 req->payload_valid = true; 555 } 556 557 return (req); 558 } 559 560 #define nvme_free_request(req) free(req, M_NVME) 561 562 void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 563 const struct nvme_completion *async_cpl, 564 uint32_t log_page_id, void *log_page_buffer, 565 uint32_t log_page_size); 566 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 567 void nvme_notify_new_controller(struct nvme_controller *ctrlr); 568 void nvme_notify_ns(struct nvme_controller *ctrlr, int nsid); 569 570 void nvme_ctrlr_shared_handler(void *arg); 571 void nvme_ctrlr_poll(struct nvme_controller *ctrlr); 572 573 int nvme_ctrlr_suspend(struct nvme_controller *ctrlr); 574 int nvme_ctrlr_resume(struct nvme_controller *ctrlr); 575 576 #endif /* __NVME_PRIVATE_H__ */ 577