1 /*- 2 * Copyright (c) 2002-2004 M. Warner Losh. 3 * Copyright (c) 2000-2001 Jonathan Chen. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 and 2000 31 * HAYAKAWA Koichi. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by HAYAKAWA Koichi. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for PCI to CardBus Bridge chips 61 * 62 * References: 63 * TI Datasheets: 64 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 65 * 66 * Written by Jonathan Chen <jon@freebsd.org> 67 * The author would like to acknowledge: 68 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 69 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 70 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 71 * * David Cross: Author of the initial ugly hack for a specific cardbus card 72 */ 73 74 #include <sys/cdefs.h> 75 __FBSDID("$FreeBSD$"); 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/proc.h> 80 #include <sys/condvar.h> 81 #include <sys/errno.h> 82 #include <sys/kernel.h> 83 #include <sys/lock.h> 84 #include <sys/malloc.h> 85 #include <sys/mutex.h> 86 #include <sys/sysctl.h> 87 #include <sys/kthread.h> 88 #include <sys/bus.h> 89 #include <machine/bus.h> 90 #include <sys/rman.h> 91 #include <machine/resource.h> 92 #include <sys/module.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 97 #include <dev/pccard/pccardreg.h> 98 #include <dev/pccard/pccardvar.h> 99 100 #include <dev/exca/excareg.h> 101 #include <dev/exca/excavar.h> 102 103 #include <dev/pccbb/pccbbreg.h> 104 #include <dev/pccbb/pccbbvar.h> 105 106 #include "power_if.h" 107 #include "card_if.h" 108 #include "pcib_if.h" 109 110 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 111 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 112 113 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 114 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 115 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 116 pci_write_config(DEV, REG, ( \ 117 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 118 119 static void cbb_chipinit(struct cbb_softc *sc); 120 static void cbb_pci_intr(void *arg); 121 122 static struct yenta_chipinfo { 123 uint32_t yc_id; 124 const char *yc_name; 125 int yc_chiptype; 126 } yc_chipsets[] = { 127 /* Texas Instruments chips */ 128 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 129 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 130 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 131 132 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 133 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 138 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 139 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 140 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 141 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 142 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 143 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 145 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 146 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 147 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX}, 158 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 162 163 /* ENE */ 164 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 165 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 166 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 167 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 168 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 169 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 170 171 /* Ricoh chips */ 172 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 173 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 174 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 175 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 176 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 177 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 178 179 /* Toshiba products */ 180 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 181 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 182 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 183 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 184 185 /* Cirrus Logic */ 186 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 187 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 188 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 189 190 /* 02Micro */ 191 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 192 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 193 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 194 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 195 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 196 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 197 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 198 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO}, 199 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO}, 200 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO}, 201 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO}, 202 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO}, 203 204 /* SMC */ 205 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS}, 206 207 /* sentinel */ 208 {0 /* null id */, "unknown", CB_UNKNOWN}, 209 }; 210 211 /************************************************************************/ 212 /* Probe/Attach */ 213 /************************************************************************/ 214 215 static int 216 cbb_chipset(uint32_t pci_id, const char **namep) 217 { 218 struct yenta_chipinfo *ycp; 219 220 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 221 continue; 222 if (namep != NULL) 223 *namep = ycp->yc_name; 224 return (ycp->yc_chiptype); 225 } 226 227 static int 228 cbb_pci_probe(device_t brdev) 229 { 230 const char *name; 231 uint32_t progif; 232 uint32_t subclass; 233 234 /* 235 * Do we know that we support the chipset? If so, then we 236 * accept the device. 237 */ 238 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 239 device_set_desc(brdev, name); 240 return (BUS_PROBE_DEFAULT); 241 } 242 243 /* 244 * We do support generic CardBus bridges. All that we've seen 245 * to date have progif 0 (the Yenta spec, and successors mandate 246 * this). 247 */ 248 subclass = pci_get_subclass(brdev); 249 progif = pci_get_progif(brdev); 250 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 251 device_set_desc(brdev, "PCI-CardBus Bridge"); 252 return (BUS_PROBE_DEFAULT); 253 } 254 return (ENXIO); 255 } 256 257 /* 258 * Still need this because the pci code only does power for type 0 259 * header devices. 260 */ 261 static void 262 cbb_powerstate_d0(device_t dev) 263 { 264 u_int32_t membase, irq; 265 266 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 267 /* Save important PCI config data. */ 268 membase = pci_read_config(dev, CBBR_SOCKBASE, 4); 269 irq = pci_read_config(dev, PCIR_INTLINE, 4); 270 271 /* Reset the power state. */ 272 device_printf(dev, "chip is in D%d power mode " 273 "-- setting to D0\n", pci_get_powerstate(dev)); 274 275 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 276 277 /* Restore PCI config data. */ 278 pci_write_config(dev, CBBR_SOCKBASE, membase, 4); 279 pci_write_config(dev, PCIR_INTLINE, irq, 4); 280 } 281 } 282 283 /* 284 * Print out the config space 285 */ 286 static void 287 cbb_print_config(device_t dev) 288 { 289 int i; 290 291 device_printf(dev, "PCI Configuration space:"); 292 for (i = 0; i < 256; i += 4) { 293 if (i % 16 == 0) 294 printf("\n 0x%02x: ", i); 295 printf("0x%08x ", pci_read_config(dev, i, 4)); 296 } 297 printf("\n"); 298 } 299 300 static int 301 cbb_pci_attach(device_t brdev) 302 { 303 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 304 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 305 struct sysctl_ctx_list *sctx; 306 struct sysctl_oid *soid; 307 int rid; 308 device_t parent; 309 uint32_t pribus; 310 311 parent = device_get_parent(brdev); 312 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 313 cv_init(&sc->cv, "cbb cv"); 314 cv_init(&sc->powercv, "cbb cv"); 315 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 316 sc->dev = brdev; 317 sc->cbdev = NULL; 318 sc->exca[0].pccarddev = NULL; 319 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1); 320 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 321 sc->pribus = pcib_get_bus(parent); 322 SLIST_INIT(&sc->rl); 323 cbb_powerstate_d0(brdev); 324 325 rid = CBBR_SOCKBASE; 326 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 327 RF_ACTIVE); 328 if (!sc->base_res) { 329 device_printf(brdev, "Could not map register memory\n"); 330 mtx_destroy(&sc->mtx); 331 cv_destroy(&sc->cv); 332 return (ENOMEM); 333 } else { 334 DEVPRINTF((brdev, "Found memory at %08lx\n", 335 rman_get_start(sc->base_res))); 336 } 337 338 sc->bst = rman_get_bustag(sc->base_res); 339 sc->bsh = rman_get_bushandle(sc->base_res); 340 exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 341 sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN; 342 sc->exca[0].chipset = EXCA_CARDBUS; 343 sc->chipinit = cbb_chipinit; 344 sc->chipinit(sc); 345 346 /*Sysctls*/ 347 sctx = device_get_sysctl_ctx(brdev); 348 soid = device_get_sysctl_tree(brdev); 349 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 350 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 351 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 352 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number"); 353 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 354 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number"); 355 356 /* 357 * This is a gross hack. We should be scanning the entire pci 358 * tree, assigning bus numbers in a way such that we (1) can 359 * reserve 1 extra bus just in case and (2) all sub busses 360 * are in an appropriate range. 361 */ 362 DEVPRINTF((brdev, "Secondary bus is %d\n", sc->secbus)); 363 pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1); 364 if (sc->secbus == 0 || sc->pribus != pribus) { 365 if (curr_bus_number <= sc->pribus) 366 curr_bus_number = sc->pribus + 1; 367 if (pribus != sc->pribus) { 368 DEVPRINTF((brdev, "Setting primary bus to %d\n", 369 sc->pribus)); 370 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 371 } 372 sc->secbus = curr_bus_number++; 373 sc->subbus = curr_bus_number++; 374 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", 375 sc->secbus, sc->subbus)); 376 pci_write_config(brdev, PCIR_SECBUS_2, sc->secbus, 1); 377 pci_write_config(brdev, PCIR_SUBBUS_2, sc->subbus, 1); 378 } 379 380 /* attach children */ 381 sc->cbdev = device_add_child(brdev, "cardbus", -1); 382 if (sc->cbdev == NULL) 383 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 384 else if (device_probe_and_attach(sc->cbdev) != 0) 385 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 386 387 sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1); 388 if (sc->exca[0].pccarddev == NULL) 389 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 390 else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0) 391 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 392 393 /* Map and establish the interrupt. */ 394 rid = 0; 395 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 396 RF_SHAREABLE | RF_ACTIVE); 397 if (sc->irq_res == NULL) { 398 device_printf(brdev, "Unable to map IRQ...\n"); 399 goto err; 400 } 401 402 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 403 NULL, cbb_pci_intr, sc, &sc->intrhand)) { 404 device_printf(brdev, "couldn't establish interrupt\n"); 405 goto err; 406 } 407 408 /* reset 16-bit pcmcia bus */ 409 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 410 411 /* turn off power */ 412 cbb_power(brdev, CARD_OFF); 413 414 /* CSC Interrupt: Card detect interrupt on */ 415 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 416 417 /* reset interrupt */ 418 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 419 420 if (bootverbose) 421 cbb_print_config(brdev); 422 423 /* Start the thread */ 424 if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 425 "%s event thread", device_get_nameunit(brdev))) { 426 device_printf(brdev, "unable to create event thread.\n"); 427 panic("cbb_create_event_thread"); 428 } 429 return (0); 430 err: 431 if (sc->irq_res) 432 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 433 if (sc->base_res) { 434 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 435 sc->base_res); 436 } 437 mtx_destroy(&sc->mtx); 438 cv_destroy(&sc->cv); 439 return (ENOMEM); 440 } 441 442 static void 443 cbb_chipinit(struct cbb_softc *sc) 444 { 445 uint32_t mux, sysctrl, reg; 446 447 /* Set CardBus latency timer */ 448 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20) 449 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1); 450 451 /* Set PCI latency timer */ 452 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 453 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 454 455 /* Enable memory access */ 456 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, 457 | PCIM_CMD_MEMEN 458 | PCIM_CMD_PORTEN 459 | PCIM_CMD_BUSMASTEREN, 2); 460 461 /* disable Legacy IO */ 462 switch (sc->chipset) { 463 case CB_RF5C46X: 464 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 465 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 466 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 467 break; 468 default: 469 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 470 break; 471 } 472 473 /* Use PCI interrupt for interrupt routing */ 474 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 475 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 476 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN), 477 | CBBM_BRIDGECTRL_WRITE_POST_EN, 478 2); 479 480 /* 481 * XXX this should be a function table, ala OLDCARD. This means 482 * that we could more easily support ISA interrupts for pccard 483 * cards if we had to. 484 */ 485 switch (sc->chipset) { 486 case CB_TI113X: 487 /* 488 * The TI 1031, TI 1130 and TI 1131 all require another bit 489 * be set to enable PCI routing of interrupts, and then 490 * a bit for each of the CSC and Function interrupts we 491 * want routed. 492 */ 493 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 494 | CBBM_CBCTRL_113X_PCI_INTR | 495 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 496 1); 497 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 498 & ~(CBBM_DEVCTRL_INT_SERIAL | 499 CBBM_DEVCTRL_INT_PCI), 1); 500 break; 501 case CB_TI12XX: 502 /* 503 * Some TI 12xx (and [14][45]xx) based pci cards 504 * sometimes have issues with the MFUNC register not 505 * being initialized due to a bad EEPROM on board. 506 * Laptops that this matters on have this register 507 * properly initialized. 508 * 509 * The TI125X parts have a different register. 510 */ 511 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 512 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 513 if (mux == 0) { 514 mux = (mux & ~CBBM_MFUNC_PIN0) | 515 CBBM_MFUNC_PIN0_INTA; 516 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 517 mux = (mux & ~CBBM_MFUNC_PIN1) | 518 CBBM_MFUNC_PIN1_INTB; 519 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 520 } 521 /*FALLTHROUGH*/ 522 case CB_TI125X: 523 /* 524 * Disable zoom video. Some machines initialize this 525 * improperly and exerpience has shown that this helps 526 * prevent strange behavior. 527 */ 528 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 529 break; 530 case CB_O2MICRO: 531 /* 532 * Issue #1: INT# generated at the same time as 533 * selected ISA IRQ. When IREQ# or STSCHG# is active, 534 * in addition to the ISA IRQ being generated, INT# 535 * will also be generated at the same time. 536 * 537 * Some of the older controllers have an issue in 538 * which the slot's PCI INT# will be asserted whenever 539 * IREQ# or STSCGH# is asserted even if ExCA registers 540 * 03h or 05h have an ISA IRQ selected. 541 * 542 * The fix for this issue, which will work for any 543 * controller (old or new), is to set ExCA registers 544 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 545 * These bits are undocumented. By setting this 546 * register (of each slot) to '1010xxxxb' a routing of 547 * IREQ# to INTC# and STSCHG# to INTC# is selected. 548 * Since INTC# isn't connected there will be no 549 * unexpected PCI INT when IREQ# or STSCHG# is active. 550 * However, INTA# (slot 0) or INTB# (slot 1) will 551 * still be correctly generated if NO ISA IRQ is 552 * selected (ExCA regs 03h or 05h are cleared). 553 */ 554 reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C); 555 reg = (reg & 0x0f) | 556 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 557 exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg); 558 break; 559 case CB_TOPIC97: 560 /* 561 * Disable Zoom Video, ToPIC 97, 100. 562 */ 563 pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1); 564 /* 565 * ToPIC 97, 100 566 * At offset 0xa1: INTERRUPT CONTROL register 567 * 0x1: Turn on INT interrupts. 568 */ 569 PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL, 570 | TOPIC97_INTCTRL_INTIRQSEL, 1); 571 /* 572 * ToPIC97, 100 573 * Need to assert support for low voltage cards 574 */ 575 exca_setb(&sc->exca[0], EXCA_TOPIC97_CTRL, 576 EXCA_TOPIC97_CTRL_LV_MASK); 577 goto topic_common; 578 case CB_TOPIC95: 579 /* 580 * SOCKETCTRL appears to be TOPIC 95/B specific 581 */ 582 PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL, 583 | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4); 584 585 topic_common:; 586 /* 587 * At offset 0xa0: SLOT CONTROL 588 * 0x80 Enable CardBus Functionality 589 * 0x40 Enable CardBus and PC Card registers 590 * 0x20 Lock ID in exca regs 591 * 0x10 Write protect ID in config regs 592 * Clear the rest of the bits, which defaults the slot 593 * in legacy mode to 0x3e0 and offset 0. (legacy 594 * mode is determined elsewhere) 595 */ 596 pci_write_config(sc->dev, TOPIC_SLOTCTRL, 597 TOPIC_SLOTCTRL_SLOTON | 598 TOPIC_SLOTCTRL_SLOTEN | 599 TOPIC_SLOTCTRL_ID_LOCK | 600 TOPIC_SLOTCTRL_ID_WP, 1); 601 602 /* 603 * At offset 0xa3 Card Detect Control Register 604 * 0x80 CARDBUS enbale 605 * 0x01 Cleared for hardware change detect 606 */ 607 PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC, 608 | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4); 609 break; 610 } 611 612 /* 613 * Need to tell ExCA registers to CSC interrupts route via PCI 614 * interrupts. There are two ways to do this. One is to set 615 * INTR_ENABLE and the other is to set CSC to 0. Since both 616 * methods are mutually compatible, we do both. 617 */ 618 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE); 619 exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0); 620 621 cbb_disable_func_intr(sc); 622 623 /* close all memory and io windows */ 624 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 625 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 626 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 627 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 628 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 629 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 630 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 631 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 632 } 633 634 static int 635 cbb_route_interrupt(device_t pcib, device_t dev, int pin) 636 { 637 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib); 638 639 return (rman_get_start(sc->irq_res)); 640 } 641 642 static int 643 cbb_pci_shutdown(device_t brdev) 644 { 645 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 646 647 /* 648 * Place the cards in reset, turn off the interrupts and power 649 * down the socket. 650 */ 651 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 652 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 653 cbb_set(sc, CBB_SOCKET_MASK, 0); 654 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); 655 cbb_power(brdev, CARD_OFF); 656 657 /* 658 * For paranoia, turn off all address decoding. Really not needed, 659 * it seems, but it can't hurt 660 */ 661 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0); 662 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 663 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 664 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 665 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 666 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 667 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 668 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 669 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 670 return (0); 671 } 672 673 static void 674 cbb_pci_intr(void *arg) 675 { 676 struct cbb_softc *sc = arg; 677 uint32_t sockevent; 678 679 /* 680 * Read the socket event. Sometimes, the theory goes, the PCI 681 * bus is so loaded that it cannot satisfy the read request, so 682 * we get garbage back from the following read. We have to filter 683 * out the garbage so that we don't spontaneously reset the card 684 * under high load. PCI isn't supposed to act like this. No doubt 685 * this is a bug in the PCI bridge chipset (or cbb brige) that's being 686 * used in certain amd64 laptops today. Work around the issue by 687 * assuming that any bits we don't know about being set means that 688 * we got garbage. 689 */ 690 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 691 if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) { 692 /* ack the interrupt */ 693 cbb_set(sc, CBB_SOCKET_EVENT, sockevent); 694 695 /* 696 * If anything has happened to the socket, we assume that 697 * the card is no longer OK, and we shouldn't call its 698 * ISR. We set CARD_OK as soon as we've attached the 699 * card. This helps in a noisy eject, which happens 700 * all too often when users are ejecting their PC Cards. 701 * 702 * We use this method in preference to checking to see if 703 * the card is still there because the check suffers from 704 * a race condition in the bouncing case. Prior versions 705 * of the pccard software used a similar trick and achieved 706 * excellent results. 707 */ 708 if (sockevent & CBB_SOCKET_EVENT_CD) { 709 mtx_lock(&sc->mtx); 710 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 711 sc->flags &= ~CBB_CARD_OK; 712 cbb_disable_func_intr(sc); 713 cv_signal(&sc->cv); 714 mtx_unlock(&sc->mtx); 715 } 716 /* 717 * If we get a power interrupt, wakeup anybody that might 718 * be waiting for one. 719 */ 720 if (sockevent & CBB_SOCKET_EVENT_POWER) { 721 mtx_lock(&sc->mtx); 722 sc->powerintr++; 723 cv_signal(&sc->powercv); 724 mtx_unlock(&sc->mtx); 725 } 726 } 727 /* 728 * Some chips also require us to read the old ExCA registe for 729 * card status change when we route CSC vis PCI. This isn't supposed 730 * to be required, but it clears the interrupt state on some chipsets. 731 * Maybe there's a setting that would obviate its need. Maybe we 732 * should test the status bits and deal with them, but so far we've 733 * not found any machines that don't also give us the socket status 734 * indication above. 735 * 736 * We have to call this unconditionally because some bridges deliver 737 * the event independent of the CBB_SOCKET_EVENT_CD above. 738 */ 739 exca_getb(&sc->exca[0], EXCA_CSC); 740 } 741 742 /************************************************************************/ 743 /* PCI compat methods */ 744 /************************************************************************/ 745 746 static int 747 cbb_maxslots(device_t brdev) 748 { 749 return (0); 750 } 751 752 static uint32_t 753 cbb_read_config(device_t brdev, int b, int s, int f, int reg, int width) 754 { 755 uint32_t rv; 756 757 /* 758 * Pass through to the next ppb up the chain (i.e. our grandparent). 759 */ 760 rv = PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 761 b, s, f, reg, width); 762 return (rv); 763 } 764 765 static void 766 cbb_write_config(device_t brdev, int b, int s, int f, int reg, uint32_t val, 767 int width) 768 { 769 /* 770 * Pass through to the next ppb up the chain (i.e. our grandparent). 771 */ 772 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 773 b, s, f, reg, val, width); 774 } 775 776 static device_method_t cbb_methods[] = { 777 /* Device interface */ 778 DEVMETHOD(device_probe, cbb_pci_probe), 779 DEVMETHOD(device_attach, cbb_pci_attach), 780 DEVMETHOD(device_detach, cbb_detach), 781 DEVMETHOD(device_shutdown, cbb_pci_shutdown), 782 DEVMETHOD(device_suspend, cbb_suspend), 783 DEVMETHOD(device_resume, cbb_resume), 784 785 /* bus methods */ 786 DEVMETHOD(bus_print_child, bus_generic_print_child), 787 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 788 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 789 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 790 DEVMETHOD(bus_release_resource, cbb_release_resource), 791 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 792 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 793 DEVMETHOD(bus_driver_added, cbb_driver_added), 794 DEVMETHOD(bus_child_detached, cbb_child_detached), 795 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 796 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 797 DEVMETHOD(bus_child_present, cbb_child_present), 798 799 /* 16-bit card interface */ 800 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 801 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 802 803 /* power interface */ 804 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 805 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 806 807 /* pcib compatibility interface */ 808 DEVMETHOD(pcib_maxslots, cbb_maxslots), 809 DEVMETHOD(pcib_read_config, cbb_read_config), 810 DEVMETHOD(pcib_write_config, cbb_write_config), 811 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt), 812 813 {0,0} 814 }; 815 816 static driver_t cbb_driver = { 817 "cbb", 818 cbb_methods, 819 sizeof(struct cbb_softc) 820 }; 821 822 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 823 MODULE_DEPEND(cbb, exca, 1, 1, 1); 824