1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2004 M. Warner Losh. 5 * Copyright (c) 2000-2001 Jonathan Chen. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 /*- 32 * Copyright (c) 1998, 1999 and 2000 33 * HAYAKAWA Koichi. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by HAYAKAWA Koichi. 46 * 4. The name of the author may not be used to endorse or promote products 47 * derived from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Driver for PCI to CardBus Bridge chips 63 * 64 * References: 65 * TI Datasheets: 66 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 67 * 68 * Written by Jonathan Chen <jon@freebsd.org> 69 * The author would like to acknowledge: 70 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 71 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 72 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 73 * * David Cross: Author of the initial ugly hack for a specific cardbus card 74 */ 75 76 #include <sys/cdefs.h> 77 __FBSDID("$FreeBSD$"); 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/proc.h> 82 #include <sys/condvar.h> 83 #include <sys/errno.h> 84 #include <sys/kernel.h> 85 #include <sys/lock.h> 86 #include <sys/malloc.h> 87 #include <sys/mutex.h> 88 #include <sys/sysctl.h> 89 #include <sys/kthread.h> 90 #include <sys/bus.h> 91 #include <machine/bus.h> 92 #include <sys/rman.h> 93 #include <machine/resource.h> 94 #include <sys/module.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcib_private.h> 99 100 #include <dev/pccard/pccardreg.h> 101 #include <dev/pccard/pccardvar.h> 102 103 #include <dev/exca/excareg.h> 104 #include <dev/exca/excavar.h> 105 106 #include <dev/pccbb/pccbbreg.h> 107 #include <dev/pccbb/pccbbvar.h> 108 109 #include "power_if.h" 110 #include "card_if.h" 111 #include "pcib_if.h" 112 113 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 114 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 115 116 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 117 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 118 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 119 pci_write_config(DEV, REG, ( \ 120 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 121 122 static void cbb_chipinit(struct cbb_softc *sc); 123 static int cbb_pci_filt(void *arg); 124 125 static struct yenta_chipinfo { 126 uint32_t yc_id; 127 const char *yc_name; 128 int yc_chiptype; 129 } yc_chipsets[] = { 130 /* Texas Instruments chips */ 131 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 132 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 133 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 134 135 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 137 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 138 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 139 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 140 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 141 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 142 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 143 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 145 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 147 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 149 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 158 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX}, 161 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 162 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 163 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 164 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 165 166 /* ENE */ 167 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 168 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 169 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 170 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 171 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 172 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 173 174 /* Ricoh chips */ 175 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 176 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 177 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 178 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 179 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 180 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 181 182 /* Toshiba products */ 183 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 184 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 185 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 186 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 187 188 /* Cirrus Logic */ 189 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 190 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 191 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 192 193 /* 02Micro */ 194 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 195 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 196 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 197 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 198 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 199 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 200 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 201 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO}, 202 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO}, 203 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO}, 204 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO}, 205 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO}, 206 207 /* SMC */ 208 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS}, 209 210 /* sentinel */ 211 {0 /* null id */, "unknown", CB_UNKNOWN}, 212 }; 213 214 /************************************************************************/ 215 /* Probe/Attach */ 216 /************************************************************************/ 217 218 static int 219 cbb_chipset(uint32_t pci_id, const char **namep) 220 { 221 struct yenta_chipinfo *ycp; 222 223 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 224 continue; 225 if (namep != NULL) 226 *namep = ycp->yc_name; 227 return (ycp->yc_chiptype); 228 } 229 230 static int 231 cbb_pci_probe(device_t brdev) 232 { 233 const char *name; 234 uint32_t progif; 235 uint32_t baseclass; 236 uint32_t subclass; 237 238 /* 239 * Do we know that we support the chipset? If so, then we 240 * accept the device. 241 */ 242 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 243 device_set_desc(brdev, name); 244 return (BUS_PROBE_DEFAULT); 245 } 246 247 /* 248 * We do support generic CardBus bridges. All that we've seen 249 * to date have progif 0 (the Yenta spec, and successors mandate 250 * this). 251 */ 252 baseclass = pci_get_class(brdev); 253 subclass = pci_get_subclass(brdev); 254 progif = pci_get_progif(brdev); 255 if (baseclass == PCIC_BRIDGE && 256 subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 257 device_set_desc(brdev, "PCI-CardBus Bridge"); 258 return (BUS_PROBE_GENERIC); 259 } 260 return (ENXIO); 261 } 262 263 /* 264 * Print out the config space 265 */ 266 static void 267 cbb_print_config(device_t dev) 268 { 269 int i; 270 271 device_printf(dev, "PCI Configuration space:"); 272 for (i = 0; i < 256; i += 4) { 273 if (i % 16 == 0) 274 printf("\n 0x%02x: ", i); 275 printf("0x%08x ", pci_read_config(dev, i, 4)); 276 } 277 printf("\n"); 278 } 279 280 static int 281 cbb_pci_attach(device_t brdev) 282 { 283 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 284 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 285 uint32_t pribus; 286 #endif 287 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 288 struct sysctl_ctx_list *sctx; 289 struct sysctl_oid *soid; 290 int rid; 291 device_t parent; 292 293 parent = device_get_parent(brdev); 294 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 295 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 296 sc->dev = brdev; 297 sc->cbdev = NULL; 298 sc->exca[0].pccarddev = NULL; 299 sc->domain = pci_get_domain(brdev); 300 sc->pribus = pcib_get_bus(parent); 301 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 302 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 303 pcib_setup_secbus(brdev, &sc->bus, 1); 304 #else 305 sc->bus.sec = pci_read_config(brdev, PCIR_SECBUS_2, 1); 306 sc->bus.sub = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 307 #endif 308 SLIST_INIT(&sc->rl); 309 310 rid = CBBR_SOCKBASE; 311 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 312 RF_ACTIVE); 313 if (!sc->base_res) { 314 device_printf(brdev, "Could not map register memory\n"); 315 mtx_destroy(&sc->mtx); 316 return (ENOMEM); 317 } else { 318 DEVPRINTF((brdev, "Found memory at %jx\n", 319 rman_get_start(sc->base_res))); 320 } 321 322 sc->bst = rman_get_bustag(sc->base_res); 323 sc->bsh = rman_get_bushandle(sc->base_res); 324 exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 325 sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN; 326 sc->exca[0].chipset = EXCA_CARDBUS; 327 sc->chipinit = cbb_chipinit; 328 sc->chipinit(sc); 329 330 /*Sysctls*/ 331 sctx = device_get_sysctl_ctx(brdev); 332 soid = device_get_sysctl_tree(brdev); 333 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 334 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 335 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 336 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 337 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 338 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 339 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 340 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 341 #if 0 342 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory", 343 CTLFLAG_RD, &sc->subbus, 0, "Memory window open"); 344 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem", 345 CTLFLAG_RD, &sc->subbus, 0, "Prefetch memory window open"); 346 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1", 347 CTLFLAG_RD, &sc->subbus, 0, "io range 1 open"); 348 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2", 349 CTLFLAG_RD, &sc->subbus, 0, "io range 2 open"); 350 #endif 351 352 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 353 /* 354 * This is a gross hack. We should be scanning the entire pci 355 * tree, assigning bus numbers in a way such that we (1) can 356 * reserve 1 extra bus just in case and (2) all sub buses 357 * are in an appropriate range. 358 */ 359 DEVPRINTF((brdev, "Secondary bus is %d\n", sc->bus.sec)); 360 pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1); 361 if (sc->bus.sec == 0 || sc->pribus != pribus) { 362 if (curr_bus_number <= sc->pribus) 363 curr_bus_number = sc->pribus + 1; 364 if (pribus != sc->pribus) { 365 DEVPRINTF((brdev, "Setting primary bus to %d\n", 366 sc->pribus)); 367 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 368 } 369 sc->bus.sec = curr_bus_number++; 370 sc->bus.sub = curr_bus_number++; 371 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", 372 sc->bus.sec, sc->bus.sub)); 373 pci_write_config(brdev, PCIR_SECBUS_2, sc->bus.sec, 1); 374 pci_write_config(brdev, PCIR_SUBBUS_2, sc->bus.sub, 1); 375 } 376 #endif 377 378 /* attach children */ 379 sc->cbdev = device_add_child(brdev, "cardbus", -1); 380 if (sc->cbdev == NULL) 381 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 382 else if (device_probe_and_attach(sc->cbdev) != 0) 383 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 384 385 sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1); 386 if (sc->exca[0].pccarddev == NULL) 387 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); 388 else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0) 389 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); 390 391 /* Map and establish the interrupt. */ 392 rid = 0; 393 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 394 RF_SHAREABLE | RF_ACTIVE); 395 if (sc->irq_res == NULL) { 396 device_printf(brdev, "Unable to map IRQ...\n"); 397 goto err; 398 } 399 400 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 401 cbb_pci_filt, NULL, sc, &sc->intrhand)) { 402 device_printf(brdev, "couldn't establish interrupt\n"); 403 goto err; 404 } 405 406 /* reset 16-bit pcmcia bus */ 407 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 408 409 /* turn off power */ 410 cbb_power(brdev, CARD_OFF); 411 412 /* CSC Interrupt: Card detect interrupt on */ 413 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 414 415 /* reset interrupt */ 416 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 417 418 if (bootverbose) 419 cbb_print_config(brdev); 420 421 /* Start the thread */ 422 if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 423 "%s event thread", device_get_nameunit(brdev))) { 424 device_printf(brdev, "unable to create event thread.\n"); 425 panic("cbb_create_event_thread"); 426 } 427 sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev)); 428 return (0); 429 err: 430 if (sc->irq_res) 431 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 432 if (sc->base_res) { 433 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 434 sc->base_res); 435 } 436 mtx_destroy(&sc->mtx); 437 return (ENOMEM); 438 } 439 440 static int 441 cbb_pci_detach(device_t brdev) 442 { 443 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 444 struct cbb_softc *sc = device_get_softc(brdev); 445 #endif 446 int error; 447 448 error = cbb_detach(brdev); 449 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 450 if (error == 0) 451 pcib_free_secbus(brdev, &sc->bus); 452 #endif 453 return (error); 454 } 455 456 static void 457 cbb_chipinit(struct cbb_softc *sc) 458 { 459 uint32_t mux, sysctrl, reg; 460 461 /* Set CardBus latency timer */ 462 if (pci_read_config(sc->dev, PCIR_SECLAT_2, 1) < 0x20) 463 pci_write_config(sc->dev, PCIR_SECLAT_2, 0x20, 1); 464 465 /* Set PCI latency timer */ 466 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 467 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 468 469 /* Enable DMA, memory access for this card and I/O access for children */ 470 pci_enable_busmaster(sc->dev); 471 pci_enable_io(sc->dev, SYS_RES_IOPORT); 472 pci_enable_io(sc->dev, SYS_RES_MEMORY); 473 474 /* disable Legacy IO */ 475 switch (sc->chipset) { 476 case CB_RF5C46X: 477 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 478 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 479 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 480 break; 481 default: 482 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 483 break; 484 } 485 486 /* Use PCI interrupt for interrupt routing */ 487 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 488 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 489 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN), 490 | CBBM_BRIDGECTRL_WRITE_POST_EN, 491 2); 492 493 /* 494 * XXX this should be a function table, ala OLDCARD. This means 495 * that we could more easily support ISA interrupts for pccard 496 * cards if we had to. 497 */ 498 switch (sc->chipset) { 499 case CB_TI113X: 500 /* 501 * The TI 1031, TI 1130 and TI 1131 all require another bit 502 * be set to enable PCI routing of interrupts, and then 503 * a bit for each of the CSC and Function interrupts we 504 * want routed. 505 */ 506 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 507 | CBBM_CBCTRL_113X_PCI_INTR | 508 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 509 1); 510 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 511 & ~(CBBM_DEVCTRL_INT_SERIAL | 512 CBBM_DEVCTRL_INT_PCI), 1); 513 break; 514 case CB_TI12XX: 515 /* 516 * Some TI 12xx (and [14][45]xx) based pci cards 517 * sometimes have issues with the MFUNC register not 518 * being initialized due to a bad EEPROM on board. 519 * Laptops that this matters on have this register 520 * properly initialized. 521 * 522 * The TI125X parts have a different register. 523 * 524 * Note: Only the lower two nibbles matter. When set 525 * to 0, the MFUNC{0,1} pins are GPIO, which isn't 526 * going to work out too well because we specifically 527 * program these parts to parallel interrupt signalling 528 * elsewhere. We preserve the upper bits of this 529 * register since changing them have subtle side effects 530 * for different variants of the card and are 531 * extremely difficult to exaustively test. 532 * 533 * Also, the TI 1510/1520 changed the default for the MFUNC 534 * register from 0x0 to 0x1000 to enable IRQSER by default. 535 * We want to be careful to avoid overriding that, and the 536 * below test will do that. Should this check prove to be 537 * too permissive, we should just check against 0 and 0x1000 538 * and not touch it otherwise. 539 */ 540 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 541 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 542 if ((mux & (CBBM_MFUNC_PIN0 | CBBM_MFUNC_PIN1)) == 0) { 543 mux = (mux & ~CBBM_MFUNC_PIN0) | 544 CBBM_MFUNC_PIN0_INTA; 545 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 546 mux = (mux & ~CBBM_MFUNC_PIN1) | 547 CBBM_MFUNC_PIN1_INTB; 548 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 549 } 550 /*FALLTHROUGH*/ 551 case CB_TI125X: 552 /* 553 * Disable zoom video. Some machines initialize this 554 * improperly and exerpience has shown that this helps 555 * prevent strange behavior. We don't support zoom 556 * video anyway, so no harm can come from this. 557 */ 558 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 559 break; 560 case CB_O2MICRO: 561 /* 562 * Issue #1: INT# generated at the same time as 563 * selected ISA IRQ. When IREQ# or STSCHG# is active, 564 * in addition to the ISA IRQ being generated, INT# 565 * will also be generated at the same time. 566 * 567 * Some of the older controllers have an issue in 568 * which the slot's PCI INT# will be asserted whenever 569 * IREQ# or STSCGH# is asserted even if ExCA registers 570 * 03h or 05h have an ISA IRQ selected. 571 * 572 * The fix for this issue, which will work for any 573 * controller (old or new), is to set ExCA registers 574 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 575 * These bits are undocumented. By setting this 576 * register (of each slot) to '1010xxxxb' a routing of 577 * IREQ# to INTC# and STSCHG# to INTC# is selected. 578 * Since INTC# isn't connected there will be no 579 * unexpected PCI INT when IREQ# or STSCHG# is active. 580 * However, INTA# (slot 0) or INTB# (slot 1) will 581 * still be correctly generated if NO ISA IRQ is 582 * selected (ExCA regs 03h or 05h are cleared). 583 */ 584 reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C); 585 reg = (reg & 0x0f) | 586 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 587 exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg); 588 break; 589 case CB_TOPIC97: 590 /* 591 * Disable Zoom Video, ToPIC 97, 100. 592 */ 593 pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1); 594 /* 595 * ToPIC 97, 100 596 * At offset 0xa1: INTERRUPT CONTROL register 597 * 0x1: Turn on INT interrupts. 598 */ 599 PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL, 600 | TOPIC97_INTCTRL_INTIRQSEL, 1); 601 /* 602 * ToPIC97, 100 603 * Need to assert support for low voltage cards 604 */ 605 exca_setb(&sc->exca[0], EXCA_TOPIC97_CTRL, 606 EXCA_TOPIC97_CTRL_LV_MASK); 607 goto topic_common; 608 case CB_TOPIC95: 609 /* 610 * SOCKETCTRL appears to be TOPIC 95/B specific 611 */ 612 PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL, 613 | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4); 614 615 topic_common:; 616 /* 617 * At offset 0xa0: SLOT CONTROL 618 * 0x80 Enable CardBus Functionality 619 * 0x40 Enable CardBus and PC Card registers 620 * 0x20 Lock ID in exca regs 621 * 0x10 Write protect ID in config regs 622 * Clear the rest of the bits, which defaults the slot 623 * in legacy mode to 0x3e0 and offset 0. (legacy 624 * mode is determined elsewhere) 625 */ 626 pci_write_config(sc->dev, TOPIC_SLOTCTRL, 627 TOPIC_SLOTCTRL_SLOTON | 628 TOPIC_SLOTCTRL_SLOTEN | 629 TOPIC_SLOTCTRL_ID_LOCK | 630 TOPIC_SLOTCTRL_ID_WP, 1); 631 632 /* 633 * At offset 0xa3 Card Detect Control Register 634 * 0x80 CARDBUS enbale 635 * 0x01 Cleared for hardware change detect 636 */ 637 PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC, 638 | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4); 639 break; 640 } 641 642 /* 643 * Need to tell ExCA registers to CSC interrupts route via PCI 644 * interrupts. There are two ways to do this. One is to set 645 * INTR_ENABLE and the other is to set CSC to 0. Since both 646 * methods are mutually compatible, we do both. 647 */ 648 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE); 649 exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0); 650 651 cbb_disable_func_intr(sc); 652 653 /* close all memory and io windows */ 654 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 655 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 656 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 657 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 658 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 659 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 660 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 661 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 662 } 663 664 static int 665 cbb_route_interrupt(device_t pcib, device_t dev, int pin) 666 { 667 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib); 668 669 return (rman_get_start(sc->irq_res)); 670 } 671 672 static int 673 cbb_pci_shutdown(device_t brdev) 674 { 675 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 676 677 /* 678 * We're about to pull the rug out from the card, so mark it as 679 * gone to prevent harm. 680 */ 681 sc->cardok = 0; 682 683 /* 684 * Place the cards in reset, turn off the interrupts and power 685 * down the socket. 686 */ 687 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 688 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET); 689 cbb_set(sc, CBB_SOCKET_MASK, 0); 690 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); 691 cbb_power(brdev, CARD_OFF); 692 693 /* 694 * For paranoia, turn off all address decoding. Really not needed, 695 * it seems, but it can't hurt 696 */ 697 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0); 698 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 699 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 700 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 701 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 702 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 703 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 704 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 705 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 706 return (0); 707 } 708 709 static int 710 cbb_pci_filt(void *arg) 711 { 712 struct cbb_softc *sc = arg; 713 uint32_t sockevent; 714 uint8_t csc; 715 int retval = FILTER_STRAY; 716 717 /* 718 * Some chips also require us to read the old ExCA registe for card 719 * status change when we route CSC vis PCI. This isn't supposed to be 720 * required, but it clears the interrupt state on some chipsets. 721 * Maybe there's a setting that would obviate its need. Maybe we 722 * should test the status bits and deal with them, but so far we've 723 * not found any machines that don't also give us the socket status 724 * indication above. 725 * 726 * This call used to be unconditional. However, further research 727 * suggests that we hit this condition when the card READY interrupt 728 * fired. So now we only read it for 16-bit cards, and we only claim 729 * the interrupt if READY is set. If this still causes problems, then 730 * the next step would be to read this if we have a 16-bit card *OR* 731 * we have no card. We treat the READY signal as if it were the power 732 * completion signal. Some bridges may double signal things here, bit 733 * signalling twice should be OK since we only sleep on the powerintr 734 * in one place and a double wakeup would be benign there. 735 */ 736 if (sc->flags & CBB_16BIT_CARD) { 737 csc = exca_getb(&sc->exca[0], EXCA_CSC); 738 if (csc & EXCA_CSC_READY) { 739 atomic_add_int(&sc->powerintr, 1); 740 wakeup((void *)&sc->powerintr); 741 retval = FILTER_HANDLED; 742 } 743 } 744 745 /* 746 * Read the socket event. Sometimes, the theory goes, the PCI bus is 747 * so loaded that it cannot satisfy the read request, so we get 748 * garbage back from the following read. We have to filter out the 749 * garbage so that we don't spontaneously reset the card under high 750 * load. PCI isn't supposed to act like this. No doubt this is a bug 751 * in the PCI bridge chipset (or cbb brige) that's being used in 752 * certain amd64 laptops today. Work around the issue by assuming 753 * that any bits we don't know about being set means that we got 754 * garbage. 755 */ 756 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 757 if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) { 758 /* 759 * If anything has happened to the socket, we assume that the 760 * card is no longer OK, and we shouldn't call its ISR. We 761 * set cardok as soon as we've attached the card. This helps 762 * in a noisy eject, which happens all too often when users 763 * are ejecting their PC Cards. 764 * 765 * We use this method in preference to checking to see if the 766 * card is still there because the check suffers from a race 767 * condition in the bouncing case. 768 */ 769 #define DELTA (CBB_SOCKET_MASK_CD) 770 if (sockevent & DELTA) { 771 cbb_clrb(sc, CBB_SOCKET_MASK, DELTA); 772 cbb_set(sc, CBB_SOCKET_EVENT, DELTA); 773 sc->cardok = 0; 774 cbb_disable_func_intr(sc); 775 wakeup(&sc->intrhand); 776 } 777 #undef DELTA 778 779 /* 780 * Wakeup anybody waiting for a power interrupt. We have to 781 * use atomic_add_int for wakups on other cores. 782 */ 783 if (sockevent & CBB_SOCKET_EVENT_POWER) { 784 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_EVENT_POWER); 785 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_POWER); 786 atomic_add_int(&sc->powerintr, 1); 787 wakeup((void *)&sc->powerintr); 788 } 789 790 /* 791 * Status change interrupts aren't presently used in the 792 * rest of the driver. For now, just ACK them. 793 */ 794 if (sockevent & CBB_SOCKET_EVENT_CSTS) 795 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS); 796 retval = FILTER_HANDLED; 797 } 798 return retval; 799 } 800 801 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 802 static struct resource * 803 cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 804 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 805 { 806 struct cbb_softc *sc; 807 808 sc = device_get_softc(bus); 809 if (type == PCI_RES_BUS) 810 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 811 count, flags)); 812 return (cbb_alloc_resource(bus, child, type, rid, start, end, count, 813 flags)); 814 } 815 816 static int 817 cbb_pci_adjust_resource(device_t bus, device_t child, int type, 818 struct resource *r, rman_res_t start, rman_res_t end) 819 { 820 struct cbb_softc *sc; 821 822 sc = device_get_softc(bus); 823 if (type == PCI_RES_BUS) { 824 if (!rman_is_region_manager(r, &sc->bus.rman)) 825 return (EINVAL); 826 return (rman_adjust_resource(r, start, end)); 827 } 828 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 829 } 830 831 static int 832 cbb_pci_release_resource(device_t bus, device_t child, int type, int rid, 833 struct resource *r) 834 { 835 struct cbb_softc *sc; 836 int error; 837 838 sc = device_get_softc(bus); 839 if (type == PCI_RES_BUS) { 840 if (!rman_is_region_manager(r, &sc->bus.rman)) 841 return (EINVAL); 842 if (rman_get_flags(r) & RF_ACTIVE) { 843 error = bus_deactivate_resource(child, type, rid, r); 844 if (error) 845 return (error); 846 } 847 return (rman_release_resource(r)); 848 } 849 return (cbb_release_resource(bus, child, type, rid, r)); 850 } 851 #endif 852 853 /************************************************************************/ 854 /* PCI compat methods */ 855 /************************************************************************/ 856 857 static int 858 cbb_maxslots(device_t brdev) 859 { 860 return (0); 861 } 862 863 static uint32_t 864 cbb_read_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, int width) 865 { 866 /* 867 * Pass through to the next ppb up the chain (i.e. our grandparent). 868 */ 869 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 870 b, s, f, reg, width)); 871 } 872 873 static void 874 cbb_write_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, 875 int width) 876 { 877 /* 878 * Pass through to the next ppb up the chain (i.e. our grandparent). 879 */ 880 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 881 b, s, f, reg, val, width); 882 } 883 884 static int 885 cbb_pci_suspend(device_t brdev) 886 { 887 int error = 0; 888 struct cbb_softc *sc = device_get_softc(brdev); 889 890 error = bus_generic_suspend(brdev); 891 if (error != 0) 892 return (error); 893 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 894 sc->cardok = 0; /* Card is bogus now */ 895 return (0); 896 } 897 898 static int 899 cbb_pci_resume(device_t brdev) 900 { 901 int error = 0; 902 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 903 uint32_t tmp; 904 905 /* 906 * In the APM and early ACPI era, BIOSes saved the PCI config 907 * registers. As chips became more complicated, that functionality moved 908 * into the ACPI code / tables. We must therefore, restore the settings 909 * we made here to make sure the device come back. Transitions to Dx 910 * from D0 and back to D0 cause the bridge to lose its config space, so 911 * all the bus mappings and such are preserved. 912 * 913 * The PCI layer handles standard PCI registers like the 914 * command register and BARs, but cbb-specific registers are 915 * handled here. 916 */ 917 sc->chipinit(sc); 918 919 /* reset interrupt -- Do we really need to do this? */ 920 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 921 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 922 923 /* CSC Interrupt: Card detect interrupt on */ 924 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 925 926 /* Signal the thread to wakeup. */ 927 wakeup(&sc->intrhand); 928 929 error = bus_generic_resume(brdev); 930 931 return (error); 932 } 933 934 static device_method_t cbb_methods[] = { 935 /* Device interface */ 936 DEVMETHOD(device_probe, cbb_pci_probe), 937 DEVMETHOD(device_attach, cbb_pci_attach), 938 DEVMETHOD(device_detach, cbb_pci_detach), 939 DEVMETHOD(device_shutdown, cbb_pci_shutdown), 940 DEVMETHOD(device_suspend, cbb_pci_suspend), 941 DEVMETHOD(device_resume, cbb_pci_resume), 942 943 /* bus methods */ 944 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 945 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 946 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 947 DEVMETHOD(bus_alloc_resource, cbb_pci_alloc_resource), 948 DEVMETHOD(bus_adjust_resource, cbb_pci_adjust_resource), 949 DEVMETHOD(bus_release_resource, cbb_pci_release_resource), 950 #else 951 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 952 DEVMETHOD(bus_release_resource, cbb_release_resource), 953 #endif 954 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 955 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 956 DEVMETHOD(bus_driver_added, cbb_driver_added), 957 DEVMETHOD(bus_child_detached, cbb_child_detached), 958 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 959 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 960 DEVMETHOD(bus_child_present, cbb_child_present), 961 962 /* 16-bit card interface */ 963 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 964 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 965 966 /* power interface */ 967 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 968 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 969 970 /* pcib compatibility interface */ 971 DEVMETHOD(pcib_maxslots, cbb_maxslots), 972 DEVMETHOD(pcib_read_config, cbb_read_config), 973 DEVMETHOD(pcib_write_config, cbb_write_config), 974 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt), 975 976 DEVMETHOD_END 977 }; 978 979 static driver_t cbb_driver = { 980 "cbb", 981 cbb_methods, 982 sizeof(struct cbb_softc) 983 }; 984 985 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); 986 MODULE_DEPEND(cbb, exca, 1, 1, 1); 987