1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2000,2001 Jonathan Chen. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Copyright (c) 1998, 1999 and 2000 33 * HAYAKAWA Koichi. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by HAYAKAWA Koichi. 46 * 4. The name of the author may not be used to endorse or promote products 47 * derived from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Register definitions for PCI to Cardbus Bridge chips 63 */ 64 65 66 /* PCI header registers */ 67 #define CBBR_SOCKBASE 0x10 /* len=4 */ 68 69 #define CBBR_MEMBASE0 0x1c /* len=4 */ 70 #define CBBR_MEMLIMIT0 0x20 /* len=4 */ 71 #define CBBR_MEMBASE1 0x24 /* len=4 */ 72 #define CBBR_MEMLIMIT1 0x28 /* len=4 */ 73 #define CBBR_IOBASE0 0x2c /* len=4 */ 74 #define CBBR_IOLIMIT0 0x30 /* len=4 */ 75 #define CBBR_IOBASE1 0x34 /* len=4 */ 76 #define CBBR_IOLIMIT1 0x38 /* len=4 */ 77 #define CBB_MEMALIGN 4096 78 #define CBB_MEMALIGN_BITS 12 79 #define CBB_IOALIGN 4 80 #define CBB_IOALIGN_BITS 2 81 82 #define CBBR_INTRLINE 0x3c /* len=1 */ 83 #define CBBR_INTRPIN 0x3d /* len=1 */ 84 #define CBBR_BRIDGECTRL 0x3e /* len=2 */ 85 # define CBBM_BRIDGECTRL_MASTER_ABORT 0x0020 86 # define CBBM_BRIDGECTRL_RESET 0x0040 87 # define CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN 0x0080 88 # define CBBM_BRIDGECTRL_PREFETCH_0 0x0100 89 # define CBBM_BRIDGECTRL_PREFETCH_1 0x0200 90 # define CBBM_BRIDGECTRL_WRITE_POST_EN 0x0400 91 /* additional bit for RF5C46[567] */ 92 # define CBBM_BRIDGECTRL_RL_3E0_EN 0x0800 93 # define CBBM_BRIDGECTRL_RL_3E2_EN 0x1000 94 95 #define CBBR_LEGACY 0x44 /* len=4 */ 96 97 /* TI */ 98 #define CBBR_SYSCTRL 0x80 /* len=4 */ 99 # define CBBM_SYSCTRL_INTRTIE 0x20000000u 100 101 /* TI [14][245]xx */ 102 #define CBBR_MMCTRL 0x84 /* len=4 */ 103 104 /* TI 12xx/14xx/15xx (except 1250/1251/1251B/1450) */ 105 #define CBBR_MFUNC 0x8c /* len=4 */ 106 # define CBBM_MFUNC_PIN0 0x0000000f 107 # define CBBM_MFUNC_PIN0_INTA 0x02 108 # define CBBM_MFUNC_PIN1 0x000000f0 109 # define CBBM_MFUNC_PIN1_INTB 0x20 110 # define CBBM_MFUNC_PIN2 0x00000f00 111 # define CBBM_MFUNC_PIN3 0x0000f000 112 # define CBBM_MFUNC_PIN4 0x000f0000 113 # define CBBM_MFUNC_PIN5 0x00f00000 114 # define CBBM_MFUNC_PIN6 0x0f000000 115 116 #define CBBR_CBCTRL 0x91 /* len=1 */ 117 /* bits for TI 113X */ 118 # define CBBM_CBCTRL_113X_RI_EN 0x80 119 # define CBBM_CBCTRL_113X_ZV_EN 0x40 120 # define CBBM_CBCTRL_113X_PCI_IRQ_EN 0x20 121 # define CBBM_CBCTRL_113X_PCI_INTR 0x10 122 # define CBBM_CBCTRL_113X_PCI_CSC 0x08 123 # define CBBM_CBCTRL_113X_PCI_CSC_D 0x04 124 # define CBBM_CBCTRL_113X_SPEAKER_EN 0x02 125 # define CBBM_CBCTRL_113X_INTR_DET 0x01 126 /* TI [14][245]xx */ 127 # define CBBM_CBCTRL_12XX_RI_EN 0x80 128 # define CBBM_CBCTRL_12XX_ZV_EN 0x40 129 # define CBBM_CBCTRL_12XX_AUD2MUX 0x04 130 # define CBBM_CBCTRL_12XX_SPEAKER_EN 0x02 131 # define CBBM_CBCTRL_12XX_INTR_DET 0x01 132 #define CBBR_DEVCTRL 0x92 /* len=1 */ 133 # define CBBM_DEVCTRL_INT_SERIAL 0x04 134 # define CBBM_DEVCTRL_INT_PCI 0x02 135 136 /* ToPIC 95 ONLY */ 137 #define TOPIC95_SOCKETCTRL 0x90 138 # define TOPIC95_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */ 139 /* ToPIC 97, 100 */ 140 #define TOPIC97_ZV_CONTROL 0x9c /* 1 byte */ 141 # define TOPIC97_ZVC_ENABLE 0x1 142 143 /* TOPIC 95+ */ 144 #define TOPIC_SLOTCTRL 0xa0 /* 1 byte */ 145 # define TOPIC_SLOTCTRL_SLOTON 0x80 146 # define TOPIC_SLOTCTRL_SLOTEN 0x40 147 # define TOPIC_SLOTCTRL_ID_LOCK 0x20 148 # define TOPIC_SLOTCTRL_ID_WP 0x10 149 # define TOPIC_SLOTCTRL_PORT_MASK 0x0c 150 # define TOPIC_SLOTCTRL_PORT_SHIFT 2 151 # define TOPIC_SLOTCTRL_OSF_MASK 0x03 152 # define TOPIC_SLOTCTRL_OSF_SHIFT 0 153 154 /* TOPIC 95+ */ 155 #define TOPIC_INTCTRL 0xa1 /* 1 byte */ 156 # define TOPIC_INTCTRL_INTB 0x20 157 # define TOPIC_INTCTRL_INTA 0x10 158 # define TOPIC_INTCTRL_INT_MASK 0x30 159 /* The following bits may be for ToPIC 95 only */ 160 # define TOPIC95_INTCTRL_CLOCK_MASK 0x0c 161 # define TOPIC95_INTCTRL_CLOCK_2 0x08 /* PCI Clk/2 */ 162 # define TOPIC95_INTCTRL_CLOCK_1 0x04 /* PCI Clk */ 163 # define TOPIC95_INTCTRL_CLOCK_0 0x00 /* no clock */ 164 /* ToPIC97, 100 defines the following bits */ 165 # define TOPIC97_INTCTRL_STSIRQNP 0x04 166 # define TOPIC97_INTCTRL_IRQNP 0x02 167 # define TOPIC97_INTCTRL_INTIRQSEL 0x01 168 169 /* TOPIC 95+ */ 170 #define TOPIC_CDC 0xa3 /* 1 byte */ 171 # define TOPIC_CDC_CARDBUS 0x80 172 # define TOPIC_CDC_VS1 0x04 173 # define TOPIC_CDC_VS2 0x02 174 # define TOPIC_CDC_SWDETECT 0x01 175 176 /* TOPIC97+? */ 177 #define TOPIC_REG_CTRL 0xa4 /* 4 bytes */ 178 # define TOPIC_REG_CTRL_RESUME_RESET 0x80000000 179 # define TOPIC_REG_CTRL_REMOVE_RESET 0x40000000 180 # define TOPIC97_REG_CTRL_CLKRUN_ENA 0x20000000 181 # define TOPIC97_REG_CTRL_TESTMODE 0x10000000 182 # define TOPIC97_REG_CTRL_IOPLUP 0x08000000 183 # define TOPIC_REG_CTRL_BUFOFF_PWROFF 0x02000000 184 # define TOPIC_REG_CTRL_BUFOFF_SIGOFF 0x01000000 185 # define TOPIC97_REG_CTRL_CB_DEV_MASK 0x0000f800 186 # define TOPIC97_REG_CTRL_CB_DEV_SHIFT 11 187 # define TOPIC97_REG_CTRL_RI_DISABLE 0x00000004 188 # define TOPIC97_REG_CTRL_CAUDIO_OFF 0x00000002 189 # define TOPIC_REG_CTRL_CAUDIO_INVERT 0x00000001 190 191 192 /* Socket definitions */ 193 #define CBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */ 194 #define CBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */ 195 #define CBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */ 196 #define CBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */ 197 #define CBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */ 198 #define CBB_SOCKET_EVENT_VALID_MASK 0x0f /* All socket events */ 199 200 #define CBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */ 201 #define CBB_SOCKET_MASK_CD 0x06 /* Card Detect */ 202 #define CBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */ 203 #define CBB_SOCKET_MASK_ALL 0x0F /* all of the above */ 204 205 #define CBB_STATE_CSTCHG (1UL << 0) /* Card Status Change */ 206 #define CBB_STATE_CD1_CHANGE (1UL << 1) /* Card Detect 1 */ 207 #define CBB_STATE_CD2_CHANGE (1UL << 2) /* Card Detect 2 */ 208 #define CBB_STATE_CD (3UL << 1) /* Card Detect all */ 209 #define CBB_STATE_POWER_CYCLE (1UL << 3) /* Power Cycle */ 210 #define CBB_STATE_R2_CARD (1UL << 4) /* 16-bit Card */ 211 #define CBB_STATE_CB_CARD (1UL << 5) /* Cardbus Card */ 212 #define CBB_STATE_IREQ (1UL << 6) /* Ready */ 213 #define CBB_STATE_NOT_A_CARD (1UL << 7) /* Unrecognized Card */ 214 #define CBB_STATE_DATA_LOST (1UL << 8) /* Data Lost */ 215 #define CBB_STATE_BAD_VCC_REQ (1UL << 9) /* Bad VccRequest */ 216 #define CBB_STATE_5VCARD (1UL << 10) /* 5 V Card */ 217 #define CBB_STATE_3VCARD (1UL << 11) /* 3.3 V Card */ 218 #define CBB_STATE_XVCARD (1UL << 12) /* X.X V Card */ 219 #define CBB_STATE_YVCARD (1UL << 13) /* Y.Y V Card */ 220 #define CBB_STATE_5VSOCK (1UL << 28) /* 5 V Socket */ 221 #define CBB_STATE_3VSOCK (1UL << 29) /* 3.3 V Socket */ 222 #define CBB_STATE_XVSOCK (1UL << 30) /* X.X V Socket */ 223 #define CBB_STATE_YVSOCK (1UL << 31) /* Y.Y V Socket */ 224 225 #define CBB_SOCKET_CTRL_VPPMASK 0x07 226 #define CBB_SOCKET_CTRL_VPP_OFF 0x00 227 #define CBB_SOCKET_CTRL_VPP_12V 0x01 228 #define CBB_SOCKET_CTRL_VPP_5V 0x02 229 #define CBB_SOCKET_CTRL_VPP_3V 0x03 230 #define CBB_SOCKET_CTRL_VPP_XV 0x04 231 #define CBB_SOCKET_CTRL_VPP_YV 0x05 232 233 #define CBB_SOCKET_CTRL_VCCMASK 0x70 234 #define CBB_SOCKET_CTRL_VCC_OFF 0x00 235 #define CBB_SOCKET_CTRL_VCC_5V 0x20 236 #define CBB_SOCKET_CTRL_VCC_3V 0x30 237 #define CBB_SOCKET_CTRL_VCC_XV 0x40 238 #define CBB_SOCKET_CTRL_VCC_YV 0x50 239 240 #define CBB_SOCKET_CTRL_STOPCLK 0x80 241 242 #define CBB_FORCE_CV_TEST (1UL << 14) 243 #define CBB_FORCE_3VCARD (1UL << 11) 244 #define CBB_FORCE_5VCARD (1UL << 10) 245 #define CBB_FORCE_BAD_VCC_REQ (1UL << 9) 246 #define CBB_FORCE_DATA_LOST (1UL << 8) 247 #define CBB_FORCE_NOT_A_CARD (1UL << 7) 248 #define CBB_FORCE_CB_CARD (1UL << 5) 249 #define CBB_FORCE_R2_CARD (1UL << 4) 250 #define CBB_FORCE_POWER_CYCLE (1UL << 3) 251 #define CBB_FORCE_CD2_CHANGE (1UL << 2) 252 #define CBB_FORCE_CD1_CHANGE (1UL << 1) 253 #define CBB_FORCE_CSTCHG (1UL << 0) 254 255 #include <dev/pccbb/pccbbdevid.h> 256 257 #define CBB_SOCKET_EVENT 0x00 258 #define CBB_SOCKET_MASK 0x04 259 #define CBB_SOCKET_STATE 0x08 260 #define CBB_SOCKET_FORCE 0x0c 261 #define CBB_SOCKET_CONTROL 0x10 262 #define CBB_SOCKET_POWER 0x14 263 264 #define CBB_EXCA_OFFSET 0x800 /* offset for exca regs */ 265