xref: /freebsd/sys/dev/pci/controller/pci_n1sdp.c (revision f126890a)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2019 Andrew Turner
5  * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
6  *
7  * This software was developed by SRI International and the University of
8  * Cambridge Computer Laboratory (Department of Computer Science and
9  * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
10  * DARPA SSITH research programme.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31  * SUCH DAMAGE.
32  */
33 
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/bus.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/rman.h>
42 
43 #include <vm/vm.h>
44 #include <vm/vm_extern.h>
45 #include <vm/vm_page.h>
46 #include <vm/vm_phys.h>
47 
48 #include <contrib/dev/acpica/include/acpi.h>
49 #include <contrib/dev/acpica/include/accommon.h>
50 
51 #include <dev/acpica/acpivar.h>
52 #include <dev/acpica/acpi_pcibvar.h>
53 
54 #include <dev/pci/pcivar.h>
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcib_private.h>
57 #include <dev/pci/pci_host_generic.h>
58 #include <dev/pci/pci_host_generic_acpi.h>
59 
60 #include "pcib_if.h"
61 
62 #define	AP_NS_SHARED_MEM_BASE	0x06000000
63 #define	N1SDP_MAX_SEGMENTS	2 /* Two PCIe root complex devices. */
64 #define	BDF_TABLE_SIZE		(16 * 1024)
65 #define	PCI_CFG_SPACE_SIZE	0x1000
66 
67 _Static_assert(BDF_TABLE_SIZE >= PAGE_SIZE,
68     "pci_n1sdp.c assumes a 4k or 16k page size when mapping the shared data");
69 
70 struct pcie_discovery_data {
71 	uint32_t rc_base_addr;
72 	uint32_t nr_bdfs;
73 	uint32_t valid_bdfs[0];
74 };
75 
76 struct generic_pcie_n1sdp_softc {
77 	struct generic_pcie_acpi_softc acpi;
78 	struct pcie_discovery_data *n1_discovery_data;
79 	bus_space_handle_t n1_bsh;
80 };
81 
82 static int
83 n1sdp_init(struct generic_pcie_n1sdp_softc *sc)
84 {
85 	struct pcie_discovery_data *shared_data;
86 	vm_offset_t vaddr;
87 	vm_paddr_t paddr_rc;
88 	vm_paddr_t paddr;
89 	vm_page_t m[BDF_TABLE_SIZE / PAGE_SIZE];
90 	int table_count;
91 	int bdfs_size;
92 	int error, i;
93 
94 	paddr = AP_NS_SHARED_MEM_BASE + sc->acpi.segment * BDF_TABLE_SIZE;
95 	vm_phys_fictitious_reg_range(paddr, paddr + BDF_TABLE_SIZE,
96 	    VM_MEMATTR_UNCACHEABLE);
97 
98 	for (i = 0; i < nitems(m); i++) {
99 		m[i] = PHYS_TO_VM_PAGE(paddr + i * PAGE_SIZE);
100 		MPASS(m[i] != NULL);
101 	}
102 
103 	vaddr = kva_alloc((vm_size_t)BDF_TABLE_SIZE);
104 	if (vaddr == 0) {
105 		printf("%s: Can't allocate KVA memory.", __func__);
106 		error = ENXIO;
107 		goto out;
108 	}
109 	pmap_qenter(vaddr, m, nitems(m));
110 
111 	shared_data = (struct pcie_discovery_data *)vaddr;
112 	paddr_rc = (vm_offset_t)shared_data->rc_base_addr;
113 	error = bus_space_map(sc->acpi.base.res->r_bustag, paddr_rc,
114 	    PCI_CFG_SPACE_SIZE, 0, &sc->n1_bsh);
115 	if (error != 0)
116 		goto out_pmap;
117 
118 	bdfs_size = sizeof(struct pcie_discovery_data) +
119 	    sizeof(uint32_t) * shared_data->nr_bdfs;
120 	sc->n1_discovery_data = malloc(bdfs_size, M_DEVBUF,
121 	    M_WAITOK | M_ZERO);
122 	memcpy(sc->n1_discovery_data, shared_data, bdfs_size);
123 
124 	if (bootverbose) {
125 		table_count = sc->n1_discovery_data->nr_bdfs;
126 		for (i = 0; i < table_count; i++)
127 			printf("valid bdf %x\n",
128 			    sc->n1_discovery_data->valid_bdfs[i]);
129 	}
130 
131 out_pmap:
132 	pmap_qremove(vaddr, nitems(m));
133 	kva_free(vaddr, (vm_size_t)BDF_TABLE_SIZE);
134 
135 out:
136 	vm_phys_fictitious_unreg_range(paddr, paddr + BDF_TABLE_SIZE);
137 	return (error);
138 }
139 
140 static int
141 n1sdp_check_bdf(struct generic_pcie_n1sdp_softc *sc,
142     u_int bus, u_int slot, u_int func)
143 {
144 	int table_count;
145 	int bdf;
146 	int i;
147 
148 	bdf = PCIE_ADDR_OFFSET(bus, slot, func, 0);
149 	if (bdf == 0)
150 		return (1);
151 
152 	table_count = sc->n1_discovery_data->nr_bdfs;
153 
154 	for (i = 0; i < table_count; i++)
155 		if (bdf == sc->n1_discovery_data->valid_bdfs[i])
156 			return (1);
157 
158 	return (0);
159 }
160 
161 static int
162 n1sdp_pcie_acpi_probe(device_t dev)
163 {
164 	ACPI_DEVICE_INFO *devinfo;
165 	ACPI_TABLE_HEADER *hdr;
166 	ACPI_STATUS status;
167 	ACPI_HANDLE h;
168 	int root;
169 
170 	if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL ||
171 	    ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo)))
172 		return (ENXIO);
173 
174 	root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0;
175 	AcpiOsFree(devinfo);
176 	if (!root)
177 		return (ENXIO);
178 
179 	/* TODO: Move this to an ACPI quirk? */
180 	status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
181 	if (ACPI_FAILURE(status))
182 		return (ENXIO);
183 
184 	if (memcmp(hdr->OemId, "ARMLTD", ACPI_OEM_ID_SIZE) != 0 ||
185 	    memcmp(hdr->OemTableId, "ARMN1SDP", ACPI_OEM_TABLE_ID_SIZE) != 0 ||
186 	    hdr->OemRevision != 0x20181101)
187 		return (ENXIO);
188 
189 	device_set_desc(dev, "ARM N1SDP PCI host controller");
190 	return (BUS_PROBE_DEFAULT);
191 }
192 
193 static int
194 n1sdp_pcie_acpi_attach(device_t dev)
195 {
196 	struct generic_pcie_n1sdp_softc *sc;
197 	ACPI_HANDLE handle;
198 	ACPI_STATUS status;
199 	int err;
200 
201 	err = pci_host_generic_acpi_init(dev);
202 	if (err != 0)
203 		return (err);
204 
205 	sc = device_get_softc(dev);
206 	handle = acpi_get_handle(dev);
207 
208 	/* Get PCI Segment (domain) needed for IOMMU space remap. */
209 	status = acpi_GetInteger(handle, "_SEG", &sc->acpi.segment);
210 	if (ACPI_FAILURE(status)) {
211 		device_printf(dev, "No _SEG for PCI Bus\n");
212 		return (ENXIO);
213 	}
214 
215 	if (sc->acpi.segment >= N1SDP_MAX_SEGMENTS) {
216 		device_printf(dev, "Unknown PCI Bus segment (domain) %d\n",
217 		    sc->acpi.segment);
218 		return (ENXIO);
219 	}
220 
221 	err = n1sdp_init(sc);
222 	if (err)
223 		return (err);
224 
225 	device_add_child(dev, "pci", -1);
226 	return (bus_generic_attach(dev));
227 }
228 
229 static int
230 n1sdp_get_bus_space(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
231     bus_space_tag_t *bst, bus_space_handle_t *bsh, bus_size_t *offset)
232 {
233 	struct generic_pcie_n1sdp_softc *sc;
234 
235 	sc = device_get_softc(dev);
236 
237 	if (n1sdp_check_bdf(sc, bus, slot, func) == 0)
238 		return (EINVAL);
239 
240 	if (bus == sc->acpi.base.bus_start) {
241 		if (slot != 0 || func != 0)
242 			return (EINVAL);
243 		*bsh = sc->n1_bsh;
244 	} else {
245 		*bsh = rman_get_bushandle(sc->acpi.base.res);
246 	}
247 
248 	*bst = rman_get_bustag(sc->acpi.base.res);
249 	*offset = PCIE_ADDR_OFFSET(bus - sc->acpi.base.bus_start, slot, func,
250 	    reg);
251 
252 	return (0);
253 }
254 
255 static uint32_t
256 n1sdp_pcie_read_config(device_t dev, u_int bus, u_int slot,
257     u_int func, u_int reg, int bytes)
258 {
259 	struct generic_pcie_n1sdp_softc *sc_n1sdp;
260 	struct generic_pcie_acpi_softc *sc_acpi;
261 	struct generic_pcie_core_softc *sc;
262 	bus_space_handle_t h;
263 	bus_space_tag_t t;
264 	bus_size_t offset;
265 	uint32_t data;
266 
267 	sc_n1sdp = device_get_softc(dev);
268 	sc_acpi = &sc_n1sdp->acpi;
269 	sc = &sc_acpi->base;
270 
271 	if ((bus < sc->bus_start) || (bus > sc->bus_end))
272 		return (~0U);
273 	if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
274 	    (reg > PCIE_REGMAX))
275 		return (~0U);
276 
277 	if (n1sdp_get_bus_space(dev, bus, slot, func, reg, &t, &h, &offset) !=0)
278 		return (~0U);
279 
280 	data = bus_space_read_4(t, h, offset & ~3);
281 
282 	switch (bytes) {
283 	case 1:
284 		data >>= (offset & 3) * 8;
285 		data &= 0xff;
286 		break;
287 	case 2:
288 		data >>= (offset & 3) * 8;
289 		data = le16toh(data);
290 		break;
291 	case 4:
292 		data = le32toh(data);
293 		break;
294 	default:
295 		return (~0U);
296 	}
297 
298 	return (data);
299 }
300 
301 static void
302 n1sdp_pcie_write_config(device_t dev, u_int bus, u_int slot,
303     u_int func, u_int reg, uint32_t val, int bytes)
304 {
305 	struct generic_pcie_n1sdp_softc *sc_n1sdp;
306 	struct generic_pcie_acpi_softc *sc_acpi;
307 	struct generic_pcie_core_softc *sc;
308 	bus_space_handle_t h;
309 	bus_space_tag_t t;
310 	bus_size_t offset;
311 	uint32_t data;
312 
313 	sc_n1sdp = device_get_softc(dev);
314 	sc_acpi = &sc_n1sdp->acpi;
315 	sc = &sc_acpi->base;
316 
317 	if ((bus < sc->bus_start) || (bus > sc->bus_end))
318 		return;
319 	if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
320 	    (reg > PCIE_REGMAX))
321 		return;
322 
323 	if (n1sdp_get_bus_space(dev, bus, slot, func, reg, &t, &h, &offset) !=0)
324 		return;
325 
326 	data = bus_space_read_4(t, h, offset & ~3);
327 
328 	switch (bytes) {
329 	case 1:
330 		data &= ~(0xff << ((offset & 3) * 8));
331 		data |= (val & 0xff) << ((offset & 3) * 8);
332 		break;
333 	case 2:
334 		data &= ~(0xffff << ((offset & 3) * 8));
335 		data |= (val & 0xffff) << ((offset & 3) * 8);
336 		break;
337 	case 4:
338 		data = val;
339 		break;
340 	default:
341 		return;
342 	}
343 
344 	bus_space_write_4(t, h, offset & ~3, data);
345 }
346 
347 static device_method_t n1sdp_pcie_acpi_methods[] = {
348 	DEVMETHOD(device_probe,		n1sdp_pcie_acpi_probe),
349 	DEVMETHOD(device_attach,	n1sdp_pcie_acpi_attach),
350 
351 	/* pcib interface */
352 	DEVMETHOD(pcib_read_config,	n1sdp_pcie_read_config),
353 	DEVMETHOD(pcib_write_config,	n1sdp_pcie_write_config),
354 
355 	DEVMETHOD_END
356 };
357 
358 DEFINE_CLASS_1(pcib, n1sdp_pcie_acpi_driver, n1sdp_pcie_acpi_methods,
359     sizeof(struct generic_pcie_n1sdp_softc), generic_pcie_acpi_driver);
360 
361 DRIVER_MODULE(n1sdp_pcib, acpi, n1sdp_pcie_acpi_driver, 0, 0);
362