1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_acpi.h" 35 #include "opt_bus.h" 36 37 #include <sys/param.h> 38 #include <sys/conf.h> 39 #include <sys/endian.h> 40 #include <sys/eventhandler.h> 41 #include <sys/fcntl.h> 42 #include <sys/kernel.h> 43 #include <sys/limits.h> 44 #include <sys/linker.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/queue.h> 48 #include <sys/sysctl.h> 49 #include <sys/systm.h> 50 51 #include <vm/vm.h> 52 #include <vm/pmap.h> 53 #include <vm/vm_extern.h> 54 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 #include <machine/stdarg.h> 60 61 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 62 #include <machine/intr_machdep.h> 63 #endif 64 65 #include <sys/pciio.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pci_private.h> 69 70 #ifdef PCI_IOV 71 #include <sys/nv.h> 72 #include <dev/pci/pci_iov_private.h> 73 #endif 74 75 #include <dev/usb/controller/xhcireg.h> 76 #include <dev/usb/controller/ehcireg.h> 77 #include <dev/usb/controller/ohcireg.h> 78 #include <dev/usb/controller/uhcireg.h> 79 80 #include "pcib_if.h" 81 #include "pci_if.h" 82 83 #define PCIR_IS_BIOS(cfg, reg) \ 84 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 85 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 86 87 static int pci_has_quirk(uint32_t devid, int quirk); 88 static pci_addr_t pci_mapbase(uint64_t mapreg); 89 static const char *pci_maptype(uint64_t mapreg); 90 static int pci_maprange(uint64_t mapreg); 91 static pci_addr_t pci_rombase(uint64_t mapreg); 92 static int pci_romsize(uint64_t testval); 93 static void pci_fixancient(pcicfgregs *cfg); 94 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 95 96 static int pci_porten(device_t dev); 97 static int pci_memen(device_t dev); 98 static void pci_assign_interrupt(device_t bus, device_t dev, 99 int force_route); 100 static int pci_add_map(device_t bus, device_t dev, int reg, 101 struct resource_list *rl, int force, int prefetch); 102 static int pci_probe(device_t dev); 103 static void pci_load_vendor_data(void); 104 static int pci_describe_parse_line(char **ptr, int *vendor, 105 int *device, char **desc); 106 static char *pci_describe_device(device_t dev); 107 static int pci_modevent(module_t mod, int what, void *arg); 108 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 109 pcicfgregs *cfg); 110 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 111 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 112 int reg, uint32_t *data); 113 #if 0 114 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 115 int reg, uint32_t data); 116 #endif 117 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 118 static void pci_mask_msix(device_t dev, u_int index); 119 static void pci_unmask_msix(device_t dev, u_int index); 120 static int pci_msi_blacklisted(void); 121 static int pci_msix_blacklisted(void); 122 static void pci_resume_msi(device_t dev); 123 static void pci_resume_msix(device_t dev); 124 static int pci_remap_intr_method(device_t bus, device_t dev, 125 u_int irq); 126 static void pci_hint_device_unit(device_t acdev, device_t child, 127 const char *name, int *unitp); 128 static int pci_reset_post(device_t dev, device_t child); 129 static int pci_reset_prepare(device_t dev, device_t child); 130 static int pci_reset_child(device_t dev, device_t child, 131 int flags); 132 133 static int pci_get_id_method(device_t dev, device_t child, 134 enum pci_id_type type, uintptr_t *rid); 135 136 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 137 int b, int s, int f, uint16_t vid, uint16_t did); 138 139 static device_method_t pci_methods[] = { 140 /* Device interface */ 141 DEVMETHOD(device_probe, pci_probe), 142 DEVMETHOD(device_attach, pci_attach), 143 DEVMETHOD(device_detach, pci_detach), 144 DEVMETHOD(device_shutdown, bus_generic_shutdown), 145 DEVMETHOD(device_suspend, bus_generic_suspend), 146 DEVMETHOD(device_resume, pci_resume), 147 148 /* Bus interface */ 149 DEVMETHOD(bus_print_child, pci_print_child), 150 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 151 DEVMETHOD(bus_read_ivar, pci_read_ivar), 152 DEVMETHOD(bus_write_ivar, pci_write_ivar), 153 DEVMETHOD(bus_driver_added, pci_driver_added), 154 DEVMETHOD(bus_setup_intr, pci_setup_intr), 155 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 156 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 157 DEVMETHOD(bus_reset_post, pci_reset_post), 158 DEVMETHOD(bus_reset_child, pci_reset_child), 159 160 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 161 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 162 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 163 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 164 DEVMETHOD(bus_delete_resource, pci_delete_resource), 165 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 166 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 167 DEVMETHOD(bus_release_resource, pci_release_resource), 168 DEVMETHOD(bus_activate_resource, pci_activate_resource), 169 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 170 DEVMETHOD(bus_child_deleted, pci_child_deleted), 171 DEVMETHOD(bus_child_detached, pci_child_detached), 172 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 173 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 174 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 175 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 176 DEVMETHOD(bus_suspend_child, pci_suspend_child), 177 DEVMETHOD(bus_resume_child, pci_resume_child), 178 DEVMETHOD(bus_rescan, pci_rescan_method), 179 180 /* PCI interface */ 181 DEVMETHOD(pci_read_config, pci_read_config_method), 182 DEVMETHOD(pci_write_config, pci_write_config_method), 183 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 184 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 185 DEVMETHOD(pci_enable_io, pci_enable_io_method), 186 DEVMETHOD(pci_disable_io, pci_disable_io_method), 187 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 188 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 189 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 190 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 191 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 192 DEVMETHOD(pci_find_cap, pci_find_cap_method), 193 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 194 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 195 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 196 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 197 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 198 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 199 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 200 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 201 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 202 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 203 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 204 DEVMETHOD(pci_release_msi, pci_release_msi_method), 205 DEVMETHOD(pci_msi_count, pci_msi_count_method), 206 DEVMETHOD(pci_msix_count, pci_msix_count_method), 207 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 208 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 209 DEVMETHOD(pci_get_id, pci_get_id_method), 210 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 211 DEVMETHOD(pci_child_added, pci_child_added_method), 212 #ifdef PCI_IOV 213 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 214 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 215 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 216 #endif 217 218 DEVMETHOD_END 219 }; 220 221 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 222 223 static devclass_t pci_devclass; 224 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL, 225 BUS_PASS_BUS); 226 MODULE_VERSION(pci, 1); 227 228 static char *pci_vendordata; 229 static size_t pci_vendordata_size; 230 231 struct pci_quirk { 232 uint32_t devid; /* Vendor/device of the card */ 233 int type; 234 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 235 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 236 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 237 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 238 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 239 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 240 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 241 int arg1; 242 int arg2; 243 }; 244 245 static const struct pci_quirk pci_quirks[] = { 246 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 247 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 248 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 249 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 250 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 251 252 /* 253 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 254 * or the CMIC-SL (AKA ServerWorks GC_LE). 255 */ 256 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 257 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 258 259 /* 260 * MSI doesn't work on earlier Intel chipsets including 261 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 262 */ 263 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 264 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 265 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 266 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 267 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 268 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 271 /* 272 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 273 * bridge. 274 */ 275 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 276 277 /* 278 * Some virtualization environments emulate an older chipset 279 * but support MSI just fine. QEMU uses the Intel 82440. 280 */ 281 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 282 283 /* 284 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 285 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 286 * It prevents us from attaching hpet(4) when the bit is unset. 287 * Note this quirk only affects SB600 revision A13 and earlier. 288 * For SB600 A21 and later, firmware must set the bit to hide it. 289 * For SB700 and later, it is unused and hardcoded to zero. 290 */ 291 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 292 293 /* 294 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 295 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 296 * of the command register is set. 297 */ 298 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 299 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 300 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 301 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 302 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 303 304 /* 305 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 306 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 307 */ 308 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 309 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 310 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 311 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 312 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 313 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 314 315 /* 316 * HPE Gen 10 VGA has a memory range that can't be allocated in the 317 * expected place. 318 */ 319 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 320 321 { 0 } 322 }; 323 324 /* map register information */ 325 #define PCI_MAPMEM 0x01 /* memory map */ 326 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 327 #define PCI_MAPPORT 0x04 /* port map */ 328 329 struct devlist pci_devq; 330 uint32_t pci_generation; 331 uint32_t pci_numdevs = 0; 332 static int pcie_chipset, pcix_chipset; 333 334 /* sysctl vars */ 335 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 336 "PCI bus tuning parameters"); 337 338 static int pci_enable_io_modes = 1; 339 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 340 &pci_enable_io_modes, 1, 341 "Enable I/O and memory bits in the config register. Some BIOSes do not" 342 " enable these bits correctly. We'd like to do this all the time, but" 343 " there are some peripherals that this causes problems with."); 344 345 static int pci_do_realloc_bars = 1; 346 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 347 &pci_do_realloc_bars, 0, 348 "Attempt to allocate a new range for any BARs whose original " 349 "firmware-assigned ranges fail to allocate during the initial device scan."); 350 351 static int pci_do_power_nodriver = 0; 352 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 353 &pci_do_power_nodriver, 0, 354 "Place a function into D3 state when no driver attaches to it. 0 means" 355 " disable. 1 means conservatively place devices into D3 state. 2 means" 356 " aggressively place devices into D3 state. 3 means put absolutely" 357 " everything in D3 state."); 358 359 int pci_do_power_resume = 1; 360 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 361 &pci_do_power_resume, 1, 362 "Transition from D3 -> D0 on resume."); 363 364 int pci_do_power_suspend = 1; 365 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 366 &pci_do_power_suspend, 1, 367 "Transition from D0 -> D3 on suspend."); 368 369 static int pci_do_msi = 1; 370 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 371 "Enable support for MSI interrupts"); 372 373 static int pci_do_msix = 1; 374 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 375 "Enable support for MSI-X interrupts"); 376 377 static int pci_msix_rewrite_table = 0; 378 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 379 &pci_msix_rewrite_table, 0, 380 "Rewrite entire MSI-X table when updating MSI-X entries"); 381 382 static int pci_honor_msi_blacklist = 1; 383 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 384 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 385 386 #if defined(__i386__) || defined(__amd64__) 387 static int pci_usb_takeover = 1; 388 #else 389 static int pci_usb_takeover = 0; 390 #endif 391 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 392 &pci_usb_takeover, 1, 393 "Enable early takeover of USB controllers. Disable this if you depend on" 394 " BIOS emulation of USB devices, that is you use USB devices (like" 395 " keyboard or mouse) but do not load USB drivers"); 396 397 static int pci_clear_bars; 398 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 399 "Ignore firmware-assigned resources for BARs."); 400 401 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 402 static int pci_clear_buses; 403 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 404 "Ignore firmware-assigned bus numbers."); 405 #endif 406 407 static int pci_enable_ari = 1; 408 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 409 0, "Enable support for PCIe Alternative RID Interpretation"); 410 411 static int pci_clear_aer_on_attach = 0; 412 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 413 &pci_clear_aer_on_attach, 0, 414 "Clear port and device AER state on driver attach"); 415 416 static int 417 pci_has_quirk(uint32_t devid, int quirk) 418 { 419 const struct pci_quirk *q; 420 421 for (q = &pci_quirks[0]; q->devid; q++) { 422 if (q->devid == devid && q->type == quirk) 423 return (1); 424 } 425 return (0); 426 } 427 428 /* Find a device_t by bus/slot/function in domain 0 */ 429 430 device_t 431 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 432 { 433 434 return (pci_find_dbsf(0, bus, slot, func)); 435 } 436 437 /* Find a device_t by domain/bus/slot/function */ 438 439 device_t 440 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 441 { 442 struct pci_devinfo *dinfo = NULL; 443 444 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 445 if ((dinfo->cfg.domain == domain) && 446 (dinfo->cfg.bus == bus) && 447 (dinfo->cfg.slot == slot) && 448 (dinfo->cfg.func == func)) { 449 break; 450 } 451 } 452 453 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 454 } 455 456 /* Find a device_t by vendor/device ID */ 457 458 device_t 459 pci_find_device(uint16_t vendor, uint16_t device) 460 { 461 struct pci_devinfo *dinfo; 462 463 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 464 if ((dinfo->cfg.vendor == vendor) && 465 (dinfo->cfg.device == device)) { 466 return (dinfo->cfg.dev); 467 } 468 } 469 470 return (NULL); 471 } 472 473 device_t 474 pci_find_class(uint8_t class, uint8_t subclass) 475 { 476 struct pci_devinfo *dinfo; 477 478 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 479 if (dinfo->cfg.baseclass == class && 480 dinfo->cfg.subclass == subclass) { 481 return (dinfo->cfg.dev); 482 } 483 } 484 485 return (NULL); 486 } 487 488 static int 489 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 490 { 491 va_list ap; 492 int retval; 493 494 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 495 cfg->func); 496 va_start(ap, fmt); 497 retval += vprintf(fmt, ap); 498 va_end(ap); 499 return (retval); 500 } 501 502 /* return base address of memory or port map */ 503 504 static pci_addr_t 505 pci_mapbase(uint64_t mapreg) 506 { 507 508 if (PCI_BAR_MEM(mapreg)) 509 return (mapreg & PCIM_BAR_MEM_BASE); 510 else 511 return (mapreg & PCIM_BAR_IO_BASE); 512 } 513 514 /* return map type of memory or port map */ 515 516 static const char * 517 pci_maptype(uint64_t mapreg) 518 { 519 520 if (PCI_BAR_IO(mapreg)) 521 return ("I/O Port"); 522 if (mapreg & PCIM_BAR_MEM_PREFETCH) 523 return ("Prefetchable Memory"); 524 return ("Memory"); 525 } 526 527 /* return log2 of map size decoded for memory or port map */ 528 529 int 530 pci_mapsize(uint64_t testval) 531 { 532 int ln2size; 533 534 testval = pci_mapbase(testval); 535 ln2size = 0; 536 if (testval != 0) { 537 while ((testval & 1) == 0) 538 { 539 ln2size++; 540 testval >>= 1; 541 } 542 } 543 return (ln2size); 544 } 545 546 /* return base address of device ROM */ 547 548 static pci_addr_t 549 pci_rombase(uint64_t mapreg) 550 { 551 552 return (mapreg & PCIM_BIOS_ADDR_MASK); 553 } 554 555 /* return log2 of map size decided for device ROM */ 556 557 static int 558 pci_romsize(uint64_t testval) 559 { 560 int ln2size; 561 562 testval = pci_rombase(testval); 563 ln2size = 0; 564 if (testval != 0) { 565 while ((testval & 1) == 0) 566 { 567 ln2size++; 568 testval >>= 1; 569 } 570 } 571 return (ln2size); 572 } 573 574 /* return log2 of address range supported by map register */ 575 576 static int 577 pci_maprange(uint64_t mapreg) 578 { 579 int ln2range = 0; 580 581 if (PCI_BAR_IO(mapreg)) 582 ln2range = 32; 583 else 584 switch (mapreg & PCIM_BAR_MEM_TYPE) { 585 case PCIM_BAR_MEM_32: 586 ln2range = 32; 587 break; 588 case PCIM_BAR_MEM_1MB: 589 ln2range = 20; 590 break; 591 case PCIM_BAR_MEM_64: 592 ln2range = 64; 593 break; 594 } 595 return (ln2range); 596 } 597 598 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 599 600 static void 601 pci_fixancient(pcicfgregs *cfg) 602 { 603 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 604 return; 605 606 /* PCI to PCI bridges use header type 1 */ 607 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 608 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 609 } 610 611 /* extract header type specific config data */ 612 613 static void 614 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 615 { 616 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 617 switch (cfg->hdrtype & PCIM_HDRTYPE) { 618 case PCIM_HDRTYPE_NORMAL: 619 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 620 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 621 cfg->mingnt = REG(PCIR_MINGNT, 1); 622 cfg->maxlat = REG(PCIR_MAXLAT, 1); 623 cfg->nummaps = PCI_MAXMAPS_0; 624 break; 625 case PCIM_HDRTYPE_BRIDGE: 626 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 627 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 628 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 629 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 630 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 631 cfg->nummaps = PCI_MAXMAPS_1; 632 break; 633 case PCIM_HDRTYPE_CARDBUS: 634 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 635 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 636 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 637 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 638 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 639 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 640 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 641 cfg->nummaps = PCI_MAXMAPS_2; 642 break; 643 } 644 #undef REG 645 } 646 647 /* read configuration header into pcicfgregs structure */ 648 struct pci_devinfo * 649 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 650 { 651 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 652 uint16_t vid, did; 653 654 vid = REG(PCIR_VENDOR, 2); 655 did = REG(PCIR_DEVICE, 2); 656 if (vid != 0xffff) 657 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 658 659 return (NULL); 660 } 661 662 struct pci_devinfo * 663 pci_alloc_devinfo_method(device_t dev) 664 { 665 666 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 667 M_WAITOK | M_ZERO)); 668 } 669 670 static struct pci_devinfo * 671 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 672 uint16_t vid, uint16_t did) 673 { 674 struct pci_devinfo *devlist_entry; 675 pcicfgregs *cfg; 676 677 devlist_entry = PCI_ALLOC_DEVINFO(bus); 678 679 cfg = &devlist_entry->cfg; 680 681 cfg->domain = d; 682 cfg->bus = b; 683 cfg->slot = s; 684 cfg->func = f; 685 cfg->vendor = vid; 686 cfg->device = did; 687 cfg->cmdreg = REG(PCIR_COMMAND, 2); 688 cfg->statreg = REG(PCIR_STATUS, 2); 689 cfg->baseclass = REG(PCIR_CLASS, 1); 690 cfg->subclass = REG(PCIR_SUBCLASS, 1); 691 cfg->progif = REG(PCIR_PROGIF, 1); 692 cfg->revid = REG(PCIR_REVID, 1); 693 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 694 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 695 cfg->lattimer = REG(PCIR_LATTIMER, 1); 696 cfg->intpin = REG(PCIR_INTPIN, 1); 697 cfg->intline = REG(PCIR_INTLINE, 1); 698 699 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 700 cfg->hdrtype &= ~PCIM_MFDEV; 701 STAILQ_INIT(&cfg->maps); 702 703 cfg->iov = NULL; 704 705 pci_fixancient(cfg); 706 pci_hdrtypedata(pcib, b, s, f, cfg); 707 708 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 709 pci_read_cap(pcib, cfg); 710 711 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 712 713 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 714 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 715 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 716 devlist_entry->conf.pc_sel.pc_func = cfg->func; 717 devlist_entry->conf.pc_hdr = cfg->hdrtype; 718 719 devlist_entry->conf.pc_subvendor = cfg->subvendor; 720 devlist_entry->conf.pc_subdevice = cfg->subdevice; 721 devlist_entry->conf.pc_vendor = cfg->vendor; 722 devlist_entry->conf.pc_device = cfg->device; 723 724 devlist_entry->conf.pc_class = cfg->baseclass; 725 devlist_entry->conf.pc_subclass = cfg->subclass; 726 devlist_entry->conf.pc_progif = cfg->progif; 727 devlist_entry->conf.pc_revid = cfg->revid; 728 729 pci_numdevs++; 730 pci_generation++; 731 732 return (devlist_entry); 733 } 734 #undef REG 735 736 static void 737 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 738 { 739 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 740 cfg->ea.ea_location + (n), w) 741 int num_ent; 742 int ptr; 743 int a, b; 744 uint32_t val; 745 int ent_size; 746 uint32_t dw[4]; 747 uint64_t base, max_offset; 748 struct pci_ea_entry *eae; 749 750 if (cfg->ea.ea_location == 0) 751 return; 752 753 STAILQ_INIT(&cfg->ea.ea_entries); 754 755 /* Determine the number of entries */ 756 num_ent = REG(PCIR_EA_NUM_ENT, 2); 757 num_ent &= PCIM_EA_NUM_ENT_MASK; 758 759 /* Find the first entry to care of */ 760 ptr = PCIR_EA_FIRST_ENT; 761 762 /* Skip DWORD 2 for type 1 functions */ 763 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 764 ptr += 4; 765 766 for (a = 0; a < num_ent; a++) { 767 768 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 769 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 770 771 /* Read a number of dwords in the entry */ 772 val = REG(ptr, 4); 773 ptr += 4; 774 ent_size = (val & PCIM_EA_ES); 775 776 for (b = 0; b < ent_size; b++) { 777 dw[b] = REG(ptr, 4); 778 ptr += 4; 779 } 780 781 eae->eae_flags = val; 782 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 783 784 base = dw[0] & PCIM_EA_FIELD_MASK; 785 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 786 b = 2; 787 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 788 base |= (uint64_t)dw[b] << 32UL; 789 b++; 790 } 791 if (((dw[1] & PCIM_EA_IS_64) != 0) 792 && (b < ent_size)) { 793 max_offset |= (uint64_t)dw[b] << 32UL; 794 b++; 795 } 796 797 eae->eae_base = base; 798 eae->eae_max_offset = max_offset; 799 800 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 801 802 if (bootverbose) { 803 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 804 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 805 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 806 } 807 } 808 } 809 #undef REG 810 811 static void 812 pci_read_cap(device_t pcib, pcicfgregs *cfg) 813 { 814 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 815 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 816 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 817 uint64_t addr; 818 #endif 819 uint32_t val; 820 int ptr, nextptr, ptrptr; 821 822 switch (cfg->hdrtype & PCIM_HDRTYPE) { 823 case PCIM_HDRTYPE_NORMAL: 824 case PCIM_HDRTYPE_BRIDGE: 825 ptrptr = PCIR_CAP_PTR; 826 break; 827 case PCIM_HDRTYPE_CARDBUS: 828 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 829 break; 830 default: 831 return; /* no extended capabilities support */ 832 } 833 nextptr = REG(ptrptr, 1); /* sanity check? */ 834 835 /* 836 * Read capability entries. 837 */ 838 while (nextptr != 0) { 839 /* Sanity check */ 840 if (nextptr > 255) { 841 printf("illegal PCI extended capability offset %d\n", 842 nextptr); 843 return; 844 } 845 /* Find the next entry */ 846 ptr = nextptr; 847 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 848 849 /* Process this entry */ 850 switch (REG(ptr + PCICAP_ID, 1)) { 851 case PCIY_PMG: /* PCI power management */ 852 if (cfg->pp.pp_cap == 0) { 853 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 854 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 855 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 856 if ((nextptr - ptr) > PCIR_POWER_DATA) 857 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 858 } 859 break; 860 case PCIY_HT: /* HyperTransport */ 861 /* Determine HT-specific capability type. */ 862 val = REG(ptr + PCIR_HT_COMMAND, 2); 863 864 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 865 cfg->ht.ht_slave = ptr; 866 867 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 868 switch (val & PCIM_HTCMD_CAP_MASK) { 869 case PCIM_HTCAP_MSI_MAPPING: 870 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 871 /* Sanity check the mapping window. */ 872 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 873 4); 874 addr <<= 32; 875 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 876 4); 877 if (addr != MSI_INTEL_ADDR_BASE) 878 device_printf(pcib, 879 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 880 cfg->domain, cfg->bus, 881 cfg->slot, cfg->func, 882 (long long)addr); 883 } else 884 addr = MSI_INTEL_ADDR_BASE; 885 886 cfg->ht.ht_msimap = ptr; 887 cfg->ht.ht_msictrl = val; 888 cfg->ht.ht_msiaddr = addr; 889 break; 890 } 891 #endif 892 break; 893 case PCIY_MSI: /* PCI MSI */ 894 cfg->msi.msi_location = ptr; 895 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 896 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 897 PCIM_MSICTRL_MMC_MASK)>>1); 898 break; 899 case PCIY_MSIX: /* PCI MSI-X */ 900 cfg->msix.msix_location = ptr; 901 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 902 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 903 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 904 val = REG(ptr + PCIR_MSIX_TABLE, 4); 905 cfg->msix.msix_table_bar = PCIR_BAR(val & 906 PCIM_MSIX_BIR_MASK); 907 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 908 val = REG(ptr + PCIR_MSIX_PBA, 4); 909 cfg->msix.msix_pba_bar = PCIR_BAR(val & 910 PCIM_MSIX_BIR_MASK); 911 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 912 break; 913 case PCIY_VPD: /* PCI Vital Product Data */ 914 cfg->vpd.vpd_reg = ptr; 915 break; 916 case PCIY_SUBVENDOR: 917 /* Should always be true. */ 918 if ((cfg->hdrtype & PCIM_HDRTYPE) == 919 PCIM_HDRTYPE_BRIDGE) { 920 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 921 cfg->subvendor = val & 0xffff; 922 cfg->subdevice = val >> 16; 923 } 924 break; 925 case PCIY_PCIX: /* PCI-X */ 926 /* 927 * Assume we have a PCI-X chipset if we have 928 * at least one PCI-PCI bridge with a PCI-X 929 * capability. Note that some systems with 930 * PCI-express or HT chipsets might match on 931 * this check as well. 932 */ 933 if ((cfg->hdrtype & PCIM_HDRTYPE) == 934 PCIM_HDRTYPE_BRIDGE) 935 pcix_chipset = 1; 936 cfg->pcix.pcix_location = ptr; 937 break; 938 case PCIY_EXPRESS: /* PCI-express */ 939 /* 940 * Assume we have a PCI-express chipset if we have 941 * at least one PCI-express device. 942 */ 943 pcie_chipset = 1; 944 cfg->pcie.pcie_location = ptr; 945 val = REG(ptr + PCIER_FLAGS, 2); 946 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 947 break; 948 case PCIY_EA: /* Enhanced Allocation */ 949 cfg->ea.ea_location = ptr; 950 pci_ea_fill_info(pcib, cfg); 951 break; 952 default: 953 break; 954 } 955 } 956 957 #if defined(__powerpc__) 958 /* 959 * Enable the MSI mapping window for all HyperTransport 960 * slaves. PCI-PCI bridges have their windows enabled via 961 * PCIB_MAP_MSI(). 962 */ 963 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 964 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 965 device_printf(pcib, 966 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 967 cfg->domain, cfg->bus, cfg->slot, cfg->func); 968 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 969 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 970 2); 971 } 972 #endif 973 /* REG and WREG use carry through to next functions */ 974 } 975 976 /* 977 * PCI Vital Product Data 978 */ 979 980 #define PCI_VPD_TIMEOUT 1000000 981 982 static int 983 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 984 { 985 int count = PCI_VPD_TIMEOUT; 986 987 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 988 989 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 990 991 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 992 if (--count < 0) 993 return (ENXIO); 994 DELAY(1); /* limit looping */ 995 } 996 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 997 998 return (0); 999 } 1000 1001 #if 0 1002 static int 1003 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1004 { 1005 int count = PCI_VPD_TIMEOUT; 1006 1007 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1008 1009 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1010 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1011 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1012 if (--count < 0) 1013 return (ENXIO); 1014 DELAY(1); /* limit looping */ 1015 } 1016 1017 return (0); 1018 } 1019 #endif 1020 1021 #undef PCI_VPD_TIMEOUT 1022 1023 struct vpd_readstate { 1024 device_t pcib; 1025 pcicfgregs *cfg; 1026 uint32_t val; 1027 int bytesinval; 1028 int off; 1029 uint8_t cksum; 1030 }; 1031 1032 static int 1033 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1034 { 1035 uint32_t reg; 1036 uint8_t byte; 1037 1038 if (vrs->bytesinval == 0) { 1039 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1040 return (ENXIO); 1041 vrs->val = le32toh(reg); 1042 vrs->off += 4; 1043 byte = vrs->val & 0xff; 1044 vrs->bytesinval = 3; 1045 } else { 1046 vrs->val = vrs->val >> 8; 1047 byte = vrs->val & 0xff; 1048 vrs->bytesinval--; 1049 } 1050 1051 vrs->cksum += byte; 1052 *data = byte; 1053 return (0); 1054 } 1055 1056 static void 1057 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1058 { 1059 struct vpd_readstate vrs; 1060 int state; 1061 int name; 1062 int remain; 1063 int i; 1064 int alloc, off; /* alloc/off for RO/W arrays */ 1065 int cksumvalid; 1066 int dflen; 1067 uint8_t byte; 1068 uint8_t byte2; 1069 1070 /* init vpd reader */ 1071 vrs.bytesinval = 0; 1072 vrs.off = 0; 1073 vrs.pcib = pcib; 1074 vrs.cfg = cfg; 1075 vrs.cksum = 0; 1076 1077 state = 0; 1078 name = remain = i = 0; /* shut up stupid gcc */ 1079 alloc = off = 0; /* shut up stupid gcc */ 1080 dflen = 0; /* shut up stupid gcc */ 1081 cksumvalid = -1; 1082 while (state >= 0) { 1083 if (vpd_nextbyte(&vrs, &byte)) { 1084 state = -2; 1085 break; 1086 } 1087 #if 0 1088 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 1089 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 1090 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 1091 #endif 1092 switch (state) { 1093 case 0: /* item name */ 1094 if (byte & 0x80) { 1095 if (vpd_nextbyte(&vrs, &byte2)) { 1096 state = -2; 1097 break; 1098 } 1099 remain = byte2; 1100 if (vpd_nextbyte(&vrs, &byte2)) { 1101 state = -2; 1102 break; 1103 } 1104 remain |= byte2 << 8; 1105 name = byte & 0x7f; 1106 } else { 1107 remain = byte & 0x7; 1108 name = (byte >> 3) & 0xf; 1109 } 1110 if (vrs.off + remain - vrs.bytesinval > 0x8000) { 1111 pci_printf(cfg, 1112 "VPD data overflow, remain %#x\n", remain); 1113 state = -1; 1114 break; 1115 } 1116 switch (name) { 1117 case 0x2: /* String */ 1118 cfg->vpd.vpd_ident = malloc(remain + 1, 1119 M_DEVBUF, M_WAITOK); 1120 i = 0; 1121 state = 1; 1122 break; 1123 case 0xf: /* End */ 1124 state = -1; 1125 break; 1126 case 0x10: /* VPD-R */ 1127 alloc = 8; 1128 off = 0; 1129 cfg->vpd.vpd_ros = malloc(alloc * 1130 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 1131 M_WAITOK | M_ZERO); 1132 state = 2; 1133 break; 1134 case 0x11: /* VPD-W */ 1135 alloc = 8; 1136 off = 0; 1137 cfg->vpd.vpd_w = malloc(alloc * 1138 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 1139 M_WAITOK | M_ZERO); 1140 state = 5; 1141 break; 1142 default: /* Invalid data, abort */ 1143 state = -1; 1144 break; 1145 } 1146 break; 1147 1148 case 1: /* Identifier String */ 1149 cfg->vpd.vpd_ident[i++] = byte; 1150 remain--; 1151 if (remain == 0) { 1152 cfg->vpd.vpd_ident[i] = '\0'; 1153 state = 0; 1154 } 1155 break; 1156 1157 case 2: /* VPD-R Keyword Header */ 1158 if (off == alloc) { 1159 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1160 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1161 M_DEVBUF, M_WAITOK | M_ZERO); 1162 } 1163 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1164 if (vpd_nextbyte(&vrs, &byte2)) { 1165 state = -2; 1166 break; 1167 } 1168 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1169 if (vpd_nextbyte(&vrs, &byte2)) { 1170 state = -2; 1171 break; 1172 } 1173 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1174 if (dflen == 0 && 1175 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1176 2) == 0) { 1177 /* 1178 * if this happens, we can't trust the rest 1179 * of the VPD. 1180 */ 1181 pci_printf(cfg, "bad keyword length: %d\n", 1182 dflen); 1183 cksumvalid = 0; 1184 state = -1; 1185 break; 1186 } else if (dflen == 0) { 1187 cfg->vpd.vpd_ros[off].value = malloc(1 * 1188 sizeof(*cfg->vpd.vpd_ros[off].value), 1189 M_DEVBUF, M_WAITOK); 1190 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1191 } else 1192 cfg->vpd.vpd_ros[off].value = malloc( 1193 (dflen + 1) * 1194 sizeof(*cfg->vpd.vpd_ros[off].value), 1195 M_DEVBUF, M_WAITOK); 1196 remain -= 3; 1197 i = 0; 1198 /* keep in sync w/ state 3's transistions */ 1199 if (dflen == 0 && remain == 0) 1200 state = 0; 1201 else if (dflen == 0) 1202 state = 2; 1203 else 1204 state = 3; 1205 break; 1206 1207 case 3: /* VPD-R Keyword Value */ 1208 cfg->vpd.vpd_ros[off].value[i++] = byte; 1209 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1210 "RV", 2) == 0 && cksumvalid == -1) { 1211 if (vrs.cksum == 0) 1212 cksumvalid = 1; 1213 else { 1214 if (bootverbose) 1215 pci_printf(cfg, 1216 "bad VPD cksum, remain %hhu\n", 1217 vrs.cksum); 1218 cksumvalid = 0; 1219 state = -1; 1220 break; 1221 } 1222 } 1223 dflen--; 1224 remain--; 1225 /* keep in sync w/ state 2's transistions */ 1226 if (dflen == 0) 1227 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1228 if (dflen == 0 && remain == 0) { 1229 cfg->vpd.vpd_rocnt = off; 1230 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1231 off * sizeof(*cfg->vpd.vpd_ros), 1232 M_DEVBUF, M_WAITOK | M_ZERO); 1233 state = 0; 1234 } else if (dflen == 0) 1235 state = 2; 1236 break; 1237 1238 case 4: 1239 remain--; 1240 if (remain == 0) 1241 state = 0; 1242 break; 1243 1244 case 5: /* VPD-W Keyword Header */ 1245 if (off == alloc) { 1246 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1247 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1248 M_DEVBUF, M_WAITOK | M_ZERO); 1249 } 1250 cfg->vpd.vpd_w[off].keyword[0] = byte; 1251 if (vpd_nextbyte(&vrs, &byte2)) { 1252 state = -2; 1253 break; 1254 } 1255 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1256 if (vpd_nextbyte(&vrs, &byte2)) { 1257 state = -2; 1258 break; 1259 } 1260 cfg->vpd.vpd_w[off].len = dflen = byte2; 1261 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1262 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1263 sizeof(*cfg->vpd.vpd_w[off].value), 1264 M_DEVBUF, M_WAITOK); 1265 remain -= 3; 1266 i = 0; 1267 /* keep in sync w/ state 6's transistions */ 1268 if (dflen == 0 && remain == 0) 1269 state = 0; 1270 else if (dflen == 0) 1271 state = 5; 1272 else 1273 state = 6; 1274 break; 1275 1276 case 6: /* VPD-W Keyword Value */ 1277 cfg->vpd.vpd_w[off].value[i++] = byte; 1278 dflen--; 1279 remain--; 1280 /* keep in sync w/ state 5's transistions */ 1281 if (dflen == 0) 1282 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1283 if (dflen == 0 && remain == 0) { 1284 cfg->vpd.vpd_wcnt = off; 1285 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1286 off * sizeof(*cfg->vpd.vpd_w), 1287 M_DEVBUF, M_WAITOK | M_ZERO); 1288 state = 0; 1289 } else if (dflen == 0) 1290 state = 5; 1291 break; 1292 1293 default: 1294 pci_printf(cfg, "invalid state: %d\n", state); 1295 state = -1; 1296 break; 1297 } 1298 } 1299 1300 if (cksumvalid == 0 || state < -1) { 1301 /* read-only data bad, clean up */ 1302 if (cfg->vpd.vpd_ros != NULL) { 1303 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1304 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1305 free(cfg->vpd.vpd_ros, M_DEVBUF); 1306 cfg->vpd.vpd_ros = NULL; 1307 } 1308 } 1309 if (state < -1) { 1310 /* I/O error, clean up */ 1311 pci_printf(cfg, "failed to read VPD data.\n"); 1312 if (cfg->vpd.vpd_ident != NULL) { 1313 free(cfg->vpd.vpd_ident, M_DEVBUF); 1314 cfg->vpd.vpd_ident = NULL; 1315 } 1316 if (cfg->vpd.vpd_w != NULL) { 1317 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1318 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1319 free(cfg->vpd.vpd_w, M_DEVBUF); 1320 cfg->vpd.vpd_w = NULL; 1321 } 1322 } 1323 cfg->vpd.vpd_cached = 1; 1324 #undef REG 1325 #undef WREG 1326 } 1327 1328 int 1329 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1330 { 1331 struct pci_devinfo *dinfo = device_get_ivars(child); 1332 pcicfgregs *cfg = &dinfo->cfg; 1333 1334 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1335 pci_read_vpd(device_get_parent(dev), cfg); 1336 1337 *identptr = cfg->vpd.vpd_ident; 1338 1339 if (*identptr == NULL) 1340 return (ENXIO); 1341 1342 return (0); 1343 } 1344 1345 int 1346 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1347 const char **vptr) 1348 { 1349 struct pci_devinfo *dinfo = device_get_ivars(child); 1350 pcicfgregs *cfg = &dinfo->cfg; 1351 int i; 1352 1353 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1354 pci_read_vpd(device_get_parent(dev), cfg); 1355 1356 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1357 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1358 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1359 *vptr = cfg->vpd.vpd_ros[i].value; 1360 return (0); 1361 } 1362 1363 *vptr = NULL; 1364 return (ENXIO); 1365 } 1366 1367 struct pcicfg_vpd * 1368 pci_fetch_vpd_list(device_t dev) 1369 { 1370 struct pci_devinfo *dinfo = device_get_ivars(dev); 1371 pcicfgregs *cfg = &dinfo->cfg; 1372 1373 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1374 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1375 return (&cfg->vpd); 1376 } 1377 1378 /* 1379 * Find the requested HyperTransport capability and return the offset 1380 * in configuration space via the pointer provided. The function 1381 * returns 0 on success and an error code otherwise. 1382 */ 1383 int 1384 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1385 { 1386 int ptr, error; 1387 uint16_t val; 1388 1389 error = pci_find_cap(child, PCIY_HT, &ptr); 1390 if (error) 1391 return (error); 1392 1393 /* 1394 * Traverse the capabilities list checking each HT capability 1395 * to see if it matches the requested HT capability. 1396 */ 1397 for (;;) { 1398 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1399 if (capability == PCIM_HTCAP_SLAVE || 1400 capability == PCIM_HTCAP_HOST) 1401 val &= 0xe000; 1402 else 1403 val &= PCIM_HTCMD_CAP_MASK; 1404 if (val == capability) { 1405 if (capreg != NULL) 1406 *capreg = ptr; 1407 return (0); 1408 } 1409 1410 /* Skip to the next HT capability. */ 1411 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1412 break; 1413 } 1414 1415 return (ENOENT); 1416 } 1417 1418 /* 1419 * Find the next requested HyperTransport capability after start and return 1420 * the offset in configuration space via the pointer provided. The function 1421 * returns 0 on success and an error code otherwise. 1422 */ 1423 int 1424 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1425 int start, int *capreg) 1426 { 1427 int ptr; 1428 uint16_t val; 1429 1430 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1431 ("start capability is not HyperTransport capability")); 1432 ptr = start; 1433 1434 /* 1435 * Traverse the capabilities list checking each HT capability 1436 * to see if it matches the requested HT capability. 1437 */ 1438 for (;;) { 1439 /* Skip to the next HT capability. */ 1440 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1441 break; 1442 1443 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1444 if (capability == PCIM_HTCAP_SLAVE || 1445 capability == PCIM_HTCAP_HOST) 1446 val &= 0xe000; 1447 else 1448 val &= PCIM_HTCMD_CAP_MASK; 1449 if (val == capability) { 1450 if (capreg != NULL) 1451 *capreg = ptr; 1452 return (0); 1453 } 1454 } 1455 1456 return (ENOENT); 1457 } 1458 1459 /* 1460 * Find the requested capability and return the offset in 1461 * configuration space via the pointer provided. The function returns 1462 * 0 on success and an error code otherwise. 1463 */ 1464 int 1465 pci_find_cap_method(device_t dev, device_t child, int capability, 1466 int *capreg) 1467 { 1468 struct pci_devinfo *dinfo = device_get_ivars(child); 1469 pcicfgregs *cfg = &dinfo->cfg; 1470 uint32_t status; 1471 uint8_t ptr; 1472 1473 /* 1474 * Check the CAP_LIST bit of the PCI status register first. 1475 */ 1476 status = pci_read_config(child, PCIR_STATUS, 2); 1477 if (!(status & PCIM_STATUS_CAPPRESENT)) 1478 return (ENXIO); 1479 1480 /* 1481 * Determine the start pointer of the capabilities list. 1482 */ 1483 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1484 case PCIM_HDRTYPE_NORMAL: 1485 case PCIM_HDRTYPE_BRIDGE: 1486 ptr = PCIR_CAP_PTR; 1487 break; 1488 case PCIM_HDRTYPE_CARDBUS: 1489 ptr = PCIR_CAP_PTR_2; 1490 break; 1491 default: 1492 /* XXX: panic? */ 1493 return (ENXIO); /* no extended capabilities support */ 1494 } 1495 ptr = pci_read_config(child, ptr, 1); 1496 1497 /* 1498 * Traverse the capabilities list. 1499 */ 1500 while (ptr != 0) { 1501 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1502 if (capreg != NULL) 1503 *capreg = ptr; 1504 return (0); 1505 } 1506 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1507 } 1508 1509 return (ENOENT); 1510 } 1511 1512 /* 1513 * Find the next requested capability after start and return the offset in 1514 * configuration space via the pointer provided. The function returns 1515 * 0 on success and an error code otherwise. 1516 */ 1517 int 1518 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1519 int start, int *capreg) 1520 { 1521 uint8_t ptr; 1522 1523 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1524 ("start capability is not expected capability")); 1525 1526 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1527 while (ptr != 0) { 1528 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1529 if (capreg != NULL) 1530 *capreg = ptr; 1531 return (0); 1532 } 1533 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1534 } 1535 1536 return (ENOENT); 1537 } 1538 1539 /* 1540 * Find the requested extended capability and return the offset in 1541 * configuration space via the pointer provided. The function returns 1542 * 0 on success and an error code otherwise. 1543 */ 1544 int 1545 pci_find_extcap_method(device_t dev, device_t child, int capability, 1546 int *capreg) 1547 { 1548 struct pci_devinfo *dinfo = device_get_ivars(child); 1549 pcicfgregs *cfg = &dinfo->cfg; 1550 uint32_t ecap; 1551 uint16_t ptr; 1552 1553 /* Only supported for PCI-express devices. */ 1554 if (cfg->pcie.pcie_location == 0) 1555 return (ENXIO); 1556 1557 ptr = PCIR_EXTCAP; 1558 ecap = pci_read_config(child, ptr, 4); 1559 if (ecap == 0xffffffff || ecap == 0) 1560 return (ENOENT); 1561 for (;;) { 1562 if (PCI_EXTCAP_ID(ecap) == capability) { 1563 if (capreg != NULL) 1564 *capreg = ptr; 1565 return (0); 1566 } 1567 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1568 if (ptr == 0) 1569 break; 1570 ecap = pci_read_config(child, ptr, 4); 1571 } 1572 1573 return (ENOENT); 1574 } 1575 1576 /* 1577 * Find the next requested extended capability after start and return the 1578 * offset in configuration space via the pointer provided. The function 1579 * returns 0 on success and an error code otherwise. 1580 */ 1581 int 1582 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1583 int start, int *capreg) 1584 { 1585 struct pci_devinfo *dinfo = device_get_ivars(child); 1586 pcicfgregs *cfg = &dinfo->cfg; 1587 uint32_t ecap; 1588 uint16_t ptr; 1589 1590 /* Only supported for PCI-express devices. */ 1591 if (cfg->pcie.pcie_location == 0) 1592 return (ENXIO); 1593 1594 ecap = pci_read_config(child, start, 4); 1595 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1596 ("start extended capability is not expected capability")); 1597 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1598 while (ptr != 0) { 1599 ecap = pci_read_config(child, ptr, 4); 1600 if (PCI_EXTCAP_ID(ecap) == capability) { 1601 if (capreg != NULL) 1602 *capreg = ptr; 1603 return (0); 1604 } 1605 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1606 } 1607 1608 return (ENOENT); 1609 } 1610 1611 /* 1612 * Support for MSI-X message interrupts. 1613 */ 1614 static void 1615 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1616 { 1617 struct pci_devinfo *dinfo = device_get_ivars(dev); 1618 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1619 uint32_t offset; 1620 1621 KASSERT(msix->msix_table_len > index, ("bogus index")); 1622 offset = msix->msix_table_offset + index * 16; 1623 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1624 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1625 bus_write_4(msix->msix_table_res, offset + 8, data); 1626 } 1627 1628 void 1629 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1630 uint64_t address, uint32_t data) 1631 { 1632 1633 if (pci_msix_rewrite_table) { 1634 struct pci_devinfo *dinfo = device_get_ivars(child); 1635 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1636 1637 /* 1638 * Some VM hosts require MSIX to be disabled in the 1639 * control register before updating the MSIX table 1640 * entries are allowed. It is not enough to only 1641 * disable MSIX while updating a single entry. MSIX 1642 * must be disabled while updating all entries in the 1643 * table. 1644 */ 1645 pci_write_config(child, 1646 msix->msix_location + PCIR_MSIX_CTRL, 1647 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1648 pci_resume_msix(child); 1649 } else 1650 pci_write_msix_entry(child, index, address, data); 1651 1652 /* Enable MSI -> HT mapping. */ 1653 pci_ht_map_msi(child, address); 1654 } 1655 1656 void 1657 pci_mask_msix(device_t dev, u_int index) 1658 { 1659 struct pci_devinfo *dinfo = device_get_ivars(dev); 1660 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1661 uint32_t offset, val; 1662 1663 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1664 offset = msix->msix_table_offset + index * 16 + 12; 1665 val = bus_read_4(msix->msix_table_res, offset); 1666 val |= PCIM_MSIX_VCTRL_MASK; 1667 1668 /* 1669 * Some devices (e.g. Samsung PM961) do not support reads of this 1670 * register, so always write the new value. 1671 */ 1672 bus_write_4(msix->msix_table_res, offset, val); 1673 } 1674 1675 void 1676 pci_unmask_msix(device_t dev, u_int index) 1677 { 1678 struct pci_devinfo *dinfo = device_get_ivars(dev); 1679 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1680 uint32_t offset, val; 1681 1682 KASSERT(msix->msix_table_len > index, ("bogus index")); 1683 offset = msix->msix_table_offset + index * 16 + 12; 1684 val = bus_read_4(msix->msix_table_res, offset); 1685 val &= ~PCIM_MSIX_VCTRL_MASK; 1686 1687 /* 1688 * Some devices (e.g. Samsung PM961) do not support reads of this 1689 * register, so always write the new value. 1690 */ 1691 bus_write_4(msix->msix_table_res, offset, val); 1692 } 1693 1694 int 1695 pci_pending_msix(device_t dev, u_int index) 1696 { 1697 struct pci_devinfo *dinfo = device_get_ivars(dev); 1698 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1699 uint32_t offset, bit; 1700 1701 KASSERT(msix->msix_table_len > index, ("bogus index")); 1702 offset = msix->msix_pba_offset + (index / 32) * 4; 1703 bit = 1 << index % 32; 1704 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1705 } 1706 1707 /* 1708 * Restore MSI-X registers and table during resume. If MSI-X is 1709 * enabled then walk the virtual table to restore the actual MSI-X 1710 * table. 1711 */ 1712 static void 1713 pci_resume_msix(device_t dev) 1714 { 1715 struct pci_devinfo *dinfo = device_get_ivars(dev); 1716 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1717 struct msix_table_entry *mte; 1718 struct msix_vector *mv; 1719 int i; 1720 1721 if (msix->msix_alloc > 0) { 1722 /* First, mask all vectors. */ 1723 for (i = 0; i < msix->msix_msgnum; i++) 1724 pci_mask_msix(dev, i); 1725 1726 /* Second, program any messages with at least one handler. */ 1727 for (i = 0; i < msix->msix_table_len; i++) { 1728 mte = &msix->msix_table[i]; 1729 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1730 continue; 1731 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1732 pci_write_msix_entry(dev, i, mv->mv_address, 1733 mv->mv_data); 1734 pci_unmask_msix(dev, i); 1735 } 1736 } 1737 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1738 msix->msix_ctrl, 2); 1739 } 1740 1741 /* 1742 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1743 * returned in *count. After this function returns, each message will be 1744 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1745 */ 1746 int 1747 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1748 { 1749 struct pci_devinfo *dinfo = device_get_ivars(child); 1750 pcicfgregs *cfg = &dinfo->cfg; 1751 struct resource_list_entry *rle; 1752 int actual, error, i, irq, max; 1753 1754 /* Don't let count == 0 get us into trouble. */ 1755 if (*count == 0) 1756 return (EINVAL); 1757 1758 /* If rid 0 is allocated, then fail. */ 1759 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1760 if (rle != NULL && rle->res != NULL) 1761 return (ENXIO); 1762 1763 /* Already have allocated messages? */ 1764 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1765 return (ENXIO); 1766 1767 /* If MSI-X is blacklisted for this system, fail. */ 1768 if (pci_msix_blacklisted()) 1769 return (ENXIO); 1770 1771 /* MSI-X capability present? */ 1772 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1773 return (ENODEV); 1774 1775 /* Make sure the appropriate BARs are mapped. */ 1776 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1777 cfg->msix.msix_table_bar); 1778 if (rle == NULL || rle->res == NULL || 1779 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1780 return (ENXIO); 1781 cfg->msix.msix_table_res = rle->res; 1782 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1783 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1784 cfg->msix.msix_pba_bar); 1785 if (rle == NULL || rle->res == NULL || 1786 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1787 return (ENXIO); 1788 } 1789 cfg->msix.msix_pba_res = rle->res; 1790 1791 if (bootverbose) 1792 device_printf(child, 1793 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1794 *count, cfg->msix.msix_msgnum); 1795 max = min(*count, cfg->msix.msix_msgnum); 1796 for (i = 0; i < max; i++) { 1797 /* Allocate a message. */ 1798 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1799 if (error) { 1800 if (i == 0) 1801 return (error); 1802 break; 1803 } 1804 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1805 irq, 1); 1806 } 1807 actual = i; 1808 1809 if (bootverbose) { 1810 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1811 if (actual == 1) 1812 device_printf(child, "using IRQ %ju for MSI-X\n", 1813 rle->start); 1814 else { 1815 int run; 1816 1817 /* 1818 * Be fancy and try to print contiguous runs of 1819 * IRQ values as ranges. 'irq' is the previous IRQ. 1820 * 'run' is true if we are in a range. 1821 */ 1822 device_printf(child, "using IRQs %ju", rle->start); 1823 irq = rle->start; 1824 run = 0; 1825 for (i = 1; i < actual; i++) { 1826 rle = resource_list_find(&dinfo->resources, 1827 SYS_RES_IRQ, i + 1); 1828 1829 /* Still in a run? */ 1830 if (rle->start == irq + 1) { 1831 run = 1; 1832 irq++; 1833 continue; 1834 } 1835 1836 /* Finish previous range. */ 1837 if (run) { 1838 printf("-%d", irq); 1839 run = 0; 1840 } 1841 1842 /* Start new range. */ 1843 printf(",%ju", rle->start); 1844 irq = rle->start; 1845 } 1846 1847 /* Unfinished range? */ 1848 if (run) 1849 printf("-%d", irq); 1850 printf(" for MSI-X\n"); 1851 } 1852 } 1853 1854 /* Mask all vectors. */ 1855 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1856 pci_mask_msix(child, i); 1857 1858 /* Allocate and initialize vector data and virtual table. */ 1859 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1860 M_DEVBUF, M_WAITOK | M_ZERO); 1861 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1862 M_DEVBUF, M_WAITOK | M_ZERO); 1863 for (i = 0; i < actual; i++) { 1864 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1865 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1866 cfg->msix.msix_table[i].mte_vector = i + 1; 1867 } 1868 1869 /* Update control register to enable MSI-X. */ 1870 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1871 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1872 cfg->msix.msix_ctrl, 2); 1873 1874 /* Update counts of alloc'd messages. */ 1875 cfg->msix.msix_alloc = actual; 1876 cfg->msix.msix_table_len = actual; 1877 *count = actual; 1878 return (0); 1879 } 1880 1881 /* 1882 * By default, pci_alloc_msix() will assign the allocated IRQ 1883 * resources consecutively to the first N messages in the MSI-X table. 1884 * However, device drivers may want to use different layouts if they 1885 * either receive fewer messages than they asked for, or they wish to 1886 * populate the MSI-X table sparsely. This method allows the driver 1887 * to specify what layout it wants. It must be called after a 1888 * successful pci_alloc_msix() but before any of the associated 1889 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1890 * 1891 * The 'vectors' array contains 'count' message vectors. The array 1892 * maps directly to the MSI-X table in that index 0 in the array 1893 * specifies the vector for the first message in the MSI-X table, etc. 1894 * The vector value in each array index can either be 0 to indicate 1895 * that no vector should be assigned to a message slot, or it can be a 1896 * number from 1 to N (where N is the count returned from a 1897 * succcessful call to pci_alloc_msix()) to indicate which message 1898 * vector (IRQ) to be used for the corresponding message. 1899 * 1900 * On successful return, each message with a non-zero vector will have 1901 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1902 * 1. Additionally, if any of the IRQs allocated via the previous 1903 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1904 * will be freed back to the system automatically. 1905 * 1906 * For example, suppose a driver has a MSI-X table with 6 messages and 1907 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1908 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1909 * C. After the call to pci_alloc_msix(), the device will be setup to 1910 * have an MSI-X table of ABC--- (where - means no vector assigned). 1911 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1912 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1913 * be freed back to the system. This device will also have valid 1914 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1915 * 1916 * In any case, the SYS_RES_IRQ rid X will always map to the message 1917 * at MSI-X table index X - 1 and will only be valid if a vector is 1918 * assigned to that table entry. 1919 */ 1920 int 1921 pci_remap_msix_method(device_t dev, device_t child, int count, 1922 const u_int *vectors) 1923 { 1924 struct pci_devinfo *dinfo = device_get_ivars(child); 1925 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1926 struct resource_list_entry *rle; 1927 int i, irq, j, *used; 1928 1929 /* 1930 * Have to have at least one message in the table but the 1931 * table can't be bigger than the actual MSI-X table in the 1932 * device. 1933 */ 1934 if (count == 0 || count > msix->msix_msgnum) 1935 return (EINVAL); 1936 1937 /* Sanity check the vectors. */ 1938 for (i = 0; i < count; i++) 1939 if (vectors[i] > msix->msix_alloc) 1940 return (EINVAL); 1941 1942 /* 1943 * Make sure there aren't any holes in the vectors to be used. 1944 * It's a big pain to support it, and it doesn't really make 1945 * sense anyway. Also, at least one vector must be used. 1946 */ 1947 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1948 M_ZERO); 1949 for (i = 0; i < count; i++) 1950 if (vectors[i] != 0) 1951 used[vectors[i] - 1] = 1; 1952 for (i = 0; i < msix->msix_alloc - 1; i++) 1953 if (used[i] == 0 && used[i + 1] == 1) { 1954 free(used, M_DEVBUF); 1955 return (EINVAL); 1956 } 1957 if (used[0] != 1) { 1958 free(used, M_DEVBUF); 1959 return (EINVAL); 1960 } 1961 1962 /* Make sure none of the resources are allocated. */ 1963 for (i = 0; i < msix->msix_table_len; i++) { 1964 if (msix->msix_table[i].mte_vector == 0) 1965 continue; 1966 if (msix->msix_table[i].mte_handlers > 0) { 1967 free(used, M_DEVBUF); 1968 return (EBUSY); 1969 } 1970 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1971 KASSERT(rle != NULL, ("missing resource")); 1972 if (rle->res != NULL) { 1973 free(used, M_DEVBUF); 1974 return (EBUSY); 1975 } 1976 } 1977 1978 /* Free the existing resource list entries. */ 1979 for (i = 0; i < msix->msix_table_len; i++) { 1980 if (msix->msix_table[i].mte_vector == 0) 1981 continue; 1982 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1983 } 1984 1985 /* 1986 * Build the new virtual table keeping track of which vectors are 1987 * used. 1988 */ 1989 free(msix->msix_table, M_DEVBUF); 1990 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 1991 M_DEVBUF, M_WAITOK | M_ZERO); 1992 for (i = 0; i < count; i++) 1993 msix->msix_table[i].mte_vector = vectors[i]; 1994 msix->msix_table_len = count; 1995 1996 /* Free any unused IRQs and resize the vectors array if necessary. */ 1997 j = msix->msix_alloc - 1; 1998 if (used[j] == 0) { 1999 struct msix_vector *vec; 2000 2001 while (used[j] == 0) { 2002 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2003 msix->msix_vectors[j].mv_irq); 2004 j--; 2005 } 2006 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 2007 M_WAITOK); 2008 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2009 (j + 1)); 2010 free(msix->msix_vectors, M_DEVBUF); 2011 msix->msix_vectors = vec; 2012 msix->msix_alloc = j + 1; 2013 } 2014 free(used, M_DEVBUF); 2015 2016 /* Map the IRQs onto the rids. */ 2017 for (i = 0; i < count; i++) { 2018 if (vectors[i] == 0) 2019 continue; 2020 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2021 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2022 irq, 1); 2023 } 2024 2025 if (bootverbose) { 2026 device_printf(child, "Remapped MSI-X IRQs as: "); 2027 for (i = 0; i < count; i++) { 2028 if (i != 0) 2029 printf(", "); 2030 if (vectors[i] == 0) 2031 printf("---"); 2032 else 2033 printf("%d", 2034 msix->msix_vectors[vectors[i] - 1].mv_irq); 2035 } 2036 printf("\n"); 2037 } 2038 2039 return (0); 2040 } 2041 2042 static int 2043 pci_release_msix(device_t dev, device_t child) 2044 { 2045 struct pci_devinfo *dinfo = device_get_ivars(child); 2046 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2047 struct resource_list_entry *rle; 2048 int i; 2049 2050 /* Do we have any messages to release? */ 2051 if (msix->msix_alloc == 0) 2052 return (ENODEV); 2053 2054 /* Make sure none of the resources are allocated. */ 2055 for (i = 0; i < msix->msix_table_len; i++) { 2056 if (msix->msix_table[i].mte_vector == 0) 2057 continue; 2058 if (msix->msix_table[i].mte_handlers > 0) 2059 return (EBUSY); 2060 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2061 KASSERT(rle != NULL, ("missing resource")); 2062 if (rle->res != NULL) 2063 return (EBUSY); 2064 } 2065 2066 /* Update control register to disable MSI-X. */ 2067 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2068 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2069 msix->msix_ctrl, 2); 2070 2071 /* Free the resource list entries. */ 2072 for (i = 0; i < msix->msix_table_len; i++) { 2073 if (msix->msix_table[i].mte_vector == 0) 2074 continue; 2075 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2076 } 2077 free(msix->msix_table, M_DEVBUF); 2078 msix->msix_table_len = 0; 2079 2080 /* Release the IRQs. */ 2081 for (i = 0; i < msix->msix_alloc; i++) 2082 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2083 msix->msix_vectors[i].mv_irq); 2084 free(msix->msix_vectors, M_DEVBUF); 2085 msix->msix_alloc = 0; 2086 return (0); 2087 } 2088 2089 /* 2090 * Return the max supported MSI-X messages this device supports. 2091 * Basically, assuming the MD code can alloc messages, this function 2092 * should return the maximum value that pci_alloc_msix() can return. 2093 * Thus, it is subject to the tunables, etc. 2094 */ 2095 int 2096 pci_msix_count_method(device_t dev, device_t child) 2097 { 2098 struct pci_devinfo *dinfo = device_get_ivars(child); 2099 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2100 2101 if (pci_do_msix && msix->msix_location != 0) 2102 return (msix->msix_msgnum); 2103 return (0); 2104 } 2105 2106 int 2107 pci_msix_pba_bar_method(device_t dev, device_t child) 2108 { 2109 struct pci_devinfo *dinfo = device_get_ivars(child); 2110 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2111 2112 if (pci_do_msix && msix->msix_location != 0) 2113 return (msix->msix_pba_bar); 2114 return (-1); 2115 } 2116 2117 int 2118 pci_msix_table_bar_method(device_t dev, device_t child) 2119 { 2120 struct pci_devinfo *dinfo = device_get_ivars(child); 2121 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2122 2123 if (pci_do_msix && msix->msix_location != 0) 2124 return (msix->msix_table_bar); 2125 return (-1); 2126 } 2127 2128 /* 2129 * HyperTransport MSI mapping control 2130 */ 2131 void 2132 pci_ht_map_msi(device_t dev, uint64_t addr) 2133 { 2134 struct pci_devinfo *dinfo = device_get_ivars(dev); 2135 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2136 2137 if (!ht->ht_msimap) 2138 return; 2139 2140 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2141 ht->ht_msiaddr >> 20 == addr >> 20) { 2142 /* Enable MSI -> HT mapping. */ 2143 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2144 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2145 ht->ht_msictrl, 2); 2146 } 2147 2148 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2149 /* Disable MSI -> HT mapping. */ 2150 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2151 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2152 ht->ht_msictrl, 2); 2153 } 2154 } 2155 2156 int 2157 pci_get_max_payload(device_t dev) 2158 { 2159 struct pci_devinfo *dinfo = device_get_ivars(dev); 2160 int cap; 2161 uint16_t val; 2162 2163 cap = dinfo->cfg.pcie.pcie_location; 2164 if (cap == 0) 2165 return (0); 2166 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2167 val &= PCIEM_CTL_MAX_PAYLOAD; 2168 val >>= 5; 2169 return (1 << (val + 7)); 2170 } 2171 2172 int 2173 pci_get_max_read_req(device_t dev) 2174 { 2175 struct pci_devinfo *dinfo = device_get_ivars(dev); 2176 int cap; 2177 uint16_t val; 2178 2179 cap = dinfo->cfg.pcie.pcie_location; 2180 if (cap == 0) 2181 return (0); 2182 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2183 val &= PCIEM_CTL_MAX_READ_REQUEST; 2184 val >>= 12; 2185 return (1 << (val + 7)); 2186 } 2187 2188 int 2189 pci_set_max_read_req(device_t dev, int size) 2190 { 2191 struct pci_devinfo *dinfo = device_get_ivars(dev); 2192 int cap; 2193 uint16_t val; 2194 2195 cap = dinfo->cfg.pcie.pcie_location; 2196 if (cap == 0) 2197 return (0); 2198 if (size < 128) 2199 size = 128; 2200 if (size > 4096) 2201 size = 4096; 2202 size = (1 << (fls(size) - 1)); 2203 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2204 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2205 val |= (fls(size) - 8) << 12; 2206 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2207 return (size); 2208 } 2209 2210 uint32_t 2211 pcie_read_config(device_t dev, int reg, int width) 2212 { 2213 struct pci_devinfo *dinfo = device_get_ivars(dev); 2214 int cap; 2215 2216 cap = dinfo->cfg.pcie.pcie_location; 2217 if (cap == 0) { 2218 if (width == 2) 2219 return (0xffff); 2220 return (0xffffffff); 2221 } 2222 2223 return (pci_read_config(dev, cap + reg, width)); 2224 } 2225 2226 void 2227 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2228 { 2229 struct pci_devinfo *dinfo = device_get_ivars(dev); 2230 int cap; 2231 2232 cap = dinfo->cfg.pcie.pcie_location; 2233 if (cap == 0) 2234 return; 2235 pci_write_config(dev, cap + reg, value, width); 2236 } 2237 2238 /* 2239 * Adjusts a PCI-e capability register by clearing the bits in mask 2240 * and setting the bits in (value & mask). Bits not set in mask are 2241 * not adjusted. 2242 * 2243 * Returns the old value on success or all ones on failure. 2244 */ 2245 uint32_t 2246 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2247 int width) 2248 { 2249 struct pci_devinfo *dinfo = device_get_ivars(dev); 2250 uint32_t old, new; 2251 int cap; 2252 2253 cap = dinfo->cfg.pcie.pcie_location; 2254 if (cap == 0) { 2255 if (width == 2) 2256 return (0xffff); 2257 return (0xffffffff); 2258 } 2259 2260 old = pci_read_config(dev, cap + reg, width); 2261 new = old & ~mask; 2262 new |= (value & mask); 2263 pci_write_config(dev, cap + reg, new, width); 2264 return (old); 2265 } 2266 2267 /* 2268 * Support for MSI message signalled interrupts. 2269 */ 2270 void 2271 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2272 uint16_t data) 2273 { 2274 struct pci_devinfo *dinfo = device_get_ivars(child); 2275 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2276 2277 /* Write data and address values. */ 2278 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2279 address & 0xffffffff, 4); 2280 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2281 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2282 address >> 32, 4); 2283 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2284 data, 2); 2285 } else 2286 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2287 2); 2288 2289 /* Enable MSI in the control register. */ 2290 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2291 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2292 msi->msi_ctrl, 2); 2293 2294 /* Enable MSI -> HT mapping. */ 2295 pci_ht_map_msi(child, address); 2296 } 2297 2298 void 2299 pci_disable_msi_method(device_t dev, device_t child) 2300 { 2301 struct pci_devinfo *dinfo = device_get_ivars(child); 2302 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2303 2304 /* Disable MSI -> HT mapping. */ 2305 pci_ht_map_msi(child, 0); 2306 2307 /* Disable MSI in the control register. */ 2308 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2309 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2310 msi->msi_ctrl, 2); 2311 } 2312 2313 /* 2314 * Restore MSI registers during resume. If MSI is enabled then 2315 * restore the data and address registers in addition to the control 2316 * register. 2317 */ 2318 static void 2319 pci_resume_msi(device_t dev) 2320 { 2321 struct pci_devinfo *dinfo = device_get_ivars(dev); 2322 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2323 uint64_t address; 2324 uint16_t data; 2325 2326 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2327 address = msi->msi_addr; 2328 data = msi->msi_data; 2329 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2330 address & 0xffffffff, 4); 2331 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2332 pci_write_config(dev, msi->msi_location + 2333 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2334 pci_write_config(dev, msi->msi_location + 2335 PCIR_MSI_DATA_64BIT, data, 2); 2336 } else 2337 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2338 data, 2); 2339 } 2340 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2341 2); 2342 } 2343 2344 static int 2345 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2346 { 2347 struct pci_devinfo *dinfo = device_get_ivars(dev); 2348 pcicfgregs *cfg = &dinfo->cfg; 2349 struct resource_list_entry *rle; 2350 struct msix_table_entry *mte; 2351 struct msix_vector *mv; 2352 uint64_t addr; 2353 uint32_t data; 2354 int error, i, j; 2355 2356 /* 2357 * Handle MSI first. We try to find this IRQ among our list 2358 * of MSI IRQs. If we find it, we request updated address and 2359 * data registers and apply the results. 2360 */ 2361 if (cfg->msi.msi_alloc > 0) { 2362 2363 /* If we don't have any active handlers, nothing to do. */ 2364 if (cfg->msi.msi_handlers == 0) 2365 return (0); 2366 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2367 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2368 i + 1); 2369 if (rle->start == irq) { 2370 error = PCIB_MAP_MSI(device_get_parent(bus), 2371 dev, irq, &addr, &data); 2372 if (error) 2373 return (error); 2374 pci_disable_msi(dev); 2375 dinfo->cfg.msi.msi_addr = addr; 2376 dinfo->cfg.msi.msi_data = data; 2377 pci_enable_msi(dev, addr, data); 2378 return (0); 2379 } 2380 } 2381 return (ENOENT); 2382 } 2383 2384 /* 2385 * For MSI-X, we check to see if we have this IRQ. If we do, 2386 * we request the updated mapping info. If that works, we go 2387 * through all the slots that use this IRQ and update them. 2388 */ 2389 if (cfg->msix.msix_alloc > 0) { 2390 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2391 mv = &cfg->msix.msix_vectors[i]; 2392 if (mv->mv_irq == irq) { 2393 error = PCIB_MAP_MSI(device_get_parent(bus), 2394 dev, irq, &addr, &data); 2395 if (error) 2396 return (error); 2397 mv->mv_address = addr; 2398 mv->mv_data = data; 2399 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2400 mte = &cfg->msix.msix_table[j]; 2401 if (mte->mte_vector != i + 1) 2402 continue; 2403 if (mte->mte_handlers == 0) 2404 continue; 2405 pci_mask_msix(dev, j); 2406 pci_enable_msix(dev, j, addr, data); 2407 pci_unmask_msix(dev, j); 2408 } 2409 } 2410 } 2411 return (ENOENT); 2412 } 2413 2414 return (ENOENT); 2415 } 2416 2417 /* 2418 * Returns true if the specified device is blacklisted because MSI 2419 * doesn't work. 2420 */ 2421 int 2422 pci_msi_device_blacklisted(device_t dev) 2423 { 2424 2425 if (!pci_honor_msi_blacklist) 2426 return (0); 2427 2428 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2429 } 2430 2431 /* 2432 * Determine if MSI is blacklisted globally on this system. Currently, 2433 * we just check for blacklisted chipsets as represented by the 2434 * host-PCI bridge at device 0:0:0. In the future, it may become 2435 * necessary to check other system attributes, such as the kenv values 2436 * that give the motherboard manufacturer and model number. 2437 */ 2438 static int 2439 pci_msi_blacklisted(void) 2440 { 2441 device_t dev; 2442 2443 if (!pci_honor_msi_blacklist) 2444 return (0); 2445 2446 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2447 if (!(pcie_chipset || pcix_chipset)) { 2448 if (vm_guest != VM_GUEST_NO) { 2449 /* 2450 * Whitelist older chipsets in virtual 2451 * machines known to support MSI. 2452 */ 2453 dev = pci_find_bsf(0, 0, 0); 2454 if (dev != NULL) 2455 return (!pci_has_quirk(pci_get_devid(dev), 2456 PCI_QUIRK_ENABLE_MSI_VM)); 2457 } 2458 return (1); 2459 } 2460 2461 dev = pci_find_bsf(0, 0, 0); 2462 if (dev != NULL) 2463 return (pci_msi_device_blacklisted(dev)); 2464 return (0); 2465 } 2466 2467 /* 2468 * Returns true if the specified device is blacklisted because MSI-X 2469 * doesn't work. Note that this assumes that if MSI doesn't work, 2470 * MSI-X doesn't either. 2471 */ 2472 int 2473 pci_msix_device_blacklisted(device_t dev) 2474 { 2475 2476 if (!pci_honor_msi_blacklist) 2477 return (0); 2478 2479 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2480 return (1); 2481 2482 return (pci_msi_device_blacklisted(dev)); 2483 } 2484 2485 /* 2486 * Determine if MSI-X is blacklisted globally on this system. If MSI 2487 * is blacklisted, assume that MSI-X is as well. Check for additional 2488 * chipsets where MSI works but MSI-X does not. 2489 */ 2490 static int 2491 pci_msix_blacklisted(void) 2492 { 2493 device_t dev; 2494 2495 if (!pci_honor_msi_blacklist) 2496 return (0); 2497 2498 dev = pci_find_bsf(0, 0, 0); 2499 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2500 PCI_QUIRK_DISABLE_MSIX)) 2501 return (1); 2502 2503 return (pci_msi_blacklisted()); 2504 } 2505 2506 /* 2507 * Attempt to allocate *count MSI messages. The actual number allocated is 2508 * returned in *count. After this function returns, each message will be 2509 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2510 */ 2511 int 2512 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2513 { 2514 struct pci_devinfo *dinfo = device_get_ivars(child); 2515 pcicfgregs *cfg = &dinfo->cfg; 2516 struct resource_list_entry *rle; 2517 int actual, error, i, irqs[32]; 2518 uint16_t ctrl; 2519 2520 /* Don't let count == 0 get us into trouble. */ 2521 if (*count == 0) 2522 return (EINVAL); 2523 2524 /* If rid 0 is allocated, then fail. */ 2525 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2526 if (rle != NULL && rle->res != NULL) 2527 return (ENXIO); 2528 2529 /* Already have allocated messages? */ 2530 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2531 return (ENXIO); 2532 2533 /* If MSI is blacklisted for this system, fail. */ 2534 if (pci_msi_blacklisted()) 2535 return (ENXIO); 2536 2537 /* MSI capability present? */ 2538 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2539 return (ENODEV); 2540 2541 if (bootverbose) 2542 device_printf(child, 2543 "attempting to allocate %d MSI vectors (%d supported)\n", 2544 *count, cfg->msi.msi_msgnum); 2545 2546 /* Don't ask for more than the device supports. */ 2547 actual = min(*count, cfg->msi.msi_msgnum); 2548 2549 /* Don't ask for more than 32 messages. */ 2550 actual = min(actual, 32); 2551 2552 /* MSI requires power of 2 number of messages. */ 2553 if (!powerof2(actual)) 2554 return (EINVAL); 2555 2556 for (;;) { 2557 /* Try to allocate N messages. */ 2558 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2559 actual, irqs); 2560 if (error == 0) 2561 break; 2562 if (actual == 1) 2563 return (error); 2564 2565 /* Try N / 2. */ 2566 actual >>= 1; 2567 } 2568 2569 /* 2570 * We now have N actual messages mapped onto SYS_RES_IRQ 2571 * resources in the irqs[] array, so add new resources 2572 * starting at rid 1. 2573 */ 2574 for (i = 0; i < actual; i++) 2575 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2576 irqs[i], irqs[i], 1); 2577 2578 if (bootverbose) { 2579 if (actual == 1) 2580 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2581 else { 2582 int run; 2583 2584 /* 2585 * Be fancy and try to print contiguous runs 2586 * of IRQ values as ranges. 'run' is true if 2587 * we are in a range. 2588 */ 2589 device_printf(child, "using IRQs %d", irqs[0]); 2590 run = 0; 2591 for (i = 1; i < actual; i++) { 2592 2593 /* Still in a run? */ 2594 if (irqs[i] == irqs[i - 1] + 1) { 2595 run = 1; 2596 continue; 2597 } 2598 2599 /* Finish previous range. */ 2600 if (run) { 2601 printf("-%d", irqs[i - 1]); 2602 run = 0; 2603 } 2604 2605 /* Start new range. */ 2606 printf(",%d", irqs[i]); 2607 } 2608 2609 /* Unfinished range? */ 2610 if (run) 2611 printf("-%d", irqs[actual - 1]); 2612 printf(" for MSI\n"); 2613 } 2614 } 2615 2616 /* Update control register with actual count. */ 2617 ctrl = cfg->msi.msi_ctrl; 2618 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2619 ctrl |= (ffs(actual) - 1) << 4; 2620 cfg->msi.msi_ctrl = ctrl; 2621 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2622 2623 /* Update counts of alloc'd messages. */ 2624 cfg->msi.msi_alloc = actual; 2625 cfg->msi.msi_handlers = 0; 2626 *count = actual; 2627 return (0); 2628 } 2629 2630 /* Release the MSI messages associated with this device. */ 2631 int 2632 pci_release_msi_method(device_t dev, device_t child) 2633 { 2634 struct pci_devinfo *dinfo = device_get_ivars(child); 2635 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2636 struct resource_list_entry *rle; 2637 int error, i, irqs[32]; 2638 2639 /* Try MSI-X first. */ 2640 error = pci_release_msix(dev, child); 2641 if (error != ENODEV) 2642 return (error); 2643 2644 /* Do we have any messages to release? */ 2645 if (msi->msi_alloc == 0) 2646 return (ENODEV); 2647 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2648 2649 /* Make sure none of the resources are allocated. */ 2650 if (msi->msi_handlers > 0) 2651 return (EBUSY); 2652 for (i = 0; i < msi->msi_alloc; i++) { 2653 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2654 KASSERT(rle != NULL, ("missing MSI resource")); 2655 if (rle->res != NULL) 2656 return (EBUSY); 2657 irqs[i] = rle->start; 2658 } 2659 2660 /* Update control register with 0 count. */ 2661 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2662 ("%s: MSI still enabled", __func__)); 2663 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2664 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2665 msi->msi_ctrl, 2); 2666 2667 /* Release the messages. */ 2668 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2669 for (i = 0; i < msi->msi_alloc; i++) 2670 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2671 2672 /* Update alloc count. */ 2673 msi->msi_alloc = 0; 2674 msi->msi_addr = 0; 2675 msi->msi_data = 0; 2676 return (0); 2677 } 2678 2679 /* 2680 * Return the max supported MSI messages this device supports. 2681 * Basically, assuming the MD code can alloc messages, this function 2682 * should return the maximum value that pci_alloc_msi() can return. 2683 * Thus, it is subject to the tunables, etc. 2684 */ 2685 int 2686 pci_msi_count_method(device_t dev, device_t child) 2687 { 2688 struct pci_devinfo *dinfo = device_get_ivars(child); 2689 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2690 2691 if (pci_do_msi && msi->msi_location != 0) 2692 return (msi->msi_msgnum); 2693 return (0); 2694 } 2695 2696 /* free pcicfgregs structure and all depending data structures */ 2697 2698 int 2699 pci_freecfg(struct pci_devinfo *dinfo) 2700 { 2701 struct devlist *devlist_head; 2702 struct pci_map *pm, *next; 2703 int i; 2704 2705 devlist_head = &pci_devq; 2706 2707 if (dinfo->cfg.vpd.vpd_reg) { 2708 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2709 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2710 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2711 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2712 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2713 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2714 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2715 } 2716 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2717 free(pm, M_DEVBUF); 2718 } 2719 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2720 free(dinfo, M_DEVBUF); 2721 2722 /* increment the generation count */ 2723 pci_generation++; 2724 2725 /* we're losing one device */ 2726 pci_numdevs--; 2727 return (0); 2728 } 2729 2730 /* 2731 * PCI power manangement 2732 */ 2733 int 2734 pci_set_powerstate_method(device_t dev, device_t child, int state) 2735 { 2736 struct pci_devinfo *dinfo = device_get_ivars(child); 2737 pcicfgregs *cfg = &dinfo->cfg; 2738 uint16_t status; 2739 int oldstate, highest, delay; 2740 2741 if (cfg->pp.pp_cap == 0) 2742 return (EOPNOTSUPP); 2743 2744 /* 2745 * Optimize a no state change request away. While it would be OK to 2746 * write to the hardware in theory, some devices have shown odd 2747 * behavior when going from D3 -> D3. 2748 */ 2749 oldstate = pci_get_powerstate(child); 2750 if (oldstate == state) 2751 return (0); 2752 2753 /* 2754 * The PCI power management specification states that after a state 2755 * transition between PCI power states, system software must 2756 * guarantee a minimal delay before the function accesses the device. 2757 * Compute the worst case delay that we need to guarantee before we 2758 * access the device. Many devices will be responsive much more 2759 * quickly than this delay, but there are some that don't respond 2760 * instantly to state changes. Transitions to/from D3 state require 2761 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2762 * is done below with DELAY rather than a sleeper function because 2763 * this function can be called from contexts where we cannot sleep. 2764 */ 2765 highest = (oldstate > state) ? oldstate : state; 2766 if (highest == PCI_POWERSTATE_D3) 2767 delay = 10000; 2768 else if (highest == PCI_POWERSTATE_D2) 2769 delay = 200; 2770 else 2771 delay = 0; 2772 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2773 & ~PCIM_PSTAT_DMASK; 2774 switch (state) { 2775 case PCI_POWERSTATE_D0: 2776 status |= PCIM_PSTAT_D0; 2777 break; 2778 case PCI_POWERSTATE_D1: 2779 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2780 return (EOPNOTSUPP); 2781 status |= PCIM_PSTAT_D1; 2782 break; 2783 case PCI_POWERSTATE_D2: 2784 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2785 return (EOPNOTSUPP); 2786 status |= PCIM_PSTAT_D2; 2787 break; 2788 case PCI_POWERSTATE_D3: 2789 status |= PCIM_PSTAT_D3; 2790 break; 2791 default: 2792 return (EINVAL); 2793 } 2794 2795 if (bootverbose) 2796 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2797 state); 2798 2799 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2800 if (delay) 2801 DELAY(delay); 2802 return (0); 2803 } 2804 2805 int 2806 pci_get_powerstate_method(device_t dev, device_t child) 2807 { 2808 struct pci_devinfo *dinfo = device_get_ivars(child); 2809 pcicfgregs *cfg = &dinfo->cfg; 2810 uint16_t status; 2811 int result; 2812 2813 if (cfg->pp.pp_cap != 0) { 2814 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2815 switch (status & PCIM_PSTAT_DMASK) { 2816 case PCIM_PSTAT_D0: 2817 result = PCI_POWERSTATE_D0; 2818 break; 2819 case PCIM_PSTAT_D1: 2820 result = PCI_POWERSTATE_D1; 2821 break; 2822 case PCIM_PSTAT_D2: 2823 result = PCI_POWERSTATE_D2; 2824 break; 2825 case PCIM_PSTAT_D3: 2826 result = PCI_POWERSTATE_D3; 2827 break; 2828 default: 2829 result = PCI_POWERSTATE_UNKNOWN; 2830 break; 2831 } 2832 } else { 2833 /* No support, device is always at D0 */ 2834 result = PCI_POWERSTATE_D0; 2835 } 2836 return (result); 2837 } 2838 2839 /* 2840 * Some convenience functions for PCI device drivers. 2841 */ 2842 2843 static __inline void 2844 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2845 { 2846 uint16_t command; 2847 2848 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2849 command |= bit; 2850 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2851 } 2852 2853 static __inline void 2854 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2855 { 2856 uint16_t command; 2857 2858 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2859 command &= ~bit; 2860 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2861 } 2862 2863 int 2864 pci_enable_busmaster_method(device_t dev, device_t child) 2865 { 2866 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2867 return (0); 2868 } 2869 2870 int 2871 pci_disable_busmaster_method(device_t dev, device_t child) 2872 { 2873 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2874 return (0); 2875 } 2876 2877 int 2878 pci_enable_io_method(device_t dev, device_t child, int space) 2879 { 2880 uint16_t bit; 2881 2882 switch(space) { 2883 case SYS_RES_IOPORT: 2884 bit = PCIM_CMD_PORTEN; 2885 break; 2886 case SYS_RES_MEMORY: 2887 bit = PCIM_CMD_MEMEN; 2888 break; 2889 default: 2890 return (EINVAL); 2891 } 2892 pci_set_command_bit(dev, child, bit); 2893 return (0); 2894 } 2895 2896 int 2897 pci_disable_io_method(device_t dev, device_t child, int space) 2898 { 2899 uint16_t bit; 2900 2901 switch(space) { 2902 case SYS_RES_IOPORT: 2903 bit = PCIM_CMD_PORTEN; 2904 break; 2905 case SYS_RES_MEMORY: 2906 bit = PCIM_CMD_MEMEN; 2907 break; 2908 default: 2909 return (EINVAL); 2910 } 2911 pci_clear_command_bit(dev, child, bit); 2912 return (0); 2913 } 2914 2915 /* 2916 * New style pci driver. Parent device is either a pci-host-bridge or a 2917 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2918 */ 2919 2920 void 2921 pci_print_verbose(struct pci_devinfo *dinfo) 2922 { 2923 2924 if (bootverbose) { 2925 pcicfgregs *cfg = &dinfo->cfg; 2926 2927 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2928 cfg->vendor, cfg->device, cfg->revid); 2929 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2930 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2931 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2932 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2933 cfg->mfdev); 2934 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2935 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2936 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2937 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2938 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2939 if (cfg->intpin > 0) 2940 printf("\tintpin=%c, irq=%d\n", 2941 cfg->intpin +'a' -1, cfg->intline); 2942 if (cfg->pp.pp_cap) { 2943 uint16_t status; 2944 2945 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2946 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2947 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2948 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2949 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2950 status & PCIM_PSTAT_DMASK); 2951 } 2952 if (cfg->msi.msi_location) { 2953 int ctrl; 2954 2955 ctrl = cfg->msi.msi_ctrl; 2956 printf("\tMSI supports %d message%s%s%s\n", 2957 cfg->msi.msi_msgnum, 2958 (cfg->msi.msi_msgnum == 1) ? "" : "s", 2959 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 2960 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 2961 } 2962 if (cfg->msix.msix_location) { 2963 printf("\tMSI-X supports %d message%s ", 2964 cfg->msix.msix_msgnum, 2965 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 2966 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 2967 printf("in map 0x%x\n", 2968 cfg->msix.msix_table_bar); 2969 else 2970 printf("in maps 0x%x and 0x%x\n", 2971 cfg->msix.msix_table_bar, 2972 cfg->msix.msix_pba_bar); 2973 } 2974 } 2975 } 2976 2977 static int 2978 pci_porten(device_t dev) 2979 { 2980 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 2981 } 2982 2983 static int 2984 pci_memen(device_t dev) 2985 { 2986 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 2987 } 2988 2989 void 2990 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 2991 int *bar64) 2992 { 2993 struct pci_devinfo *dinfo; 2994 pci_addr_t map, testval; 2995 int ln2range; 2996 uint16_t cmd; 2997 2998 /* 2999 * The device ROM BAR is special. It is always a 32-bit 3000 * memory BAR. Bit 0 is special and should not be set when 3001 * sizing the BAR. 3002 */ 3003 dinfo = device_get_ivars(dev); 3004 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3005 map = pci_read_config(dev, reg, 4); 3006 pci_write_config(dev, reg, 0xfffffffe, 4); 3007 testval = pci_read_config(dev, reg, 4); 3008 pci_write_config(dev, reg, map, 4); 3009 *mapp = map; 3010 *testvalp = testval; 3011 if (bar64 != NULL) 3012 *bar64 = 0; 3013 return; 3014 } 3015 3016 map = pci_read_config(dev, reg, 4); 3017 ln2range = pci_maprange(map); 3018 if (ln2range == 64) 3019 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3020 3021 /* 3022 * Disable decoding via the command register before 3023 * determining the BAR's length since we will be placing it in 3024 * a weird state. 3025 */ 3026 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3027 pci_write_config(dev, PCIR_COMMAND, 3028 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3029 3030 /* 3031 * Determine the BAR's length by writing all 1's. The bottom 3032 * log_2(size) bits of the BAR will stick as 0 when we read 3033 * the value back. 3034 * 3035 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3036 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3037 * and combines the result into a 64-bit value." (section 6.2.5.1) 3038 * 3039 * Writes to both registers must be performed before attempting to 3040 * read back the size value. 3041 */ 3042 testval = 0; 3043 pci_write_config(dev, reg, 0xffffffff, 4); 3044 if (ln2range == 64) { 3045 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3046 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3047 } 3048 testval |= pci_read_config(dev, reg, 4); 3049 3050 /* 3051 * Restore the original value of the BAR. We may have reprogrammed 3052 * the BAR of the low-level console device and when booting verbose, 3053 * we need the console device addressable. 3054 */ 3055 pci_write_config(dev, reg, map, 4); 3056 if (ln2range == 64) 3057 pci_write_config(dev, reg + 4, map >> 32, 4); 3058 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3059 3060 *mapp = map; 3061 *testvalp = testval; 3062 if (bar64 != NULL) 3063 *bar64 = (ln2range == 64); 3064 } 3065 3066 static void 3067 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3068 { 3069 struct pci_devinfo *dinfo; 3070 int ln2range; 3071 3072 /* The device ROM BAR is always a 32-bit memory BAR. */ 3073 dinfo = device_get_ivars(dev); 3074 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3075 ln2range = 32; 3076 else 3077 ln2range = pci_maprange(pm->pm_value); 3078 pci_write_config(dev, pm->pm_reg, base, 4); 3079 if (ln2range == 64) 3080 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3081 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3082 if (ln2range == 64) 3083 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3084 pm->pm_reg + 4, 4) << 32; 3085 } 3086 3087 struct pci_map * 3088 pci_find_bar(device_t dev, int reg) 3089 { 3090 struct pci_devinfo *dinfo; 3091 struct pci_map *pm; 3092 3093 dinfo = device_get_ivars(dev); 3094 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3095 if (pm->pm_reg == reg) 3096 return (pm); 3097 } 3098 return (NULL); 3099 } 3100 3101 int 3102 pci_bar_enabled(device_t dev, struct pci_map *pm) 3103 { 3104 struct pci_devinfo *dinfo; 3105 uint16_t cmd; 3106 3107 dinfo = device_get_ivars(dev); 3108 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3109 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3110 return (0); 3111 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3112 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3113 return ((cmd & PCIM_CMD_MEMEN) != 0); 3114 else 3115 return ((cmd & PCIM_CMD_PORTEN) != 0); 3116 } 3117 3118 struct pci_map * 3119 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3120 { 3121 struct pci_devinfo *dinfo; 3122 struct pci_map *pm, *prev; 3123 3124 dinfo = device_get_ivars(dev); 3125 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3126 pm->pm_reg = reg; 3127 pm->pm_value = value; 3128 pm->pm_size = size; 3129 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3130 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3131 reg)); 3132 if (STAILQ_NEXT(prev, pm_link) == NULL || 3133 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3134 break; 3135 } 3136 if (prev != NULL) 3137 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3138 else 3139 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3140 return (pm); 3141 } 3142 3143 static void 3144 pci_restore_bars(device_t dev) 3145 { 3146 struct pci_devinfo *dinfo; 3147 struct pci_map *pm; 3148 int ln2range; 3149 3150 dinfo = device_get_ivars(dev); 3151 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3152 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3153 ln2range = 32; 3154 else 3155 ln2range = pci_maprange(pm->pm_value); 3156 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3157 if (ln2range == 64) 3158 pci_write_config(dev, pm->pm_reg + 4, 3159 pm->pm_value >> 32, 4); 3160 } 3161 } 3162 3163 /* 3164 * Add a resource based on a pci map register. Return 1 if the map 3165 * register is a 32bit map register or 2 if it is a 64bit register. 3166 */ 3167 static int 3168 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3169 int force, int prefetch) 3170 { 3171 struct pci_map *pm; 3172 pci_addr_t base, map, testval; 3173 pci_addr_t start, end, count; 3174 int barlen, basezero, flags, maprange, mapsize, type; 3175 uint16_t cmd; 3176 struct resource *res; 3177 3178 /* 3179 * The BAR may already exist if the device is a CardBus card 3180 * whose CIS is stored in this BAR. 3181 */ 3182 pm = pci_find_bar(dev, reg); 3183 if (pm != NULL) { 3184 maprange = pci_maprange(pm->pm_value); 3185 barlen = maprange == 64 ? 2 : 1; 3186 return (barlen); 3187 } 3188 3189 pci_read_bar(dev, reg, &map, &testval, NULL); 3190 if (PCI_BAR_MEM(map)) { 3191 type = SYS_RES_MEMORY; 3192 if (map & PCIM_BAR_MEM_PREFETCH) 3193 prefetch = 1; 3194 } else 3195 type = SYS_RES_IOPORT; 3196 mapsize = pci_mapsize(testval); 3197 base = pci_mapbase(map); 3198 #ifdef __PCI_BAR_ZERO_VALID 3199 basezero = 0; 3200 #else 3201 basezero = base == 0; 3202 #endif 3203 maprange = pci_maprange(map); 3204 barlen = maprange == 64 ? 2 : 1; 3205 3206 /* 3207 * For I/O registers, if bottom bit is set, and the next bit up 3208 * isn't clear, we know we have a BAR that doesn't conform to the 3209 * spec, so ignore it. Also, sanity check the size of the data 3210 * areas to the type of memory involved. Memory must be at least 3211 * 16 bytes in size, while I/O ranges must be at least 4. 3212 */ 3213 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3214 return (barlen); 3215 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3216 (type == SYS_RES_IOPORT && mapsize < 2)) 3217 return (barlen); 3218 3219 /* Save a record of this BAR. */ 3220 pm = pci_add_bar(dev, reg, map, mapsize); 3221 if (bootverbose) { 3222 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3223 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3224 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3225 printf(", port disabled\n"); 3226 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3227 printf(", memory disabled\n"); 3228 else 3229 printf(", enabled\n"); 3230 } 3231 3232 /* 3233 * If base is 0, then we have problems if this architecture does 3234 * not allow that. It is best to ignore such entries for the 3235 * moment. These will be allocated later if the driver specifically 3236 * requests them. However, some removable buses look better when 3237 * all resources are allocated, so allow '0' to be overriden. 3238 * 3239 * Similarly treat maps whose values is the same as the test value 3240 * read back. These maps have had all f's written to them by the 3241 * BIOS in an attempt to disable the resources. 3242 */ 3243 if (!force && (basezero || map == testval)) 3244 return (barlen); 3245 if ((u_long)base != base) { 3246 device_printf(bus, 3247 "pci%d:%d:%d:%d bar %#x too many address bits", 3248 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3249 pci_get_function(dev), reg); 3250 return (barlen); 3251 } 3252 3253 /* 3254 * This code theoretically does the right thing, but has 3255 * undesirable side effects in some cases where peripherals 3256 * respond oddly to having these bits enabled. Let the user 3257 * be able to turn them off (since pci_enable_io_modes is 1 by 3258 * default). 3259 */ 3260 if (pci_enable_io_modes) { 3261 /* Turn on resources that have been left off by a lazy BIOS */ 3262 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3263 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3264 cmd |= PCIM_CMD_PORTEN; 3265 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3266 } 3267 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3268 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3269 cmd |= PCIM_CMD_MEMEN; 3270 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3271 } 3272 } else { 3273 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3274 return (barlen); 3275 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3276 return (barlen); 3277 } 3278 3279 count = (pci_addr_t)1 << mapsize; 3280 flags = RF_ALIGNMENT_LOG2(mapsize); 3281 if (prefetch) 3282 flags |= RF_PREFETCHABLE; 3283 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3284 start = 0; /* Let the parent decide. */ 3285 end = ~0; 3286 } else { 3287 start = base; 3288 end = base + count - 1; 3289 } 3290 resource_list_add(rl, type, reg, start, end, count); 3291 3292 /* 3293 * Try to allocate the resource for this BAR from our parent 3294 * so that this resource range is already reserved. The 3295 * driver for this device will later inherit this resource in 3296 * pci_alloc_resource(). 3297 */ 3298 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3299 flags); 3300 if ((pci_do_realloc_bars 3301 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3302 && res == NULL && (start != 0 || end != ~0)) { 3303 /* 3304 * If the allocation fails, try to allocate a resource for 3305 * this BAR using any available range. The firmware felt 3306 * it was important enough to assign a resource, so don't 3307 * disable decoding if we can help it. 3308 */ 3309 resource_list_delete(rl, type, reg); 3310 resource_list_add(rl, type, reg, 0, ~0, count); 3311 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3312 count, flags); 3313 } 3314 if (res == NULL) { 3315 /* 3316 * If the allocation fails, delete the resource list entry 3317 * and disable decoding for this device. 3318 * 3319 * If the driver requests this resource in the future, 3320 * pci_reserve_map() will try to allocate a fresh 3321 * resource range. 3322 */ 3323 resource_list_delete(rl, type, reg); 3324 pci_disable_io(dev, type); 3325 if (bootverbose) 3326 device_printf(bus, 3327 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3328 pci_get_domain(dev), pci_get_bus(dev), 3329 pci_get_slot(dev), pci_get_function(dev), reg); 3330 } else { 3331 start = rman_get_start(res); 3332 pci_write_bar(dev, pm, start); 3333 } 3334 return (barlen); 3335 } 3336 3337 /* 3338 * For ATA devices we need to decide early what addressing mode to use. 3339 * Legacy demands that the primary and secondary ATA ports sits on the 3340 * same addresses that old ISA hardware did. This dictates that we use 3341 * those addresses and ignore the BAR's if we cannot set PCI native 3342 * addressing mode. 3343 */ 3344 static void 3345 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3346 uint32_t prefetchmask) 3347 { 3348 int rid, type, progif; 3349 #if 0 3350 /* if this device supports PCI native addressing use it */ 3351 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3352 if ((progif & 0x8a) == 0x8a) { 3353 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3354 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3355 printf("Trying ATA native PCI addressing mode\n"); 3356 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3357 } 3358 } 3359 #endif 3360 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3361 type = SYS_RES_IOPORT; 3362 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3363 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3364 prefetchmask & (1 << 0)); 3365 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3366 prefetchmask & (1 << 1)); 3367 } else { 3368 rid = PCIR_BAR(0); 3369 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3370 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3371 0x1f7, 8, 0); 3372 rid = PCIR_BAR(1); 3373 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3374 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3375 0x3f6, 1, 0); 3376 } 3377 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3378 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3379 prefetchmask & (1 << 2)); 3380 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3381 prefetchmask & (1 << 3)); 3382 } else { 3383 rid = PCIR_BAR(2); 3384 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3385 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3386 0x177, 8, 0); 3387 rid = PCIR_BAR(3); 3388 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3389 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3390 0x376, 1, 0); 3391 } 3392 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3393 prefetchmask & (1 << 4)); 3394 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3395 prefetchmask & (1 << 5)); 3396 } 3397 3398 static void 3399 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3400 { 3401 struct pci_devinfo *dinfo = device_get_ivars(dev); 3402 pcicfgregs *cfg = &dinfo->cfg; 3403 char tunable_name[64]; 3404 int irq; 3405 3406 /* Has to have an intpin to have an interrupt. */ 3407 if (cfg->intpin == 0) 3408 return; 3409 3410 /* Let the user override the IRQ with a tunable. */ 3411 irq = PCI_INVALID_IRQ; 3412 snprintf(tunable_name, sizeof(tunable_name), 3413 "hw.pci%d.%d.%d.INT%c.irq", 3414 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3415 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3416 irq = PCI_INVALID_IRQ; 3417 3418 /* 3419 * If we didn't get an IRQ via the tunable, then we either use the 3420 * IRQ value in the intline register or we ask the bus to route an 3421 * interrupt for us. If force_route is true, then we only use the 3422 * value in the intline register if the bus was unable to assign an 3423 * IRQ. 3424 */ 3425 if (!PCI_INTERRUPT_VALID(irq)) { 3426 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3427 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3428 if (!PCI_INTERRUPT_VALID(irq)) 3429 irq = cfg->intline; 3430 } 3431 3432 /* If after all that we don't have an IRQ, just bail. */ 3433 if (!PCI_INTERRUPT_VALID(irq)) 3434 return; 3435 3436 /* Update the config register if it changed. */ 3437 if (irq != cfg->intline) { 3438 cfg->intline = irq; 3439 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3440 } 3441 3442 /* Add this IRQ as rid 0 interrupt resource. */ 3443 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3444 } 3445 3446 /* Perform early OHCI takeover from SMM. */ 3447 static void 3448 ohci_early_takeover(device_t self) 3449 { 3450 struct resource *res; 3451 uint32_t ctl; 3452 int rid; 3453 int i; 3454 3455 rid = PCIR_BAR(0); 3456 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3457 if (res == NULL) 3458 return; 3459 3460 ctl = bus_read_4(res, OHCI_CONTROL); 3461 if (ctl & OHCI_IR) { 3462 if (bootverbose) 3463 printf("ohci early: " 3464 "SMM active, request owner change\n"); 3465 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3466 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3467 DELAY(1000); 3468 ctl = bus_read_4(res, OHCI_CONTROL); 3469 } 3470 if (ctl & OHCI_IR) { 3471 if (bootverbose) 3472 printf("ohci early: " 3473 "SMM does not respond, resetting\n"); 3474 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3475 } 3476 /* Disable interrupts */ 3477 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3478 } 3479 3480 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3481 } 3482 3483 /* Perform early UHCI takeover from SMM. */ 3484 static void 3485 uhci_early_takeover(device_t self) 3486 { 3487 struct resource *res; 3488 int rid; 3489 3490 /* 3491 * Set the PIRQD enable bit and switch off all the others. We don't 3492 * want legacy support to interfere with us XXX Does this also mean 3493 * that the BIOS won't touch the keyboard anymore if it is connected 3494 * to the ports of the root hub? 3495 */ 3496 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3497 3498 /* Disable interrupts */ 3499 rid = PCI_UHCI_BASE_REG; 3500 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3501 if (res != NULL) { 3502 bus_write_2(res, UHCI_INTR, 0); 3503 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3504 } 3505 } 3506 3507 /* Perform early EHCI takeover from SMM. */ 3508 static void 3509 ehci_early_takeover(device_t self) 3510 { 3511 struct resource *res; 3512 uint32_t cparams; 3513 uint32_t eec; 3514 uint8_t eecp; 3515 uint8_t bios_sem; 3516 uint8_t offs; 3517 int rid; 3518 int i; 3519 3520 rid = PCIR_BAR(0); 3521 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3522 if (res == NULL) 3523 return; 3524 3525 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3526 3527 /* Synchronise with the BIOS if it owns the controller. */ 3528 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3529 eecp = EHCI_EECP_NEXT(eec)) { 3530 eec = pci_read_config(self, eecp, 4); 3531 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3532 continue; 3533 } 3534 bios_sem = pci_read_config(self, eecp + 3535 EHCI_LEGSUP_BIOS_SEM, 1); 3536 if (bios_sem == 0) { 3537 continue; 3538 } 3539 if (bootverbose) 3540 printf("ehci early: " 3541 "SMM active, request owner change\n"); 3542 3543 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3544 3545 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3546 DELAY(1000); 3547 bios_sem = pci_read_config(self, eecp + 3548 EHCI_LEGSUP_BIOS_SEM, 1); 3549 } 3550 3551 if (bios_sem != 0) { 3552 if (bootverbose) 3553 printf("ehci early: " 3554 "SMM does not respond\n"); 3555 } 3556 /* Disable interrupts */ 3557 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3558 bus_write_4(res, offs + EHCI_USBINTR, 0); 3559 } 3560 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3561 } 3562 3563 /* Perform early XHCI takeover from SMM. */ 3564 static void 3565 xhci_early_takeover(device_t self) 3566 { 3567 struct resource *res; 3568 uint32_t cparams; 3569 uint32_t eec; 3570 uint8_t eecp; 3571 uint8_t bios_sem; 3572 uint8_t offs; 3573 int rid; 3574 int i; 3575 3576 rid = PCIR_BAR(0); 3577 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3578 if (res == NULL) 3579 return; 3580 3581 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3582 3583 eec = -1; 3584 3585 /* Synchronise with the BIOS if it owns the controller. */ 3586 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3587 eecp += XHCI_XECP_NEXT(eec) << 2) { 3588 eec = bus_read_4(res, eecp); 3589 3590 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3591 continue; 3592 3593 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3594 if (bios_sem == 0) 3595 continue; 3596 3597 if (bootverbose) 3598 printf("xhci early: " 3599 "SMM active, request owner change\n"); 3600 3601 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3602 3603 /* wait a maximum of 5 second */ 3604 3605 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3606 DELAY(1000); 3607 bios_sem = bus_read_1(res, eecp + 3608 XHCI_XECP_BIOS_SEM); 3609 } 3610 3611 if (bios_sem != 0) { 3612 if (bootverbose) 3613 printf("xhci early: " 3614 "SMM does not respond\n"); 3615 } 3616 3617 /* Disable interrupts */ 3618 offs = bus_read_1(res, XHCI_CAPLENGTH); 3619 bus_write_4(res, offs + XHCI_USBCMD, 0); 3620 bus_read_4(res, offs + XHCI_USBSTS); 3621 } 3622 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3623 } 3624 3625 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3626 static void 3627 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3628 struct resource_list *rl) 3629 { 3630 struct resource *res; 3631 char *cp; 3632 rman_res_t start, end, count; 3633 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3634 3635 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3636 case PCIM_HDRTYPE_BRIDGE: 3637 sec_reg = PCIR_SECBUS_1; 3638 sub_reg = PCIR_SUBBUS_1; 3639 break; 3640 case PCIM_HDRTYPE_CARDBUS: 3641 sec_reg = PCIR_SECBUS_2; 3642 sub_reg = PCIR_SUBBUS_2; 3643 break; 3644 default: 3645 return; 3646 } 3647 3648 /* 3649 * If the existing bus range is valid, attempt to reserve it 3650 * from our parent. If this fails for any reason, clear the 3651 * secbus and subbus registers. 3652 * 3653 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3654 * This would at least preserve the existing sec_bus if it is 3655 * valid. 3656 */ 3657 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3658 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3659 3660 /* Quirk handling. */ 3661 switch (pci_get_devid(dev)) { 3662 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3663 sup_bus = pci_read_config(dev, 0x41, 1); 3664 if (sup_bus != 0xff) { 3665 sec_bus = sup_bus + 1; 3666 sub_bus = sup_bus + 1; 3667 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3668 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3669 } 3670 break; 3671 3672 case 0x00dd10de: 3673 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3674 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3675 break; 3676 if (strncmp(cp, "Compal", 6) != 0) { 3677 freeenv(cp); 3678 break; 3679 } 3680 freeenv(cp); 3681 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3682 break; 3683 if (strncmp(cp, "08A0", 4) != 0) { 3684 freeenv(cp); 3685 break; 3686 } 3687 freeenv(cp); 3688 if (sub_bus < 0xa) { 3689 sub_bus = 0xa; 3690 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3691 } 3692 break; 3693 } 3694 3695 if (bootverbose) 3696 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3697 if (sec_bus > 0 && sub_bus >= sec_bus) { 3698 start = sec_bus; 3699 end = sub_bus; 3700 count = end - start + 1; 3701 3702 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3703 3704 /* 3705 * If requested, clear secondary bus registers in 3706 * bridge devices to force a complete renumbering 3707 * rather than reserving the existing range. However, 3708 * preserve the existing size. 3709 */ 3710 if (pci_clear_buses) 3711 goto clear; 3712 3713 rid = 0; 3714 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3715 start, end, count, 0); 3716 if (res != NULL) 3717 return; 3718 3719 if (bootverbose) 3720 device_printf(bus, 3721 "pci%d:%d:%d:%d secbus failed to allocate\n", 3722 pci_get_domain(dev), pci_get_bus(dev), 3723 pci_get_slot(dev), pci_get_function(dev)); 3724 } 3725 3726 clear: 3727 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3728 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3729 } 3730 3731 static struct resource * 3732 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3733 rman_res_t end, rman_res_t count, u_int flags) 3734 { 3735 struct pci_devinfo *dinfo; 3736 pcicfgregs *cfg; 3737 struct resource_list *rl; 3738 struct resource *res; 3739 int sec_reg, sub_reg; 3740 3741 dinfo = device_get_ivars(child); 3742 cfg = &dinfo->cfg; 3743 rl = &dinfo->resources; 3744 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3745 case PCIM_HDRTYPE_BRIDGE: 3746 sec_reg = PCIR_SECBUS_1; 3747 sub_reg = PCIR_SUBBUS_1; 3748 break; 3749 case PCIM_HDRTYPE_CARDBUS: 3750 sec_reg = PCIR_SECBUS_2; 3751 sub_reg = PCIR_SUBBUS_2; 3752 break; 3753 default: 3754 return (NULL); 3755 } 3756 3757 if (*rid != 0) 3758 return (NULL); 3759 3760 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3761 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3762 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3763 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3764 start, end, count, flags & ~RF_ACTIVE); 3765 if (res == NULL) { 3766 resource_list_delete(rl, PCI_RES_BUS, *rid); 3767 device_printf(child, "allocating %ju bus%s failed\n", 3768 count, count == 1 ? "" : "es"); 3769 return (NULL); 3770 } 3771 if (bootverbose) 3772 device_printf(child, 3773 "Lazy allocation of %ju bus%s at %ju\n", count, 3774 count == 1 ? "" : "es", rman_get_start(res)); 3775 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3776 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3777 } 3778 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3779 end, count, flags)); 3780 } 3781 #endif 3782 3783 static int 3784 pci_ea_bei_to_rid(device_t dev, int bei) 3785 { 3786 #ifdef PCI_IOV 3787 struct pci_devinfo *dinfo; 3788 int iov_pos; 3789 struct pcicfg_iov *iov; 3790 3791 dinfo = device_get_ivars(dev); 3792 iov = dinfo->cfg.iov; 3793 if (iov != NULL) 3794 iov_pos = iov->iov_pos; 3795 else 3796 iov_pos = 0; 3797 #endif 3798 3799 /* Check if matches BAR */ 3800 if ((bei >= PCIM_EA_BEI_BAR_0) && 3801 (bei <= PCIM_EA_BEI_BAR_5)) 3802 return (PCIR_BAR(bei)); 3803 3804 /* Check ROM */ 3805 if (bei == PCIM_EA_BEI_ROM) 3806 return (PCIR_BIOS); 3807 3808 #ifdef PCI_IOV 3809 /* Check if matches VF_BAR */ 3810 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3811 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3812 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3813 iov_pos); 3814 #endif 3815 3816 return (-1); 3817 } 3818 3819 int 3820 pci_ea_is_enabled(device_t dev, int rid) 3821 { 3822 struct pci_ea_entry *ea; 3823 struct pci_devinfo *dinfo; 3824 3825 dinfo = device_get_ivars(dev); 3826 3827 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3828 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3829 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3830 } 3831 3832 return (0); 3833 } 3834 3835 void 3836 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 3837 { 3838 struct pci_ea_entry *ea; 3839 struct pci_devinfo *dinfo; 3840 pci_addr_t start, end, count; 3841 struct resource_list *rl; 3842 int type, flags, rid; 3843 struct resource *res; 3844 uint32_t tmp; 3845 #ifdef PCI_IOV 3846 struct pcicfg_iov *iov; 3847 #endif 3848 3849 dinfo = device_get_ivars(dev); 3850 rl = &dinfo->resources; 3851 flags = 0; 3852 3853 #ifdef PCI_IOV 3854 iov = dinfo->cfg.iov; 3855 #endif 3856 3857 if (dinfo->cfg.ea.ea_location == 0) 3858 return; 3859 3860 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3861 3862 /* 3863 * TODO: Ignore EA-BAR if is not enabled. 3864 * Currently the EA implementation supports 3865 * only situation, where EA structure contains 3866 * predefined entries. In case they are not enabled 3867 * leave them unallocated and proceed with 3868 * a legacy-BAR mechanism. 3869 */ 3870 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 3871 continue; 3872 3873 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 3874 case PCIM_EA_P_MEM_PREFETCH: 3875 case PCIM_EA_P_VF_MEM_PREFETCH: 3876 flags = RF_PREFETCHABLE; 3877 /* FALLTHROUGH */ 3878 case PCIM_EA_P_VF_MEM: 3879 case PCIM_EA_P_MEM: 3880 type = SYS_RES_MEMORY; 3881 break; 3882 case PCIM_EA_P_IO: 3883 type = SYS_RES_IOPORT; 3884 break; 3885 default: 3886 continue; 3887 } 3888 3889 if (alloc_iov != 0) { 3890 #ifdef PCI_IOV 3891 /* Allocating IOV, confirm BEI matches */ 3892 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 3893 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 3894 continue; 3895 #else 3896 continue; 3897 #endif 3898 } else { 3899 /* Allocating BAR, confirm BEI matches */ 3900 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 3901 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 3902 (ea->eae_bei != PCIM_EA_BEI_ROM)) 3903 continue; 3904 } 3905 3906 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 3907 if (rid < 0) 3908 continue; 3909 3910 /* Skip resources already allocated by EA */ 3911 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 3912 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 3913 continue; 3914 3915 start = ea->eae_base; 3916 count = ea->eae_max_offset + 1; 3917 #ifdef PCI_IOV 3918 if (iov != NULL) 3919 count = count * iov->iov_num_vfs; 3920 #endif 3921 end = start + count - 1; 3922 if (count == 0) 3923 continue; 3924 3925 resource_list_add(rl, type, rid, start, end, count); 3926 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 3927 flags); 3928 if (res == NULL) { 3929 resource_list_delete(rl, type, rid); 3930 3931 /* 3932 * Failed to allocate using EA, disable entry. 3933 * Another attempt to allocation will be performed 3934 * further, but this time using legacy BAR registers 3935 */ 3936 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 3937 tmp &= ~PCIM_EA_ENABLE; 3938 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 3939 3940 /* 3941 * Disabling entry might fail in case it is hardwired. 3942 * Read flags again to match current status. 3943 */ 3944 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 3945 3946 continue; 3947 } 3948 3949 /* As per specification, fill BAR with zeros */ 3950 pci_write_config(dev, rid, 0, 4); 3951 } 3952 } 3953 3954 void 3955 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 3956 { 3957 struct pci_devinfo *dinfo; 3958 pcicfgregs *cfg; 3959 struct resource_list *rl; 3960 const struct pci_quirk *q; 3961 uint32_t devid; 3962 int i; 3963 3964 dinfo = device_get_ivars(dev); 3965 cfg = &dinfo->cfg; 3966 rl = &dinfo->resources; 3967 devid = (cfg->device << 16) | cfg->vendor; 3968 3969 /* Allocate resources using Enhanced Allocation */ 3970 pci_add_resources_ea(bus, dev, 0); 3971 3972 /* ATA devices needs special map treatment */ 3973 if ((pci_get_class(dev) == PCIC_STORAGE) && 3974 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 3975 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 3976 (!pci_read_config(dev, PCIR_BAR(0), 4) && 3977 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 3978 pci_ata_maps(bus, dev, rl, force, prefetchmask); 3979 else 3980 for (i = 0; i < cfg->nummaps;) { 3981 /* Skip resources already managed by EA */ 3982 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 3983 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 3984 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 3985 i++; 3986 continue; 3987 } 3988 3989 /* 3990 * Skip quirked resources. 3991 */ 3992 for (q = &pci_quirks[0]; q->devid != 0; q++) 3993 if (q->devid == devid && 3994 q->type == PCI_QUIRK_UNMAP_REG && 3995 q->arg1 == PCIR_BAR(i)) 3996 break; 3997 if (q->devid != 0) { 3998 i++; 3999 continue; 4000 } 4001 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4002 prefetchmask & (1 << i)); 4003 } 4004 4005 /* 4006 * Add additional, quirked resources. 4007 */ 4008 for (q = &pci_quirks[0]; q->devid != 0; q++) 4009 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4010 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4011 4012 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4013 #ifdef __PCI_REROUTE_INTERRUPT 4014 /* 4015 * Try to re-route interrupts. Sometimes the BIOS or 4016 * firmware may leave bogus values in these registers. 4017 * If the re-route fails, then just stick with what we 4018 * have. 4019 */ 4020 pci_assign_interrupt(bus, dev, 1); 4021 #else 4022 pci_assign_interrupt(bus, dev, 0); 4023 #endif 4024 } 4025 4026 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4027 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4028 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4029 xhci_early_takeover(dev); 4030 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4031 ehci_early_takeover(dev); 4032 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4033 ohci_early_takeover(dev); 4034 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4035 uhci_early_takeover(dev); 4036 } 4037 4038 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4039 /* 4040 * Reserve resources for secondary bus ranges behind bridge 4041 * devices. 4042 */ 4043 pci_reserve_secbus(bus, dev, cfg, rl); 4044 #endif 4045 } 4046 4047 static struct pci_devinfo * 4048 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4049 int slot, int func) 4050 { 4051 struct pci_devinfo *dinfo; 4052 4053 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4054 if (dinfo != NULL) 4055 pci_add_child(dev, dinfo); 4056 4057 return (dinfo); 4058 } 4059 4060 void 4061 pci_add_children(device_t dev, int domain, int busno) 4062 { 4063 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4064 device_t pcib = device_get_parent(dev); 4065 struct pci_devinfo *dinfo; 4066 int maxslots; 4067 int s, f, pcifunchigh; 4068 uint8_t hdrtype; 4069 int first_func; 4070 4071 /* 4072 * Try to detect a device at slot 0, function 0. If it exists, try to 4073 * enable ARI. We must enable ARI before detecting the rest of the 4074 * functions on this bus as ARI changes the set of slots and functions 4075 * that are legal on this bus. 4076 */ 4077 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4078 if (dinfo != NULL && pci_enable_ari) 4079 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4080 4081 /* 4082 * Start looking for new devices on slot 0 at function 1 because we 4083 * just identified the device at slot 0, function 0. 4084 */ 4085 first_func = 1; 4086 4087 maxslots = PCIB_MAXSLOTS(pcib); 4088 for (s = 0; s <= maxslots; s++, first_func = 0) { 4089 pcifunchigh = 0; 4090 f = 0; 4091 DELAY(1); 4092 hdrtype = REG(PCIR_HDRTYPE, 1); 4093 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4094 continue; 4095 if (hdrtype & PCIM_MFDEV) 4096 pcifunchigh = PCIB_MAXFUNCS(pcib); 4097 for (f = first_func; f <= pcifunchigh; f++) 4098 pci_identify_function(pcib, dev, domain, busno, s, f); 4099 } 4100 #undef REG 4101 } 4102 4103 int 4104 pci_rescan_method(device_t dev) 4105 { 4106 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4107 device_t pcib = device_get_parent(dev); 4108 device_t child, *devlist, *unchanged; 4109 int devcount, error, i, j, maxslots, oldcount; 4110 int busno, domain, s, f, pcifunchigh; 4111 uint8_t hdrtype; 4112 4113 /* No need to check for ARI on a rescan. */ 4114 error = device_get_children(dev, &devlist, &devcount); 4115 if (error) 4116 return (error); 4117 if (devcount != 0) { 4118 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4119 M_NOWAIT | M_ZERO); 4120 if (unchanged == NULL) { 4121 free(devlist, M_TEMP); 4122 return (ENOMEM); 4123 } 4124 } else 4125 unchanged = NULL; 4126 4127 domain = pcib_get_domain(dev); 4128 busno = pcib_get_bus(dev); 4129 maxslots = PCIB_MAXSLOTS(pcib); 4130 for (s = 0; s <= maxslots; s++) { 4131 /* If function 0 is not present, skip to the next slot. */ 4132 f = 0; 4133 if (REG(PCIR_VENDOR, 2) == 0xffff) 4134 continue; 4135 pcifunchigh = 0; 4136 hdrtype = REG(PCIR_HDRTYPE, 1); 4137 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4138 continue; 4139 if (hdrtype & PCIM_MFDEV) 4140 pcifunchigh = PCIB_MAXFUNCS(pcib); 4141 for (f = 0; f <= pcifunchigh; f++) { 4142 if (REG(PCIR_VENDOR, 2) == 0xffff) 4143 continue; 4144 4145 /* 4146 * Found a valid function. Check if a 4147 * device_t for this device already exists. 4148 */ 4149 for (i = 0; i < devcount; i++) { 4150 child = devlist[i]; 4151 if (child == NULL) 4152 continue; 4153 if (pci_get_slot(child) == s && 4154 pci_get_function(child) == f) { 4155 unchanged[i] = child; 4156 goto next_func; 4157 } 4158 } 4159 4160 pci_identify_function(pcib, dev, domain, busno, s, f); 4161 next_func:; 4162 } 4163 } 4164 4165 /* Remove devices that are no longer present. */ 4166 for (i = 0; i < devcount; i++) { 4167 if (unchanged[i] != NULL) 4168 continue; 4169 device_delete_child(dev, devlist[i]); 4170 } 4171 4172 free(devlist, M_TEMP); 4173 oldcount = devcount; 4174 4175 /* Try to attach the devices just added. */ 4176 error = device_get_children(dev, &devlist, &devcount); 4177 if (error) { 4178 free(unchanged, M_TEMP); 4179 return (error); 4180 } 4181 4182 for (i = 0; i < devcount; i++) { 4183 for (j = 0; j < oldcount; j++) { 4184 if (devlist[i] == unchanged[j]) 4185 goto next_device; 4186 } 4187 4188 device_probe_and_attach(devlist[i]); 4189 next_device:; 4190 } 4191 4192 free(unchanged, M_TEMP); 4193 free(devlist, M_TEMP); 4194 return (0); 4195 #undef REG 4196 } 4197 4198 #ifdef PCI_IOV 4199 device_t 4200 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4201 uint16_t did) 4202 { 4203 struct pci_devinfo *vf_dinfo; 4204 device_t pcib; 4205 int busno, slot, func; 4206 4207 pcib = device_get_parent(bus); 4208 4209 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4210 4211 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4212 slot, func, vid, did); 4213 4214 vf_dinfo->cfg.flags |= PCICFG_VF; 4215 pci_add_child(bus, vf_dinfo); 4216 4217 return (vf_dinfo->cfg.dev); 4218 } 4219 4220 device_t 4221 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4222 uint16_t vid, uint16_t did) 4223 { 4224 4225 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4226 } 4227 #endif 4228 4229 static void 4230 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4231 { 4232 int aer; 4233 uint32_t r; 4234 uint16_t r2; 4235 4236 if (dinfo->cfg.pcie.pcie_location != 0 && 4237 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4238 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4239 PCIER_ROOT_CTL, 2); 4240 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4241 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4242 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4243 PCIER_ROOT_CTL, r2, 2); 4244 } 4245 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4246 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4247 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4248 if (r != 0 && bootverbose) { 4249 pci_printf(&dinfo->cfg, 4250 "clearing AER UC 0x%08x -> 0x%08x\n", 4251 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4252 4)); 4253 } 4254 4255 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4256 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4257 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4258 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4259 PCIM_AER_UC_POISONED_TLP | 4260 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4261 PCIM_AER_UC_COMPLETION_TIMEOUT | 4262 PCIM_AER_UC_COMPLETER_ABORT | 4263 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4264 PCIM_AER_UC_RECEIVER_OVERFLOW | 4265 PCIM_AER_UC_MALFORMED_TLP | 4266 PCIM_AER_UC_ECRC_ERROR | 4267 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4268 PCIM_AER_UC_ACS_VIOLATION | 4269 PCIM_AER_UC_INTERNAL_ERROR | 4270 PCIM_AER_UC_MC_BLOCKED_TLP | 4271 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4272 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4273 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4274 4275 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4276 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4277 if (r != 0 && bootverbose) { 4278 pci_printf(&dinfo->cfg, 4279 "clearing AER COR 0x%08x -> 0x%08x\n", 4280 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4281 4)); 4282 } 4283 4284 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4285 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4286 PCIM_AER_COR_BAD_TLP | 4287 PCIM_AER_COR_BAD_DLLP | 4288 PCIM_AER_COR_REPLAY_ROLLOVER | 4289 PCIM_AER_COR_REPLAY_TIMEOUT | 4290 PCIM_AER_COR_ADVISORY_NF_ERROR | 4291 PCIM_AER_COR_INTERNAL_ERROR | 4292 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4293 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4294 4295 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4296 PCIER_DEVICE_CTL, 2); 4297 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4298 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4299 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4300 PCIER_DEVICE_CTL, r, 2); 4301 } 4302 } 4303 4304 void 4305 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4306 { 4307 device_t dev; 4308 4309 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1); 4310 device_set_ivars(dev, dinfo); 4311 resource_list_init(&dinfo->resources); 4312 pci_cfg_save(dev, dinfo, 0); 4313 pci_cfg_restore(dev, dinfo); 4314 pci_print_verbose(dinfo); 4315 pci_add_resources(bus, dev, 0, 0); 4316 pci_child_added(dinfo->cfg.dev); 4317 4318 if (pci_clear_aer_on_attach) 4319 pci_add_child_clear_aer(dev, dinfo); 4320 4321 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4322 } 4323 4324 void 4325 pci_child_added_method(device_t dev, device_t child) 4326 { 4327 4328 } 4329 4330 static int 4331 pci_probe(device_t dev) 4332 { 4333 4334 device_set_desc(dev, "PCI bus"); 4335 4336 /* Allow other subclasses to override this driver. */ 4337 return (BUS_PROBE_GENERIC); 4338 } 4339 4340 int 4341 pci_attach_common(device_t dev) 4342 { 4343 struct pci_softc *sc; 4344 int busno, domain; 4345 #ifdef PCI_RES_BUS 4346 int rid; 4347 #endif 4348 4349 sc = device_get_softc(dev); 4350 domain = pcib_get_domain(dev); 4351 busno = pcib_get_bus(dev); 4352 #ifdef PCI_RES_BUS 4353 rid = 0; 4354 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4355 1, 0); 4356 if (sc->sc_bus == NULL) { 4357 device_printf(dev, "failed to allocate bus number\n"); 4358 return (ENXIO); 4359 } 4360 #endif 4361 if (bootverbose) 4362 device_printf(dev, "domain=%d, physical bus=%d\n", 4363 domain, busno); 4364 sc->sc_dma_tag = bus_get_dma_tag(dev); 4365 return (0); 4366 } 4367 4368 int 4369 pci_attach(device_t dev) 4370 { 4371 int busno, domain, error; 4372 4373 error = pci_attach_common(dev); 4374 if (error) 4375 return (error); 4376 4377 /* 4378 * Since there can be multiple independently numbered PCI 4379 * buses on systems with multiple PCI domains, we can't use 4380 * the unit number to decide which bus we are probing. We ask 4381 * the parent pcib what our domain and bus numbers are. 4382 */ 4383 domain = pcib_get_domain(dev); 4384 busno = pcib_get_bus(dev); 4385 pci_add_children(dev, domain, busno); 4386 return (bus_generic_attach(dev)); 4387 } 4388 4389 int 4390 pci_detach(device_t dev) 4391 { 4392 #ifdef PCI_RES_BUS 4393 struct pci_softc *sc; 4394 #endif 4395 int error; 4396 4397 error = bus_generic_detach(dev); 4398 if (error) 4399 return (error); 4400 #ifdef PCI_RES_BUS 4401 sc = device_get_softc(dev); 4402 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4403 if (error) 4404 return (error); 4405 #endif 4406 return (device_delete_children(dev)); 4407 } 4408 4409 static void 4410 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4411 { 4412 int line, unit; 4413 const char *at; 4414 char me1[24], me2[32]; 4415 uint8_t b, s, f; 4416 uint32_t d; 4417 4418 d = pci_get_domain(child); 4419 b = pci_get_bus(child); 4420 s = pci_get_slot(child); 4421 f = pci_get_function(child); 4422 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4423 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4424 line = 0; 4425 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4426 resource_string_value(name, unit, "at", &at); 4427 if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0) 4428 continue; /* No match, try next candidate */ 4429 *unitp = unit; 4430 return; 4431 } 4432 } 4433 4434 static void 4435 pci_set_power_child(device_t dev, device_t child, int state) 4436 { 4437 device_t pcib; 4438 int dstate; 4439 4440 /* 4441 * Set the device to the given state. If the firmware suggests 4442 * a different power state, use it instead. If power management 4443 * is not present, the firmware is responsible for managing 4444 * device power. Skip children who aren't attached since they 4445 * are handled separately. 4446 */ 4447 pcib = device_get_parent(dev); 4448 dstate = state; 4449 if (device_is_attached(child) && 4450 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4451 pci_set_powerstate(child, dstate); 4452 } 4453 4454 int 4455 pci_suspend_child(device_t dev, device_t child) 4456 { 4457 struct pci_devinfo *dinfo; 4458 struct resource_list_entry *rle; 4459 int error; 4460 4461 dinfo = device_get_ivars(child); 4462 4463 /* 4464 * Save the PCI configuration space for the child and set the 4465 * device in the appropriate power state for this sleep state. 4466 */ 4467 pci_cfg_save(child, dinfo, 0); 4468 4469 /* Suspend devices before potentially powering them down. */ 4470 error = bus_generic_suspend_child(dev, child); 4471 4472 if (error) 4473 return (error); 4474 4475 if (pci_do_power_suspend) { 4476 /* 4477 * Make sure this device's interrupt handler is not invoked 4478 * in the case the device uses a shared interrupt that can 4479 * be raised by some other device. 4480 * This is applicable only to regular (legacy) PCI interrupts 4481 * as MSI/MSI-X interrupts are never shared. 4482 */ 4483 rle = resource_list_find(&dinfo->resources, 4484 SYS_RES_IRQ, 0); 4485 if (rle != NULL && rle->res != NULL) 4486 (void)bus_suspend_intr(child, rle->res); 4487 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4488 } 4489 4490 return (0); 4491 } 4492 4493 int 4494 pci_resume_child(device_t dev, device_t child) 4495 { 4496 struct pci_devinfo *dinfo; 4497 struct resource_list_entry *rle; 4498 4499 if (pci_do_power_resume) 4500 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4501 4502 dinfo = device_get_ivars(child); 4503 pci_cfg_restore(child, dinfo); 4504 if (!device_is_attached(child)) 4505 pci_cfg_save(child, dinfo, 1); 4506 4507 bus_generic_resume_child(dev, child); 4508 4509 /* 4510 * Allow interrupts only after fully resuming the driver and hardware. 4511 */ 4512 if (pci_do_power_suspend) { 4513 /* See pci_suspend_child for details. */ 4514 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4515 if (rle != NULL && rle->res != NULL) 4516 (void)bus_resume_intr(child, rle->res); 4517 } 4518 4519 return (0); 4520 } 4521 4522 int 4523 pci_resume(device_t dev) 4524 { 4525 device_t child, *devlist; 4526 int error, i, numdevs; 4527 4528 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4529 return (error); 4530 4531 /* 4532 * Resume critical devices first, then everything else later. 4533 */ 4534 for (i = 0; i < numdevs; i++) { 4535 child = devlist[i]; 4536 switch (pci_get_class(child)) { 4537 case PCIC_DISPLAY: 4538 case PCIC_MEMORY: 4539 case PCIC_BRIDGE: 4540 case PCIC_BASEPERIPH: 4541 BUS_RESUME_CHILD(dev, child); 4542 break; 4543 } 4544 } 4545 for (i = 0; i < numdevs; i++) { 4546 child = devlist[i]; 4547 switch (pci_get_class(child)) { 4548 case PCIC_DISPLAY: 4549 case PCIC_MEMORY: 4550 case PCIC_BRIDGE: 4551 case PCIC_BASEPERIPH: 4552 break; 4553 default: 4554 BUS_RESUME_CHILD(dev, child); 4555 } 4556 } 4557 free(devlist, M_TEMP); 4558 return (0); 4559 } 4560 4561 static void 4562 pci_load_vendor_data(void) 4563 { 4564 caddr_t data; 4565 void *ptr; 4566 size_t sz; 4567 4568 data = preload_search_by_type("pci_vendor_data"); 4569 if (data != NULL) { 4570 ptr = preload_fetch_addr(data); 4571 sz = preload_fetch_size(data); 4572 if (ptr != NULL && sz != 0) { 4573 pci_vendordata = ptr; 4574 pci_vendordata_size = sz; 4575 /* terminate the database */ 4576 pci_vendordata[pci_vendordata_size] = '\n'; 4577 } 4578 } 4579 } 4580 4581 void 4582 pci_driver_added(device_t dev, driver_t *driver) 4583 { 4584 int numdevs; 4585 device_t *devlist; 4586 device_t child; 4587 struct pci_devinfo *dinfo; 4588 int i; 4589 4590 if (bootverbose) 4591 device_printf(dev, "driver added\n"); 4592 DEVICE_IDENTIFY(driver, dev); 4593 if (device_get_children(dev, &devlist, &numdevs) != 0) 4594 return; 4595 for (i = 0; i < numdevs; i++) { 4596 child = devlist[i]; 4597 if (device_get_state(child) != DS_NOTPRESENT) 4598 continue; 4599 dinfo = device_get_ivars(child); 4600 pci_print_verbose(dinfo); 4601 if (bootverbose) 4602 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4603 pci_cfg_restore(child, dinfo); 4604 if (device_probe_and_attach(child) != 0) 4605 pci_child_detached(dev, child); 4606 } 4607 free(devlist, M_TEMP); 4608 } 4609 4610 int 4611 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4612 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4613 { 4614 struct pci_devinfo *dinfo; 4615 struct msix_table_entry *mte; 4616 struct msix_vector *mv; 4617 uint64_t addr; 4618 uint32_t data; 4619 void *cookie; 4620 int error, rid; 4621 4622 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4623 arg, &cookie); 4624 if (error) 4625 return (error); 4626 4627 /* If this is not a direct child, just bail out. */ 4628 if (device_get_parent(child) != dev) { 4629 *cookiep = cookie; 4630 return(0); 4631 } 4632 4633 rid = rman_get_rid(irq); 4634 if (rid == 0) { 4635 /* Make sure that INTx is enabled */ 4636 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4637 } else { 4638 /* 4639 * Check to see if the interrupt is MSI or MSI-X. 4640 * Ask our parent to map the MSI and give 4641 * us the address and data register values. 4642 * If we fail for some reason, teardown the 4643 * interrupt handler. 4644 */ 4645 dinfo = device_get_ivars(child); 4646 if (dinfo->cfg.msi.msi_alloc > 0) { 4647 if (dinfo->cfg.msi.msi_addr == 0) { 4648 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4649 ("MSI has handlers, but vectors not mapped")); 4650 error = PCIB_MAP_MSI(device_get_parent(dev), 4651 child, rman_get_start(irq), &addr, &data); 4652 if (error) 4653 goto bad; 4654 dinfo->cfg.msi.msi_addr = addr; 4655 dinfo->cfg.msi.msi_data = data; 4656 } 4657 if (dinfo->cfg.msi.msi_handlers == 0) 4658 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4659 dinfo->cfg.msi.msi_data); 4660 dinfo->cfg.msi.msi_handlers++; 4661 } else { 4662 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4663 ("No MSI or MSI-X interrupts allocated")); 4664 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4665 ("MSI-X index too high")); 4666 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4667 KASSERT(mte->mte_vector != 0, ("no message vector")); 4668 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4669 KASSERT(mv->mv_irq == rman_get_start(irq), 4670 ("IRQ mismatch")); 4671 if (mv->mv_address == 0) { 4672 KASSERT(mte->mte_handlers == 0, 4673 ("MSI-X table entry has handlers, but vector not mapped")); 4674 error = PCIB_MAP_MSI(device_get_parent(dev), 4675 child, rman_get_start(irq), &addr, &data); 4676 if (error) 4677 goto bad; 4678 mv->mv_address = addr; 4679 mv->mv_data = data; 4680 } 4681 4682 /* 4683 * The MSIX table entry must be made valid by 4684 * incrementing the mte_handlers before 4685 * calling pci_enable_msix() and 4686 * pci_resume_msix(). Else the MSIX rewrite 4687 * table quirk will not work as expected. 4688 */ 4689 mte->mte_handlers++; 4690 if (mte->mte_handlers == 1) { 4691 pci_enable_msix(child, rid - 1, mv->mv_address, 4692 mv->mv_data); 4693 pci_unmask_msix(child, rid - 1); 4694 } 4695 } 4696 4697 /* 4698 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4699 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4700 * in which case we "enable" INTx so MSI/MSI-X actually works. 4701 */ 4702 if (!pci_has_quirk(pci_get_devid(child), 4703 PCI_QUIRK_MSI_INTX_BUG)) 4704 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4705 else 4706 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4707 bad: 4708 if (error) { 4709 (void)bus_generic_teardown_intr(dev, child, irq, 4710 cookie); 4711 return (error); 4712 } 4713 } 4714 *cookiep = cookie; 4715 return (0); 4716 } 4717 4718 int 4719 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4720 void *cookie) 4721 { 4722 struct msix_table_entry *mte; 4723 struct resource_list_entry *rle; 4724 struct pci_devinfo *dinfo; 4725 int error, rid; 4726 4727 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4728 return (EINVAL); 4729 4730 /* If this isn't a direct child, just bail out */ 4731 if (device_get_parent(child) != dev) 4732 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4733 4734 rid = rman_get_rid(irq); 4735 if (rid == 0) { 4736 /* Mask INTx */ 4737 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4738 } else { 4739 /* 4740 * Check to see if the interrupt is MSI or MSI-X. If so, 4741 * decrement the appropriate handlers count and mask the 4742 * MSI-X message, or disable MSI messages if the count 4743 * drops to 0. 4744 */ 4745 dinfo = device_get_ivars(child); 4746 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4747 if (rle->res != irq) 4748 return (EINVAL); 4749 if (dinfo->cfg.msi.msi_alloc > 0) { 4750 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4751 ("MSI-X index too high")); 4752 if (dinfo->cfg.msi.msi_handlers == 0) 4753 return (EINVAL); 4754 dinfo->cfg.msi.msi_handlers--; 4755 if (dinfo->cfg.msi.msi_handlers == 0) 4756 pci_disable_msi(child); 4757 } else { 4758 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4759 ("No MSI or MSI-X interrupts allocated")); 4760 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4761 ("MSI-X index too high")); 4762 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4763 if (mte->mte_handlers == 0) 4764 return (EINVAL); 4765 mte->mte_handlers--; 4766 if (mte->mte_handlers == 0) 4767 pci_mask_msix(child, rid - 1); 4768 } 4769 } 4770 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4771 if (rid > 0) 4772 KASSERT(error == 0, 4773 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4774 return (error); 4775 } 4776 4777 int 4778 pci_print_child(device_t dev, device_t child) 4779 { 4780 struct pci_devinfo *dinfo; 4781 struct resource_list *rl; 4782 int retval = 0; 4783 4784 dinfo = device_get_ivars(child); 4785 rl = &dinfo->resources; 4786 4787 retval += bus_print_child_header(dev, child); 4788 4789 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4790 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4791 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4792 if (device_get_flags(dev)) 4793 retval += printf(" flags %#x", device_get_flags(dev)); 4794 4795 retval += printf(" at device %d.%d", pci_get_slot(child), 4796 pci_get_function(child)); 4797 4798 retval += bus_print_child_domain(dev, child); 4799 retval += bus_print_child_footer(dev, child); 4800 4801 return (retval); 4802 } 4803 4804 static const struct 4805 { 4806 int class; 4807 int subclass; 4808 int report; /* 0 = bootverbose, 1 = always */ 4809 const char *desc; 4810 } pci_nomatch_tab[] = { 4811 {PCIC_OLD, -1, 1, "old"}, 4812 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4813 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4814 {PCIC_STORAGE, -1, 1, "mass storage"}, 4815 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4816 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4817 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4818 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4819 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4820 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4821 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4822 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4823 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4824 {PCIC_NETWORK, -1, 1, "network"}, 4825 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4826 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4827 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4828 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4829 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4830 {PCIC_DISPLAY, -1, 1, "display"}, 4831 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4832 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4833 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4834 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4835 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4836 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4837 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4838 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4839 {PCIC_MEMORY, -1, 1, "memory"}, 4840 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4841 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4842 {PCIC_BRIDGE, -1, 1, "bridge"}, 4843 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4844 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4845 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4846 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4847 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4848 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4849 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4850 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4851 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4852 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4853 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4854 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4855 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4856 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4857 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4858 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4859 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4860 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4861 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4862 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4863 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4864 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4865 {PCIC_INPUTDEV, -1, 1, "input device"}, 4866 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4867 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4868 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4869 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4870 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4871 {PCIC_DOCKING, -1, 1, "docking station"}, 4872 {PCIC_PROCESSOR, -1, 1, "processor"}, 4873 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4874 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4875 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4876 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4877 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4878 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4879 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4880 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4881 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4882 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4883 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4884 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4885 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4886 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4887 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4888 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4889 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4890 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4891 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4892 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4893 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4894 {PCIC_DASP, -1, 0, "dasp"}, 4895 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4896 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 4897 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 4898 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 4899 {0, 0, 0, NULL} 4900 }; 4901 4902 void 4903 pci_probe_nomatch(device_t dev, device_t child) 4904 { 4905 int i, report; 4906 const char *cp, *scp; 4907 char *device; 4908 4909 /* 4910 * Look for a listing for this device in a loaded device database. 4911 */ 4912 report = 1; 4913 if ((device = pci_describe_device(child)) != NULL) { 4914 device_printf(dev, "<%s>", device); 4915 free(device, M_DEVBUF); 4916 } else { 4917 /* 4918 * Scan the class/subclass descriptions for a general 4919 * description. 4920 */ 4921 cp = "unknown"; 4922 scp = NULL; 4923 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 4924 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 4925 if (pci_nomatch_tab[i].subclass == -1) { 4926 cp = pci_nomatch_tab[i].desc; 4927 report = pci_nomatch_tab[i].report; 4928 } else if (pci_nomatch_tab[i].subclass == 4929 pci_get_subclass(child)) { 4930 scp = pci_nomatch_tab[i].desc; 4931 report = pci_nomatch_tab[i].report; 4932 } 4933 } 4934 } 4935 if (report || bootverbose) { 4936 device_printf(dev, "<%s%s%s>", 4937 cp ? cp : "", 4938 ((cp != NULL) && (scp != NULL)) ? ", " : "", 4939 scp ? scp : ""); 4940 } 4941 } 4942 if (report || bootverbose) { 4943 printf(" at device %d.%d (no driver attached)\n", 4944 pci_get_slot(child), pci_get_function(child)); 4945 } 4946 pci_cfg_save(child, device_get_ivars(child), 1); 4947 } 4948 4949 void 4950 pci_child_detached(device_t dev, device_t child) 4951 { 4952 struct pci_devinfo *dinfo; 4953 struct resource_list *rl; 4954 4955 dinfo = device_get_ivars(child); 4956 rl = &dinfo->resources; 4957 4958 /* 4959 * Have to deallocate IRQs before releasing any MSI messages and 4960 * have to release MSI messages before deallocating any memory 4961 * BARs. 4962 */ 4963 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 4964 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 4965 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 4966 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n"); 4967 (void)pci_release_msi(child); 4968 } 4969 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 4970 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 4971 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 4972 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 4973 #ifdef PCI_RES_BUS 4974 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 4975 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 4976 #endif 4977 4978 pci_cfg_save(child, dinfo, 1); 4979 } 4980 4981 /* 4982 * Parse the PCI device database, if loaded, and return a pointer to a 4983 * description of the device. 4984 * 4985 * The database is flat text formatted as follows: 4986 * 4987 * Any line not in a valid format is ignored. 4988 * Lines are terminated with newline '\n' characters. 4989 * 4990 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 4991 * the vendor name. 4992 * 4993 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 4994 * - devices cannot be listed without a corresponding VENDOR line. 4995 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 4996 * another TAB, then the device name. 4997 */ 4998 4999 /* 5000 * Assuming (ptr) points to the beginning of a line in the database, 5001 * return the vendor or device and description of the next entry. 5002 * The value of (vendor) or (device) inappropriate for the entry type 5003 * is set to -1. Returns nonzero at the end of the database. 5004 * 5005 * Note that this is slightly unrobust in the face of corrupt data; 5006 * we attempt to safeguard against this by spamming the end of the 5007 * database with a newline when we initialise. 5008 */ 5009 static int 5010 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5011 { 5012 char *cp = *ptr; 5013 int left; 5014 5015 *device = -1; 5016 *vendor = -1; 5017 **desc = '\0'; 5018 for (;;) { 5019 left = pci_vendordata_size - (cp - pci_vendordata); 5020 if (left <= 0) { 5021 *ptr = cp; 5022 return(1); 5023 } 5024 5025 /* vendor entry? */ 5026 if (*cp != '\t' && 5027 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5028 break; 5029 /* device entry? */ 5030 if (*cp == '\t' && 5031 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5032 break; 5033 5034 /* skip to next line */ 5035 while (*cp != '\n' && left > 0) { 5036 cp++; 5037 left--; 5038 } 5039 if (*cp == '\n') { 5040 cp++; 5041 left--; 5042 } 5043 } 5044 /* skip to next line */ 5045 while (*cp != '\n' && left > 0) { 5046 cp++; 5047 left--; 5048 } 5049 if (*cp == '\n' && left > 0) 5050 cp++; 5051 *ptr = cp; 5052 return(0); 5053 } 5054 5055 static char * 5056 pci_describe_device(device_t dev) 5057 { 5058 int vendor, device; 5059 char *desc, *vp, *dp, *line; 5060 5061 desc = vp = dp = NULL; 5062 5063 /* 5064 * If we have no vendor data, we can't do anything. 5065 */ 5066 if (pci_vendordata == NULL) 5067 goto out; 5068 5069 /* 5070 * Scan the vendor data looking for this device 5071 */ 5072 line = pci_vendordata; 5073 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5074 goto out; 5075 for (;;) { 5076 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5077 goto out; 5078 if (vendor == pci_get_vendor(dev)) 5079 break; 5080 } 5081 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5082 goto out; 5083 for (;;) { 5084 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5085 *dp = 0; 5086 break; 5087 } 5088 if (vendor != -1) { 5089 *dp = 0; 5090 break; 5091 } 5092 if (device == pci_get_device(dev)) 5093 break; 5094 } 5095 if (dp[0] == '\0') 5096 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5097 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5098 NULL) 5099 sprintf(desc, "%s, %s", vp, dp); 5100 out: 5101 if (vp != NULL) 5102 free(vp, M_DEVBUF); 5103 if (dp != NULL) 5104 free(dp, M_DEVBUF); 5105 return(desc); 5106 } 5107 5108 int 5109 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5110 { 5111 struct pci_devinfo *dinfo; 5112 pcicfgregs *cfg; 5113 5114 dinfo = device_get_ivars(child); 5115 cfg = &dinfo->cfg; 5116 5117 switch (which) { 5118 case PCI_IVAR_ETHADDR: 5119 /* 5120 * The generic accessor doesn't deal with failure, so 5121 * we set the return value, then return an error. 5122 */ 5123 *((uint8_t **) result) = NULL; 5124 return (EINVAL); 5125 case PCI_IVAR_SUBVENDOR: 5126 *result = cfg->subvendor; 5127 break; 5128 case PCI_IVAR_SUBDEVICE: 5129 *result = cfg->subdevice; 5130 break; 5131 case PCI_IVAR_VENDOR: 5132 *result = cfg->vendor; 5133 break; 5134 case PCI_IVAR_DEVICE: 5135 *result = cfg->device; 5136 break; 5137 case PCI_IVAR_DEVID: 5138 *result = (cfg->device << 16) | cfg->vendor; 5139 break; 5140 case PCI_IVAR_CLASS: 5141 *result = cfg->baseclass; 5142 break; 5143 case PCI_IVAR_SUBCLASS: 5144 *result = cfg->subclass; 5145 break; 5146 case PCI_IVAR_PROGIF: 5147 *result = cfg->progif; 5148 break; 5149 case PCI_IVAR_REVID: 5150 *result = cfg->revid; 5151 break; 5152 case PCI_IVAR_INTPIN: 5153 *result = cfg->intpin; 5154 break; 5155 case PCI_IVAR_IRQ: 5156 *result = cfg->intline; 5157 break; 5158 case PCI_IVAR_DOMAIN: 5159 *result = cfg->domain; 5160 break; 5161 case PCI_IVAR_BUS: 5162 *result = cfg->bus; 5163 break; 5164 case PCI_IVAR_SLOT: 5165 *result = cfg->slot; 5166 break; 5167 case PCI_IVAR_FUNCTION: 5168 *result = cfg->func; 5169 break; 5170 case PCI_IVAR_CMDREG: 5171 *result = cfg->cmdreg; 5172 break; 5173 case PCI_IVAR_CACHELNSZ: 5174 *result = cfg->cachelnsz; 5175 break; 5176 case PCI_IVAR_MINGNT: 5177 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5178 *result = -1; 5179 return (EINVAL); 5180 } 5181 *result = cfg->mingnt; 5182 break; 5183 case PCI_IVAR_MAXLAT: 5184 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5185 *result = -1; 5186 return (EINVAL); 5187 } 5188 *result = cfg->maxlat; 5189 break; 5190 case PCI_IVAR_LATTIMER: 5191 *result = cfg->lattimer; 5192 break; 5193 default: 5194 return (ENOENT); 5195 } 5196 return (0); 5197 } 5198 5199 int 5200 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5201 { 5202 struct pci_devinfo *dinfo; 5203 5204 dinfo = device_get_ivars(child); 5205 5206 switch (which) { 5207 case PCI_IVAR_INTPIN: 5208 dinfo->cfg.intpin = value; 5209 return (0); 5210 case PCI_IVAR_ETHADDR: 5211 case PCI_IVAR_SUBVENDOR: 5212 case PCI_IVAR_SUBDEVICE: 5213 case PCI_IVAR_VENDOR: 5214 case PCI_IVAR_DEVICE: 5215 case PCI_IVAR_DEVID: 5216 case PCI_IVAR_CLASS: 5217 case PCI_IVAR_SUBCLASS: 5218 case PCI_IVAR_PROGIF: 5219 case PCI_IVAR_REVID: 5220 case PCI_IVAR_IRQ: 5221 case PCI_IVAR_DOMAIN: 5222 case PCI_IVAR_BUS: 5223 case PCI_IVAR_SLOT: 5224 case PCI_IVAR_FUNCTION: 5225 return (EINVAL); /* disallow for now */ 5226 5227 default: 5228 return (ENOENT); 5229 } 5230 } 5231 5232 #include "opt_ddb.h" 5233 #ifdef DDB 5234 #include <ddb/ddb.h> 5235 #include <sys/cons.h> 5236 5237 /* 5238 * List resources based on pci map registers, used for within ddb 5239 */ 5240 5241 DB_SHOW_COMMAND(pciregs, db_pci_dump) 5242 { 5243 struct pci_devinfo *dinfo; 5244 struct devlist *devlist_head; 5245 struct pci_conf *p; 5246 const char *name; 5247 int i, error, none_count; 5248 5249 none_count = 0; 5250 /* get the head of the device queue */ 5251 devlist_head = &pci_devq; 5252 5253 /* 5254 * Go through the list of devices and print out devices 5255 */ 5256 for (error = 0, i = 0, 5257 dinfo = STAILQ_FIRST(devlist_head); 5258 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5259 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5260 5261 /* Populate pd_name and pd_unit */ 5262 name = NULL; 5263 if (dinfo->cfg.dev) 5264 name = device_get_name(dinfo->cfg.dev); 5265 5266 p = &dinfo->conf; 5267 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5268 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5269 (name && *name) ? name : "none", 5270 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5271 none_count++, 5272 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5273 p->pc_sel.pc_func, (p->pc_class << 16) | 5274 (p->pc_subclass << 8) | p->pc_progif, 5275 (p->pc_subdevice << 16) | p->pc_subvendor, 5276 (p->pc_device << 16) | p->pc_vendor, 5277 p->pc_revid, p->pc_hdr); 5278 } 5279 } 5280 #endif /* DDB */ 5281 5282 static struct resource * 5283 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5284 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5285 u_int flags) 5286 { 5287 struct pci_devinfo *dinfo = device_get_ivars(child); 5288 struct resource_list *rl = &dinfo->resources; 5289 struct resource *res; 5290 struct pci_map *pm; 5291 uint16_t cmd; 5292 pci_addr_t map, testval; 5293 int mapsize; 5294 5295 res = NULL; 5296 5297 /* If rid is managed by EA, ignore it */ 5298 if (pci_ea_is_enabled(child, *rid)) 5299 goto out; 5300 5301 pm = pci_find_bar(child, *rid); 5302 if (pm != NULL) { 5303 /* This is a BAR that we failed to allocate earlier. */ 5304 mapsize = pm->pm_size; 5305 map = pm->pm_value; 5306 } else { 5307 /* 5308 * Weed out the bogons, and figure out how large the 5309 * BAR/map is. BARs that read back 0 here are bogus 5310 * and unimplemented. Note: atapci in legacy mode are 5311 * special and handled elsewhere in the code. If you 5312 * have a atapci device in legacy mode and it fails 5313 * here, that other code is broken. 5314 */ 5315 pci_read_bar(child, *rid, &map, &testval, NULL); 5316 5317 /* 5318 * Determine the size of the BAR and ignore BARs with a size 5319 * of 0. Device ROM BARs use a different mask value. 5320 */ 5321 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5322 mapsize = pci_romsize(testval); 5323 else 5324 mapsize = pci_mapsize(testval); 5325 if (mapsize == 0) 5326 goto out; 5327 pm = pci_add_bar(child, *rid, map, mapsize); 5328 } 5329 5330 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5331 if (type != SYS_RES_MEMORY) { 5332 if (bootverbose) 5333 device_printf(dev, 5334 "child %s requested type %d for rid %#x," 5335 " but the BAR says it is an memio\n", 5336 device_get_nameunit(child), type, *rid); 5337 goto out; 5338 } 5339 } else { 5340 if (type != SYS_RES_IOPORT) { 5341 if (bootverbose) 5342 device_printf(dev, 5343 "child %s requested type %d for rid %#x," 5344 " but the BAR says it is an ioport\n", 5345 device_get_nameunit(child), type, *rid); 5346 goto out; 5347 } 5348 } 5349 5350 /* 5351 * For real BARs, we need to override the size that 5352 * the driver requests, because that's what the BAR 5353 * actually uses and we would otherwise have a 5354 * situation where we might allocate the excess to 5355 * another driver, which won't work. 5356 */ 5357 count = ((pci_addr_t)1 << mapsize) * num; 5358 if (RF_ALIGNMENT(flags) < mapsize) 5359 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5360 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5361 flags |= RF_PREFETCHABLE; 5362 5363 /* 5364 * Allocate enough resource, and then write back the 5365 * appropriate BAR for that resource. 5366 */ 5367 resource_list_add(rl, type, *rid, start, end, count); 5368 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5369 count, flags & ~RF_ACTIVE); 5370 if (res == NULL) { 5371 resource_list_delete(rl, type, *rid); 5372 device_printf(child, 5373 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5374 count, *rid, type, start, end); 5375 goto out; 5376 } 5377 if (bootverbose) 5378 device_printf(child, 5379 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5380 count, *rid, type, rman_get_start(res)); 5381 5382 /* Disable decoding via the CMD register before updating the BAR */ 5383 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5384 pci_write_config(child, PCIR_COMMAND, 5385 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5386 5387 map = rman_get_start(res); 5388 pci_write_bar(child, pm, map); 5389 5390 /* Restore the original value of the CMD register */ 5391 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5392 out: 5393 return (res); 5394 } 5395 5396 struct resource * 5397 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5398 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5399 u_int flags) 5400 { 5401 struct pci_devinfo *dinfo; 5402 struct resource_list *rl; 5403 struct resource_list_entry *rle; 5404 struct resource *res; 5405 pcicfgregs *cfg; 5406 5407 /* 5408 * Perform lazy resource allocation 5409 */ 5410 dinfo = device_get_ivars(child); 5411 rl = &dinfo->resources; 5412 cfg = &dinfo->cfg; 5413 switch (type) { 5414 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 5415 case PCI_RES_BUS: 5416 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5417 flags)); 5418 #endif 5419 case SYS_RES_IRQ: 5420 /* 5421 * Can't alloc legacy interrupt once MSI messages have 5422 * been allocated. 5423 */ 5424 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5425 cfg->msix.msix_alloc > 0)) 5426 return (NULL); 5427 5428 /* 5429 * If the child device doesn't have an interrupt 5430 * routed and is deserving of an interrupt, try to 5431 * assign it one. 5432 */ 5433 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5434 (cfg->intpin != 0)) 5435 pci_assign_interrupt(dev, child, 0); 5436 break; 5437 case SYS_RES_IOPORT: 5438 case SYS_RES_MEMORY: 5439 #ifdef NEW_PCIB 5440 /* 5441 * PCI-PCI bridge I/O window resources are not BARs. 5442 * For those allocations just pass the request up the 5443 * tree. 5444 */ 5445 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5446 switch (*rid) { 5447 case PCIR_IOBASEL_1: 5448 case PCIR_MEMBASE_1: 5449 case PCIR_PMBASEL_1: 5450 /* 5451 * XXX: Should we bother creating a resource 5452 * list entry? 5453 */ 5454 return (bus_generic_alloc_resource(dev, child, 5455 type, rid, start, end, count, flags)); 5456 } 5457 } 5458 #endif 5459 /* Reserve resources for this BAR if needed. */ 5460 rle = resource_list_find(rl, type, *rid); 5461 if (rle == NULL) { 5462 res = pci_reserve_map(dev, child, type, rid, start, end, 5463 count, num, flags); 5464 if (res == NULL) 5465 return (NULL); 5466 } 5467 } 5468 return (resource_list_alloc(rl, dev, child, type, rid, 5469 start, end, count, flags)); 5470 } 5471 5472 struct resource * 5473 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5474 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5475 { 5476 #ifdef PCI_IOV 5477 struct pci_devinfo *dinfo; 5478 #endif 5479 5480 if (device_get_parent(child) != dev) 5481 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5482 type, rid, start, end, count, flags)); 5483 5484 #ifdef PCI_IOV 5485 dinfo = device_get_ivars(child); 5486 if (dinfo->cfg.flags & PCICFG_VF) { 5487 switch (type) { 5488 /* VFs can't have I/O BARs. */ 5489 case SYS_RES_IOPORT: 5490 return (NULL); 5491 case SYS_RES_MEMORY: 5492 return (pci_vf_alloc_mem_resource(dev, child, rid, 5493 start, end, count, flags)); 5494 } 5495 5496 /* Fall through for other types of resource allocations. */ 5497 } 5498 #endif 5499 5500 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5501 count, 1, flags)); 5502 } 5503 5504 int 5505 pci_release_resource(device_t dev, device_t child, int type, int rid, 5506 struct resource *r) 5507 { 5508 struct pci_devinfo *dinfo; 5509 struct resource_list *rl; 5510 pcicfgregs *cfg; 5511 5512 if (device_get_parent(child) != dev) 5513 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 5514 type, rid, r)); 5515 5516 dinfo = device_get_ivars(child); 5517 cfg = &dinfo->cfg; 5518 5519 #ifdef PCI_IOV 5520 if (dinfo->cfg.flags & PCICFG_VF) { 5521 switch (type) { 5522 /* VFs can't have I/O BARs. */ 5523 case SYS_RES_IOPORT: 5524 return (EDOOFUS); 5525 case SYS_RES_MEMORY: 5526 return (pci_vf_release_mem_resource(dev, child, rid, 5527 r)); 5528 } 5529 5530 /* Fall through for other types of resource allocations. */ 5531 } 5532 #endif 5533 5534 #ifdef NEW_PCIB 5535 /* 5536 * PCI-PCI bridge I/O window resources are not BARs. For 5537 * those allocations just pass the request up the tree. 5538 */ 5539 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5540 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 5541 switch (rid) { 5542 case PCIR_IOBASEL_1: 5543 case PCIR_MEMBASE_1: 5544 case PCIR_PMBASEL_1: 5545 return (bus_generic_release_resource(dev, child, type, 5546 rid, r)); 5547 } 5548 } 5549 #endif 5550 5551 rl = &dinfo->resources; 5552 return (resource_list_release(rl, dev, child, type, rid, r)); 5553 } 5554 5555 int 5556 pci_activate_resource(device_t dev, device_t child, int type, int rid, 5557 struct resource *r) 5558 { 5559 struct pci_devinfo *dinfo; 5560 int error; 5561 5562 error = bus_generic_activate_resource(dev, child, type, rid, r); 5563 if (error) 5564 return (error); 5565 5566 /* Enable decoding in the command register when activating BARs. */ 5567 if (device_get_parent(child) == dev) { 5568 /* Device ROMs need their decoding explicitly enabled. */ 5569 dinfo = device_get_ivars(child); 5570 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5571 pci_write_bar(child, pci_find_bar(child, rid), 5572 rman_get_start(r) | PCIM_BIOS_ENABLE); 5573 switch (type) { 5574 case SYS_RES_IOPORT: 5575 case SYS_RES_MEMORY: 5576 error = PCI_ENABLE_IO(dev, child, type); 5577 break; 5578 } 5579 } 5580 return (error); 5581 } 5582 5583 int 5584 pci_deactivate_resource(device_t dev, device_t child, int type, 5585 int rid, struct resource *r) 5586 { 5587 struct pci_devinfo *dinfo; 5588 int error; 5589 5590 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 5591 if (error) 5592 return (error); 5593 5594 /* Disable decoding for device ROMs. */ 5595 if (device_get_parent(child) == dev) { 5596 dinfo = device_get_ivars(child); 5597 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5598 pci_write_bar(child, pci_find_bar(child, rid), 5599 rman_get_start(r)); 5600 } 5601 return (0); 5602 } 5603 5604 void 5605 pci_child_deleted(device_t dev, device_t child) 5606 { 5607 struct resource_list_entry *rle; 5608 struct resource_list *rl; 5609 struct pci_devinfo *dinfo; 5610 5611 dinfo = device_get_ivars(child); 5612 rl = &dinfo->resources; 5613 5614 EVENTHANDLER_INVOKE(pci_delete_device, child); 5615 5616 /* Turn off access to resources we're about to free */ 5617 if (bus_child_present(child) != 0) { 5618 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5619 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5620 5621 pci_disable_busmaster(child); 5622 } 5623 5624 /* Free all allocated resources */ 5625 STAILQ_FOREACH(rle, rl, link) { 5626 if (rle->res) { 5627 if (rman_get_flags(rle->res) & RF_ACTIVE || 5628 resource_list_busy(rl, rle->type, rle->rid)) { 5629 pci_printf(&dinfo->cfg, 5630 "Resource still owned, oops. " 5631 "(type=%d, rid=%d, addr=%lx)\n", 5632 rle->type, rle->rid, 5633 rman_get_start(rle->res)); 5634 bus_release_resource(child, rle->type, rle->rid, 5635 rle->res); 5636 } 5637 resource_list_unreserve(rl, dev, child, rle->type, 5638 rle->rid); 5639 } 5640 } 5641 resource_list_free(rl); 5642 5643 pci_freecfg(dinfo); 5644 } 5645 5646 void 5647 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5648 { 5649 struct pci_devinfo *dinfo; 5650 struct resource_list *rl; 5651 struct resource_list_entry *rle; 5652 5653 if (device_get_parent(child) != dev) 5654 return; 5655 5656 dinfo = device_get_ivars(child); 5657 rl = &dinfo->resources; 5658 rle = resource_list_find(rl, type, rid); 5659 if (rle == NULL) 5660 return; 5661 5662 if (rle->res) { 5663 if (rman_get_flags(rle->res) & RF_ACTIVE || 5664 resource_list_busy(rl, type, rid)) { 5665 device_printf(dev, "delete_resource: " 5666 "Resource still owned by child, oops. " 5667 "(type=%d, rid=%d, addr=%jx)\n", 5668 type, rid, rman_get_start(rle->res)); 5669 return; 5670 } 5671 resource_list_unreserve(rl, dev, child, type, rid); 5672 } 5673 resource_list_delete(rl, type, rid); 5674 } 5675 5676 struct resource_list * 5677 pci_get_resource_list (device_t dev, device_t child) 5678 { 5679 struct pci_devinfo *dinfo = device_get_ivars(child); 5680 5681 return (&dinfo->resources); 5682 } 5683 5684 #ifdef ACPI_DMAR 5685 bus_dma_tag_t acpi_iommu_get_dma_tag(device_t dev, device_t child); 5686 bus_dma_tag_t 5687 pci_get_dma_tag(device_t bus, device_t dev) 5688 { 5689 bus_dma_tag_t tag; 5690 struct pci_softc *sc; 5691 5692 if (device_get_parent(dev) == bus) { 5693 /* try iommu and return if it works */ 5694 tag = acpi_iommu_get_dma_tag(bus, dev); 5695 } else 5696 tag = NULL; 5697 if (tag == NULL) { 5698 sc = device_get_softc(bus); 5699 tag = sc->sc_dma_tag; 5700 } 5701 return (tag); 5702 } 5703 #else 5704 bus_dma_tag_t 5705 pci_get_dma_tag(device_t bus, device_t dev) 5706 { 5707 struct pci_softc *sc = device_get_softc(bus); 5708 5709 return (sc->sc_dma_tag); 5710 } 5711 #endif 5712 5713 uint32_t 5714 pci_read_config_method(device_t dev, device_t child, int reg, int width) 5715 { 5716 struct pci_devinfo *dinfo = device_get_ivars(child); 5717 pcicfgregs *cfg = &dinfo->cfg; 5718 5719 #ifdef PCI_IOV 5720 /* 5721 * SR-IOV VFs don't implement the VID or DID registers, so we have to 5722 * emulate them here. 5723 */ 5724 if (cfg->flags & PCICFG_VF) { 5725 if (reg == PCIR_VENDOR) { 5726 switch (width) { 5727 case 4: 5728 return (cfg->device << 16 | cfg->vendor); 5729 case 2: 5730 return (cfg->vendor); 5731 case 1: 5732 return (cfg->vendor & 0xff); 5733 default: 5734 return (0xffffffff); 5735 } 5736 } else if (reg == PCIR_DEVICE) { 5737 switch (width) { 5738 /* Note that an unaligned 4-byte read is an error. */ 5739 case 2: 5740 return (cfg->device); 5741 case 1: 5742 return (cfg->device & 0xff); 5743 default: 5744 return (0xffffffff); 5745 } 5746 } 5747 } 5748 #endif 5749 5750 return (PCIB_READ_CONFIG(device_get_parent(dev), 5751 cfg->bus, cfg->slot, cfg->func, reg, width)); 5752 } 5753 5754 void 5755 pci_write_config_method(device_t dev, device_t child, int reg, 5756 uint32_t val, int width) 5757 { 5758 struct pci_devinfo *dinfo = device_get_ivars(child); 5759 pcicfgregs *cfg = &dinfo->cfg; 5760 5761 PCIB_WRITE_CONFIG(device_get_parent(dev), 5762 cfg->bus, cfg->slot, cfg->func, reg, val, width); 5763 } 5764 5765 int 5766 pci_child_location_str_method(device_t dev, device_t child, char *buf, 5767 size_t buflen) 5768 { 5769 5770 snprintf(buf, buflen, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 5771 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 5772 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 5773 return (0); 5774 } 5775 5776 int 5777 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 5778 size_t buflen) 5779 { 5780 struct pci_devinfo *dinfo; 5781 pcicfgregs *cfg; 5782 5783 dinfo = device_get_ivars(child); 5784 cfg = &dinfo->cfg; 5785 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 5786 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 5787 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 5788 cfg->progif); 5789 return (0); 5790 } 5791 5792 int 5793 pci_assign_interrupt_method(device_t dev, device_t child) 5794 { 5795 struct pci_devinfo *dinfo = device_get_ivars(child); 5796 pcicfgregs *cfg = &dinfo->cfg; 5797 5798 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 5799 cfg->intpin)); 5800 } 5801 5802 static void 5803 pci_lookup(void *arg, const char *name, device_t *dev) 5804 { 5805 long val; 5806 char *end; 5807 int domain, bus, slot, func; 5808 5809 if (*dev != NULL) 5810 return; 5811 5812 /* 5813 * Accept pciconf-style selectors of either pciD:B:S:F or 5814 * pciB:S:F. In the latter case, the domain is assumed to 5815 * be zero. 5816 */ 5817 if (strncmp(name, "pci", 3) != 0) 5818 return; 5819 val = strtol(name + 3, &end, 10); 5820 if (val < 0 || val > INT_MAX || *end != ':') 5821 return; 5822 domain = val; 5823 val = strtol(end + 1, &end, 10); 5824 if (val < 0 || val > INT_MAX || *end != ':') 5825 return; 5826 bus = val; 5827 val = strtol(end + 1, &end, 10); 5828 if (val < 0 || val > INT_MAX) 5829 return; 5830 slot = val; 5831 if (*end == ':') { 5832 val = strtol(end + 1, &end, 10); 5833 if (val < 0 || val > INT_MAX || *end != '\0') 5834 return; 5835 func = val; 5836 } else if (*end == '\0') { 5837 func = slot; 5838 slot = bus; 5839 bus = domain; 5840 domain = 0; 5841 } else 5842 return; 5843 5844 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 5845 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 5846 return; 5847 5848 *dev = pci_find_dbsf(domain, bus, slot, func); 5849 } 5850 5851 static int 5852 pci_modevent(module_t mod, int what, void *arg) 5853 { 5854 static struct cdev *pci_cdev; 5855 static eventhandler_tag tag; 5856 5857 switch (what) { 5858 case MOD_LOAD: 5859 STAILQ_INIT(&pci_devq); 5860 pci_generation = 0; 5861 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 5862 "pci"); 5863 pci_load_vendor_data(); 5864 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 5865 1000); 5866 break; 5867 5868 case MOD_UNLOAD: 5869 if (tag != NULL) 5870 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 5871 destroy_dev(pci_cdev); 5872 break; 5873 } 5874 5875 return (0); 5876 } 5877 5878 static void 5879 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 5880 { 5881 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 5882 struct pcicfg_pcie *cfg; 5883 int version, pos; 5884 5885 cfg = &dinfo->cfg.pcie; 5886 pos = cfg->pcie_location; 5887 5888 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 5889 5890 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 5891 5892 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5893 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 5894 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 5895 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 5896 5897 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5898 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 5899 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 5900 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 5901 5902 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5903 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 5904 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 5905 5906 if (version > 1) { 5907 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 5908 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 5909 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 5910 } 5911 #undef WREG 5912 } 5913 5914 static void 5915 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 5916 { 5917 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 5918 dinfo->cfg.pcix.pcix_command, 2); 5919 } 5920 5921 void 5922 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 5923 { 5924 5925 /* 5926 * Restore the device to full power mode. We must do this 5927 * before we restore the registers because moving from D3 to 5928 * D0 will cause the chip's BARs and some other registers to 5929 * be reset to some unknown power on reset values. Cut down 5930 * the noise on boot by doing nothing if we are already in 5931 * state D0. 5932 */ 5933 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 5934 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 5935 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 5936 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 5937 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 5938 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 5939 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 5940 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 5941 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 5942 case PCIM_HDRTYPE_NORMAL: 5943 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 5944 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 5945 break; 5946 case PCIM_HDRTYPE_BRIDGE: 5947 pci_write_config(dev, PCIR_SECLAT_1, 5948 dinfo->cfg.bridge.br_seclat, 1); 5949 pci_write_config(dev, PCIR_SUBBUS_1, 5950 dinfo->cfg.bridge.br_subbus, 1); 5951 pci_write_config(dev, PCIR_SECBUS_1, 5952 dinfo->cfg.bridge.br_secbus, 1); 5953 pci_write_config(dev, PCIR_PRIBUS_1, 5954 dinfo->cfg.bridge.br_pribus, 1); 5955 pci_write_config(dev, PCIR_BRIDGECTL_1, 5956 dinfo->cfg.bridge.br_control, 2); 5957 break; 5958 case PCIM_HDRTYPE_CARDBUS: 5959 pci_write_config(dev, PCIR_SECLAT_2, 5960 dinfo->cfg.bridge.br_seclat, 1); 5961 pci_write_config(dev, PCIR_SUBBUS_2, 5962 dinfo->cfg.bridge.br_subbus, 1); 5963 pci_write_config(dev, PCIR_SECBUS_2, 5964 dinfo->cfg.bridge.br_secbus, 1); 5965 pci_write_config(dev, PCIR_PRIBUS_2, 5966 dinfo->cfg.bridge.br_pribus, 1); 5967 pci_write_config(dev, PCIR_BRIDGECTL_2, 5968 dinfo->cfg.bridge.br_control, 2); 5969 break; 5970 } 5971 pci_restore_bars(dev); 5972 5973 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 5974 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 5975 5976 /* 5977 * Restore extended capabilities for PCI-Express and PCI-X 5978 */ 5979 if (dinfo->cfg.pcie.pcie_location != 0) 5980 pci_cfg_restore_pcie(dev, dinfo); 5981 if (dinfo->cfg.pcix.pcix_location != 0) 5982 pci_cfg_restore_pcix(dev, dinfo); 5983 5984 /* Restore MSI and MSI-X configurations if they are present. */ 5985 if (dinfo->cfg.msi.msi_location != 0) 5986 pci_resume_msi(dev); 5987 if (dinfo->cfg.msix.msix_location != 0) 5988 pci_resume_msix(dev); 5989 5990 #ifdef PCI_IOV 5991 if (dinfo->cfg.iov != NULL) 5992 pci_iov_cfg_restore(dev, dinfo); 5993 #endif 5994 } 5995 5996 static void 5997 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 5998 { 5999 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6000 struct pcicfg_pcie *cfg; 6001 int version, pos; 6002 6003 cfg = &dinfo->cfg.pcie; 6004 pos = cfg->pcie_location; 6005 6006 cfg->pcie_flags = RREG(PCIER_FLAGS); 6007 6008 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6009 6010 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6011 6012 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6013 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6014 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6015 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6016 6017 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6018 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6019 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6020 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6021 6022 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6023 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6024 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6025 6026 if (version > 1) { 6027 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6028 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6029 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6030 } 6031 #undef RREG 6032 } 6033 6034 static void 6035 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6036 { 6037 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6038 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6039 } 6040 6041 void 6042 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6043 { 6044 uint32_t cls; 6045 int ps; 6046 6047 /* 6048 * Some drivers apparently write to these registers w/o updating our 6049 * cached copy. No harm happens if we update the copy, so do so here 6050 * so we can restore them. The COMMAND register is modified by the 6051 * bus w/o updating the cache. This should represent the normally 6052 * writable portion of the 'defined' part of type 0/1/2 headers. 6053 */ 6054 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6055 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6056 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6057 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6058 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6059 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6060 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6061 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6062 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6063 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6064 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6065 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6066 case PCIM_HDRTYPE_NORMAL: 6067 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6068 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6069 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6070 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6071 break; 6072 case PCIM_HDRTYPE_BRIDGE: 6073 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6074 PCIR_SECLAT_1, 1); 6075 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6076 PCIR_SUBBUS_1, 1); 6077 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6078 PCIR_SECBUS_1, 1); 6079 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6080 PCIR_PRIBUS_1, 1); 6081 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6082 PCIR_BRIDGECTL_1, 2); 6083 break; 6084 case PCIM_HDRTYPE_CARDBUS: 6085 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6086 PCIR_SECLAT_2, 1); 6087 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6088 PCIR_SUBBUS_2, 1); 6089 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6090 PCIR_SECBUS_2, 1); 6091 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6092 PCIR_PRIBUS_2, 1); 6093 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6094 PCIR_BRIDGECTL_2, 2); 6095 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6096 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6097 break; 6098 } 6099 6100 if (dinfo->cfg.pcie.pcie_location != 0) 6101 pci_cfg_save_pcie(dev, dinfo); 6102 6103 if (dinfo->cfg.pcix.pcix_location != 0) 6104 pci_cfg_save_pcix(dev, dinfo); 6105 6106 #ifdef PCI_IOV 6107 if (dinfo->cfg.iov != NULL) 6108 pci_iov_cfg_save(dev, dinfo); 6109 #endif 6110 6111 /* 6112 * don't set the state for display devices, base peripherals and 6113 * memory devices since bad things happen when they are powered down. 6114 * We should (a) have drivers that can easily detach and (b) use 6115 * generic drivers for these devices so that some device actually 6116 * attaches. We need to make sure that when we implement (a) we don't 6117 * power the device down on a reattach. 6118 */ 6119 cls = pci_get_class(dev); 6120 if (!setstate) 6121 return; 6122 switch (pci_do_power_nodriver) 6123 { 6124 case 0: /* NO powerdown at all */ 6125 return; 6126 case 1: /* Conservative about what to power down */ 6127 if (cls == PCIC_STORAGE) 6128 return; 6129 /*FALLTHROUGH*/ 6130 case 2: /* Aggressive about what to power down */ 6131 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6132 cls == PCIC_BASEPERIPH) 6133 return; 6134 /*FALLTHROUGH*/ 6135 case 3: /* Power down everything */ 6136 break; 6137 } 6138 /* 6139 * PCI spec says we can only go into D3 state from D0 state. 6140 * Transition from D[12] into D0 before going to D3 state. 6141 */ 6142 ps = pci_get_powerstate(dev); 6143 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6144 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6145 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6146 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6147 } 6148 6149 /* Wrapper APIs suitable for device driver use. */ 6150 void 6151 pci_save_state(device_t dev) 6152 { 6153 struct pci_devinfo *dinfo; 6154 6155 dinfo = device_get_ivars(dev); 6156 pci_cfg_save(dev, dinfo, 0); 6157 } 6158 6159 void 6160 pci_restore_state(device_t dev) 6161 { 6162 struct pci_devinfo *dinfo; 6163 6164 dinfo = device_get_ivars(dev); 6165 pci_cfg_restore(dev, dinfo); 6166 } 6167 6168 static int 6169 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6170 uintptr_t *id) 6171 { 6172 6173 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6174 } 6175 6176 /* Find the upstream port of a given PCI device in a root complex. */ 6177 device_t 6178 pci_find_pcie_root_port(device_t dev) 6179 { 6180 struct pci_devinfo *dinfo; 6181 devclass_t pci_class; 6182 device_t pcib, bus; 6183 6184 pci_class = devclass_find("pci"); 6185 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6186 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6187 6188 /* 6189 * Walk the bridge hierarchy until we find a PCI-e root 6190 * port or a non-PCI device. 6191 */ 6192 for (;;) { 6193 bus = device_get_parent(dev); 6194 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6195 device_get_nameunit(dev))); 6196 6197 pcib = device_get_parent(bus); 6198 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6199 device_get_nameunit(bus))); 6200 6201 /* 6202 * pcib's parent must be a PCI bus for this to be a 6203 * PCI-PCI bridge. 6204 */ 6205 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6206 return (NULL); 6207 6208 dinfo = device_get_ivars(pcib); 6209 if (dinfo->cfg.pcie.pcie_location != 0 && 6210 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6211 return (pcib); 6212 6213 dev = pcib; 6214 } 6215 } 6216 6217 /* 6218 * Wait for pending transactions to complete on a PCI-express function. 6219 * 6220 * The maximum delay is specified in milliseconds in max_delay. Note 6221 * that this function may sleep. 6222 * 6223 * Returns true if the function is idle and false if the timeout is 6224 * exceeded. If dev is not a PCI-express function, this returns true. 6225 */ 6226 bool 6227 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6228 { 6229 struct pci_devinfo *dinfo = device_get_ivars(dev); 6230 uint16_t sta; 6231 int cap; 6232 6233 cap = dinfo->cfg.pcie.pcie_location; 6234 if (cap == 0) 6235 return (true); 6236 6237 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6238 while (sta & PCIEM_STA_TRANSACTION_PND) { 6239 if (max_delay == 0) 6240 return (false); 6241 6242 /* Poll once every 100 milliseconds up to the timeout. */ 6243 if (max_delay > 100) { 6244 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6245 max_delay -= 100; 6246 } else { 6247 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6248 C_HARDCLOCK); 6249 max_delay = 0; 6250 } 6251 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6252 } 6253 6254 return (true); 6255 } 6256 6257 /* 6258 * Determine the maximum Completion Timeout in microseconds. 6259 * 6260 * For non-PCI-express functions this returns 0. 6261 */ 6262 int 6263 pcie_get_max_completion_timeout(device_t dev) 6264 { 6265 struct pci_devinfo *dinfo = device_get_ivars(dev); 6266 int cap; 6267 6268 cap = dinfo->cfg.pcie.pcie_location; 6269 if (cap == 0) 6270 return (0); 6271 6272 /* 6273 * Functions using the 1.x spec use the default timeout range of 6274 * 50 microseconds to 50 milliseconds. Functions that do not 6275 * support programmable timeouts also use this range. 6276 */ 6277 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6278 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6279 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6280 return (50 * 1000); 6281 6282 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6283 PCIEM_CTL2_COMP_TIMO_VAL) { 6284 case PCIEM_CTL2_COMP_TIMO_100US: 6285 return (100); 6286 case PCIEM_CTL2_COMP_TIMO_10MS: 6287 return (10 * 1000); 6288 case PCIEM_CTL2_COMP_TIMO_55MS: 6289 return (55 * 1000); 6290 case PCIEM_CTL2_COMP_TIMO_210MS: 6291 return (210 * 1000); 6292 case PCIEM_CTL2_COMP_TIMO_900MS: 6293 return (900 * 1000); 6294 case PCIEM_CTL2_COMP_TIMO_3500MS: 6295 return (3500 * 1000); 6296 case PCIEM_CTL2_COMP_TIMO_13S: 6297 return (13 * 1000 * 1000); 6298 case PCIEM_CTL2_COMP_TIMO_64S: 6299 return (64 * 1000 * 1000); 6300 default: 6301 return (50 * 1000); 6302 } 6303 } 6304 6305 /* 6306 * Perform a Function Level Reset (FLR) on a device. 6307 * 6308 * This function first waits for any pending transactions to complete 6309 * within the timeout specified by max_delay. If transactions are 6310 * still pending, the function will return false without attempting a 6311 * reset. 6312 * 6313 * If dev is not a PCI-express function or does not support FLR, this 6314 * function returns false. 6315 * 6316 * Note that no registers are saved or restored. The caller is 6317 * responsible for saving and restoring any registers including 6318 * PCI-standard registers via pci_save_state() and 6319 * pci_restore_state(). 6320 */ 6321 bool 6322 pcie_flr(device_t dev, u_int max_delay, bool force) 6323 { 6324 struct pci_devinfo *dinfo = device_get_ivars(dev); 6325 uint16_t cmd, ctl; 6326 int compl_delay; 6327 int cap; 6328 6329 cap = dinfo->cfg.pcie.pcie_location; 6330 if (cap == 0) 6331 return (false); 6332 6333 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6334 return (false); 6335 6336 /* 6337 * Disable busmastering to prevent generation of new 6338 * transactions while waiting for the device to go idle. If 6339 * the idle timeout fails, the command register is restored 6340 * which will re-enable busmastering. 6341 */ 6342 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6343 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6344 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6345 if (!force) { 6346 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6347 return (false); 6348 } 6349 pci_printf(&dinfo->cfg, 6350 "Resetting with transactions pending after %d ms\n", 6351 max_delay); 6352 6353 /* 6354 * Extend the post-FLR delay to cover the maximum 6355 * Completion Timeout delay of anything in flight 6356 * during the FLR delay. Enforce a minimum delay of 6357 * at least 10ms. 6358 */ 6359 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6360 if (compl_delay < 10) 6361 compl_delay = 10; 6362 } else 6363 compl_delay = 0; 6364 6365 /* Initiate the reset. */ 6366 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6367 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6368 PCIEM_CTL_INITIATE_FLR, 2); 6369 6370 /* Wait for 100ms. */ 6371 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6372 6373 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6374 PCIEM_STA_TRANSACTION_PND) 6375 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6376 return (true); 6377 } 6378 6379 /* 6380 * Attempt a power-management reset by cycling the device in/out of D3 6381 * state. PCI spec says we can only go into D3 state from D0 state. 6382 * Transition from D[12] into D0 before going to D3 state. 6383 */ 6384 int 6385 pci_power_reset(device_t dev) 6386 { 6387 int ps; 6388 6389 ps = pci_get_powerstate(dev); 6390 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6391 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6392 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6393 pci_set_powerstate(dev, ps); 6394 return (0); 6395 } 6396 6397 /* 6398 * Try link drop and retrain of the downstream port of upstream 6399 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6400 * cause Conventional Hot reset of the device in the slot. 6401 * Alternative, for PCIe, could be the secondary bus reset initiatied 6402 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6403 */ 6404 int 6405 pcie_link_reset(device_t port, int pcie_location) 6406 { 6407 uint16_t v; 6408 6409 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6410 v |= PCIEM_LINK_CTL_LINK_DIS; 6411 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6412 pause_sbt("pcier1", mstosbt(20), 0, 0); 6413 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6414 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6415 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6416 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6417 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6418 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6419 } 6420 6421 static int 6422 pci_reset_post(device_t dev, device_t child) 6423 { 6424 6425 if (dev == device_get_parent(child)) 6426 pci_restore_state(child); 6427 return (0); 6428 } 6429 6430 static int 6431 pci_reset_prepare(device_t dev, device_t child) 6432 { 6433 6434 if (dev == device_get_parent(child)) 6435 pci_save_state(child); 6436 return (0); 6437 } 6438 6439 static int 6440 pci_reset_child(device_t dev, device_t child, int flags) 6441 { 6442 int error; 6443 6444 if (dev == NULL || device_get_parent(child) != dev) 6445 return (0); 6446 if ((flags & DEVF_RESET_DETACH) != 0) { 6447 error = device_get_state(child) == DS_ATTACHED ? 6448 device_detach(child) : 0; 6449 } else { 6450 error = BUS_SUSPEND_CHILD(dev, child); 6451 } 6452 if (error == 0) { 6453 if (!pcie_flr(child, 1000, false)) { 6454 error = BUS_RESET_PREPARE(dev, child); 6455 if (error == 0) 6456 pci_power_reset(child); 6457 BUS_RESET_POST(dev, child); 6458 } 6459 if ((flags & DEVF_RESET_DETACH) != 0) 6460 device_probe_and_attach(child); 6461 else 6462 BUS_RESUME_CHILD(dev, child); 6463 } 6464 return (error); 6465 } 6466 6467 const struct pci_device_table * 6468 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6469 { 6470 bool match; 6471 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6472 6473 vendor = pci_get_vendor(child); 6474 device = pci_get_device(child); 6475 subvendor = pci_get_subvendor(child); 6476 subdevice = pci_get_subdevice(child); 6477 class = pci_get_class(child); 6478 subclass = pci_get_subclass(child); 6479 revid = pci_get_revid(child); 6480 while (nelt-- > 0) { 6481 match = true; 6482 if (id->match_flag_vendor) 6483 match &= vendor == id->vendor; 6484 if (id->match_flag_device) 6485 match &= device == id->device; 6486 if (id->match_flag_subvendor) 6487 match &= subvendor == id->subvendor; 6488 if (id->match_flag_subdevice) 6489 match &= subdevice == id->subdevice; 6490 if (id->match_flag_class) 6491 match &= class == id->class_id; 6492 if (id->match_flag_subclass) 6493 match &= subclass == id->subclass; 6494 if (id->match_flag_revid) 6495 match &= revid == id->revid; 6496 if (match) 6497 return (id); 6498 id++; 6499 } 6500 return (NULL); 6501 } 6502 6503 static void 6504 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6505 { 6506 const char *dev_name; 6507 device_t dev; 6508 6509 dev = dinfo->cfg.dev; 6510 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6511 dinfo->cfg.slot, dinfo->cfg.func); 6512 dev_name = device_get_name(dev); 6513 if (dev_name != NULL) 6514 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6515 } 6516 6517 void 6518 pci_print_faulted_dev(void) 6519 { 6520 struct pci_devinfo *dinfo; 6521 device_t dev; 6522 int aer, i; 6523 uint32_t r1, r2; 6524 uint16_t status; 6525 6526 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6527 dev = dinfo->cfg.dev; 6528 status = pci_read_config(dev, PCIR_STATUS, 2); 6529 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6530 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6531 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6532 if (status != 0) { 6533 pci_print_faulted_dev_name(dinfo); 6534 printf(" error 0x%04x\n", status); 6535 } 6536 if (dinfo->cfg.pcie.pcie_location != 0) { 6537 status = pci_read_config(dev, 6538 dinfo->cfg.pcie.pcie_location + 6539 PCIER_DEVICE_STA, 2); 6540 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6541 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6542 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6543 pci_print_faulted_dev_name(dinfo); 6544 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6545 pci_read_config(dev, 6546 dinfo->cfg.pcie.pcie_location + 6547 PCIER_DEVICE_CTL, 2), 6548 status); 6549 } 6550 } 6551 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6552 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6553 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6554 if (r1 != 0 || r2 != 0) { 6555 pci_print_faulted_dev_name(dinfo); 6556 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6557 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6558 r1, pci_read_config(dev, aer + 6559 PCIR_AER_UC_MASK, 4), 6560 pci_read_config(dev, aer + 6561 PCIR_AER_UC_SEVERITY, 4), 6562 r2, pci_read_config(dev, aer + 6563 PCIR_AER_COR_MASK, 4), 6564 pci_read_config(dev, aer + 6565 PCIR_AER_CAP_CONTROL, 4)); 6566 for (i = 0; i < 4; i++) { 6567 r1 = pci_read_config(dev, aer + 6568 PCIR_AER_HEADER_LOG + i * 4, 4); 6569 printf(" HL%d: 0x%08x\n", i, r1); 6570 } 6571 } 6572 } 6573 } 6574 } 6575 6576 #ifdef DDB 6577 DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db) 6578 { 6579 6580 pci_print_faulted_dev(); 6581 } 6582 6583 static void 6584 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6585 { 6586 device_t dev; 6587 int aer; 6588 uint32_t r; 6589 6590 dev = dinfo->cfg.dev; 6591 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6592 PCIER_DEVICE_STA, 2); 6593 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6594 PCIER_DEVICE_STA, r, 2); 6595 6596 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6597 return; 6598 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6599 if (r != 0) 6600 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6601 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6602 if (r != 0) 6603 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6604 } 6605 6606 DB_COMMAND(pci_clearerr, db_pci_clearerr) 6607 { 6608 struct pci_devinfo *dinfo; 6609 device_t dev; 6610 uint16_t status, status1; 6611 6612 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6613 dev = dinfo->cfg.dev; 6614 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 6615 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6616 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6617 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6618 if (status1 != 0) { 6619 status &= ~status1; 6620 pci_write_config(dev, PCIR_STATUS, status, 2); 6621 } 6622 if (dinfo->cfg.pcie.pcie_location != 0) 6623 db_clear_pcie_errors(dinfo); 6624 } 6625 } 6626 #endif 6627