1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_acpi.h" 35 #include "opt_iommu.h" 36 #include "opt_bus.h" 37 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/endian.h> 41 #include <sys/eventhandler.h> 42 #include <sys/fcntl.h> 43 #include <sys/kernel.h> 44 #include <sys/limits.h> 45 #include <sys/linker.h> 46 #include <sys/malloc.h> 47 #include <sys/module.h> 48 #include <sys/queue.h> 49 #include <sys/sbuf.h> 50 #include <sys/sysctl.h> 51 #include <sys/systm.h> 52 #include <sys/taskqueue.h> 53 #include <sys/tree.h> 54 55 #include <vm/vm.h> 56 #include <vm/pmap.h> 57 #include <vm/vm_extern.h> 58 59 #include <sys/bus.h> 60 #include <machine/bus.h> 61 #include <sys/rman.h> 62 #include <machine/resource.h> 63 #include <machine/stdarg.h> 64 65 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 66 #include <machine/intr_machdep.h> 67 #endif 68 69 #include <sys/pciio.h> 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pci_private.h> 73 74 #ifdef PCI_IOV 75 #include <sys/nv.h> 76 #include <dev/pci/pci_iov_private.h> 77 #endif 78 79 #include <dev/usb/controller/xhcireg.h> 80 #include <dev/usb/controller/ehcireg.h> 81 #include <dev/usb/controller/ohcireg.h> 82 #include <dev/usb/controller/uhcireg.h> 83 84 #include <dev/iommu/iommu.h> 85 86 #include "pcib_if.h" 87 #include "pci_if.h" 88 89 #define PCIR_IS_BIOS(cfg, reg) \ 90 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 91 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 92 93 static int pci_has_quirk(uint32_t devid, int quirk); 94 static pci_addr_t pci_mapbase(uint64_t mapreg); 95 static const char *pci_maptype(uint64_t mapreg); 96 static int pci_maprange(uint64_t mapreg); 97 static pci_addr_t pci_rombase(uint64_t mapreg); 98 static int pci_romsize(uint64_t testval); 99 static void pci_fixancient(pcicfgregs *cfg); 100 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 101 102 static int pci_porten(device_t dev); 103 static int pci_memen(device_t dev); 104 static void pci_assign_interrupt(device_t bus, device_t dev, 105 int force_route); 106 static int pci_add_map(device_t bus, device_t dev, int reg, 107 struct resource_list *rl, int force, int prefetch); 108 static int pci_probe(device_t dev); 109 static void pci_load_vendor_data(void); 110 static int pci_describe_parse_line(char **ptr, int *vendor, 111 int *device, char **desc); 112 static char *pci_describe_device(device_t dev); 113 static int pci_modevent(module_t mod, int what, void *arg); 114 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 115 pcicfgregs *cfg); 116 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 117 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 118 int reg, uint32_t *data); 119 #if 0 120 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 121 int reg, uint32_t data); 122 #endif 123 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 124 static void pci_mask_msix(device_t dev, u_int index); 125 static void pci_unmask_msix(device_t dev, u_int index); 126 static int pci_msi_blacklisted(void); 127 static int pci_msix_blacklisted(void); 128 static void pci_resume_msi(device_t dev); 129 static void pci_resume_msix(device_t dev); 130 static int pci_remap_intr_method(device_t bus, device_t dev, 131 u_int irq); 132 static void pci_hint_device_unit(device_t acdev, device_t child, 133 const char *name, int *unitp); 134 static int pci_reset_post(device_t dev, device_t child); 135 static int pci_reset_prepare(device_t dev, device_t child); 136 static int pci_reset_child(device_t dev, device_t child, 137 int flags); 138 139 static int pci_get_id_method(device_t dev, device_t child, 140 enum pci_id_type type, uintptr_t *rid); 141 142 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 143 int b, int s, int f, uint16_t vid, uint16_t did); 144 145 static device_method_t pci_methods[] = { 146 /* Device interface */ 147 DEVMETHOD(device_probe, pci_probe), 148 DEVMETHOD(device_attach, pci_attach), 149 DEVMETHOD(device_detach, pci_detach), 150 DEVMETHOD(device_shutdown, bus_generic_shutdown), 151 DEVMETHOD(device_suspend, bus_generic_suspend), 152 DEVMETHOD(device_resume, pci_resume), 153 154 /* Bus interface */ 155 DEVMETHOD(bus_print_child, pci_print_child), 156 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 157 DEVMETHOD(bus_read_ivar, pci_read_ivar), 158 DEVMETHOD(bus_write_ivar, pci_write_ivar), 159 DEVMETHOD(bus_driver_added, pci_driver_added), 160 DEVMETHOD(bus_setup_intr, pci_setup_intr), 161 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 162 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 163 DEVMETHOD(bus_reset_post, pci_reset_post), 164 DEVMETHOD(bus_reset_child, pci_reset_child), 165 166 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 167 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 168 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 169 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 170 DEVMETHOD(bus_delete_resource, pci_delete_resource), 171 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 172 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 173 DEVMETHOD(bus_release_resource, pci_release_resource), 174 DEVMETHOD(bus_activate_resource, pci_activate_resource), 175 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 176 DEVMETHOD(bus_child_deleted, pci_child_deleted), 177 DEVMETHOD(bus_child_detached, pci_child_detached), 178 DEVMETHOD(bus_child_pnpinfo, pci_child_pnpinfo_method), 179 DEVMETHOD(bus_child_location, pci_child_location_method), 180 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 181 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 182 DEVMETHOD(bus_suspend_child, pci_suspend_child), 183 DEVMETHOD(bus_resume_child, pci_resume_child), 184 DEVMETHOD(bus_rescan, pci_rescan_method), 185 186 /* PCI interface */ 187 DEVMETHOD(pci_read_config, pci_read_config_method), 188 DEVMETHOD(pci_write_config, pci_write_config_method), 189 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 190 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 191 DEVMETHOD(pci_enable_io, pci_enable_io_method), 192 DEVMETHOD(pci_disable_io, pci_disable_io_method), 193 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 194 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 195 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 196 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 197 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 198 DEVMETHOD(pci_find_cap, pci_find_cap_method), 199 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 200 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 201 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 202 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 203 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 204 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 205 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 206 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 207 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 208 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 209 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 210 DEVMETHOD(pci_release_msi, pci_release_msi_method), 211 DEVMETHOD(pci_msi_count, pci_msi_count_method), 212 DEVMETHOD(pci_msix_count, pci_msix_count_method), 213 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 214 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 215 DEVMETHOD(pci_get_id, pci_get_id_method), 216 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 217 DEVMETHOD(pci_child_added, pci_child_added_method), 218 #ifdef PCI_IOV 219 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 220 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 221 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 222 #endif 223 224 DEVMETHOD_END 225 }; 226 227 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 228 229 static devclass_t pci_devclass; 230 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL, 231 BUS_PASS_BUS); 232 MODULE_VERSION(pci, 1); 233 234 static char *pci_vendordata; 235 static size_t pci_vendordata_size; 236 237 struct pci_quirk { 238 uint32_t devid; /* Vendor/device of the card */ 239 int type; 240 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 241 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 242 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 243 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 244 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 245 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 246 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 247 int arg1; 248 int arg2; 249 }; 250 251 static const struct pci_quirk pci_quirks[] = { 252 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 253 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 254 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 255 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 256 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 257 258 /* 259 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 260 * or the CMIC-SL (AKA ServerWorks GC_LE). 261 */ 262 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 263 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 264 265 /* 266 * MSI doesn't work on earlier Intel chipsets including 267 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 268 */ 269 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 273 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 274 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 275 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 276 277 /* 278 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 279 * bridge. 280 */ 281 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 282 283 /* 284 * Some virtualization environments emulate an older chipset 285 * but support MSI just fine. QEMU uses the Intel 82440. 286 */ 287 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 288 289 /* 290 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 291 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 292 * It prevents us from attaching hpet(4) when the bit is unset. 293 * Note this quirk only affects SB600 revision A13 and earlier. 294 * For SB600 A21 and later, firmware must set the bit to hide it. 295 * For SB700 and later, it is unused and hardcoded to zero. 296 */ 297 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 298 299 /* 300 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 301 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 302 * of the command register is set. 303 */ 304 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 305 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 306 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 307 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 308 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 309 310 /* 311 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 312 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 313 */ 314 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 315 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 316 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 317 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 318 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 319 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 320 321 /* 322 * HPE Gen 10 VGA has a memory range that can't be allocated in the 323 * expected place. 324 */ 325 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 326 { 0 } 327 }; 328 329 /* map register information */ 330 #define PCI_MAPMEM 0x01 /* memory map */ 331 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 332 #define PCI_MAPPORT 0x04 /* port map */ 333 334 struct devlist pci_devq; 335 uint32_t pci_generation; 336 uint32_t pci_numdevs = 0; 337 static int pcie_chipset, pcix_chipset; 338 339 /* sysctl vars */ 340 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 341 "PCI bus tuning parameters"); 342 343 static int pci_enable_io_modes = 1; 344 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 345 &pci_enable_io_modes, 1, 346 "Enable I/O and memory bits in the config register. Some BIOSes do not" 347 " enable these bits correctly. We'd like to do this all the time, but" 348 " there are some peripherals that this causes problems with."); 349 350 static int pci_do_realloc_bars = 1; 351 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 352 &pci_do_realloc_bars, 0, 353 "Attempt to allocate a new range for any BARs whose original " 354 "firmware-assigned ranges fail to allocate during the initial device scan."); 355 356 static int pci_do_power_nodriver = 0; 357 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 358 &pci_do_power_nodriver, 0, 359 "Place a function into D3 state when no driver attaches to it. 0 means" 360 " disable. 1 means conservatively place devices into D3 state. 2 means" 361 " aggressively place devices into D3 state. 3 means put absolutely" 362 " everything in D3 state."); 363 364 int pci_do_power_resume = 1; 365 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 366 &pci_do_power_resume, 1, 367 "Transition from D3 -> D0 on resume."); 368 369 int pci_do_power_suspend = 1; 370 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 371 &pci_do_power_suspend, 1, 372 "Transition from D0 -> D3 on suspend."); 373 374 static int pci_do_msi = 1; 375 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 376 "Enable support for MSI interrupts"); 377 378 static int pci_do_msix = 1; 379 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 380 "Enable support for MSI-X interrupts"); 381 382 static int pci_msix_rewrite_table = 0; 383 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 384 &pci_msix_rewrite_table, 0, 385 "Rewrite entire MSI-X table when updating MSI-X entries"); 386 387 static int pci_honor_msi_blacklist = 1; 388 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 389 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 390 391 #if defined(__i386__) || defined(__amd64__) 392 static int pci_usb_takeover = 1; 393 #else 394 static int pci_usb_takeover = 0; 395 #endif 396 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 397 &pci_usb_takeover, 1, 398 "Enable early takeover of USB controllers. Disable this if you depend on" 399 " BIOS emulation of USB devices, that is you use USB devices (like" 400 " keyboard or mouse) but do not load USB drivers"); 401 402 static int pci_clear_bars; 403 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 404 "Ignore firmware-assigned resources for BARs."); 405 406 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 407 static int pci_clear_buses; 408 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 409 "Ignore firmware-assigned bus numbers."); 410 #endif 411 412 static int pci_enable_ari = 1; 413 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 414 0, "Enable support for PCIe Alternative RID Interpretation"); 415 416 int pci_enable_aspm = 1; 417 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 418 0, "Enable support for PCIe Active State Power Management"); 419 420 static int pci_clear_aer_on_attach = 0; 421 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 422 &pci_clear_aer_on_attach, 0, 423 "Clear port and device AER state on driver attach"); 424 425 static int 426 pci_has_quirk(uint32_t devid, int quirk) 427 { 428 const struct pci_quirk *q; 429 430 for (q = &pci_quirks[0]; q->devid; q++) { 431 if (q->devid == devid && q->type == quirk) 432 return (1); 433 } 434 return (0); 435 } 436 437 /* Find a device_t by bus/slot/function in domain 0 */ 438 439 device_t 440 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 441 { 442 443 return (pci_find_dbsf(0, bus, slot, func)); 444 } 445 446 /* Find a device_t by domain/bus/slot/function */ 447 448 device_t 449 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 450 { 451 struct pci_devinfo *dinfo = NULL; 452 453 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 454 if ((dinfo->cfg.domain == domain) && 455 (dinfo->cfg.bus == bus) && 456 (dinfo->cfg.slot == slot) && 457 (dinfo->cfg.func == func)) { 458 break; 459 } 460 } 461 462 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 463 } 464 465 /* Find a device_t by vendor/device ID */ 466 467 device_t 468 pci_find_device(uint16_t vendor, uint16_t device) 469 { 470 struct pci_devinfo *dinfo; 471 472 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 473 if ((dinfo->cfg.vendor == vendor) && 474 (dinfo->cfg.device == device)) { 475 return (dinfo->cfg.dev); 476 } 477 } 478 479 return (NULL); 480 } 481 482 device_t 483 pci_find_class(uint8_t class, uint8_t subclass) 484 { 485 struct pci_devinfo *dinfo; 486 487 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 488 if (dinfo->cfg.baseclass == class && 489 dinfo->cfg.subclass == subclass) { 490 return (dinfo->cfg.dev); 491 } 492 } 493 494 return (NULL); 495 } 496 497 device_t 498 pci_find_class_from(uint8_t class, uint8_t subclass, device_t from) 499 { 500 struct pci_devinfo *dinfo; 501 bool found = false; 502 503 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 504 if (from != NULL && found == false) { 505 if (from != dinfo->cfg.dev) 506 continue; 507 found = true; 508 continue; 509 } 510 if (dinfo->cfg.baseclass == class && 511 dinfo->cfg.subclass == subclass) { 512 return (dinfo->cfg.dev); 513 } 514 } 515 516 return (NULL); 517 } 518 519 static int 520 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 521 { 522 va_list ap; 523 int retval; 524 525 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 526 cfg->func); 527 va_start(ap, fmt); 528 retval += vprintf(fmt, ap); 529 va_end(ap); 530 return (retval); 531 } 532 533 /* return base address of memory or port map */ 534 535 static pci_addr_t 536 pci_mapbase(uint64_t mapreg) 537 { 538 539 if (PCI_BAR_MEM(mapreg)) 540 return (mapreg & PCIM_BAR_MEM_BASE); 541 else 542 return (mapreg & PCIM_BAR_IO_BASE); 543 } 544 545 /* return map type of memory or port map */ 546 547 static const char * 548 pci_maptype(uint64_t mapreg) 549 { 550 551 if (PCI_BAR_IO(mapreg)) 552 return ("I/O Port"); 553 if (mapreg & PCIM_BAR_MEM_PREFETCH) 554 return ("Prefetchable Memory"); 555 return ("Memory"); 556 } 557 558 /* return log2 of map size decoded for memory or port map */ 559 560 int 561 pci_mapsize(uint64_t testval) 562 { 563 int ln2size; 564 565 testval = pci_mapbase(testval); 566 ln2size = 0; 567 if (testval != 0) { 568 while ((testval & 1) == 0) 569 { 570 ln2size++; 571 testval >>= 1; 572 } 573 } 574 return (ln2size); 575 } 576 577 /* return base address of device ROM */ 578 579 static pci_addr_t 580 pci_rombase(uint64_t mapreg) 581 { 582 583 return (mapreg & PCIM_BIOS_ADDR_MASK); 584 } 585 586 /* return log2 of map size decided for device ROM */ 587 588 static int 589 pci_romsize(uint64_t testval) 590 { 591 int ln2size; 592 593 testval = pci_rombase(testval); 594 ln2size = 0; 595 if (testval != 0) { 596 while ((testval & 1) == 0) 597 { 598 ln2size++; 599 testval >>= 1; 600 } 601 } 602 return (ln2size); 603 } 604 605 /* return log2 of address range supported by map register */ 606 607 static int 608 pci_maprange(uint64_t mapreg) 609 { 610 int ln2range = 0; 611 612 if (PCI_BAR_IO(mapreg)) 613 ln2range = 32; 614 else 615 switch (mapreg & PCIM_BAR_MEM_TYPE) { 616 case PCIM_BAR_MEM_32: 617 ln2range = 32; 618 break; 619 case PCIM_BAR_MEM_1MB: 620 ln2range = 20; 621 break; 622 case PCIM_BAR_MEM_64: 623 ln2range = 64; 624 break; 625 } 626 return (ln2range); 627 } 628 629 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 630 631 static void 632 pci_fixancient(pcicfgregs *cfg) 633 { 634 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 635 return; 636 637 /* PCI to PCI bridges use header type 1 */ 638 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 639 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 640 } 641 642 /* extract header type specific config data */ 643 644 static void 645 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 646 { 647 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 648 switch (cfg->hdrtype & PCIM_HDRTYPE) { 649 case PCIM_HDRTYPE_NORMAL: 650 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 651 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 652 cfg->mingnt = REG(PCIR_MINGNT, 1); 653 cfg->maxlat = REG(PCIR_MAXLAT, 1); 654 cfg->nummaps = PCI_MAXMAPS_0; 655 break; 656 case PCIM_HDRTYPE_BRIDGE: 657 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 658 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 659 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 660 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 661 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 662 cfg->nummaps = PCI_MAXMAPS_1; 663 break; 664 case PCIM_HDRTYPE_CARDBUS: 665 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 666 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 667 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 668 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 669 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 670 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 671 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 672 cfg->nummaps = PCI_MAXMAPS_2; 673 break; 674 } 675 #undef REG 676 } 677 678 /* read configuration header into pcicfgregs structure */ 679 struct pci_devinfo * 680 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 681 { 682 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 683 uint16_t vid, did; 684 685 vid = REG(PCIR_VENDOR, 2); 686 if (vid == PCIV_INVALID) 687 return (NULL); 688 689 did = REG(PCIR_DEVICE, 2); 690 691 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 692 } 693 694 struct pci_devinfo * 695 pci_alloc_devinfo_method(device_t dev) 696 { 697 698 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 699 M_WAITOK | M_ZERO)); 700 } 701 702 static struct pci_devinfo * 703 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 704 uint16_t vid, uint16_t did) 705 { 706 struct pci_devinfo *devlist_entry; 707 pcicfgregs *cfg; 708 709 devlist_entry = PCI_ALLOC_DEVINFO(bus); 710 711 cfg = &devlist_entry->cfg; 712 713 cfg->domain = d; 714 cfg->bus = b; 715 cfg->slot = s; 716 cfg->func = f; 717 cfg->vendor = vid; 718 cfg->device = did; 719 cfg->cmdreg = REG(PCIR_COMMAND, 2); 720 cfg->statreg = REG(PCIR_STATUS, 2); 721 cfg->baseclass = REG(PCIR_CLASS, 1); 722 cfg->subclass = REG(PCIR_SUBCLASS, 1); 723 cfg->progif = REG(PCIR_PROGIF, 1); 724 cfg->revid = REG(PCIR_REVID, 1); 725 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 726 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 727 cfg->lattimer = REG(PCIR_LATTIMER, 1); 728 cfg->intpin = REG(PCIR_INTPIN, 1); 729 cfg->intline = REG(PCIR_INTLINE, 1); 730 731 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 732 cfg->hdrtype &= ~PCIM_MFDEV; 733 STAILQ_INIT(&cfg->maps); 734 735 cfg->iov = NULL; 736 737 pci_fixancient(cfg); 738 pci_hdrtypedata(pcib, b, s, f, cfg); 739 740 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 741 pci_read_cap(pcib, cfg); 742 743 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 744 745 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 746 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 747 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 748 devlist_entry->conf.pc_sel.pc_func = cfg->func; 749 devlist_entry->conf.pc_hdr = cfg->hdrtype; 750 751 devlist_entry->conf.pc_subvendor = cfg->subvendor; 752 devlist_entry->conf.pc_subdevice = cfg->subdevice; 753 devlist_entry->conf.pc_vendor = cfg->vendor; 754 devlist_entry->conf.pc_device = cfg->device; 755 756 devlist_entry->conf.pc_class = cfg->baseclass; 757 devlist_entry->conf.pc_subclass = cfg->subclass; 758 devlist_entry->conf.pc_progif = cfg->progif; 759 devlist_entry->conf.pc_revid = cfg->revid; 760 761 pci_numdevs++; 762 pci_generation++; 763 764 return (devlist_entry); 765 } 766 #undef REG 767 768 static void 769 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 770 { 771 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 772 cfg->ea.ea_location + (n), w) 773 int num_ent; 774 int ptr; 775 int a, b; 776 uint32_t val; 777 int ent_size; 778 uint32_t dw[4]; 779 uint64_t base, max_offset; 780 struct pci_ea_entry *eae; 781 782 if (cfg->ea.ea_location == 0) 783 return; 784 785 STAILQ_INIT(&cfg->ea.ea_entries); 786 787 /* Determine the number of entries */ 788 num_ent = REG(PCIR_EA_NUM_ENT, 2); 789 num_ent &= PCIM_EA_NUM_ENT_MASK; 790 791 /* Find the first entry to care of */ 792 ptr = PCIR_EA_FIRST_ENT; 793 794 /* Skip DWORD 2 for type 1 functions */ 795 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 796 ptr += 4; 797 798 for (a = 0; a < num_ent; a++) { 799 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 800 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 801 802 /* Read a number of dwords in the entry */ 803 val = REG(ptr, 4); 804 ptr += 4; 805 ent_size = (val & PCIM_EA_ES); 806 807 for (b = 0; b < ent_size; b++) { 808 dw[b] = REG(ptr, 4); 809 ptr += 4; 810 } 811 812 eae->eae_flags = val; 813 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 814 815 base = dw[0] & PCIM_EA_FIELD_MASK; 816 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 817 b = 2; 818 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 819 base |= (uint64_t)dw[b] << 32UL; 820 b++; 821 } 822 if (((dw[1] & PCIM_EA_IS_64) != 0) 823 && (b < ent_size)) { 824 max_offset |= (uint64_t)dw[b] << 32UL; 825 b++; 826 } 827 828 eae->eae_base = base; 829 eae->eae_max_offset = max_offset; 830 831 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 832 833 if (bootverbose) { 834 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 835 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 836 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 837 } 838 } 839 } 840 #undef REG 841 842 static void 843 pci_read_cap(device_t pcib, pcicfgregs *cfg) 844 { 845 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 846 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 847 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 848 uint64_t addr; 849 #endif 850 uint32_t val; 851 int ptr, nextptr, ptrptr; 852 853 switch (cfg->hdrtype & PCIM_HDRTYPE) { 854 case PCIM_HDRTYPE_NORMAL: 855 case PCIM_HDRTYPE_BRIDGE: 856 ptrptr = PCIR_CAP_PTR; 857 break; 858 case PCIM_HDRTYPE_CARDBUS: 859 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 860 break; 861 default: 862 return; /* no extended capabilities support */ 863 } 864 nextptr = REG(ptrptr, 1); /* sanity check? */ 865 866 /* 867 * Read capability entries. 868 */ 869 while (nextptr != 0) { 870 /* Sanity check */ 871 if (nextptr > 255) { 872 printf("illegal PCI extended capability offset %d\n", 873 nextptr); 874 return; 875 } 876 /* Find the next entry */ 877 ptr = nextptr; 878 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 879 880 /* Process this entry */ 881 switch (REG(ptr + PCICAP_ID, 1)) { 882 case PCIY_PMG: /* PCI power management */ 883 if (cfg->pp.pp_cap == 0) { 884 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 885 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 886 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 887 if ((nextptr - ptr) > PCIR_POWER_DATA) 888 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 889 } 890 break; 891 case PCIY_HT: /* HyperTransport */ 892 /* Determine HT-specific capability type. */ 893 val = REG(ptr + PCIR_HT_COMMAND, 2); 894 895 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 896 cfg->ht.ht_slave = ptr; 897 898 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 899 switch (val & PCIM_HTCMD_CAP_MASK) { 900 case PCIM_HTCAP_MSI_MAPPING: 901 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 902 /* Sanity check the mapping window. */ 903 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 904 4); 905 addr <<= 32; 906 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 907 4); 908 if (addr != MSI_INTEL_ADDR_BASE) 909 device_printf(pcib, 910 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 911 cfg->domain, cfg->bus, 912 cfg->slot, cfg->func, 913 (long long)addr); 914 } else 915 addr = MSI_INTEL_ADDR_BASE; 916 917 cfg->ht.ht_msimap = ptr; 918 cfg->ht.ht_msictrl = val; 919 cfg->ht.ht_msiaddr = addr; 920 break; 921 } 922 #endif 923 break; 924 case PCIY_MSI: /* PCI MSI */ 925 cfg->msi.msi_location = ptr; 926 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 927 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 928 PCIM_MSICTRL_MMC_MASK)>>1); 929 break; 930 case PCIY_MSIX: /* PCI MSI-X */ 931 cfg->msix.msix_location = ptr; 932 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 933 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 934 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 935 val = REG(ptr + PCIR_MSIX_TABLE, 4); 936 cfg->msix.msix_table_bar = PCIR_BAR(val & 937 PCIM_MSIX_BIR_MASK); 938 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 939 val = REG(ptr + PCIR_MSIX_PBA, 4); 940 cfg->msix.msix_pba_bar = PCIR_BAR(val & 941 PCIM_MSIX_BIR_MASK); 942 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 943 break; 944 case PCIY_VPD: /* PCI Vital Product Data */ 945 cfg->vpd.vpd_reg = ptr; 946 break; 947 case PCIY_SUBVENDOR: 948 /* Should always be true. */ 949 if ((cfg->hdrtype & PCIM_HDRTYPE) == 950 PCIM_HDRTYPE_BRIDGE) { 951 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 952 cfg->subvendor = val & 0xffff; 953 cfg->subdevice = val >> 16; 954 } 955 break; 956 case PCIY_PCIX: /* PCI-X */ 957 /* 958 * Assume we have a PCI-X chipset if we have 959 * at least one PCI-PCI bridge with a PCI-X 960 * capability. Note that some systems with 961 * PCI-express or HT chipsets might match on 962 * this check as well. 963 */ 964 if ((cfg->hdrtype & PCIM_HDRTYPE) == 965 PCIM_HDRTYPE_BRIDGE) 966 pcix_chipset = 1; 967 cfg->pcix.pcix_location = ptr; 968 break; 969 case PCIY_EXPRESS: /* PCI-express */ 970 /* 971 * Assume we have a PCI-express chipset if we have 972 * at least one PCI-express device. 973 */ 974 pcie_chipset = 1; 975 cfg->pcie.pcie_location = ptr; 976 val = REG(ptr + PCIER_FLAGS, 2); 977 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 978 break; 979 case PCIY_EA: /* Enhanced Allocation */ 980 cfg->ea.ea_location = ptr; 981 pci_ea_fill_info(pcib, cfg); 982 break; 983 default: 984 break; 985 } 986 } 987 988 #if defined(__powerpc__) 989 /* 990 * Enable the MSI mapping window for all HyperTransport 991 * slaves. PCI-PCI bridges have their windows enabled via 992 * PCIB_MAP_MSI(). 993 */ 994 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 995 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 996 device_printf(pcib, 997 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 998 cfg->domain, cfg->bus, cfg->slot, cfg->func); 999 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1000 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 1001 2); 1002 } 1003 #endif 1004 /* REG and WREG use carry through to next functions */ 1005 } 1006 1007 /* 1008 * PCI Vital Product Data 1009 */ 1010 1011 #define PCI_VPD_TIMEOUT 1000000 1012 1013 static int 1014 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 1015 { 1016 int count = PCI_VPD_TIMEOUT; 1017 1018 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1019 1020 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 1021 1022 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 1023 if (--count < 0) 1024 return (ENXIO); 1025 DELAY(1); /* limit looping */ 1026 } 1027 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1028 1029 return (0); 1030 } 1031 1032 #if 0 1033 static int 1034 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1035 { 1036 int count = PCI_VPD_TIMEOUT; 1037 1038 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1039 1040 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1041 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1042 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1043 if (--count < 0) 1044 return (ENXIO); 1045 DELAY(1); /* limit looping */ 1046 } 1047 1048 return (0); 1049 } 1050 #endif 1051 1052 #undef PCI_VPD_TIMEOUT 1053 1054 struct vpd_readstate { 1055 device_t pcib; 1056 pcicfgregs *cfg; 1057 uint32_t val; 1058 int bytesinval; 1059 int off; 1060 uint8_t cksum; 1061 }; 1062 1063 static int 1064 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1065 { 1066 uint32_t reg; 1067 uint8_t byte; 1068 1069 if (vrs->bytesinval == 0) { 1070 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1071 return (ENXIO); 1072 vrs->val = le32toh(reg); 1073 vrs->off += 4; 1074 byte = vrs->val & 0xff; 1075 vrs->bytesinval = 3; 1076 } else { 1077 vrs->val = vrs->val >> 8; 1078 byte = vrs->val & 0xff; 1079 vrs->bytesinval--; 1080 } 1081 1082 vrs->cksum += byte; 1083 *data = byte; 1084 return (0); 1085 } 1086 1087 static void 1088 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1089 { 1090 struct vpd_readstate vrs; 1091 int state; 1092 int name; 1093 int remain; 1094 int i; 1095 int alloc, off; /* alloc/off for RO/W arrays */ 1096 int cksumvalid; 1097 int dflen; 1098 uint8_t byte; 1099 uint8_t byte2; 1100 1101 /* init vpd reader */ 1102 vrs.bytesinval = 0; 1103 vrs.off = 0; 1104 vrs.pcib = pcib; 1105 vrs.cfg = cfg; 1106 vrs.cksum = 0; 1107 1108 state = 0; 1109 name = remain = i = 0; /* shut up stupid gcc */ 1110 alloc = off = 0; /* shut up stupid gcc */ 1111 dflen = 0; /* shut up stupid gcc */ 1112 cksumvalid = -1; 1113 while (state >= 0) { 1114 if (vpd_nextbyte(&vrs, &byte)) { 1115 state = -2; 1116 break; 1117 } 1118 #if 0 1119 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 1120 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 1121 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 1122 #endif 1123 switch (state) { 1124 case 0: /* item name */ 1125 if (byte & 0x80) { 1126 if (vpd_nextbyte(&vrs, &byte2)) { 1127 state = -2; 1128 break; 1129 } 1130 remain = byte2; 1131 if (vpd_nextbyte(&vrs, &byte2)) { 1132 state = -2; 1133 break; 1134 } 1135 remain |= byte2 << 8; 1136 name = byte & 0x7f; 1137 } else { 1138 remain = byte & 0x7; 1139 name = (byte >> 3) & 0xf; 1140 } 1141 if (vrs.off + remain - vrs.bytesinval > 0x8000) { 1142 pci_printf(cfg, 1143 "VPD data overflow, remain %#x\n", remain); 1144 state = -1; 1145 break; 1146 } 1147 switch (name) { 1148 case 0x2: /* String */ 1149 cfg->vpd.vpd_ident = malloc(remain + 1, 1150 M_DEVBUF, M_WAITOK); 1151 i = 0; 1152 state = 1; 1153 break; 1154 case 0xf: /* End */ 1155 state = -1; 1156 break; 1157 case 0x10: /* VPD-R */ 1158 alloc = 8; 1159 off = 0; 1160 cfg->vpd.vpd_ros = malloc(alloc * 1161 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 1162 M_WAITOK | M_ZERO); 1163 state = 2; 1164 break; 1165 case 0x11: /* VPD-W */ 1166 alloc = 8; 1167 off = 0; 1168 cfg->vpd.vpd_w = malloc(alloc * 1169 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 1170 M_WAITOK | M_ZERO); 1171 state = 5; 1172 break; 1173 default: /* Invalid data, abort */ 1174 state = -1; 1175 break; 1176 } 1177 break; 1178 1179 case 1: /* Identifier String */ 1180 cfg->vpd.vpd_ident[i++] = byte; 1181 remain--; 1182 if (remain == 0) { 1183 cfg->vpd.vpd_ident[i] = '\0'; 1184 state = 0; 1185 } 1186 break; 1187 1188 case 2: /* VPD-R Keyword Header */ 1189 if (off == alloc) { 1190 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1191 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1192 M_DEVBUF, M_WAITOK | M_ZERO); 1193 } 1194 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1195 if (vpd_nextbyte(&vrs, &byte2)) { 1196 state = -2; 1197 break; 1198 } 1199 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1200 if (vpd_nextbyte(&vrs, &byte2)) { 1201 state = -2; 1202 break; 1203 } 1204 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1205 if (dflen == 0 && 1206 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1207 2) == 0) { 1208 /* 1209 * if this happens, we can't trust the rest 1210 * of the VPD. 1211 */ 1212 pci_printf(cfg, "bad keyword length: %d\n", 1213 dflen); 1214 cksumvalid = 0; 1215 state = -1; 1216 break; 1217 } else if (dflen == 0) { 1218 cfg->vpd.vpd_ros[off].value = malloc(1 * 1219 sizeof(*cfg->vpd.vpd_ros[off].value), 1220 M_DEVBUF, M_WAITOK); 1221 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1222 } else 1223 cfg->vpd.vpd_ros[off].value = malloc( 1224 (dflen + 1) * 1225 sizeof(*cfg->vpd.vpd_ros[off].value), 1226 M_DEVBUF, M_WAITOK); 1227 remain -= 3; 1228 i = 0; 1229 /* keep in sync w/ state 3's transistions */ 1230 if (dflen == 0 && remain == 0) 1231 state = 0; 1232 else if (dflen == 0) 1233 state = 2; 1234 else 1235 state = 3; 1236 break; 1237 1238 case 3: /* VPD-R Keyword Value */ 1239 cfg->vpd.vpd_ros[off].value[i++] = byte; 1240 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1241 "RV", 2) == 0 && cksumvalid == -1) { 1242 if (vrs.cksum == 0) 1243 cksumvalid = 1; 1244 else { 1245 if (bootverbose) 1246 pci_printf(cfg, 1247 "bad VPD cksum, remain %hhu\n", 1248 vrs.cksum); 1249 cksumvalid = 0; 1250 state = -1; 1251 break; 1252 } 1253 } 1254 dflen--; 1255 remain--; 1256 /* keep in sync w/ state 2's transistions */ 1257 if (dflen == 0) 1258 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1259 if (dflen == 0 && remain == 0) { 1260 cfg->vpd.vpd_rocnt = off; 1261 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1262 off * sizeof(*cfg->vpd.vpd_ros), 1263 M_DEVBUF, M_WAITOK | M_ZERO); 1264 state = 0; 1265 } else if (dflen == 0) 1266 state = 2; 1267 break; 1268 1269 case 4: 1270 remain--; 1271 if (remain == 0) 1272 state = 0; 1273 break; 1274 1275 case 5: /* VPD-W Keyword Header */ 1276 if (off == alloc) { 1277 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1278 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1279 M_DEVBUF, M_WAITOK | M_ZERO); 1280 } 1281 cfg->vpd.vpd_w[off].keyword[0] = byte; 1282 if (vpd_nextbyte(&vrs, &byte2)) { 1283 state = -2; 1284 break; 1285 } 1286 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1287 if (vpd_nextbyte(&vrs, &byte2)) { 1288 state = -2; 1289 break; 1290 } 1291 cfg->vpd.vpd_w[off].len = dflen = byte2; 1292 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1293 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1294 sizeof(*cfg->vpd.vpd_w[off].value), 1295 M_DEVBUF, M_WAITOK); 1296 remain -= 3; 1297 i = 0; 1298 /* keep in sync w/ state 6's transistions */ 1299 if (dflen == 0 && remain == 0) 1300 state = 0; 1301 else if (dflen == 0) 1302 state = 5; 1303 else 1304 state = 6; 1305 break; 1306 1307 case 6: /* VPD-W Keyword Value */ 1308 cfg->vpd.vpd_w[off].value[i++] = byte; 1309 dflen--; 1310 remain--; 1311 /* keep in sync w/ state 5's transistions */ 1312 if (dflen == 0) 1313 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1314 if (dflen == 0 && remain == 0) { 1315 cfg->vpd.vpd_wcnt = off; 1316 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1317 off * sizeof(*cfg->vpd.vpd_w), 1318 M_DEVBUF, M_WAITOK | M_ZERO); 1319 state = 0; 1320 } else if (dflen == 0) 1321 state = 5; 1322 break; 1323 1324 default: 1325 pci_printf(cfg, "invalid state: %d\n", state); 1326 state = -1; 1327 break; 1328 } 1329 } 1330 1331 if (cksumvalid == 0 || state < -1) { 1332 /* read-only data bad, clean up */ 1333 if (cfg->vpd.vpd_ros != NULL) { 1334 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1335 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1336 free(cfg->vpd.vpd_ros, M_DEVBUF); 1337 cfg->vpd.vpd_ros = NULL; 1338 } 1339 } 1340 if (state < -1) { 1341 /* I/O error, clean up */ 1342 pci_printf(cfg, "failed to read VPD data.\n"); 1343 if (cfg->vpd.vpd_ident != NULL) { 1344 free(cfg->vpd.vpd_ident, M_DEVBUF); 1345 cfg->vpd.vpd_ident = NULL; 1346 } 1347 if (cfg->vpd.vpd_w != NULL) { 1348 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1349 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1350 free(cfg->vpd.vpd_w, M_DEVBUF); 1351 cfg->vpd.vpd_w = NULL; 1352 } 1353 } 1354 cfg->vpd.vpd_cached = 1; 1355 #undef REG 1356 #undef WREG 1357 } 1358 1359 int 1360 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1361 { 1362 struct pci_devinfo *dinfo = device_get_ivars(child); 1363 pcicfgregs *cfg = &dinfo->cfg; 1364 1365 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1366 pci_read_vpd(device_get_parent(dev), cfg); 1367 1368 *identptr = cfg->vpd.vpd_ident; 1369 1370 if (*identptr == NULL) 1371 return (ENXIO); 1372 1373 return (0); 1374 } 1375 1376 int 1377 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1378 const char **vptr) 1379 { 1380 struct pci_devinfo *dinfo = device_get_ivars(child); 1381 pcicfgregs *cfg = &dinfo->cfg; 1382 int i; 1383 1384 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1385 pci_read_vpd(device_get_parent(dev), cfg); 1386 1387 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1388 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1389 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1390 *vptr = cfg->vpd.vpd_ros[i].value; 1391 return (0); 1392 } 1393 1394 *vptr = NULL; 1395 return (ENXIO); 1396 } 1397 1398 struct pcicfg_vpd * 1399 pci_fetch_vpd_list(device_t dev) 1400 { 1401 struct pci_devinfo *dinfo = device_get_ivars(dev); 1402 pcicfgregs *cfg = &dinfo->cfg; 1403 1404 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1405 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1406 return (&cfg->vpd); 1407 } 1408 1409 /* 1410 * Find the requested HyperTransport capability and return the offset 1411 * in configuration space via the pointer provided. The function 1412 * returns 0 on success and an error code otherwise. 1413 */ 1414 int 1415 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1416 { 1417 int ptr, error; 1418 uint16_t val; 1419 1420 error = pci_find_cap(child, PCIY_HT, &ptr); 1421 if (error) 1422 return (error); 1423 1424 /* 1425 * Traverse the capabilities list checking each HT capability 1426 * to see if it matches the requested HT capability. 1427 */ 1428 for (;;) { 1429 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1430 if (capability == PCIM_HTCAP_SLAVE || 1431 capability == PCIM_HTCAP_HOST) 1432 val &= 0xe000; 1433 else 1434 val &= PCIM_HTCMD_CAP_MASK; 1435 if (val == capability) { 1436 if (capreg != NULL) 1437 *capreg = ptr; 1438 return (0); 1439 } 1440 1441 /* Skip to the next HT capability. */ 1442 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1443 break; 1444 } 1445 1446 return (ENOENT); 1447 } 1448 1449 /* 1450 * Find the next requested HyperTransport capability after start and return 1451 * the offset in configuration space via the pointer provided. The function 1452 * returns 0 on success and an error code otherwise. 1453 */ 1454 int 1455 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1456 int start, int *capreg) 1457 { 1458 int ptr; 1459 uint16_t val; 1460 1461 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1462 ("start capability is not HyperTransport capability")); 1463 ptr = start; 1464 1465 /* 1466 * Traverse the capabilities list checking each HT capability 1467 * to see if it matches the requested HT capability. 1468 */ 1469 for (;;) { 1470 /* Skip to the next HT capability. */ 1471 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1472 break; 1473 1474 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1475 if (capability == PCIM_HTCAP_SLAVE || 1476 capability == PCIM_HTCAP_HOST) 1477 val &= 0xe000; 1478 else 1479 val &= PCIM_HTCMD_CAP_MASK; 1480 if (val == capability) { 1481 if (capreg != NULL) 1482 *capreg = ptr; 1483 return (0); 1484 } 1485 } 1486 1487 return (ENOENT); 1488 } 1489 1490 /* 1491 * Find the requested capability and return the offset in 1492 * configuration space via the pointer provided. The function returns 1493 * 0 on success and an error code otherwise. 1494 */ 1495 int 1496 pci_find_cap_method(device_t dev, device_t child, int capability, 1497 int *capreg) 1498 { 1499 struct pci_devinfo *dinfo = device_get_ivars(child); 1500 pcicfgregs *cfg = &dinfo->cfg; 1501 uint32_t status; 1502 uint8_t ptr; 1503 1504 /* 1505 * Check the CAP_LIST bit of the PCI status register first. 1506 */ 1507 status = pci_read_config(child, PCIR_STATUS, 2); 1508 if (!(status & PCIM_STATUS_CAPPRESENT)) 1509 return (ENXIO); 1510 1511 /* 1512 * Determine the start pointer of the capabilities list. 1513 */ 1514 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1515 case PCIM_HDRTYPE_NORMAL: 1516 case PCIM_HDRTYPE_BRIDGE: 1517 ptr = PCIR_CAP_PTR; 1518 break; 1519 case PCIM_HDRTYPE_CARDBUS: 1520 ptr = PCIR_CAP_PTR_2; 1521 break; 1522 default: 1523 /* XXX: panic? */ 1524 return (ENXIO); /* no extended capabilities support */ 1525 } 1526 ptr = pci_read_config(child, ptr, 1); 1527 1528 /* 1529 * Traverse the capabilities list. 1530 */ 1531 while (ptr != 0) { 1532 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1533 if (capreg != NULL) 1534 *capreg = ptr; 1535 return (0); 1536 } 1537 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1538 } 1539 1540 return (ENOENT); 1541 } 1542 1543 /* 1544 * Find the next requested capability after start and return the offset in 1545 * configuration space via the pointer provided. The function returns 1546 * 0 on success and an error code otherwise. 1547 */ 1548 int 1549 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1550 int start, int *capreg) 1551 { 1552 uint8_t ptr; 1553 1554 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1555 ("start capability is not expected capability")); 1556 1557 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1558 while (ptr != 0) { 1559 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1560 if (capreg != NULL) 1561 *capreg = ptr; 1562 return (0); 1563 } 1564 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1565 } 1566 1567 return (ENOENT); 1568 } 1569 1570 /* 1571 * Find the requested extended capability and return the offset in 1572 * configuration space via the pointer provided. The function returns 1573 * 0 on success and an error code otherwise. 1574 */ 1575 int 1576 pci_find_extcap_method(device_t dev, device_t child, int capability, 1577 int *capreg) 1578 { 1579 struct pci_devinfo *dinfo = device_get_ivars(child); 1580 pcicfgregs *cfg = &dinfo->cfg; 1581 uint32_t ecap; 1582 uint16_t ptr; 1583 1584 /* Only supported for PCI-express devices. */ 1585 if (cfg->pcie.pcie_location == 0) 1586 return (ENXIO); 1587 1588 ptr = PCIR_EXTCAP; 1589 ecap = pci_read_config(child, ptr, 4); 1590 if (ecap == 0xffffffff || ecap == 0) 1591 return (ENOENT); 1592 for (;;) { 1593 if (PCI_EXTCAP_ID(ecap) == capability) { 1594 if (capreg != NULL) 1595 *capreg = ptr; 1596 return (0); 1597 } 1598 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1599 if (ptr == 0) 1600 break; 1601 ecap = pci_read_config(child, ptr, 4); 1602 } 1603 1604 return (ENOENT); 1605 } 1606 1607 /* 1608 * Find the next requested extended capability after start and return the 1609 * offset in configuration space via the pointer provided. The function 1610 * returns 0 on success and an error code otherwise. 1611 */ 1612 int 1613 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1614 int start, int *capreg) 1615 { 1616 struct pci_devinfo *dinfo = device_get_ivars(child); 1617 pcicfgregs *cfg = &dinfo->cfg; 1618 uint32_t ecap; 1619 uint16_t ptr; 1620 1621 /* Only supported for PCI-express devices. */ 1622 if (cfg->pcie.pcie_location == 0) 1623 return (ENXIO); 1624 1625 ecap = pci_read_config(child, start, 4); 1626 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1627 ("start extended capability is not expected capability")); 1628 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1629 while (ptr != 0) { 1630 ecap = pci_read_config(child, ptr, 4); 1631 if (PCI_EXTCAP_ID(ecap) == capability) { 1632 if (capreg != NULL) 1633 *capreg = ptr; 1634 return (0); 1635 } 1636 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1637 } 1638 1639 return (ENOENT); 1640 } 1641 1642 /* 1643 * Support for MSI-X message interrupts. 1644 */ 1645 static void 1646 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1647 { 1648 struct pci_devinfo *dinfo = device_get_ivars(dev); 1649 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1650 uint32_t offset; 1651 1652 KASSERT(msix->msix_table_len > index, ("bogus index")); 1653 offset = msix->msix_table_offset + index * 16; 1654 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1655 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1656 bus_write_4(msix->msix_table_res, offset + 8, data); 1657 } 1658 1659 void 1660 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1661 uint64_t address, uint32_t data) 1662 { 1663 1664 if (pci_msix_rewrite_table) { 1665 struct pci_devinfo *dinfo = device_get_ivars(child); 1666 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1667 1668 /* 1669 * Some VM hosts require MSIX to be disabled in the 1670 * control register before updating the MSIX table 1671 * entries are allowed. It is not enough to only 1672 * disable MSIX while updating a single entry. MSIX 1673 * must be disabled while updating all entries in the 1674 * table. 1675 */ 1676 pci_write_config(child, 1677 msix->msix_location + PCIR_MSIX_CTRL, 1678 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1679 pci_resume_msix(child); 1680 } else 1681 pci_write_msix_entry(child, index, address, data); 1682 1683 /* Enable MSI -> HT mapping. */ 1684 pci_ht_map_msi(child, address); 1685 } 1686 1687 void 1688 pci_mask_msix(device_t dev, u_int index) 1689 { 1690 struct pci_devinfo *dinfo = device_get_ivars(dev); 1691 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1692 uint32_t offset, val; 1693 1694 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1695 offset = msix->msix_table_offset + index * 16 + 12; 1696 val = bus_read_4(msix->msix_table_res, offset); 1697 val |= PCIM_MSIX_VCTRL_MASK; 1698 1699 /* 1700 * Some devices (e.g. Samsung PM961) do not support reads of this 1701 * register, so always write the new value. 1702 */ 1703 bus_write_4(msix->msix_table_res, offset, val); 1704 } 1705 1706 void 1707 pci_unmask_msix(device_t dev, u_int index) 1708 { 1709 struct pci_devinfo *dinfo = device_get_ivars(dev); 1710 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1711 uint32_t offset, val; 1712 1713 KASSERT(msix->msix_table_len > index, ("bogus index")); 1714 offset = msix->msix_table_offset + index * 16 + 12; 1715 val = bus_read_4(msix->msix_table_res, offset); 1716 val &= ~PCIM_MSIX_VCTRL_MASK; 1717 1718 /* 1719 * Some devices (e.g. Samsung PM961) do not support reads of this 1720 * register, so always write the new value. 1721 */ 1722 bus_write_4(msix->msix_table_res, offset, val); 1723 } 1724 1725 int 1726 pci_pending_msix(device_t dev, u_int index) 1727 { 1728 struct pci_devinfo *dinfo = device_get_ivars(dev); 1729 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1730 uint32_t offset, bit; 1731 1732 KASSERT(msix->msix_table_len > index, ("bogus index")); 1733 offset = msix->msix_pba_offset + (index / 32) * 4; 1734 bit = 1 << index % 32; 1735 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1736 } 1737 1738 /* 1739 * Restore MSI-X registers and table during resume. If MSI-X is 1740 * enabled then walk the virtual table to restore the actual MSI-X 1741 * table. 1742 */ 1743 static void 1744 pci_resume_msix(device_t dev) 1745 { 1746 struct pci_devinfo *dinfo = device_get_ivars(dev); 1747 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1748 struct msix_table_entry *mte; 1749 struct msix_vector *mv; 1750 int i; 1751 1752 if (msix->msix_alloc > 0) { 1753 /* First, mask all vectors. */ 1754 for (i = 0; i < msix->msix_msgnum; i++) 1755 pci_mask_msix(dev, i); 1756 1757 /* Second, program any messages with at least one handler. */ 1758 for (i = 0; i < msix->msix_table_len; i++) { 1759 mte = &msix->msix_table[i]; 1760 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1761 continue; 1762 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1763 pci_write_msix_entry(dev, i, mv->mv_address, 1764 mv->mv_data); 1765 pci_unmask_msix(dev, i); 1766 } 1767 } 1768 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1769 msix->msix_ctrl, 2); 1770 } 1771 1772 /* 1773 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1774 * returned in *count. After this function returns, each message will be 1775 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1776 */ 1777 int 1778 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1779 { 1780 struct pci_devinfo *dinfo = device_get_ivars(child); 1781 pcicfgregs *cfg = &dinfo->cfg; 1782 struct resource_list_entry *rle; 1783 int actual, error, i, irq, max; 1784 1785 /* Don't let count == 0 get us into trouble. */ 1786 if (*count == 0) 1787 return (EINVAL); 1788 1789 /* If rid 0 is allocated, then fail. */ 1790 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1791 if (rle != NULL && rle->res != NULL) 1792 return (ENXIO); 1793 1794 /* Already have allocated messages? */ 1795 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1796 return (ENXIO); 1797 1798 /* If MSI-X is blacklisted for this system, fail. */ 1799 if (pci_msix_blacklisted()) 1800 return (ENXIO); 1801 1802 /* MSI-X capability present? */ 1803 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1804 return (ENODEV); 1805 1806 /* Make sure the appropriate BARs are mapped. */ 1807 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1808 cfg->msix.msix_table_bar); 1809 if (rle == NULL || rle->res == NULL || 1810 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1811 return (ENXIO); 1812 cfg->msix.msix_table_res = rle->res; 1813 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1814 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1815 cfg->msix.msix_pba_bar); 1816 if (rle == NULL || rle->res == NULL || 1817 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1818 return (ENXIO); 1819 } 1820 cfg->msix.msix_pba_res = rle->res; 1821 1822 if (bootverbose) 1823 device_printf(child, 1824 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1825 *count, cfg->msix.msix_msgnum); 1826 max = min(*count, cfg->msix.msix_msgnum); 1827 for (i = 0; i < max; i++) { 1828 /* Allocate a message. */ 1829 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1830 if (error) { 1831 if (i == 0) 1832 return (error); 1833 break; 1834 } 1835 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1836 irq, 1); 1837 } 1838 actual = i; 1839 1840 if (bootverbose) { 1841 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1842 if (actual == 1) 1843 device_printf(child, "using IRQ %ju for MSI-X\n", 1844 rle->start); 1845 else { 1846 int run; 1847 1848 /* 1849 * Be fancy and try to print contiguous runs of 1850 * IRQ values as ranges. 'irq' is the previous IRQ. 1851 * 'run' is true if we are in a range. 1852 */ 1853 device_printf(child, "using IRQs %ju", rle->start); 1854 irq = rle->start; 1855 run = 0; 1856 for (i = 1; i < actual; i++) { 1857 rle = resource_list_find(&dinfo->resources, 1858 SYS_RES_IRQ, i + 1); 1859 1860 /* Still in a run? */ 1861 if (rle->start == irq + 1) { 1862 run = 1; 1863 irq++; 1864 continue; 1865 } 1866 1867 /* Finish previous range. */ 1868 if (run) { 1869 printf("-%d", irq); 1870 run = 0; 1871 } 1872 1873 /* Start new range. */ 1874 printf(",%ju", rle->start); 1875 irq = rle->start; 1876 } 1877 1878 /* Unfinished range? */ 1879 if (run) 1880 printf("-%d", irq); 1881 printf(" for MSI-X\n"); 1882 } 1883 } 1884 1885 /* Mask all vectors. */ 1886 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1887 pci_mask_msix(child, i); 1888 1889 /* Allocate and initialize vector data and virtual table. */ 1890 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1891 M_DEVBUF, M_WAITOK | M_ZERO); 1892 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1893 M_DEVBUF, M_WAITOK | M_ZERO); 1894 for (i = 0; i < actual; i++) { 1895 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1896 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1897 cfg->msix.msix_table[i].mte_vector = i + 1; 1898 } 1899 1900 /* Update control register to enable MSI-X. */ 1901 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1902 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1903 cfg->msix.msix_ctrl, 2); 1904 1905 /* Update counts of alloc'd messages. */ 1906 cfg->msix.msix_alloc = actual; 1907 cfg->msix.msix_table_len = actual; 1908 *count = actual; 1909 return (0); 1910 } 1911 1912 /* 1913 * By default, pci_alloc_msix() will assign the allocated IRQ 1914 * resources consecutively to the first N messages in the MSI-X table. 1915 * However, device drivers may want to use different layouts if they 1916 * either receive fewer messages than they asked for, or they wish to 1917 * populate the MSI-X table sparsely. This method allows the driver 1918 * to specify what layout it wants. It must be called after a 1919 * successful pci_alloc_msix() but before any of the associated 1920 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1921 * 1922 * The 'vectors' array contains 'count' message vectors. The array 1923 * maps directly to the MSI-X table in that index 0 in the array 1924 * specifies the vector for the first message in the MSI-X table, etc. 1925 * The vector value in each array index can either be 0 to indicate 1926 * that no vector should be assigned to a message slot, or it can be a 1927 * number from 1 to N (where N is the count returned from a 1928 * succcessful call to pci_alloc_msix()) to indicate which message 1929 * vector (IRQ) to be used for the corresponding message. 1930 * 1931 * On successful return, each message with a non-zero vector will have 1932 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1933 * 1. Additionally, if any of the IRQs allocated via the previous 1934 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1935 * will be freed back to the system automatically. 1936 * 1937 * For example, suppose a driver has a MSI-X table with 6 messages and 1938 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1939 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1940 * C. After the call to pci_alloc_msix(), the device will be setup to 1941 * have an MSI-X table of ABC--- (where - means no vector assigned). 1942 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1943 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1944 * be freed back to the system. This device will also have valid 1945 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1946 * 1947 * In any case, the SYS_RES_IRQ rid X will always map to the message 1948 * at MSI-X table index X - 1 and will only be valid if a vector is 1949 * assigned to that table entry. 1950 */ 1951 int 1952 pci_remap_msix_method(device_t dev, device_t child, int count, 1953 const u_int *vectors) 1954 { 1955 struct pci_devinfo *dinfo = device_get_ivars(child); 1956 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1957 struct resource_list_entry *rle; 1958 int i, irq, j, *used; 1959 1960 /* 1961 * Have to have at least one message in the table but the 1962 * table can't be bigger than the actual MSI-X table in the 1963 * device. 1964 */ 1965 if (count == 0 || count > msix->msix_msgnum) 1966 return (EINVAL); 1967 1968 /* Sanity check the vectors. */ 1969 for (i = 0; i < count; i++) 1970 if (vectors[i] > msix->msix_alloc) 1971 return (EINVAL); 1972 1973 /* 1974 * Make sure there aren't any holes in the vectors to be used. 1975 * It's a big pain to support it, and it doesn't really make 1976 * sense anyway. Also, at least one vector must be used. 1977 */ 1978 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1979 M_ZERO); 1980 for (i = 0; i < count; i++) 1981 if (vectors[i] != 0) 1982 used[vectors[i] - 1] = 1; 1983 for (i = 0; i < msix->msix_alloc - 1; i++) 1984 if (used[i] == 0 && used[i + 1] == 1) { 1985 free(used, M_DEVBUF); 1986 return (EINVAL); 1987 } 1988 if (used[0] != 1) { 1989 free(used, M_DEVBUF); 1990 return (EINVAL); 1991 } 1992 1993 /* Make sure none of the resources are allocated. */ 1994 for (i = 0; i < msix->msix_table_len; i++) { 1995 if (msix->msix_table[i].mte_vector == 0) 1996 continue; 1997 if (msix->msix_table[i].mte_handlers > 0) { 1998 free(used, M_DEVBUF); 1999 return (EBUSY); 2000 } 2001 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2002 KASSERT(rle != NULL, ("missing resource")); 2003 if (rle->res != NULL) { 2004 free(used, M_DEVBUF); 2005 return (EBUSY); 2006 } 2007 } 2008 2009 /* Free the existing resource list entries. */ 2010 for (i = 0; i < msix->msix_table_len; i++) { 2011 if (msix->msix_table[i].mte_vector == 0) 2012 continue; 2013 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2014 } 2015 2016 /* 2017 * Build the new virtual table keeping track of which vectors are 2018 * used. 2019 */ 2020 free(msix->msix_table, M_DEVBUF); 2021 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 2022 M_DEVBUF, M_WAITOK | M_ZERO); 2023 for (i = 0; i < count; i++) 2024 msix->msix_table[i].mte_vector = vectors[i]; 2025 msix->msix_table_len = count; 2026 2027 /* Free any unused IRQs and resize the vectors array if necessary. */ 2028 j = msix->msix_alloc - 1; 2029 if (used[j] == 0) { 2030 struct msix_vector *vec; 2031 2032 while (used[j] == 0) { 2033 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2034 msix->msix_vectors[j].mv_irq); 2035 j--; 2036 } 2037 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 2038 M_WAITOK); 2039 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2040 (j + 1)); 2041 free(msix->msix_vectors, M_DEVBUF); 2042 msix->msix_vectors = vec; 2043 msix->msix_alloc = j + 1; 2044 } 2045 free(used, M_DEVBUF); 2046 2047 /* Map the IRQs onto the rids. */ 2048 for (i = 0; i < count; i++) { 2049 if (vectors[i] == 0) 2050 continue; 2051 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2052 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2053 irq, 1); 2054 } 2055 2056 if (bootverbose) { 2057 device_printf(child, "Remapped MSI-X IRQs as: "); 2058 for (i = 0; i < count; i++) { 2059 if (i != 0) 2060 printf(", "); 2061 if (vectors[i] == 0) 2062 printf("---"); 2063 else 2064 printf("%d", 2065 msix->msix_vectors[vectors[i] - 1].mv_irq); 2066 } 2067 printf("\n"); 2068 } 2069 2070 return (0); 2071 } 2072 2073 static int 2074 pci_release_msix(device_t dev, device_t child) 2075 { 2076 struct pci_devinfo *dinfo = device_get_ivars(child); 2077 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2078 struct resource_list_entry *rle; 2079 int i; 2080 2081 /* Do we have any messages to release? */ 2082 if (msix->msix_alloc == 0) 2083 return (ENODEV); 2084 2085 /* Make sure none of the resources are allocated. */ 2086 for (i = 0; i < msix->msix_table_len; i++) { 2087 if (msix->msix_table[i].mte_vector == 0) 2088 continue; 2089 if (msix->msix_table[i].mte_handlers > 0) 2090 return (EBUSY); 2091 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2092 KASSERT(rle != NULL, ("missing resource")); 2093 if (rle->res != NULL) 2094 return (EBUSY); 2095 } 2096 2097 /* Update control register to disable MSI-X. */ 2098 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2099 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2100 msix->msix_ctrl, 2); 2101 2102 /* Free the resource list entries. */ 2103 for (i = 0; i < msix->msix_table_len; i++) { 2104 if (msix->msix_table[i].mte_vector == 0) 2105 continue; 2106 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2107 } 2108 free(msix->msix_table, M_DEVBUF); 2109 msix->msix_table_len = 0; 2110 2111 /* Release the IRQs. */ 2112 for (i = 0; i < msix->msix_alloc; i++) 2113 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2114 msix->msix_vectors[i].mv_irq); 2115 free(msix->msix_vectors, M_DEVBUF); 2116 msix->msix_alloc = 0; 2117 return (0); 2118 } 2119 2120 /* 2121 * Return the max supported MSI-X messages this device supports. 2122 * Basically, assuming the MD code can alloc messages, this function 2123 * should return the maximum value that pci_alloc_msix() can return. 2124 * Thus, it is subject to the tunables, etc. 2125 */ 2126 int 2127 pci_msix_count_method(device_t dev, device_t child) 2128 { 2129 struct pci_devinfo *dinfo = device_get_ivars(child); 2130 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2131 2132 if (pci_do_msix && msix->msix_location != 0) 2133 return (msix->msix_msgnum); 2134 return (0); 2135 } 2136 2137 int 2138 pci_msix_pba_bar_method(device_t dev, device_t child) 2139 { 2140 struct pci_devinfo *dinfo = device_get_ivars(child); 2141 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2142 2143 if (pci_do_msix && msix->msix_location != 0) 2144 return (msix->msix_pba_bar); 2145 return (-1); 2146 } 2147 2148 int 2149 pci_msix_table_bar_method(device_t dev, device_t child) 2150 { 2151 struct pci_devinfo *dinfo = device_get_ivars(child); 2152 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2153 2154 if (pci_do_msix && msix->msix_location != 0) 2155 return (msix->msix_table_bar); 2156 return (-1); 2157 } 2158 2159 /* 2160 * HyperTransport MSI mapping control 2161 */ 2162 void 2163 pci_ht_map_msi(device_t dev, uint64_t addr) 2164 { 2165 struct pci_devinfo *dinfo = device_get_ivars(dev); 2166 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2167 2168 if (!ht->ht_msimap) 2169 return; 2170 2171 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2172 ht->ht_msiaddr >> 20 == addr >> 20) { 2173 /* Enable MSI -> HT mapping. */ 2174 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2175 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2176 ht->ht_msictrl, 2); 2177 } 2178 2179 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2180 /* Disable MSI -> HT mapping. */ 2181 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2182 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2183 ht->ht_msictrl, 2); 2184 } 2185 } 2186 2187 int 2188 pci_get_relaxed_ordering_enabled(device_t dev) 2189 { 2190 struct pci_devinfo *dinfo = device_get_ivars(dev); 2191 int cap; 2192 uint16_t val; 2193 2194 cap = dinfo->cfg.pcie.pcie_location; 2195 if (cap == 0) 2196 return (0); 2197 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2198 val &= PCIEM_CTL_RELAXED_ORD_ENABLE; 2199 return (val != 0); 2200 } 2201 2202 int 2203 pci_get_max_payload(device_t dev) 2204 { 2205 struct pci_devinfo *dinfo = device_get_ivars(dev); 2206 int cap; 2207 uint16_t val; 2208 2209 cap = dinfo->cfg.pcie.pcie_location; 2210 if (cap == 0) 2211 return (0); 2212 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2213 val &= PCIEM_CTL_MAX_PAYLOAD; 2214 val >>= 5; 2215 return (1 << (val + 7)); 2216 } 2217 2218 int 2219 pci_get_max_read_req(device_t dev) 2220 { 2221 struct pci_devinfo *dinfo = device_get_ivars(dev); 2222 int cap; 2223 uint16_t val; 2224 2225 cap = dinfo->cfg.pcie.pcie_location; 2226 if (cap == 0) 2227 return (0); 2228 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2229 val &= PCIEM_CTL_MAX_READ_REQUEST; 2230 val >>= 12; 2231 return (1 << (val + 7)); 2232 } 2233 2234 int 2235 pci_set_max_read_req(device_t dev, int size) 2236 { 2237 struct pci_devinfo *dinfo = device_get_ivars(dev); 2238 int cap; 2239 uint16_t val; 2240 2241 cap = dinfo->cfg.pcie.pcie_location; 2242 if (cap == 0) 2243 return (0); 2244 if (size < 128) 2245 size = 128; 2246 if (size > 4096) 2247 size = 4096; 2248 size = (1 << (fls(size) - 1)); 2249 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2250 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2251 val |= (fls(size) - 8) << 12; 2252 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2253 return (size); 2254 } 2255 2256 uint32_t 2257 pcie_read_config(device_t dev, int reg, int width) 2258 { 2259 struct pci_devinfo *dinfo = device_get_ivars(dev); 2260 int cap; 2261 2262 cap = dinfo->cfg.pcie.pcie_location; 2263 if (cap == 0) { 2264 if (width == 2) 2265 return (0xffff); 2266 return (0xffffffff); 2267 } 2268 2269 return (pci_read_config(dev, cap + reg, width)); 2270 } 2271 2272 void 2273 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2274 { 2275 struct pci_devinfo *dinfo = device_get_ivars(dev); 2276 int cap; 2277 2278 cap = dinfo->cfg.pcie.pcie_location; 2279 if (cap == 0) 2280 return; 2281 pci_write_config(dev, cap + reg, value, width); 2282 } 2283 2284 /* 2285 * Adjusts a PCI-e capability register by clearing the bits in mask 2286 * and setting the bits in (value & mask). Bits not set in mask are 2287 * not adjusted. 2288 * 2289 * Returns the old value on success or all ones on failure. 2290 */ 2291 uint32_t 2292 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2293 int width) 2294 { 2295 struct pci_devinfo *dinfo = device_get_ivars(dev); 2296 uint32_t old, new; 2297 int cap; 2298 2299 cap = dinfo->cfg.pcie.pcie_location; 2300 if (cap == 0) { 2301 if (width == 2) 2302 return (0xffff); 2303 return (0xffffffff); 2304 } 2305 2306 old = pci_read_config(dev, cap + reg, width); 2307 new = old & ~mask; 2308 new |= (value & mask); 2309 pci_write_config(dev, cap + reg, new, width); 2310 return (old); 2311 } 2312 2313 /* 2314 * Support for MSI message signalled interrupts. 2315 */ 2316 void 2317 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2318 uint16_t data) 2319 { 2320 struct pci_devinfo *dinfo = device_get_ivars(child); 2321 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2322 2323 /* Write data and address values. */ 2324 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2325 address & 0xffffffff, 4); 2326 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2327 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2328 address >> 32, 4); 2329 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2330 data, 2); 2331 } else 2332 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2333 2); 2334 2335 /* Enable MSI in the control register. */ 2336 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2337 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2338 msi->msi_ctrl, 2); 2339 2340 /* Enable MSI -> HT mapping. */ 2341 pci_ht_map_msi(child, address); 2342 } 2343 2344 void 2345 pci_disable_msi_method(device_t dev, device_t child) 2346 { 2347 struct pci_devinfo *dinfo = device_get_ivars(child); 2348 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2349 2350 /* Disable MSI -> HT mapping. */ 2351 pci_ht_map_msi(child, 0); 2352 2353 /* Disable MSI in the control register. */ 2354 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2355 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2356 msi->msi_ctrl, 2); 2357 } 2358 2359 /* 2360 * Restore MSI registers during resume. If MSI is enabled then 2361 * restore the data and address registers in addition to the control 2362 * register. 2363 */ 2364 static void 2365 pci_resume_msi(device_t dev) 2366 { 2367 struct pci_devinfo *dinfo = device_get_ivars(dev); 2368 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2369 uint64_t address; 2370 uint16_t data; 2371 2372 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2373 address = msi->msi_addr; 2374 data = msi->msi_data; 2375 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2376 address & 0xffffffff, 4); 2377 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2378 pci_write_config(dev, msi->msi_location + 2379 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2380 pci_write_config(dev, msi->msi_location + 2381 PCIR_MSI_DATA_64BIT, data, 2); 2382 } else 2383 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2384 data, 2); 2385 } 2386 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2387 2); 2388 } 2389 2390 static int 2391 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2392 { 2393 struct pci_devinfo *dinfo = device_get_ivars(dev); 2394 pcicfgregs *cfg = &dinfo->cfg; 2395 struct resource_list_entry *rle; 2396 struct msix_table_entry *mte; 2397 struct msix_vector *mv; 2398 uint64_t addr; 2399 uint32_t data; 2400 int error, i, j; 2401 2402 /* 2403 * Handle MSI first. We try to find this IRQ among our list 2404 * of MSI IRQs. If we find it, we request updated address and 2405 * data registers and apply the results. 2406 */ 2407 if (cfg->msi.msi_alloc > 0) { 2408 /* If we don't have any active handlers, nothing to do. */ 2409 if (cfg->msi.msi_handlers == 0) 2410 return (0); 2411 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2412 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2413 i + 1); 2414 if (rle->start == irq) { 2415 error = PCIB_MAP_MSI(device_get_parent(bus), 2416 dev, irq, &addr, &data); 2417 if (error) 2418 return (error); 2419 pci_disable_msi(dev); 2420 dinfo->cfg.msi.msi_addr = addr; 2421 dinfo->cfg.msi.msi_data = data; 2422 pci_enable_msi(dev, addr, data); 2423 return (0); 2424 } 2425 } 2426 return (ENOENT); 2427 } 2428 2429 /* 2430 * For MSI-X, we check to see if we have this IRQ. If we do, 2431 * we request the updated mapping info. If that works, we go 2432 * through all the slots that use this IRQ and update them. 2433 */ 2434 if (cfg->msix.msix_alloc > 0) { 2435 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2436 mv = &cfg->msix.msix_vectors[i]; 2437 if (mv->mv_irq == irq) { 2438 error = PCIB_MAP_MSI(device_get_parent(bus), 2439 dev, irq, &addr, &data); 2440 if (error) 2441 return (error); 2442 mv->mv_address = addr; 2443 mv->mv_data = data; 2444 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2445 mte = &cfg->msix.msix_table[j]; 2446 if (mte->mte_vector != i + 1) 2447 continue; 2448 if (mte->mte_handlers == 0) 2449 continue; 2450 pci_mask_msix(dev, j); 2451 pci_enable_msix(dev, j, addr, data); 2452 pci_unmask_msix(dev, j); 2453 } 2454 } 2455 } 2456 return (ENOENT); 2457 } 2458 2459 return (ENOENT); 2460 } 2461 2462 /* 2463 * Returns true if the specified device is blacklisted because MSI 2464 * doesn't work. 2465 */ 2466 int 2467 pci_msi_device_blacklisted(device_t dev) 2468 { 2469 2470 if (!pci_honor_msi_blacklist) 2471 return (0); 2472 2473 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2474 } 2475 2476 /* 2477 * Determine if MSI is blacklisted globally on this system. Currently, 2478 * we just check for blacklisted chipsets as represented by the 2479 * host-PCI bridge at device 0:0:0. In the future, it may become 2480 * necessary to check other system attributes, such as the kenv values 2481 * that give the motherboard manufacturer and model number. 2482 */ 2483 static int 2484 pci_msi_blacklisted(void) 2485 { 2486 device_t dev; 2487 2488 if (!pci_honor_msi_blacklist) 2489 return (0); 2490 2491 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2492 if (!(pcie_chipset || pcix_chipset)) { 2493 if (vm_guest != VM_GUEST_NO) { 2494 /* 2495 * Whitelist older chipsets in virtual 2496 * machines known to support MSI. 2497 */ 2498 dev = pci_find_bsf(0, 0, 0); 2499 if (dev != NULL) 2500 return (!pci_has_quirk(pci_get_devid(dev), 2501 PCI_QUIRK_ENABLE_MSI_VM)); 2502 } 2503 return (1); 2504 } 2505 2506 dev = pci_find_bsf(0, 0, 0); 2507 if (dev != NULL) 2508 return (pci_msi_device_blacklisted(dev)); 2509 return (0); 2510 } 2511 2512 /* 2513 * Returns true if the specified device is blacklisted because MSI-X 2514 * doesn't work. Note that this assumes that if MSI doesn't work, 2515 * MSI-X doesn't either. 2516 */ 2517 int 2518 pci_msix_device_blacklisted(device_t dev) 2519 { 2520 2521 if (!pci_honor_msi_blacklist) 2522 return (0); 2523 2524 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2525 return (1); 2526 2527 return (pci_msi_device_blacklisted(dev)); 2528 } 2529 2530 /* 2531 * Determine if MSI-X is blacklisted globally on this system. If MSI 2532 * is blacklisted, assume that MSI-X is as well. Check for additional 2533 * chipsets where MSI works but MSI-X does not. 2534 */ 2535 static int 2536 pci_msix_blacklisted(void) 2537 { 2538 device_t dev; 2539 2540 if (!pci_honor_msi_blacklist) 2541 return (0); 2542 2543 dev = pci_find_bsf(0, 0, 0); 2544 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2545 PCI_QUIRK_DISABLE_MSIX)) 2546 return (1); 2547 2548 return (pci_msi_blacklisted()); 2549 } 2550 2551 /* 2552 * Attempt to allocate *count MSI messages. The actual number allocated is 2553 * returned in *count. After this function returns, each message will be 2554 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2555 */ 2556 int 2557 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2558 { 2559 struct pci_devinfo *dinfo = device_get_ivars(child); 2560 pcicfgregs *cfg = &dinfo->cfg; 2561 struct resource_list_entry *rle; 2562 int actual, error, i, irqs[32]; 2563 uint16_t ctrl; 2564 2565 /* Don't let count == 0 get us into trouble. */ 2566 if (*count == 0) 2567 return (EINVAL); 2568 2569 /* If rid 0 is allocated, then fail. */ 2570 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2571 if (rle != NULL && rle->res != NULL) 2572 return (ENXIO); 2573 2574 /* Already have allocated messages? */ 2575 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2576 return (ENXIO); 2577 2578 /* If MSI is blacklisted for this system, fail. */ 2579 if (pci_msi_blacklisted()) 2580 return (ENXIO); 2581 2582 /* MSI capability present? */ 2583 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2584 return (ENODEV); 2585 2586 if (bootverbose) 2587 device_printf(child, 2588 "attempting to allocate %d MSI vectors (%d supported)\n", 2589 *count, cfg->msi.msi_msgnum); 2590 2591 /* Don't ask for more than the device supports. */ 2592 actual = min(*count, cfg->msi.msi_msgnum); 2593 2594 /* Don't ask for more than 32 messages. */ 2595 actual = min(actual, 32); 2596 2597 /* MSI requires power of 2 number of messages. */ 2598 if (!powerof2(actual)) 2599 return (EINVAL); 2600 2601 for (;;) { 2602 /* Try to allocate N messages. */ 2603 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2604 actual, irqs); 2605 if (error == 0) 2606 break; 2607 if (actual == 1) 2608 return (error); 2609 2610 /* Try N / 2. */ 2611 actual >>= 1; 2612 } 2613 2614 /* 2615 * We now have N actual messages mapped onto SYS_RES_IRQ 2616 * resources in the irqs[] array, so add new resources 2617 * starting at rid 1. 2618 */ 2619 for (i = 0; i < actual; i++) 2620 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2621 irqs[i], irqs[i], 1); 2622 2623 if (bootverbose) { 2624 if (actual == 1) 2625 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2626 else { 2627 int run; 2628 2629 /* 2630 * Be fancy and try to print contiguous runs 2631 * of IRQ values as ranges. 'run' is true if 2632 * we are in a range. 2633 */ 2634 device_printf(child, "using IRQs %d", irqs[0]); 2635 run = 0; 2636 for (i = 1; i < actual; i++) { 2637 /* Still in a run? */ 2638 if (irqs[i] == irqs[i - 1] + 1) { 2639 run = 1; 2640 continue; 2641 } 2642 2643 /* Finish previous range. */ 2644 if (run) { 2645 printf("-%d", irqs[i - 1]); 2646 run = 0; 2647 } 2648 2649 /* Start new range. */ 2650 printf(",%d", irqs[i]); 2651 } 2652 2653 /* Unfinished range? */ 2654 if (run) 2655 printf("-%d", irqs[actual - 1]); 2656 printf(" for MSI\n"); 2657 } 2658 } 2659 2660 /* Update control register with actual count. */ 2661 ctrl = cfg->msi.msi_ctrl; 2662 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2663 ctrl |= (ffs(actual) - 1) << 4; 2664 cfg->msi.msi_ctrl = ctrl; 2665 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2666 2667 /* Update counts of alloc'd messages. */ 2668 cfg->msi.msi_alloc = actual; 2669 cfg->msi.msi_handlers = 0; 2670 *count = actual; 2671 return (0); 2672 } 2673 2674 /* Release the MSI messages associated with this device. */ 2675 int 2676 pci_release_msi_method(device_t dev, device_t child) 2677 { 2678 struct pci_devinfo *dinfo = device_get_ivars(child); 2679 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2680 struct resource_list_entry *rle; 2681 int error, i, irqs[32]; 2682 2683 /* Try MSI-X first. */ 2684 error = pci_release_msix(dev, child); 2685 if (error != ENODEV) 2686 return (error); 2687 2688 /* Do we have any messages to release? */ 2689 if (msi->msi_alloc == 0) 2690 return (ENODEV); 2691 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2692 2693 /* Make sure none of the resources are allocated. */ 2694 if (msi->msi_handlers > 0) 2695 return (EBUSY); 2696 for (i = 0; i < msi->msi_alloc; i++) { 2697 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2698 KASSERT(rle != NULL, ("missing MSI resource")); 2699 if (rle->res != NULL) 2700 return (EBUSY); 2701 irqs[i] = rle->start; 2702 } 2703 2704 /* Update control register with 0 count. */ 2705 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2706 ("%s: MSI still enabled", __func__)); 2707 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2708 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2709 msi->msi_ctrl, 2); 2710 2711 /* Release the messages. */ 2712 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2713 for (i = 0; i < msi->msi_alloc; i++) 2714 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2715 2716 /* Update alloc count. */ 2717 msi->msi_alloc = 0; 2718 msi->msi_addr = 0; 2719 msi->msi_data = 0; 2720 return (0); 2721 } 2722 2723 /* 2724 * Return the max supported MSI messages this device supports. 2725 * Basically, assuming the MD code can alloc messages, this function 2726 * should return the maximum value that pci_alloc_msi() can return. 2727 * Thus, it is subject to the tunables, etc. 2728 */ 2729 int 2730 pci_msi_count_method(device_t dev, device_t child) 2731 { 2732 struct pci_devinfo *dinfo = device_get_ivars(child); 2733 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2734 2735 if (pci_do_msi && msi->msi_location != 0) 2736 return (msi->msi_msgnum); 2737 return (0); 2738 } 2739 2740 /* free pcicfgregs structure and all depending data structures */ 2741 2742 int 2743 pci_freecfg(struct pci_devinfo *dinfo) 2744 { 2745 struct devlist *devlist_head; 2746 struct pci_map *pm, *next; 2747 int i; 2748 2749 devlist_head = &pci_devq; 2750 2751 if (dinfo->cfg.vpd.vpd_reg) { 2752 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2753 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2754 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2755 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2756 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2757 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2758 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2759 } 2760 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2761 free(pm, M_DEVBUF); 2762 } 2763 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2764 free(dinfo, M_DEVBUF); 2765 2766 /* increment the generation count */ 2767 pci_generation++; 2768 2769 /* we're losing one device */ 2770 pci_numdevs--; 2771 return (0); 2772 } 2773 2774 /* 2775 * PCI power manangement 2776 */ 2777 int 2778 pci_set_powerstate_method(device_t dev, device_t child, int state) 2779 { 2780 struct pci_devinfo *dinfo = device_get_ivars(child); 2781 pcicfgregs *cfg = &dinfo->cfg; 2782 uint16_t status; 2783 int oldstate, highest, delay; 2784 2785 if (cfg->pp.pp_cap == 0) 2786 return (EOPNOTSUPP); 2787 2788 /* 2789 * Optimize a no state change request away. While it would be OK to 2790 * write to the hardware in theory, some devices have shown odd 2791 * behavior when going from D3 -> D3. 2792 */ 2793 oldstate = pci_get_powerstate(child); 2794 if (oldstate == state) 2795 return (0); 2796 2797 /* 2798 * The PCI power management specification states that after a state 2799 * transition between PCI power states, system software must 2800 * guarantee a minimal delay before the function accesses the device. 2801 * Compute the worst case delay that we need to guarantee before we 2802 * access the device. Many devices will be responsive much more 2803 * quickly than this delay, but there are some that don't respond 2804 * instantly to state changes. Transitions to/from D3 state require 2805 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2806 * is done below with DELAY rather than a sleeper function because 2807 * this function can be called from contexts where we cannot sleep. 2808 */ 2809 highest = (oldstate > state) ? oldstate : state; 2810 if (highest == PCI_POWERSTATE_D3) 2811 delay = 10000; 2812 else if (highest == PCI_POWERSTATE_D2) 2813 delay = 200; 2814 else 2815 delay = 0; 2816 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2817 & ~PCIM_PSTAT_DMASK; 2818 switch (state) { 2819 case PCI_POWERSTATE_D0: 2820 status |= PCIM_PSTAT_D0; 2821 break; 2822 case PCI_POWERSTATE_D1: 2823 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2824 return (EOPNOTSUPP); 2825 status |= PCIM_PSTAT_D1; 2826 break; 2827 case PCI_POWERSTATE_D2: 2828 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2829 return (EOPNOTSUPP); 2830 status |= PCIM_PSTAT_D2; 2831 break; 2832 case PCI_POWERSTATE_D3: 2833 status |= PCIM_PSTAT_D3; 2834 break; 2835 default: 2836 return (EINVAL); 2837 } 2838 2839 if (bootverbose) 2840 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2841 state); 2842 2843 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2844 if (delay) 2845 DELAY(delay); 2846 return (0); 2847 } 2848 2849 int 2850 pci_get_powerstate_method(device_t dev, device_t child) 2851 { 2852 struct pci_devinfo *dinfo = device_get_ivars(child); 2853 pcicfgregs *cfg = &dinfo->cfg; 2854 uint16_t status; 2855 int result; 2856 2857 if (cfg->pp.pp_cap != 0) { 2858 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2859 switch (status & PCIM_PSTAT_DMASK) { 2860 case PCIM_PSTAT_D0: 2861 result = PCI_POWERSTATE_D0; 2862 break; 2863 case PCIM_PSTAT_D1: 2864 result = PCI_POWERSTATE_D1; 2865 break; 2866 case PCIM_PSTAT_D2: 2867 result = PCI_POWERSTATE_D2; 2868 break; 2869 case PCIM_PSTAT_D3: 2870 result = PCI_POWERSTATE_D3; 2871 break; 2872 default: 2873 result = PCI_POWERSTATE_UNKNOWN; 2874 break; 2875 } 2876 } else { 2877 /* No support, device is always at D0 */ 2878 result = PCI_POWERSTATE_D0; 2879 } 2880 return (result); 2881 } 2882 2883 /* 2884 * Some convenience functions for PCI device drivers. 2885 */ 2886 2887 static __inline void 2888 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2889 { 2890 uint16_t command; 2891 2892 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2893 command |= bit; 2894 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2895 } 2896 2897 static __inline void 2898 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2899 { 2900 uint16_t command; 2901 2902 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2903 command &= ~bit; 2904 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2905 } 2906 2907 int 2908 pci_enable_busmaster_method(device_t dev, device_t child) 2909 { 2910 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2911 return (0); 2912 } 2913 2914 int 2915 pci_disable_busmaster_method(device_t dev, device_t child) 2916 { 2917 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2918 return (0); 2919 } 2920 2921 int 2922 pci_enable_io_method(device_t dev, device_t child, int space) 2923 { 2924 uint16_t bit; 2925 2926 switch(space) { 2927 case SYS_RES_IOPORT: 2928 bit = PCIM_CMD_PORTEN; 2929 break; 2930 case SYS_RES_MEMORY: 2931 bit = PCIM_CMD_MEMEN; 2932 break; 2933 default: 2934 return (EINVAL); 2935 } 2936 pci_set_command_bit(dev, child, bit); 2937 return (0); 2938 } 2939 2940 int 2941 pci_disable_io_method(device_t dev, device_t child, int space) 2942 { 2943 uint16_t bit; 2944 2945 switch(space) { 2946 case SYS_RES_IOPORT: 2947 bit = PCIM_CMD_PORTEN; 2948 break; 2949 case SYS_RES_MEMORY: 2950 bit = PCIM_CMD_MEMEN; 2951 break; 2952 default: 2953 return (EINVAL); 2954 } 2955 pci_clear_command_bit(dev, child, bit); 2956 return (0); 2957 } 2958 2959 /* 2960 * New style pci driver. Parent device is either a pci-host-bridge or a 2961 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2962 */ 2963 2964 void 2965 pci_print_verbose(struct pci_devinfo *dinfo) 2966 { 2967 2968 if (bootverbose) { 2969 pcicfgregs *cfg = &dinfo->cfg; 2970 2971 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2972 cfg->vendor, cfg->device, cfg->revid); 2973 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2974 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2975 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2976 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2977 cfg->mfdev); 2978 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2979 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2980 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2981 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2982 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2983 if (cfg->intpin > 0) 2984 printf("\tintpin=%c, irq=%d\n", 2985 cfg->intpin +'a' -1, cfg->intline); 2986 if (cfg->pp.pp_cap) { 2987 uint16_t status; 2988 2989 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2990 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2991 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2992 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2993 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2994 status & PCIM_PSTAT_DMASK); 2995 } 2996 if (cfg->msi.msi_location) { 2997 int ctrl; 2998 2999 ctrl = cfg->msi.msi_ctrl; 3000 printf("\tMSI supports %d message%s%s%s\n", 3001 cfg->msi.msi_msgnum, 3002 (cfg->msi.msi_msgnum == 1) ? "" : "s", 3003 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 3004 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 3005 } 3006 if (cfg->msix.msix_location) { 3007 printf("\tMSI-X supports %d message%s ", 3008 cfg->msix.msix_msgnum, 3009 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 3010 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 3011 printf("in map 0x%x\n", 3012 cfg->msix.msix_table_bar); 3013 else 3014 printf("in maps 0x%x and 0x%x\n", 3015 cfg->msix.msix_table_bar, 3016 cfg->msix.msix_pba_bar); 3017 } 3018 } 3019 } 3020 3021 static int 3022 pci_porten(device_t dev) 3023 { 3024 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 3025 } 3026 3027 static int 3028 pci_memen(device_t dev) 3029 { 3030 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 3031 } 3032 3033 void 3034 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 3035 int *bar64) 3036 { 3037 struct pci_devinfo *dinfo; 3038 pci_addr_t map, testval; 3039 int ln2range; 3040 uint16_t cmd; 3041 3042 /* 3043 * The device ROM BAR is special. It is always a 32-bit 3044 * memory BAR. Bit 0 is special and should not be set when 3045 * sizing the BAR. 3046 */ 3047 dinfo = device_get_ivars(dev); 3048 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3049 map = pci_read_config(dev, reg, 4); 3050 pci_write_config(dev, reg, 0xfffffffe, 4); 3051 testval = pci_read_config(dev, reg, 4); 3052 pci_write_config(dev, reg, map, 4); 3053 *mapp = map; 3054 *testvalp = testval; 3055 if (bar64 != NULL) 3056 *bar64 = 0; 3057 return; 3058 } 3059 3060 map = pci_read_config(dev, reg, 4); 3061 ln2range = pci_maprange(map); 3062 if (ln2range == 64) 3063 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3064 3065 /* 3066 * Disable decoding via the command register before 3067 * determining the BAR's length since we will be placing it in 3068 * a weird state. 3069 */ 3070 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3071 pci_write_config(dev, PCIR_COMMAND, 3072 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3073 3074 /* 3075 * Determine the BAR's length by writing all 1's. The bottom 3076 * log_2(size) bits of the BAR will stick as 0 when we read 3077 * the value back. 3078 * 3079 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3080 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3081 * and combines the result into a 64-bit value." (section 6.2.5.1) 3082 * 3083 * Writes to both registers must be performed before attempting to 3084 * read back the size value. 3085 */ 3086 testval = 0; 3087 pci_write_config(dev, reg, 0xffffffff, 4); 3088 if (ln2range == 64) { 3089 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3090 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3091 } 3092 testval |= pci_read_config(dev, reg, 4); 3093 3094 /* 3095 * Restore the original value of the BAR. We may have reprogrammed 3096 * the BAR of the low-level console device and when booting verbose, 3097 * we need the console device addressable. 3098 */ 3099 pci_write_config(dev, reg, map, 4); 3100 if (ln2range == 64) 3101 pci_write_config(dev, reg + 4, map >> 32, 4); 3102 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3103 3104 *mapp = map; 3105 *testvalp = testval; 3106 if (bar64 != NULL) 3107 *bar64 = (ln2range == 64); 3108 } 3109 3110 static void 3111 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3112 { 3113 struct pci_devinfo *dinfo; 3114 int ln2range; 3115 3116 /* The device ROM BAR is always a 32-bit memory BAR. */ 3117 dinfo = device_get_ivars(dev); 3118 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3119 ln2range = 32; 3120 else 3121 ln2range = pci_maprange(pm->pm_value); 3122 pci_write_config(dev, pm->pm_reg, base, 4); 3123 if (ln2range == 64) 3124 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3125 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3126 if (ln2range == 64) 3127 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3128 pm->pm_reg + 4, 4) << 32; 3129 } 3130 3131 struct pci_map * 3132 pci_find_bar(device_t dev, int reg) 3133 { 3134 struct pci_devinfo *dinfo; 3135 struct pci_map *pm; 3136 3137 dinfo = device_get_ivars(dev); 3138 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3139 if (pm->pm_reg == reg) 3140 return (pm); 3141 } 3142 return (NULL); 3143 } 3144 3145 int 3146 pci_bar_enabled(device_t dev, struct pci_map *pm) 3147 { 3148 struct pci_devinfo *dinfo; 3149 uint16_t cmd; 3150 3151 dinfo = device_get_ivars(dev); 3152 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3153 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3154 return (0); 3155 #ifdef PCI_IOV 3156 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { 3157 struct pcicfg_iov *iov; 3158 3159 iov = dinfo->cfg.iov; 3160 cmd = pci_read_config(iov->iov_pf, 3161 iov->iov_pos + PCIR_SRIOV_CTL, 2); 3162 return ((cmd & PCIM_SRIOV_VF_MSE) != 0); 3163 } 3164 #endif 3165 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3166 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3167 return ((cmd & PCIM_CMD_MEMEN) != 0); 3168 else 3169 return ((cmd & PCIM_CMD_PORTEN) != 0); 3170 } 3171 3172 struct pci_map * 3173 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3174 { 3175 struct pci_devinfo *dinfo; 3176 struct pci_map *pm, *prev; 3177 3178 dinfo = device_get_ivars(dev); 3179 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3180 pm->pm_reg = reg; 3181 pm->pm_value = value; 3182 pm->pm_size = size; 3183 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3184 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3185 reg)); 3186 if (STAILQ_NEXT(prev, pm_link) == NULL || 3187 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3188 break; 3189 } 3190 if (prev != NULL) 3191 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3192 else 3193 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3194 return (pm); 3195 } 3196 3197 static void 3198 pci_restore_bars(device_t dev) 3199 { 3200 struct pci_devinfo *dinfo; 3201 struct pci_map *pm; 3202 int ln2range; 3203 3204 dinfo = device_get_ivars(dev); 3205 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3206 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3207 ln2range = 32; 3208 else 3209 ln2range = pci_maprange(pm->pm_value); 3210 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3211 if (ln2range == 64) 3212 pci_write_config(dev, pm->pm_reg + 4, 3213 pm->pm_value >> 32, 4); 3214 } 3215 } 3216 3217 /* 3218 * Add a resource based on a pci map register. Return 1 if the map 3219 * register is a 32bit map register or 2 if it is a 64bit register. 3220 */ 3221 static int 3222 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3223 int force, int prefetch) 3224 { 3225 struct pci_map *pm; 3226 pci_addr_t base, map, testval; 3227 pci_addr_t start, end, count; 3228 int barlen, basezero, flags, maprange, mapsize, type; 3229 uint16_t cmd; 3230 struct resource *res; 3231 3232 /* 3233 * The BAR may already exist if the device is a CardBus card 3234 * whose CIS is stored in this BAR. 3235 */ 3236 pm = pci_find_bar(dev, reg); 3237 if (pm != NULL) { 3238 maprange = pci_maprange(pm->pm_value); 3239 barlen = maprange == 64 ? 2 : 1; 3240 return (barlen); 3241 } 3242 3243 pci_read_bar(dev, reg, &map, &testval, NULL); 3244 if (PCI_BAR_MEM(map)) { 3245 type = SYS_RES_MEMORY; 3246 if (map & PCIM_BAR_MEM_PREFETCH) 3247 prefetch = 1; 3248 } else 3249 type = SYS_RES_IOPORT; 3250 mapsize = pci_mapsize(testval); 3251 base = pci_mapbase(map); 3252 #ifdef __PCI_BAR_ZERO_VALID 3253 basezero = 0; 3254 #else 3255 basezero = base == 0; 3256 #endif 3257 maprange = pci_maprange(map); 3258 barlen = maprange == 64 ? 2 : 1; 3259 3260 /* 3261 * For I/O registers, if bottom bit is set, and the next bit up 3262 * isn't clear, we know we have a BAR that doesn't conform to the 3263 * spec, so ignore it. Also, sanity check the size of the data 3264 * areas to the type of memory involved. Memory must be at least 3265 * 16 bytes in size, while I/O ranges must be at least 4. 3266 */ 3267 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3268 return (barlen); 3269 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3270 (type == SYS_RES_IOPORT && mapsize < 2)) 3271 return (barlen); 3272 3273 /* Save a record of this BAR. */ 3274 pm = pci_add_bar(dev, reg, map, mapsize); 3275 if (bootverbose) { 3276 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3277 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3278 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3279 printf(", port disabled\n"); 3280 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3281 printf(", memory disabled\n"); 3282 else 3283 printf(", enabled\n"); 3284 } 3285 3286 /* 3287 * If base is 0, then we have problems if this architecture does 3288 * not allow that. It is best to ignore such entries for the 3289 * moment. These will be allocated later if the driver specifically 3290 * requests them. However, some removable buses look better when 3291 * all resources are allocated, so allow '0' to be overriden. 3292 * 3293 * Similarly treat maps whose values is the same as the test value 3294 * read back. These maps have had all f's written to them by the 3295 * BIOS in an attempt to disable the resources. 3296 */ 3297 if (!force && (basezero || map == testval)) 3298 return (barlen); 3299 if ((u_long)base != base) { 3300 device_printf(bus, 3301 "pci%d:%d:%d:%d bar %#x too many address bits", 3302 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3303 pci_get_function(dev), reg); 3304 return (barlen); 3305 } 3306 3307 /* 3308 * This code theoretically does the right thing, but has 3309 * undesirable side effects in some cases where peripherals 3310 * respond oddly to having these bits enabled. Let the user 3311 * be able to turn them off (since pci_enable_io_modes is 1 by 3312 * default). 3313 */ 3314 if (pci_enable_io_modes) { 3315 /* Turn on resources that have been left off by a lazy BIOS */ 3316 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3317 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3318 cmd |= PCIM_CMD_PORTEN; 3319 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3320 } 3321 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3322 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3323 cmd |= PCIM_CMD_MEMEN; 3324 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3325 } 3326 } else { 3327 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3328 return (barlen); 3329 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3330 return (barlen); 3331 } 3332 3333 count = (pci_addr_t)1 << mapsize; 3334 flags = RF_ALIGNMENT_LOG2(mapsize); 3335 if (prefetch) 3336 flags |= RF_PREFETCHABLE; 3337 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3338 start = 0; /* Let the parent decide. */ 3339 end = ~0; 3340 } else { 3341 start = base; 3342 end = base + count - 1; 3343 } 3344 resource_list_add(rl, type, reg, start, end, count); 3345 3346 /* 3347 * Try to allocate the resource for this BAR from our parent 3348 * so that this resource range is already reserved. The 3349 * driver for this device will later inherit this resource in 3350 * pci_alloc_resource(). 3351 */ 3352 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3353 flags); 3354 if ((pci_do_realloc_bars 3355 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3356 && res == NULL && (start != 0 || end != ~0)) { 3357 /* 3358 * If the allocation fails, try to allocate a resource for 3359 * this BAR using any available range. The firmware felt 3360 * it was important enough to assign a resource, so don't 3361 * disable decoding if we can help it. 3362 */ 3363 resource_list_delete(rl, type, reg); 3364 resource_list_add(rl, type, reg, 0, ~0, count); 3365 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3366 count, flags); 3367 } 3368 if (res == NULL) { 3369 /* 3370 * If the allocation fails, delete the resource list entry 3371 * and disable decoding for this device. 3372 * 3373 * If the driver requests this resource in the future, 3374 * pci_reserve_map() will try to allocate a fresh 3375 * resource range. 3376 */ 3377 resource_list_delete(rl, type, reg); 3378 pci_disable_io(dev, type); 3379 if (bootverbose) 3380 device_printf(bus, 3381 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3382 pci_get_domain(dev), pci_get_bus(dev), 3383 pci_get_slot(dev), pci_get_function(dev), reg); 3384 } else { 3385 start = rman_get_start(res); 3386 pci_write_bar(dev, pm, start); 3387 } 3388 return (barlen); 3389 } 3390 3391 /* 3392 * For ATA devices we need to decide early what addressing mode to use. 3393 * Legacy demands that the primary and secondary ATA ports sits on the 3394 * same addresses that old ISA hardware did. This dictates that we use 3395 * those addresses and ignore the BAR's if we cannot set PCI native 3396 * addressing mode. 3397 */ 3398 static void 3399 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3400 uint32_t prefetchmask) 3401 { 3402 int rid, type, progif; 3403 #if 0 3404 /* if this device supports PCI native addressing use it */ 3405 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3406 if ((progif & 0x8a) == 0x8a) { 3407 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3408 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3409 printf("Trying ATA native PCI addressing mode\n"); 3410 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3411 } 3412 } 3413 #endif 3414 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3415 type = SYS_RES_IOPORT; 3416 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3417 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3418 prefetchmask & (1 << 0)); 3419 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3420 prefetchmask & (1 << 1)); 3421 } else { 3422 rid = PCIR_BAR(0); 3423 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3424 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3425 0x1f7, 8, 0); 3426 rid = PCIR_BAR(1); 3427 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3428 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3429 0x3f6, 1, 0); 3430 } 3431 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3432 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3433 prefetchmask & (1 << 2)); 3434 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3435 prefetchmask & (1 << 3)); 3436 } else { 3437 rid = PCIR_BAR(2); 3438 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3439 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3440 0x177, 8, 0); 3441 rid = PCIR_BAR(3); 3442 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3443 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3444 0x376, 1, 0); 3445 } 3446 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3447 prefetchmask & (1 << 4)); 3448 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3449 prefetchmask & (1 << 5)); 3450 } 3451 3452 static void 3453 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3454 { 3455 struct pci_devinfo *dinfo = device_get_ivars(dev); 3456 pcicfgregs *cfg = &dinfo->cfg; 3457 char tunable_name[64]; 3458 int irq; 3459 3460 /* Has to have an intpin to have an interrupt. */ 3461 if (cfg->intpin == 0) 3462 return; 3463 3464 /* Let the user override the IRQ with a tunable. */ 3465 irq = PCI_INVALID_IRQ; 3466 snprintf(tunable_name, sizeof(tunable_name), 3467 "hw.pci%d.%d.%d.INT%c.irq", 3468 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3469 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3470 irq = PCI_INVALID_IRQ; 3471 3472 /* 3473 * If we didn't get an IRQ via the tunable, then we either use the 3474 * IRQ value in the intline register or we ask the bus to route an 3475 * interrupt for us. If force_route is true, then we only use the 3476 * value in the intline register if the bus was unable to assign an 3477 * IRQ. 3478 */ 3479 if (!PCI_INTERRUPT_VALID(irq)) { 3480 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3481 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3482 if (!PCI_INTERRUPT_VALID(irq)) 3483 irq = cfg->intline; 3484 } 3485 3486 /* If after all that we don't have an IRQ, just bail. */ 3487 if (!PCI_INTERRUPT_VALID(irq)) 3488 return; 3489 3490 /* Update the config register if it changed. */ 3491 if (irq != cfg->intline) { 3492 cfg->intline = irq; 3493 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3494 } 3495 3496 /* Add this IRQ as rid 0 interrupt resource. */ 3497 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3498 } 3499 3500 /* Perform early OHCI takeover from SMM. */ 3501 static void 3502 ohci_early_takeover(device_t self) 3503 { 3504 struct resource *res; 3505 uint32_t ctl; 3506 int rid; 3507 int i; 3508 3509 rid = PCIR_BAR(0); 3510 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3511 if (res == NULL) 3512 return; 3513 3514 ctl = bus_read_4(res, OHCI_CONTROL); 3515 if (ctl & OHCI_IR) { 3516 if (bootverbose) 3517 printf("ohci early: " 3518 "SMM active, request owner change\n"); 3519 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3520 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3521 DELAY(1000); 3522 ctl = bus_read_4(res, OHCI_CONTROL); 3523 } 3524 if (ctl & OHCI_IR) { 3525 if (bootverbose) 3526 printf("ohci early: " 3527 "SMM does not respond, resetting\n"); 3528 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3529 } 3530 /* Disable interrupts */ 3531 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3532 } 3533 3534 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3535 } 3536 3537 /* Perform early UHCI takeover from SMM. */ 3538 static void 3539 uhci_early_takeover(device_t self) 3540 { 3541 struct resource *res; 3542 int rid; 3543 3544 /* 3545 * Set the PIRQD enable bit and switch off all the others. We don't 3546 * want legacy support to interfere with us XXX Does this also mean 3547 * that the BIOS won't touch the keyboard anymore if it is connected 3548 * to the ports of the root hub? 3549 */ 3550 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3551 3552 /* Disable interrupts */ 3553 rid = PCI_UHCI_BASE_REG; 3554 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3555 if (res != NULL) { 3556 bus_write_2(res, UHCI_INTR, 0); 3557 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3558 } 3559 } 3560 3561 /* Perform early EHCI takeover from SMM. */ 3562 static void 3563 ehci_early_takeover(device_t self) 3564 { 3565 struct resource *res; 3566 uint32_t cparams; 3567 uint32_t eec; 3568 uint8_t eecp; 3569 uint8_t bios_sem; 3570 uint8_t offs; 3571 int rid; 3572 int i; 3573 3574 rid = PCIR_BAR(0); 3575 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3576 if (res == NULL) 3577 return; 3578 3579 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3580 3581 /* Synchronise with the BIOS if it owns the controller. */ 3582 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3583 eecp = EHCI_EECP_NEXT(eec)) { 3584 eec = pci_read_config(self, eecp, 4); 3585 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3586 continue; 3587 } 3588 bios_sem = pci_read_config(self, eecp + 3589 EHCI_LEGSUP_BIOS_SEM, 1); 3590 if (bios_sem == 0) { 3591 continue; 3592 } 3593 if (bootverbose) 3594 printf("ehci early: " 3595 "SMM active, request owner change\n"); 3596 3597 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3598 3599 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3600 DELAY(1000); 3601 bios_sem = pci_read_config(self, eecp + 3602 EHCI_LEGSUP_BIOS_SEM, 1); 3603 } 3604 3605 if (bios_sem != 0) { 3606 if (bootverbose) 3607 printf("ehci early: " 3608 "SMM does not respond\n"); 3609 } 3610 /* Disable interrupts */ 3611 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3612 bus_write_4(res, offs + EHCI_USBINTR, 0); 3613 } 3614 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3615 } 3616 3617 /* Perform early XHCI takeover from SMM. */ 3618 static void 3619 xhci_early_takeover(device_t self) 3620 { 3621 struct resource *res; 3622 uint32_t cparams; 3623 uint32_t eec; 3624 uint8_t eecp; 3625 uint8_t bios_sem; 3626 uint8_t offs; 3627 int rid; 3628 int i; 3629 3630 rid = PCIR_BAR(0); 3631 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3632 if (res == NULL) 3633 return; 3634 3635 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3636 3637 eec = -1; 3638 3639 /* Synchronise with the BIOS if it owns the controller. */ 3640 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3641 eecp += XHCI_XECP_NEXT(eec) << 2) { 3642 eec = bus_read_4(res, eecp); 3643 3644 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3645 continue; 3646 3647 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3648 if (bios_sem == 0) 3649 continue; 3650 3651 if (bootverbose) 3652 printf("xhci early: " 3653 "SMM active, request owner change\n"); 3654 3655 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3656 3657 /* wait a maximum of 5 second */ 3658 3659 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3660 DELAY(1000); 3661 bios_sem = bus_read_1(res, eecp + 3662 XHCI_XECP_BIOS_SEM); 3663 } 3664 3665 if (bios_sem != 0) { 3666 if (bootverbose) 3667 printf("xhci early: " 3668 "SMM does not respond\n"); 3669 } 3670 3671 /* Disable interrupts */ 3672 offs = bus_read_1(res, XHCI_CAPLENGTH); 3673 bus_write_4(res, offs + XHCI_USBCMD, 0); 3674 bus_read_4(res, offs + XHCI_USBSTS); 3675 } 3676 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3677 } 3678 3679 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3680 static void 3681 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3682 struct resource_list *rl) 3683 { 3684 struct resource *res; 3685 char *cp; 3686 rman_res_t start, end, count; 3687 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3688 3689 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3690 case PCIM_HDRTYPE_BRIDGE: 3691 sec_reg = PCIR_SECBUS_1; 3692 sub_reg = PCIR_SUBBUS_1; 3693 break; 3694 case PCIM_HDRTYPE_CARDBUS: 3695 sec_reg = PCIR_SECBUS_2; 3696 sub_reg = PCIR_SUBBUS_2; 3697 break; 3698 default: 3699 return; 3700 } 3701 3702 /* 3703 * If the existing bus range is valid, attempt to reserve it 3704 * from our parent. If this fails for any reason, clear the 3705 * secbus and subbus registers. 3706 * 3707 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3708 * This would at least preserve the existing sec_bus if it is 3709 * valid. 3710 */ 3711 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3712 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3713 3714 /* Quirk handling. */ 3715 switch (pci_get_devid(dev)) { 3716 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3717 sup_bus = pci_read_config(dev, 0x41, 1); 3718 if (sup_bus != 0xff) { 3719 sec_bus = sup_bus + 1; 3720 sub_bus = sup_bus + 1; 3721 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3722 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3723 } 3724 break; 3725 3726 case 0x00dd10de: 3727 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3728 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3729 break; 3730 if (strncmp(cp, "Compal", 6) != 0) { 3731 freeenv(cp); 3732 break; 3733 } 3734 freeenv(cp); 3735 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3736 break; 3737 if (strncmp(cp, "08A0", 4) != 0) { 3738 freeenv(cp); 3739 break; 3740 } 3741 freeenv(cp); 3742 if (sub_bus < 0xa) { 3743 sub_bus = 0xa; 3744 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3745 } 3746 break; 3747 } 3748 3749 if (bootverbose) 3750 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3751 if (sec_bus > 0 && sub_bus >= sec_bus) { 3752 start = sec_bus; 3753 end = sub_bus; 3754 count = end - start + 1; 3755 3756 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3757 3758 /* 3759 * If requested, clear secondary bus registers in 3760 * bridge devices to force a complete renumbering 3761 * rather than reserving the existing range. However, 3762 * preserve the existing size. 3763 */ 3764 if (pci_clear_buses) 3765 goto clear; 3766 3767 rid = 0; 3768 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3769 start, end, count, 0); 3770 if (res != NULL) 3771 return; 3772 3773 if (bootverbose) 3774 device_printf(bus, 3775 "pci%d:%d:%d:%d secbus failed to allocate\n", 3776 pci_get_domain(dev), pci_get_bus(dev), 3777 pci_get_slot(dev), pci_get_function(dev)); 3778 } 3779 3780 clear: 3781 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3782 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3783 } 3784 3785 static struct resource * 3786 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3787 rman_res_t end, rman_res_t count, u_int flags) 3788 { 3789 struct pci_devinfo *dinfo; 3790 pcicfgregs *cfg; 3791 struct resource_list *rl; 3792 struct resource *res; 3793 int sec_reg, sub_reg; 3794 3795 dinfo = device_get_ivars(child); 3796 cfg = &dinfo->cfg; 3797 rl = &dinfo->resources; 3798 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3799 case PCIM_HDRTYPE_BRIDGE: 3800 sec_reg = PCIR_SECBUS_1; 3801 sub_reg = PCIR_SUBBUS_1; 3802 break; 3803 case PCIM_HDRTYPE_CARDBUS: 3804 sec_reg = PCIR_SECBUS_2; 3805 sub_reg = PCIR_SUBBUS_2; 3806 break; 3807 default: 3808 return (NULL); 3809 } 3810 3811 if (*rid != 0) 3812 return (NULL); 3813 3814 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3815 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3816 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3817 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3818 start, end, count, flags & ~RF_ACTIVE); 3819 if (res == NULL) { 3820 resource_list_delete(rl, PCI_RES_BUS, *rid); 3821 device_printf(child, "allocating %ju bus%s failed\n", 3822 count, count == 1 ? "" : "es"); 3823 return (NULL); 3824 } 3825 if (bootverbose) 3826 device_printf(child, 3827 "Lazy allocation of %ju bus%s at %ju\n", count, 3828 count == 1 ? "" : "es", rman_get_start(res)); 3829 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3830 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3831 } 3832 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3833 end, count, flags)); 3834 } 3835 #endif 3836 3837 static int 3838 pci_ea_bei_to_rid(device_t dev, int bei) 3839 { 3840 #ifdef PCI_IOV 3841 struct pci_devinfo *dinfo; 3842 int iov_pos; 3843 struct pcicfg_iov *iov; 3844 3845 dinfo = device_get_ivars(dev); 3846 iov = dinfo->cfg.iov; 3847 if (iov != NULL) 3848 iov_pos = iov->iov_pos; 3849 else 3850 iov_pos = 0; 3851 #endif 3852 3853 /* Check if matches BAR */ 3854 if ((bei >= PCIM_EA_BEI_BAR_0) && 3855 (bei <= PCIM_EA_BEI_BAR_5)) 3856 return (PCIR_BAR(bei)); 3857 3858 /* Check ROM */ 3859 if (bei == PCIM_EA_BEI_ROM) 3860 return (PCIR_BIOS); 3861 3862 #ifdef PCI_IOV 3863 /* Check if matches VF_BAR */ 3864 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3865 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3866 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3867 iov_pos); 3868 #endif 3869 3870 return (-1); 3871 } 3872 3873 int 3874 pci_ea_is_enabled(device_t dev, int rid) 3875 { 3876 struct pci_ea_entry *ea; 3877 struct pci_devinfo *dinfo; 3878 3879 dinfo = device_get_ivars(dev); 3880 3881 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3882 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3883 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3884 } 3885 3886 return (0); 3887 } 3888 3889 void 3890 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 3891 { 3892 struct pci_ea_entry *ea; 3893 struct pci_devinfo *dinfo; 3894 pci_addr_t start, end, count; 3895 struct resource_list *rl; 3896 int type, flags, rid; 3897 struct resource *res; 3898 uint32_t tmp; 3899 #ifdef PCI_IOV 3900 struct pcicfg_iov *iov; 3901 #endif 3902 3903 dinfo = device_get_ivars(dev); 3904 rl = &dinfo->resources; 3905 flags = 0; 3906 3907 #ifdef PCI_IOV 3908 iov = dinfo->cfg.iov; 3909 #endif 3910 3911 if (dinfo->cfg.ea.ea_location == 0) 3912 return; 3913 3914 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3915 /* 3916 * TODO: Ignore EA-BAR if is not enabled. 3917 * Currently the EA implementation supports 3918 * only situation, where EA structure contains 3919 * predefined entries. In case they are not enabled 3920 * leave them unallocated and proceed with 3921 * a legacy-BAR mechanism. 3922 */ 3923 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 3924 continue; 3925 3926 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 3927 case PCIM_EA_P_MEM_PREFETCH: 3928 case PCIM_EA_P_VF_MEM_PREFETCH: 3929 flags = RF_PREFETCHABLE; 3930 /* FALLTHROUGH */ 3931 case PCIM_EA_P_VF_MEM: 3932 case PCIM_EA_P_MEM: 3933 type = SYS_RES_MEMORY; 3934 break; 3935 case PCIM_EA_P_IO: 3936 type = SYS_RES_IOPORT; 3937 break; 3938 default: 3939 continue; 3940 } 3941 3942 if (alloc_iov != 0) { 3943 #ifdef PCI_IOV 3944 /* Allocating IOV, confirm BEI matches */ 3945 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 3946 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 3947 continue; 3948 #else 3949 continue; 3950 #endif 3951 } else { 3952 /* Allocating BAR, confirm BEI matches */ 3953 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 3954 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 3955 (ea->eae_bei != PCIM_EA_BEI_ROM)) 3956 continue; 3957 } 3958 3959 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 3960 if (rid < 0) 3961 continue; 3962 3963 /* Skip resources already allocated by EA */ 3964 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 3965 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 3966 continue; 3967 3968 start = ea->eae_base; 3969 count = ea->eae_max_offset + 1; 3970 #ifdef PCI_IOV 3971 if (iov != NULL) 3972 count = count * iov->iov_num_vfs; 3973 #endif 3974 end = start + count - 1; 3975 if (count == 0) 3976 continue; 3977 3978 resource_list_add(rl, type, rid, start, end, count); 3979 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 3980 flags); 3981 if (res == NULL) { 3982 resource_list_delete(rl, type, rid); 3983 3984 /* 3985 * Failed to allocate using EA, disable entry. 3986 * Another attempt to allocation will be performed 3987 * further, but this time using legacy BAR registers 3988 */ 3989 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 3990 tmp &= ~PCIM_EA_ENABLE; 3991 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 3992 3993 /* 3994 * Disabling entry might fail in case it is hardwired. 3995 * Read flags again to match current status. 3996 */ 3997 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 3998 3999 continue; 4000 } 4001 4002 /* As per specification, fill BAR with zeros */ 4003 pci_write_config(dev, rid, 0, 4); 4004 } 4005 } 4006 4007 void 4008 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 4009 { 4010 struct pci_devinfo *dinfo; 4011 pcicfgregs *cfg; 4012 struct resource_list *rl; 4013 const struct pci_quirk *q; 4014 uint32_t devid; 4015 int i; 4016 4017 dinfo = device_get_ivars(dev); 4018 cfg = &dinfo->cfg; 4019 rl = &dinfo->resources; 4020 devid = (cfg->device << 16) | cfg->vendor; 4021 4022 /* Allocate resources using Enhanced Allocation */ 4023 pci_add_resources_ea(bus, dev, 0); 4024 4025 /* ATA devices needs special map treatment */ 4026 if ((pci_get_class(dev) == PCIC_STORAGE) && 4027 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 4028 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 4029 (!pci_read_config(dev, PCIR_BAR(0), 4) && 4030 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 4031 pci_ata_maps(bus, dev, rl, force, prefetchmask); 4032 else 4033 for (i = 0; i < cfg->nummaps;) { 4034 /* Skip resources already managed by EA */ 4035 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 4036 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 4037 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 4038 i++; 4039 continue; 4040 } 4041 4042 /* 4043 * Skip quirked resources. 4044 */ 4045 for (q = &pci_quirks[0]; q->devid != 0; q++) 4046 if (q->devid == devid && 4047 q->type == PCI_QUIRK_UNMAP_REG && 4048 q->arg1 == PCIR_BAR(i)) 4049 break; 4050 if (q->devid != 0) { 4051 i++; 4052 continue; 4053 } 4054 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4055 prefetchmask & (1 << i)); 4056 } 4057 4058 /* 4059 * Add additional, quirked resources. 4060 */ 4061 for (q = &pci_quirks[0]; q->devid != 0; q++) 4062 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4063 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4064 4065 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4066 #ifdef __PCI_REROUTE_INTERRUPT 4067 /* 4068 * Try to re-route interrupts. Sometimes the BIOS or 4069 * firmware may leave bogus values in these registers. 4070 * If the re-route fails, then just stick with what we 4071 * have. 4072 */ 4073 pci_assign_interrupt(bus, dev, 1); 4074 #else 4075 pci_assign_interrupt(bus, dev, 0); 4076 #endif 4077 } 4078 4079 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4080 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4081 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4082 xhci_early_takeover(dev); 4083 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4084 ehci_early_takeover(dev); 4085 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4086 ohci_early_takeover(dev); 4087 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4088 uhci_early_takeover(dev); 4089 } 4090 4091 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4092 /* 4093 * Reserve resources for secondary bus ranges behind bridge 4094 * devices. 4095 */ 4096 pci_reserve_secbus(bus, dev, cfg, rl); 4097 #endif 4098 } 4099 4100 static struct pci_devinfo * 4101 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4102 int slot, int func) 4103 { 4104 struct pci_devinfo *dinfo; 4105 4106 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4107 if (dinfo != NULL) 4108 pci_add_child(dev, dinfo); 4109 4110 return (dinfo); 4111 } 4112 4113 void 4114 pci_add_children(device_t dev, int domain, int busno) 4115 { 4116 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4117 device_t pcib = device_get_parent(dev); 4118 struct pci_devinfo *dinfo; 4119 int maxslots; 4120 int s, f, pcifunchigh; 4121 uint8_t hdrtype; 4122 int first_func; 4123 4124 /* 4125 * Try to detect a device at slot 0, function 0. If it exists, try to 4126 * enable ARI. We must enable ARI before detecting the rest of the 4127 * functions on this bus as ARI changes the set of slots and functions 4128 * that are legal on this bus. 4129 */ 4130 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4131 if (dinfo != NULL && pci_enable_ari) 4132 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4133 4134 /* 4135 * Start looking for new devices on slot 0 at function 1 because we 4136 * just identified the device at slot 0, function 0. 4137 */ 4138 first_func = 1; 4139 4140 maxslots = PCIB_MAXSLOTS(pcib); 4141 for (s = 0; s <= maxslots; s++, first_func = 0) { 4142 pcifunchigh = 0; 4143 f = 0; 4144 DELAY(1); 4145 4146 /* If function 0 is not present, skip to the next slot. */ 4147 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4148 continue; 4149 hdrtype = REG(PCIR_HDRTYPE, 1); 4150 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4151 continue; 4152 if (hdrtype & PCIM_MFDEV) 4153 pcifunchigh = PCIB_MAXFUNCS(pcib); 4154 for (f = first_func; f <= pcifunchigh; f++) 4155 pci_identify_function(pcib, dev, domain, busno, s, f); 4156 } 4157 #undef REG 4158 } 4159 4160 int 4161 pci_rescan_method(device_t dev) 4162 { 4163 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4164 device_t pcib = device_get_parent(dev); 4165 device_t child, *devlist, *unchanged; 4166 int devcount, error, i, j, maxslots, oldcount; 4167 int busno, domain, s, f, pcifunchigh; 4168 uint8_t hdrtype; 4169 4170 /* No need to check for ARI on a rescan. */ 4171 error = device_get_children(dev, &devlist, &devcount); 4172 if (error) 4173 return (error); 4174 if (devcount != 0) { 4175 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4176 M_NOWAIT | M_ZERO); 4177 if (unchanged == NULL) { 4178 free(devlist, M_TEMP); 4179 return (ENOMEM); 4180 } 4181 } else 4182 unchanged = NULL; 4183 4184 domain = pcib_get_domain(dev); 4185 busno = pcib_get_bus(dev); 4186 maxslots = PCIB_MAXSLOTS(pcib); 4187 for (s = 0; s <= maxslots; s++) { 4188 /* If function 0 is not present, skip to the next slot. */ 4189 f = 0; 4190 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4191 continue; 4192 pcifunchigh = 0; 4193 hdrtype = REG(PCIR_HDRTYPE, 1); 4194 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4195 continue; 4196 if (hdrtype & PCIM_MFDEV) 4197 pcifunchigh = PCIB_MAXFUNCS(pcib); 4198 for (f = 0; f <= pcifunchigh; f++) { 4199 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4200 continue; 4201 4202 /* 4203 * Found a valid function. Check if a 4204 * device_t for this device already exists. 4205 */ 4206 for (i = 0; i < devcount; i++) { 4207 child = devlist[i]; 4208 if (child == NULL) 4209 continue; 4210 if (pci_get_slot(child) == s && 4211 pci_get_function(child) == f) { 4212 unchanged[i] = child; 4213 goto next_func; 4214 } 4215 } 4216 4217 pci_identify_function(pcib, dev, domain, busno, s, f); 4218 next_func:; 4219 } 4220 } 4221 4222 /* Remove devices that are no longer present. */ 4223 for (i = 0; i < devcount; i++) { 4224 if (unchanged[i] != NULL) 4225 continue; 4226 device_delete_child(dev, devlist[i]); 4227 } 4228 4229 free(devlist, M_TEMP); 4230 oldcount = devcount; 4231 4232 /* Try to attach the devices just added. */ 4233 error = device_get_children(dev, &devlist, &devcount); 4234 if (error) { 4235 free(unchanged, M_TEMP); 4236 return (error); 4237 } 4238 4239 for (i = 0; i < devcount; i++) { 4240 for (j = 0; j < oldcount; j++) { 4241 if (devlist[i] == unchanged[j]) 4242 goto next_device; 4243 } 4244 4245 device_probe_and_attach(devlist[i]); 4246 next_device:; 4247 } 4248 4249 free(unchanged, M_TEMP); 4250 free(devlist, M_TEMP); 4251 return (0); 4252 #undef REG 4253 } 4254 4255 #ifdef PCI_IOV 4256 device_t 4257 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4258 uint16_t did) 4259 { 4260 struct pci_devinfo *vf_dinfo; 4261 device_t pcib; 4262 int busno, slot, func; 4263 4264 pcib = device_get_parent(bus); 4265 4266 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4267 4268 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4269 slot, func, vid, did); 4270 4271 vf_dinfo->cfg.flags |= PCICFG_VF; 4272 pci_add_child(bus, vf_dinfo); 4273 4274 return (vf_dinfo->cfg.dev); 4275 } 4276 4277 device_t 4278 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4279 uint16_t vid, uint16_t did) 4280 { 4281 4282 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4283 } 4284 #endif 4285 4286 /* 4287 * For PCIe device set Max_Payload_Size to match PCIe root's. 4288 */ 4289 static void 4290 pcie_setup_mps(device_t dev) 4291 { 4292 struct pci_devinfo *dinfo = device_get_ivars(dev); 4293 device_t root; 4294 uint16_t rmps, mmps, mps; 4295 4296 if (dinfo->cfg.pcie.pcie_location == 0) 4297 return; 4298 root = pci_find_pcie_root_port(dev); 4299 if (root == NULL) 4300 return; 4301 /* Check whether the MPS is already configured. */ 4302 rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) & 4303 PCIEM_CTL_MAX_PAYLOAD; 4304 mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) & 4305 PCIEM_CTL_MAX_PAYLOAD; 4306 if (mps == rmps) 4307 return; 4308 /* Check whether the device is capable of the root's MPS. */ 4309 mmps = (pcie_read_config(dev, PCIER_DEVICE_CAP, 2) & 4310 PCIEM_CAP_MAX_PAYLOAD) << 5; 4311 if (rmps > mmps) { 4312 /* 4313 * The device is unable to handle root's MPS. Limit root. 4314 * XXX: We should traverse through all the tree, applying 4315 * it to all the devices. 4316 */ 4317 pcie_adjust_config(root, PCIER_DEVICE_CTL, 4318 PCIEM_CTL_MAX_PAYLOAD, mmps, 2); 4319 } else { 4320 pcie_adjust_config(dev, PCIER_DEVICE_CTL, 4321 PCIEM_CTL_MAX_PAYLOAD, rmps, 2); 4322 } 4323 } 4324 4325 static void 4326 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4327 { 4328 int aer; 4329 uint32_t r; 4330 uint16_t r2; 4331 4332 if (dinfo->cfg.pcie.pcie_location != 0 && 4333 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4334 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4335 PCIER_ROOT_CTL, 2); 4336 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4337 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4338 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4339 PCIER_ROOT_CTL, r2, 2); 4340 } 4341 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4342 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4343 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4344 if (r != 0 && bootverbose) { 4345 pci_printf(&dinfo->cfg, 4346 "clearing AER UC 0x%08x -> 0x%08x\n", 4347 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4348 4)); 4349 } 4350 4351 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4352 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4353 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4354 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4355 PCIM_AER_UC_POISONED_TLP | 4356 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4357 PCIM_AER_UC_COMPLETION_TIMEOUT | 4358 PCIM_AER_UC_COMPLETER_ABORT | 4359 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4360 PCIM_AER_UC_RECEIVER_OVERFLOW | 4361 PCIM_AER_UC_MALFORMED_TLP | 4362 PCIM_AER_UC_ECRC_ERROR | 4363 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4364 PCIM_AER_UC_ACS_VIOLATION | 4365 PCIM_AER_UC_INTERNAL_ERROR | 4366 PCIM_AER_UC_MC_BLOCKED_TLP | 4367 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4368 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4369 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4370 4371 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4372 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4373 if (r != 0 && bootverbose) { 4374 pci_printf(&dinfo->cfg, 4375 "clearing AER COR 0x%08x -> 0x%08x\n", 4376 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4377 4)); 4378 } 4379 4380 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4381 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4382 PCIM_AER_COR_BAD_TLP | 4383 PCIM_AER_COR_BAD_DLLP | 4384 PCIM_AER_COR_REPLAY_ROLLOVER | 4385 PCIM_AER_COR_REPLAY_TIMEOUT | 4386 PCIM_AER_COR_ADVISORY_NF_ERROR | 4387 PCIM_AER_COR_INTERNAL_ERROR | 4388 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4389 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4390 4391 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4392 PCIER_DEVICE_CTL, 2); 4393 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4394 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4395 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4396 PCIER_DEVICE_CTL, r, 2); 4397 } 4398 } 4399 4400 void 4401 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4402 { 4403 device_t dev; 4404 4405 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1); 4406 device_set_ivars(dev, dinfo); 4407 resource_list_init(&dinfo->resources); 4408 pci_cfg_save(dev, dinfo, 0); 4409 pci_cfg_restore(dev, dinfo); 4410 pci_print_verbose(dinfo); 4411 pci_add_resources(bus, dev, 0, 0); 4412 pcie_setup_mps(dev); 4413 pci_child_added(dinfo->cfg.dev); 4414 4415 if (pci_clear_aer_on_attach) 4416 pci_add_child_clear_aer(dev, dinfo); 4417 4418 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4419 } 4420 4421 void 4422 pci_child_added_method(device_t dev, device_t child) 4423 { 4424 4425 } 4426 4427 static int 4428 pci_probe(device_t dev) 4429 { 4430 4431 device_set_desc(dev, "PCI bus"); 4432 4433 /* Allow other subclasses to override this driver. */ 4434 return (BUS_PROBE_GENERIC); 4435 } 4436 4437 int 4438 pci_attach_common(device_t dev) 4439 { 4440 struct pci_softc *sc; 4441 int busno, domain; 4442 #ifdef PCI_RES_BUS 4443 int rid; 4444 #endif 4445 4446 sc = device_get_softc(dev); 4447 domain = pcib_get_domain(dev); 4448 busno = pcib_get_bus(dev); 4449 #ifdef PCI_RES_BUS 4450 rid = 0; 4451 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4452 1, 0); 4453 if (sc->sc_bus == NULL) { 4454 device_printf(dev, "failed to allocate bus number\n"); 4455 return (ENXIO); 4456 } 4457 #endif 4458 if (bootverbose) 4459 device_printf(dev, "domain=%d, physical bus=%d\n", 4460 domain, busno); 4461 sc->sc_dma_tag = bus_get_dma_tag(dev); 4462 return (0); 4463 } 4464 4465 int 4466 pci_attach(device_t dev) 4467 { 4468 int busno, domain, error; 4469 4470 error = pci_attach_common(dev); 4471 if (error) 4472 return (error); 4473 4474 /* 4475 * Since there can be multiple independently numbered PCI 4476 * buses on systems with multiple PCI domains, we can't use 4477 * the unit number to decide which bus we are probing. We ask 4478 * the parent pcib what our domain and bus numbers are. 4479 */ 4480 domain = pcib_get_domain(dev); 4481 busno = pcib_get_bus(dev); 4482 pci_add_children(dev, domain, busno); 4483 return (bus_generic_attach(dev)); 4484 } 4485 4486 int 4487 pci_detach(device_t dev) 4488 { 4489 #ifdef PCI_RES_BUS 4490 struct pci_softc *sc; 4491 #endif 4492 int error; 4493 4494 error = bus_generic_detach(dev); 4495 if (error) 4496 return (error); 4497 #ifdef PCI_RES_BUS 4498 sc = device_get_softc(dev); 4499 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4500 if (error) 4501 return (error); 4502 #endif 4503 return (device_delete_children(dev)); 4504 } 4505 4506 static void 4507 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4508 { 4509 int line, unit; 4510 const char *at; 4511 char me1[24], me2[32]; 4512 uint8_t b, s, f; 4513 uint32_t d; 4514 4515 d = pci_get_domain(child); 4516 b = pci_get_bus(child); 4517 s = pci_get_slot(child); 4518 f = pci_get_function(child); 4519 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4520 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4521 line = 0; 4522 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4523 resource_string_value(name, unit, "at", &at); 4524 if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0) 4525 continue; /* No match, try next candidate */ 4526 *unitp = unit; 4527 return; 4528 } 4529 } 4530 4531 static void 4532 pci_set_power_child(device_t dev, device_t child, int state) 4533 { 4534 device_t pcib; 4535 int dstate; 4536 4537 /* 4538 * Set the device to the given state. If the firmware suggests 4539 * a different power state, use it instead. If power management 4540 * is not present, the firmware is responsible for managing 4541 * device power. Skip children who aren't attached since they 4542 * are handled separately. 4543 */ 4544 pcib = device_get_parent(dev); 4545 dstate = state; 4546 if (device_is_attached(child) && 4547 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4548 pci_set_powerstate(child, dstate); 4549 } 4550 4551 int 4552 pci_suspend_child(device_t dev, device_t child) 4553 { 4554 struct pci_devinfo *dinfo; 4555 struct resource_list_entry *rle; 4556 int error; 4557 4558 dinfo = device_get_ivars(child); 4559 4560 /* 4561 * Save the PCI configuration space for the child and set the 4562 * device in the appropriate power state for this sleep state. 4563 */ 4564 pci_cfg_save(child, dinfo, 0); 4565 4566 /* Suspend devices before potentially powering them down. */ 4567 error = bus_generic_suspend_child(dev, child); 4568 4569 if (error) 4570 return (error); 4571 4572 if (pci_do_power_suspend) { 4573 /* 4574 * Make sure this device's interrupt handler is not invoked 4575 * in the case the device uses a shared interrupt that can 4576 * be raised by some other device. 4577 * This is applicable only to regular (legacy) PCI interrupts 4578 * as MSI/MSI-X interrupts are never shared. 4579 */ 4580 rle = resource_list_find(&dinfo->resources, 4581 SYS_RES_IRQ, 0); 4582 if (rle != NULL && rle->res != NULL) 4583 (void)bus_suspend_intr(child, rle->res); 4584 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4585 } 4586 4587 return (0); 4588 } 4589 4590 int 4591 pci_resume_child(device_t dev, device_t child) 4592 { 4593 struct pci_devinfo *dinfo; 4594 struct resource_list_entry *rle; 4595 4596 if (pci_do_power_resume) 4597 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4598 4599 dinfo = device_get_ivars(child); 4600 pci_cfg_restore(child, dinfo); 4601 if (!device_is_attached(child)) 4602 pci_cfg_save(child, dinfo, 1); 4603 4604 bus_generic_resume_child(dev, child); 4605 4606 /* 4607 * Allow interrupts only after fully resuming the driver and hardware. 4608 */ 4609 if (pci_do_power_suspend) { 4610 /* See pci_suspend_child for details. */ 4611 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4612 if (rle != NULL && rle->res != NULL) 4613 (void)bus_resume_intr(child, rle->res); 4614 } 4615 4616 return (0); 4617 } 4618 4619 int 4620 pci_resume(device_t dev) 4621 { 4622 device_t child, *devlist; 4623 int error, i, numdevs; 4624 4625 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4626 return (error); 4627 4628 /* 4629 * Resume critical devices first, then everything else later. 4630 */ 4631 for (i = 0; i < numdevs; i++) { 4632 child = devlist[i]; 4633 switch (pci_get_class(child)) { 4634 case PCIC_DISPLAY: 4635 case PCIC_MEMORY: 4636 case PCIC_BRIDGE: 4637 case PCIC_BASEPERIPH: 4638 BUS_RESUME_CHILD(dev, child); 4639 break; 4640 } 4641 } 4642 for (i = 0; i < numdevs; i++) { 4643 child = devlist[i]; 4644 switch (pci_get_class(child)) { 4645 case PCIC_DISPLAY: 4646 case PCIC_MEMORY: 4647 case PCIC_BRIDGE: 4648 case PCIC_BASEPERIPH: 4649 break; 4650 default: 4651 BUS_RESUME_CHILD(dev, child); 4652 } 4653 } 4654 free(devlist, M_TEMP); 4655 return (0); 4656 } 4657 4658 static void 4659 pci_load_vendor_data(void) 4660 { 4661 caddr_t data; 4662 void *ptr; 4663 size_t sz; 4664 4665 data = preload_search_by_type("pci_vendor_data"); 4666 if (data != NULL) { 4667 ptr = preload_fetch_addr(data); 4668 sz = preload_fetch_size(data); 4669 if (ptr != NULL && sz != 0) { 4670 pci_vendordata = ptr; 4671 pci_vendordata_size = sz; 4672 /* terminate the database */ 4673 pci_vendordata[pci_vendordata_size] = '\n'; 4674 } 4675 } 4676 } 4677 4678 void 4679 pci_driver_added(device_t dev, driver_t *driver) 4680 { 4681 int numdevs; 4682 device_t *devlist; 4683 device_t child; 4684 struct pci_devinfo *dinfo; 4685 int i; 4686 4687 if (bootverbose) 4688 device_printf(dev, "driver added\n"); 4689 DEVICE_IDENTIFY(driver, dev); 4690 if (device_get_children(dev, &devlist, &numdevs) != 0) 4691 return; 4692 for (i = 0; i < numdevs; i++) { 4693 child = devlist[i]; 4694 if (device_get_state(child) != DS_NOTPRESENT) 4695 continue; 4696 dinfo = device_get_ivars(child); 4697 pci_print_verbose(dinfo); 4698 if (bootverbose) 4699 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4700 pci_cfg_restore(child, dinfo); 4701 if (device_probe_and_attach(child) != 0) 4702 pci_child_detached(dev, child); 4703 } 4704 free(devlist, M_TEMP); 4705 } 4706 4707 int 4708 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4709 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4710 { 4711 struct pci_devinfo *dinfo; 4712 struct msix_table_entry *mte; 4713 struct msix_vector *mv; 4714 uint64_t addr; 4715 uint32_t data; 4716 void *cookie; 4717 int error, rid; 4718 4719 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4720 arg, &cookie); 4721 if (error) 4722 return (error); 4723 4724 /* If this is not a direct child, just bail out. */ 4725 if (device_get_parent(child) != dev) { 4726 *cookiep = cookie; 4727 return(0); 4728 } 4729 4730 rid = rman_get_rid(irq); 4731 if (rid == 0) { 4732 /* Make sure that INTx is enabled */ 4733 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4734 } else { 4735 /* 4736 * Check to see if the interrupt is MSI or MSI-X. 4737 * Ask our parent to map the MSI and give 4738 * us the address and data register values. 4739 * If we fail for some reason, teardown the 4740 * interrupt handler. 4741 */ 4742 dinfo = device_get_ivars(child); 4743 if (dinfo->cfg.msi.msi_alloc > 0) { 4744 if (dinfo->cfg.msi.msi_addr == 0) { 4745 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4746 ("MSI has handlers, but vectors not mapped")); 4747 error = PCIB_MAP_MSI(device_get_parent(dev), 4748 child, rman_get_start(irq), &addr, &data); 4749 if (error) 4750 goto bad; 4751 dinfo->cfg.msi.msi_addr = addr; 4752 dinfo->cfg.msi.msi_data = data; 4753 } 4754 if (dinfo->cfg.msi.msi_handlers == 0) 4755 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4756 dinfo->cfg.msi.msi_data); 4757 dinfo->cfg.msi.msi_handlers++; 4758 } else { 4759 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4760 ("No MSI or MSI-X interrupts allocated")); 4761 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4762 ("MSI-X index too high")); 4763 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4764 KASSERT(mte->mte_vector != 0, ("no message vector")); 4765 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4766 KASSERT(mv->mv_irq == rman_get_start(irq), 4767 ("IRQ mismatch")); 4768 if (mv->mv_address == 0) { 4769 KASSERT(mte->mte_handlers == 0, 4770 ("MSI-X table entry has handlers, but vector not mapped")); 4771 error = PCIB_MAP_MSI(device_get_parent(dev), 4772 child, rman_get_start(irq), &addr, &data); 4773 if (error) 4774 goto bad; 4775 mv->mv_address = addr; 4776 mv->mv_data = data; 4777 } 4778 4779 /* 4780 * The MSIX table entry must be made valid by 4781 * incrementing the mte_handlers before 4782 * calling pci_enable_msix() and 4783 * pci_resume_msix(). Else the MSIX rewrite 4784 * table quirk will not work as expected. 4785 */ 4786 mte->mte_handlers++; 4787 if (mte->mte_handlers == 1) { 4788 pci_enable_msix(child, rid - 1, mv->mv_address, 4789 mv->mv_data); 4790 pci_unmask_msix(child, rid - 1); 4791 } 4792 } 4793 4794 /* 4795 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4796 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4797 * in which case we "enable" INTx so MSI/MSI-X actually works. 4798 */ 4799 if (!pci_has_quirk(pci_get_devid(child), 4800 PCI_QUIRK_MSI_INTX_BUG)) 4801 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4802 else 4803 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4804 bad: 4805 if (error) { 4806 (void)bus_generic_teardown_intr(dev, child, irq, 4807 cookie); 4808 return (error); 4809 } 4810 } 4811 *cookiep = cookie; 4812 return (0); 4813 } 4814 4815 int 4816 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4817 void *cookie) 4818 { 4819 struct msix_table_entry *mte; 4820 struct resource_list_entry *rle; 4821 struct pci_devinfo *dinfo; 4822 int error, rid; 4823 4824 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4825 return (EINVAL); 4826 4827 /* If this isn't a direct child, just bail out */ 4828 if (device_get_parent(child) != dev) 4829 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4830 4831 rid = rman_get_rid(irq); 4832 if (rid == 0) { 4833 /* Mask INTx */ 4834 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4835 } else { 4836 /* 4837 * Check to see if the interrupt is MSI or MSI-X. If so, 4838 * decrement the appropriate handlers count and mask the 4839 * MSI-X message, or disable MSI messages if the count 4840 * drops to 0. 4841 */ 4842 dinfo = device_get_ivars(child); 4843 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4844 if (rle->res != irq) 4845 return (EINVAL); 4846 if (dinfo->cfg.msi.msi_alloc > 0) { 4847 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4848 ("MSI-X index too high")); 4849 if (dinfo->cfg.msi.msi_handlers == 0) 4850 return (EINVAL); 4851 dinfo->cfg.msi.msi_handlers--; 4852 if (dinfo->cfg.msi.msi_handlers == 0) 4853 pci_disable_msi(child); 4854 } else { 4855 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4856 ("No MSI or MSI-X interrupts allocated")); 4857 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4858 ("MSI-X index too high")); 4859 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4860 if (mte->mte_handlers == 0) 4861 return (EINVAL); 4862 mte->mte_handlers--; 4863 if (mte->mte_handlers == 0) 4864 pci_mask_msix(child, rid - 1); 4865 } 4866 } 4867 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4868 if (rid > 0) 4869 KASSERT(error == 0, 4870 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4871 return (error); 4872 } 4873 4874 int 4875 pci_print_child(device_t dev, device_t child) 4876 { 4877 struct pci_devinfo *dinfo; 4878 struct resource_list *rl; 4879 int retval = 0; 4880 4881 dinfo = device_get_ivars(child); 4882 rl = &dinfo->resources; 4883 4884 retval += bus_print_child_header(dev, child); 4885 4886 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4887 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4888 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4889 if (device_get_flags(dev)) 4890 retval += printf(" flags %#x", device_get_flags(dev)); 4891 4892 retval += printf(" at device %d.%d", pci_get_slot(child), 4893 pci_get_function(child)); 4894 4895 retval += bus_print_child_domain(dev, child); 4896 retval += bus_print_child_footer(dev, child); 4897 4898 return (retval); 4899 } 4900 4901 static const struct 4902 { 4903 int class; 4904 int subclass; 4905 int report; /* 0 = bootverbose, 1 = always */ 4906 const char *desc; 4907 } pci_nomatch_tab[] = { 4908 {PCIC_OLD, -1, 1, "old"}, 4909 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4910 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4911 {PCIC_STORAGE, -1, 1, "mass storage"}, 4912 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4913 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4914 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4915 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4916 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4917 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4918 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4919 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4920 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4921 {PCIC_NETWORK, -1, 1, "network"}, 4922 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4923 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4924 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4925 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4926 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4927 {PCIC_DISPLAY, -1, 1, "display"}, 4928 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4929 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4930 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4931 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4932 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4933 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4934 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4935 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4936 {PCIC_MEMORY, -1, 1, "memory"}, 4937 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4938 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4939 {PCIC_BRIDGE, -1, 1, "bridge"}, 4940 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4941 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4942 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4943 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4944 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4945 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4946 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4947 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4948 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4949 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4950 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4951 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4952 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4953 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4954 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4955 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4956 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4957 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4958 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4959 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4960 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4961 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4962 {PCIC_INPUTDEV, -1, 1, "input device"}, 4963 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4964 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4965 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4966 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4967 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4968 {PCIC_DOCKING, -1, 1, "docking station"}, 4969 {PCIC_PROCESSOR, -1, 1, "processor"}, 4970 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4971 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4972 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4973 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4974 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4975 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4976 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4977 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4978 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4979 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4980 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4981 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4982 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4983 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4984 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4985 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4986 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4987 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4988 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4989 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4990 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4991 {PCIC_DASP, -1, 0, "dasp"}, 4992 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4993 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 4994 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 4995 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 4996 {0, 0, 0, NULL} 4997 }; 4998 4999 void 5000 pci_probe_nomatch(device_t dev, device_t child) 5001 { 5002 int i, report; 5003 const char *cp, *scp; 5004 char *device; 5005 5006 /* 5007 * Look for a listing for this device in a loaded device database. 5008 */ 5009 report = 1; 5010 if ((device = pci_describe_device(child)) != NULL) { 5011 device_printf(dev, "<%s>", device); 5012 free(device, M_DEVBUF); 5013 } else { 5014 /* 5015 * Scan the class/subclass descriptions for a general 5016 * description. 5017 */ 5018 cp = "unknown"; 5019 scp = NULL; 5020 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 5021 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 5022 if (pci_nomatch_tab[i].subclass == -1) { 5023 cp = pci_nomatch_tab[i].desc; 5024 report = pci_nomatch_tab[i].report; 5025 } else if (pci_nomatch_tab[i].subclass == 5026 pci_get_subclass(child)) { 5027 scp = pci_nomatch_tab[i].desc; 5028 report = pci_nomatch_tab[i].report; 5029 } 5030 } 5031 } 5032 if (report || bootverbose) { 5033 device_printf(dev, "<%s%s%s>", 5034 cp ? cp : "", 5035 ((cp != NULL) && (scp != NULL)) ? ", " : "", 5036 scp ? scp : ""); 5037 } 5038 } 5039 if (report || bootverbose) { 5040 printf(" at device %d.%d (no driver attached)\n", 5041 pci_get_slot(child), pci_get_function(child)); 5042 } 5043 pci_cfg_save(child, device_get_ivars(child), 1); 5044 } 5045 5046 void 5047 pci_child_detached(device_t dev, device_t child) 5048 { 5049 struct pci_devinfo *dinfo; 5050 struct resource_list *rl; 5051 5052 dinfo = device_get_ivars(child); 5053 rl = &dinfo->resources; 5054 5055 /* 5056 * Have to deallocate IRQs before releasing any MSI messages and 5057 * have to release MSI messages before deallocating any memory 5058 * BARs. 5059 */ 5060 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 5061 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 5062 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 5063 if (dinfo->cfg.msi.msi_alloc != 0) 5064 pci_printf(&dinfo->cfg, "Device leaked %d MSI " 5065 "vectors\n", dinfo->cfg.msi.msi_alloc); 5066 else 5067 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " 5068 "vectors\n", dinfo->cfg.msix.msix_alloc); 5069 (void)pci_release_msi(child); 5070 } 5071 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 5072 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 5073 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 5074 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 5075 #ifdef PCI_RES_BUS 5076 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 5077 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 5078 #endif 5079 5080 pci_cfg_save(child, dinfo, 1); 5081 } 5082 5083 /* 5084 * Parse the PCI device database, if loaded, and return a pointer to a 5085 * description of the device. 5086 * 5087 * The database is flat text formatted as follows: 5088 * 5089 * Any line not in a valid format is ignored. 5090 * Lines are terminated with newline '\n' characters. 5091 * 5092 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 5093 * the vendor name. 5094 * 5095 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5096 * - devices cannot be listed without a corresponding VENDOR line. 5097 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5098 * another TAB, then the device name. 5099 */ 5100 5101 /* 5102 * Assuming (ptr) points to the beginning of a line in the database, 5103 * return the vendor or device and description of the next entry. 5104 * The value of (vendor) or (device) inappropriate for the entry type 5105 * is set to -1. Returns nonzero at the end of the database. 5106 * 5107 * Note that this is slightly unrobust in the face of corrupt data; 5108 * we attempt to safeguard against this by spamming the end of the 5109 * database with a newline when we initialise. 5110 */ 5111 static int 5112 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5113 { 5114 char *cp = *ptr; 5115 int left; 5116 5117 *device = -1; 5118 *vendor = -1; 5119 **desc = '\0'; 5120 for (;;) { 5121 left = pci_vendordata_size - (cp - pci_vendordata); 5122 if (left <= 0) { 5123 *ptr = cp; 5124 return(1); 5125 } 5126 5127 /* vendor entry? */ 5128 if (*cp != '\t' && 5129 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5130 break; 5131 /* device entry? */ 5132 if (*cp == '\t' && 5133 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5134 break; 5135 5136 /* skip to next line */ 5137 while (*cp != '\n' && left > 0) { 5138 cp++; 5139 left--; 5140 } 5141 if (*cp == '\n') { 5142 cp++; 5143 left--; 5144 } 5145 } 5146 /* skip to next line */ 5147 while (*cp != '\n' && left > 0) { 5148 cp++; 5149 left--; 5150 } 5151 if (*cp == '\n' && left > 0) 5152 cp++; 5153 *ptr = cp; 5154 return(0); 5155 } 5156 5157 static char * 5158 pci_describe_device(device_t dev) 5159 { 5160 int vendor, device; 5161 char *desc, *vp, *dp, *line; 5162 5163 desc = vp = dp = NULL; 5164 5165 /* 5166 * If we have no vendor data, we can't do anything. 5167 */ 5168 if (pci_vendordata == NULL) 5169 goto out; 5170 5171 /* 5172 * Scan the vendor data looking for this device 5173 */ 5174 line = pci_vendordata; 5175 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5176 goto out; 5177 for (;;) { 5178 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5179 goto out; 5180 if (vendor == pci_get_vendor(dev)) 5181 break; 5182 } 5183 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5184 goto out; 5185 for (;;) { 5186 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5187 *dp = 0; 5188 break; 5189 } 5190 if (vendor != -1) { 5191 *dp = 0; 5192 break; 5193 } 5194 if (device == pci_get_device(dev)) 5195 break; 5196 } 5197 if (dp[0] == '\0') 5198 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5199 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5200 NULL) 5201 sprintf(desc, "%s, %s", vp, dp); 5202 out: 5203 if (vp != NULL) 5204 free(vp, M_DEVBUF); 5205 if (dp != NULL) 5206 free(dp, M_DEVBUF); 5207 return(desc); 5208 } 5209 5210 int 5211 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5212 { 5213 struct pci_devinfo *dinfo; 5214 pcicfgregs *cfg; 5215 5216 dinfo = device_get_ivars(child); 5217 cfg = &dinfo->cfg; 5218 5219 switch (which) { 5220 case PCI_IVAR_ETHADDR: 5221 /* 5222 * The generic accessor doesn't deal with failure, so 5223 * we set the return value, then return an error. 5224 */ 5225 *((uint8_t **) result) = NULL; 5226 return (EINVAL); 5227 case PCI_IVAR_SUBVENDOR: 5228 *result = cfg->subvendor; 5229 break; 5230 case PCI_IVAR_SUBDEVICE: 5231 *result = cfg->subdevice; 5232 break; 5233 case PCI_IVAR_VENDOR: 5234 *result = cfg->vendor; 5235 break; 5236 case PCI_IVAR_DEVICE: 5237 *result = cfg->device; 5238 break; 5239 case PCI_IVAR_DEVID: 5240 *result = (cfg->device << 16) | cfg->vendor; 5241 break; 5242 case PCI_IVAR_CLASS: 5243 *result = cfg->baseclass; 5244 break; 5245 case PCI_IVAR_SUBCLASS: 5246 *result = cfg->subclass; 5247 break; 5248 case PCI_IVAR_PROGIF: 5249 *result = cfg->progif; 5250 break; 5251 case PCI_IVAR_REVID: 5252 *result = cfg->revid; 5253 break; 5254 case PCI_IVAR_INTPIN: 5255 *result = cfg->intpin; 5256 break; 5257 case PCI_IVAR_IRQ: 5258 *result = cfg->intline; 5259 break; 5260 case PCI_IVAR_DOMAIN: 5261 *result = cfg->domain; 5262 break; 5263 case PCI_IVAR_BUS: 5264 *result = cfg->bus; 5265 break; 5266 case PCI_IVAR_SLOT: 5267 *result = cfg->slot; 5268 break; 5269 case PCI_IVAR_FUNCTION: 5270 *result = cfg->func; 5271 break; 5272 case PCI_IVAR_CMDREG: 5273 *result = cfg->cmdreg; 5274 break; 5275 case PCI_IVAR_CACHELNSZ: 5276 *result = cfg->cachelnsz; 5277 break; 5278 case PCI_IVAR_MINGNT: 5279 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5280 *result = -1; 5281 return (EINVAL); 5282 } 5283 *result = cfg->mingnt; 5284 break; 5285 case PCI_IVAR_MAXLAT: 5286 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5287 *result = -1; 5288 return (EINVAL); 5289 } 5290 *result = cfg->maxlat; 5291 break; 5292 case PCI_IVAR_LATTIMER: 5293 *result = cfg->lattimer; 5294 break; 5295 default: 5296 return (ENOENT); 5297 } 5298 return (0); 5299 } 5300 5301 int 5302 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5303 { 5304 struct pci_devinfo *dinfo; 5305 5306 dinfo = device_get_ivars(child); 5307 5308 switch (which) { 5309 case PCI_IVAR_INTPIN: 5310 dinfo->cfg.intpin = value; 5311 return (0); 5312 case PCI_IVAR_ETHADDR: 5313 case PCI_IVAR_SUBVENDOR: 5314 case PCI_IVAR_SUBDEVICE: 5315 case PCI_IVAR_VENDOR: 5316 case PCI_IVAR_DEVICE: 5317 case PCI_IVAR_DEVID: 5318 case PCI_IVAR_CLASS: 5319 case PCI_IVAR_SUBCLASS: 5320 case PCI_IVAR_PROGIF: 5321 case PCI_IVAR_REVID: 5322 case PCI_IVAR_IRQ: 5323 case PCI_IVAR_DOMAIN: 5324 case PCI_IVAR_BUS: 5325 case PCI_IVAR_SLOT: 5326 case PCI_IVAR_FUNCTION: 5327 return (EINVAL); /* disallow for now */ 5328 5329 default: 5330 return (ENOENT); 5331 } 5332 } 5333 5334 #include "opt_ddb.h" 5335 #ifdef DDB 5336 #include <ddb/ddb.h> 5337 #include <sys/cons.h> 5338 5339 /* 5340 * List resources based on pci map registers, used for within ddb 5341 */ 5342 5343 DB_SHOW_COMMAND(pciregs, db_pci_dump) 5344 { 5345 struct pci_devinfo *dinfo; 5346 struct devlist *devlist_head; 5347 struct pci_conf *p; 5348 const char *name; 5349 int i, error, none_count; 5350 5351 none_count = 0; 5352 /* get the head of the device queue */ 5353 devlist_head = &pci_devq; 5354 5355 /* 5356 * Go through the list of devices and print out devices 5357 */ 5358 for (error = 0, i = 0, 5359 dinfo = STAILQ_FIRST(devlist_head); 5360 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5361 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5362 /* Populate pd_name and pd_unit */ 5363 name = NULL; 5364 if (dinfo->cfg.dev) 5365 name = device_get_name(dinfo->cfg.dev); 5366 5367 p = &dinfo->conf; 5368 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5369 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5370 (name && *name) ? name : "none", 5371 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5372 none_count++, 5373 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5374 p->pc_sel.pc_func, (p->pc_class << 16) | 5375 (p->pc_subclass << 8) | p->pc_progif, 5376 (p->pc_subdevice << 16) | p->pc_subvendor, 5377 (p->pc_device << 16) | p->pc_vendor, 5378 p->pc_revid, p->pc_hdr); 5379 } 5380 } 5381 #endif /* DDB */ 5382 5383 struct resource * 5384 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5385 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5386 u_int flags) 5387 { 5388 struct pci_devinfo *dinfo = device_get_ivars(child); 5389 struct resource_list *rl = &dinfo->resources; 5390 struct resource *res; 5391 struct pci_map *pm; 5392 uint16_t cmd; 5393 pci_addr_t map, testval; 5394 int mapsize; 5395 5396 res = NULL; 5397 5398 /* If rid is managed by EA, ignore it */ 5399 if (pci_ea_is_enabled(child, *rid)) 5400 goto out; 5401 5402 pm = pci_find_bar(child, *rid); 5403 if (pm != NULL) { 5404 /* This is a BAR that we failed to allocate earlier. */ 5405 mapsize = pm->pm_size; 5406 map = pm->pm_value; 5407 } else { 5408 /* 5409 * Weed out the bogons, and figure out how large the 5410 * BAR/map is. BARs that read back 0 here are bogus 5411 * and unimplemented. Note: atapci in legacy mode are 5412 * special and handled elsewhere in the code. If you 5413 * have a atapci device in legacy mode and it fails 5414 * here, that other code is broken. 5415 */ 5416 pci_read_bar(child, *rid, &map, &testval, NULL); 5417 5418 /* 5419 * Determine the size of the BAR and ignore BARs with a size 5420 * of 0. Device ROM BARs use a different mask value. 5421 */ 5422 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5423 mapsize = pci_romsize(testval); 5424 else 5425 mapsize = pci_mapsize(testval); 5426 if (mapsize == 0) 5427 goto out; 5428 pm = pci_add_bar(child, *rid, map, mapsize); 5429 } 5430 5431 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5432 if (type != SYS_RES_MEMORY) { 5433 if (bootverbose) 5434 device_printf(dev, 5435 "child %s requested type %d for rid %#x," 5436 " but the BAR says it is an memio\n", 5437 device_get_nameunit(child), type, *rid); 5438 goto out; 5439 } 5440 } else { 5441 if (type != SYS_RES_IOPORT) { 5442 if (bootverbose) 5443 device_printf(dev, 5444 "child %s requested type %d for rid %#x," 5445 " but the BAR says it is an ioport\n", 5446 device_get_nameunit(child), type, *rid); 5447 goto out; 5448 } 5449 } 5450 5451 /* 5452 * For real BARs, we need to override the size that 5453 * the driver requests, because that's what the BAR 5454 * actually uses and we would otherwise have a 5455 * situation where we might allocate the excess to 5456 * another driver, which won't work. 5457 */ 5458 count = ((pci_addr_t)1 << mapsize) * num; 5459 if (RF_ALIGNMENT(flags) < mapsize) 5460 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5461 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5462 flags |= RF_PREFETCHABLE; 5463 5464 /* 5465 * Allocate enough resource, and then write back the 5466 * appropriate BAR for that resource. 5467 */ 5468 resource_list_add(rl, type, *rid, start, end, count); 5469 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5470 count, flags & ~RF_ACTIVE); 5471 if (res == NULL) { 5472 resource_list_delete(rl, type, *rid); 5473 device_printf(child, 5474 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5475 count, *rid, type, start, end); 5476 goto out; 5477 } 5478 if (bootverbose) 5479 device_printf(child, 5480 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5481 count, *rid, type, rman_get_start(res)); 5482 5483 /* Disable decoding via the CMD register before updating the BAR */ 5484 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5485 pci_write_config(child, PCIR_COMMAND, 5486 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5487 5488 map = rman_get_start(res); 5489 pci_write_bar(child, pm, map); 5490 5491 /* Restore the original value of the CMD register */ 5492 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5493 out: 5494 return (res); 5495 } 5496 5497 struct resource * 5498 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5499 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5500 u_int flags) 5501 { 5502 struct pci_devinfo *dinfo; 5503 struct resource_list *rl; 5504 struct resource_list_entry *rle; 5505 struct resource *res; 5506 pcicfgregs *cfg; 5507 5508 /* 5509 * Perform lazy resource allocation 5510 */ 5511 dinfo = device_get_ivars(child); 5512 rl = &dinfo->resources; 5513 cfg = &dinfo->cfg; 5514 switch (type) { 5515 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 5516 case PCI_RES_BUS: 5517 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5518 flags)); 5519 #endif 5520 case SYS_RES_IRQ: 5521 /* 5522 * Can't alloc legacy interrupt once MSI messages have 5523 * been allocated. 5524 */ 5525 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5526 cfg->msix.msix_alloc > 0)) 5527 return (NULL); 5528 5529 /* 5530 * If the child device doesn't have an interrupt 5531 * routed and is deserving of an interrupt, try to 5532 * assign it one. 5533 */ 5534 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5535 (cfg->intpin != 0)) 5536 pci_assign_interrupt(dev, child, 0); 5537 break; 5538 case SYS_RES_IOPORT: 5539 case SYS_RES_MEMORY: 5540 #ifdef NEW_PCIB 5541 /* 5542 * PCI-PCI bridge I/O window resources are not BARs. 5543 * For those allocations just pass the request up the 5544 * tree. 5545 */ 5546 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5547 switch (*rid) { 5548 case PCIR_IOBASEL_1: 5549 case PCIR_MEMBASE_1: 5550 case PCIR_PMBASEL_1: 5551 /* 5552 * XXX: Should we bother creating a resource 5553 * list entry? 5554 */ 5555 return (bus_generic_alloc_resource(dev, child, 5556 type, rid, start, end, count, flags)); 5557 } 5558 } 5559 #endif 5560 /* Reserve resources for this BAR if needed. */ 5561 rle = resource_list_find(rl, type, *rid); 5562 if (rle == NULL) { 5563 res = pci_reserve_map(dev, child, type, rid, start, end, 5564 count, num, flags); 5565 if (res == NULL) 5566 return (NULL); 5567 } 5568 } 5569 return (resource_list_alloc(rl, dev, child, type, rid, 5570 start, end, count, flags)); 5571 } 5572 5573 struct resource * 5574 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5575 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5576 { 5577 #ifdef PCI_IOV 5578 struct pci_devinfo *dinfo; 5579 #endif 5580 5581 if (device_get_parent(child) != dev) 5582 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5583 type, rid, start, end, count, flags)); 5584 5585 #ifdef PCI_IOV 5586 dinfo = device_get_ivars(child); 5587 if (dinfo->cfg.flags & PCICFG_VF) { 5588 switch (type) { 5589 /* VFs can't have I/O BARs. */ 5590 case SYS_RES_IOPORT: 5591 return (NULL); 5592 case SYS_RES_MEMORY: 5593 return (pci_vf_alloc_mem_resource(dev, child, rid, 5594 start, end, count, flags)); 5595 } 5596 5597 /* Fall through for other types of resource allocations. */ 5598 } 5599 #endif 5600 5601 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5602 count, 1, flags)); 5603 } 5604 5605 int 5606 pci_release_resource(device_t dev, device_t child, int type, int rid, 5607 struct resource *r) 5608 { 5609 struct pci_devinfo *dinfo; 5610 struct resource_list *rl; 5611 pcicfgregs *cfg; 5612 5613 if (device_get_parent(child) != dev) 5614 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 5615 type, rid, r)); 5616 5617 dinfo = device_get_ivars(child); 5618 cfg = &dinfo->cfg; 5619 5620 #ifdef PCI_IOV 5621 if (dinfo->cfg.flags & PCICFG_VF) { 5622 switch (type) { 5623 /* VFs can't have I/O BARs. */ 5624 case SYS_RES_IOPORT: 5625 return (EDOOFUS); 5626 case SYS_RES_MEMORY: 5627 return (pci_vf_release_mem_resource(dev, child, rid, 5628 r)); 5629 } 5630 5631 /* Fall through for other types of resource allocations. */ 5632 } 5633 #endif 5634 5635 #ifdef NEW_PCIB 5636 /* 5637 * PCI-PCI bridge I/O window resources are not BARs. For 5638 * those allocations just pass the request up the tree. 5639 */ 5640 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5641 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 5642 switch (rid) { 5643 case PCIR_IOBASEL_1: 5644 case PCIR_MEMBASE_1: 5645 case PCIR_PMBASEL_1: 5646 return (bus_generic_release_resource(dev, child, type, 5647 rid, r)); 5648 } 5649 } 5650 #endif 5651 5652 rl = &dinfo->resources; 5653 return (resource_list_release(rl, dev, child, type, rid, r)); 5654 } 5655 5656 int 5657 pci_activate_resource(device_t dev, device_t child, int type, int rid, 5658 struct resource *r) 5659 { 5660 struct pci_devinfo *dinfo; 5661 int error; 5662 5663 error = bus_generic_activate_resource(dev, child, type, rid, r); 5664 if (error) 5665 return (error); 5666 5667 /* Enable decoding in the command register when activating BARs. */ 5668 if (device_get_parent(child) == dev) { 5669 /* Device ROMs need their decoding explicitly enabled. */ 5670 dinfo = device_get_ivars(child); 5671 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5672 pci_write_bar(child, pci_find_bar(child, rid), 5673 rman_get_start(r) | PCIM_BIOS_ENABLE); 5674 switch (type) { 5675 case SYS_RES_IOPORT: 5676 case SYS_RES_MEMORY: 5677 error = PCI_ENABLE_IO(dev, child, type); 5678 break; 5679 } 5680 } 5681 return (error); 5682 } 5683 5684 int 5685 pci_deactivate_resource(device_t dev, device_t child, int type, 5686 int rid, struct resource *r) 5687 { 5688 struct pci_devinfo *dinfo; 5689 int error; 5690 5691 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 5692 if (error) 5693 return (error); 5694 5695 /* Disable decoding for device ROMs. */ 5696 if (device_get_parent(child) == dev) { 5697 dinfo = device_get_ivars(child); 5698 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5699 pci_write_bar(child, pci_find_bar(child, rid), 5700 rman_get_start(r)); 5701 } 5702 return (0); 5703 } 5704 5705 void 5706 pci_child_deleted(device_t dev, device_t child) 5707 { 5708 struct resource_list_entry *rle; 5709 struct resource_list *rl; 5710 struct pci_devinfo *dinfo; 5711 5712 dinfo = device_get_ivars(child); 5713 rl = &dinfo->resources; 5714 5715 EVENTHANDLER_INVOKE(pci_delete_device, child); 5716 5717 /* Turn off access to resources we're about to free */ 5718 if (bus_child_present(child) != 0) { 5719 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5720 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5721 5722 pci_disable_busmaster(child); 5723 } 5724 5725 /* Free all allocated resources */ 5726 STAILQ_FOREACH(rle, rl, link) { 5727 if (rle->res) { 5728 if (rman_get_flags(rle->res) & RF_ACTIVE || 5729 resource_list_busy(rl, rle->type, rle->rid)) { 5730 pci_printf(&dinfo->cfg, 5731 "Resource still owned, oops. " 5732 "(type=%d, rid=%d, addr=%lx)\n", 5733 rle->type, rle->rid, 5734 rman_get_start(rle->res)); 5735 bus_release_resource(child, rle->type, rle->rid, 5736 rle->res); 5737 } 5738 resource_list_unreserve(rl, dev, child, rle->type, 5739 rle->rid); 5740 } 5741 } 5742 resource_list_free(rl); 5743 5744 pci_freecfg(dinfo); 5745 } 5746 5747 void 5748 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5749 { 5750 struct pci_devinfo *dinfo; 5751 struct resource_list *rl; 5752 struct resource_list_entry *rle; 5753 5754 if (device_get_parent(child) != dev) 5755 return; 5756 5757 dinfo = device_get_ivars(child); 5758 rl = &dinfo->resources; 5759 rle = resource_list_find(rl, type, rid); 5760 if (rle == NULL) 5761 return; 5762 5763 if (rle->res) { 5764 if (rman_get_flags(rle->res) & RF_ACTIVE || 5765 resource_list_busy(rl, type, rid)) { 5766 device_printf(dev, "delete_resource: " 5767 "Resource still owned by child, oops. " 5768 "(type=%d, rid=%d, addr=%jx)\n", 5769 type, rid, rman_get_start(rle->res)); 5770 return; 5771 } 5772 resource_list_unreserve(rl, dev, child, type, rid); 5773 } 5774 resource_list_delete(rl, type, rid); 5775 } 5776 5777 struct resource_list * 5778 pci_get_resource_list (device_t dev, device_t child) 5779 { 5780 struct pci_devinfo *dinfo = device_get_ivars(child); 5781 5782 return (&dinfo->resources); 5783 } 5784 5785 #ifdef IOMMU 5786 bus_dma_tag_t 5787 pci_get_dma_tag(device_t bus, device_t dev) 5788 { 5789 bus_dma_tag_t tag; 5790 struct pci_softc *sc; 5791 5792 if (device_get_parent(dev) == bus) { 5793 /* try iommu and return if it works */ 5794 tag = iommu_get_dma_tag(bus, dev); 5795 } else 5796 tag = NULL; 5797 if (tag == NULL) { 5798 sc = device_get_softc(bus); 5799 tag = sc->sc_dma_tag; 5800 } 5801 return (tag); 5802 } 5803 #else 5804 bus_dma_tag_t 5805 pci_get_dma_tag(device_t bus, device_t dev) 5806 { 5807 struct pci_softc *sc = device_get_softc(bus); 5808 5809 return (sc->sc_dma_tag); 5810 } 5811 #endif 5812 5813 uint32_t 5814 pci_read_config_method(device_t dev, device_t child, int reg, int width) 5815 { 5816 struct pci_devinfo *dinfo = device_get_ivars(child); 5817 pcicfgregs *cfg = &dinfo->cfg; 5818 5819 #ifdef PCI_IOV 5820 /* 5821 * SR-IOV VFs don't implement the VID or DID registers, so we have to 5822 * emulate them here. 5823 */ 5824 if (cfg->flags & PCICFG_VF) { 5825 if (reg == PCIR_VENDOR) { 5826 switch (width) { 5827 case 4: 5828 return (cfg->device << 16 | cfg->vendor); 5829 case 2: 5830 return (cfg->vendor); 5831 case 1: 5832 return (cfg->vendor & 0xff); 5833 default: 5834 return (0xffffffff); 5835 } 5836 } else if (reg == PCIR_DEVICE) { 5837 switch (width) { 5838 /* Note that an unaligned 4-byte read is an error. */ 5839 case 2: 5840 return (cfg->device); 5841 case 1: 5842 return (cfg->device & 0xff); 5843 default: 5844 return (0xffffffff); 5845 } 5846 } 5847 } 5848 #endif 5849 5850 return (PCIB_READ_CONFIG(device_get_parent(dev), 5851 cfg->bus, cfg->slot, cfg->func, reg, width)); 5852 } 5853 5854 void 5855 pci_write_config_method(device_t dev, device_t child, int reg, 5856 uint32_t val, int width) 5857 { 5858 struct pci_devinfo *dinfo = device_get_ivars(child); 5859 pcicfgregs *cfg = &dinfo->cfg; 5860 5861 PCIB_WRITE_CONFIG(device_get_parent(dev), 5862 cfg->bus, cfg->slot, cfg->func, reg, val, width); 5863 } 5864 5865 int 5866 pci_child_location_method(device_t dev, device_t child, struct sbuf *sb) 5867 { 5868 5869 sbuf_printf(sb, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 5870 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 5871 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 5872 return (0); 5873 } 5874 5875 int 5876 pci_child_pnpinfo_method(device_t dev, device_t child, struct sbuf *sb) 5877 { 5878 struct pci_devinfo *dinfo; 5879 pcicfgregs *cfg; 5880 5881 dinfo = device_get_ivars(child); 5882 cfg = &dinfo->cfg; 5883 sbuf_printf(sb, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 5884 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 5885 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 5886 cfg->progif); 5887 return (0); 5888 } 5889 5890 int 5891 pci_assign_interrupt_method(device_t dev, device_t child) 5892 { 5893 struct pci_devinfo *dinfo = device_get_ivars(child); 5894 pcicfgregs *cfg = &dinfo->cfg; 5895 5896 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 5897 cfg->intpin)); 5898 } 5899 5900 static void 5901 pci_lookup(void *arg, const char *name, device_t *dev) 5902 { 5903 long val; 5904 char *end; 5905 int domain, bus, slot, func; 5906 5907 if (*dev != NULL) 5908 return; 5909 5910 /* 5911 * Accept pciconf-style selectors of either pciD:B:S:F or 5912 * pciB:S:F. In the latter case, the domain is assumed to 5913 * be zero. 5914 */ 5915 if (strncmp(name, "pci", 3) != 0) 5916 return; 5917 val = strtol(name + 3, &end, 10); 5918 if (val < 0 || val > INT_MAX || *end != ':') 5919 return; 5920 domain = val; 5921 val = strtol(end + 1, &end, 10); 5922 if (val < 0 || val > INT_MAX || *end != ':') 5923 return; 5924 bus = val; 5925 val = strtol(end + 1, &end, 10); 5926 if (val < 0 || val > INT_MAX) 5927 return; 5928 slot = val; 5929 if (*end == ':') { 5930 val = strtol(end + 1, &end, 10); 5931 if (val < 0 || val > INT_MAX || *end != '\0') 5932 return; 5933 func = val; 5934 } else if (*end == '\0') { 5935 func = slot; 5936 slot = bus; 5937 bus = domain; 5938 domain = 0; 5939 } else 5940 return; 5941 5942 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 5943 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 5944 return; 5945 5946 *dev = pci_find_dbsf(domain, bus, slot, func); 5947 } 5948 5949 static int 5950 pci_modevent(module_t mod, int what, void *arg) 5951 { 5952 static struct cdev *pci_cdev; 5953 static eventhandler_tag tag; 5954 5955 switch (what) { 5956 case MOD_LOAD: 5957 STAILQ_INIT(&pci_devq); 5958 pci_generation = 0; 5959 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 5960 "pci"); 5961 pci_load_vendor_data(); 5962 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 5963 1000); 5964 break; 5965 5966 case MOD_UNLOAD: 5967 if (tag != NULL) 5968 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 5969 destroy_dev(pci_cdev); 5970 break; 5971 } 5972 5973 return (0); 5974 } 5975 5976 static void 5977 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 5978 { 5979 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 5980 struct pcicfg_pcie *cfg; 5981 int version, pos; 5982 5983 cfg = &dinfo->cfg.pcie; 5984 pos = cfg->pcie_location; 5985 5986 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 5987 5988 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 5989 5990 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5991 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 5992 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 5993 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 5994 5995 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5996 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 5997 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 5998 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 5999 6000 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6001 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6002 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 6003 6004 if (version > 1) { 6005 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 6006 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 6007 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 6008 } 6009 #undef WREG 6010 } 6011 6012 static void 6013 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 6014 { 6015 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 6016 dinfo->cfg.pcix.pcix_command, 2); 6017 } 6018 6019 void 6020 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 6021 { 6022 6023 /* 6024 * Restore the device to full power mode. We must do this 6025 * before we restore the registers because moving from D3 to 6026 * D0 will cause the chip's BARs and some other registers to 6027 * be reset to some unknown power on reset values. Cut down 6028 * the noise on boot by doing nothing if we are already in 6029 * state D0. 6030 */ 6031 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 6032 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6033 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 6034 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 6035 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 6036 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 6037 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 6038 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 6039 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6040 case PCIM_HDRTYPE_NORMAL: 6041 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 6042 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 6043 break; 6044 case PCIM_HDRTYPE_BRIDGE: 6045 pci_write_config(dev, PCIR_SECLAT_1, 6046 dinfo->cfg.bridge.br_seclat, 1); 6047 pci_write_config(dev, PCIR_SUBBUS_1, 6048 dinfo->cfg.bridge.br_subbus, 1); 6049 pci_write_config(dev, PCIR_SECBUS_1, 6050 dinfo->cfg.bridge.br_secbus, 1); 6051 pci_write_config(dev, PCIR_PRIBUS_1, 6052 dinfo->cfg.bridge.br_pribus, 1); 6053 pci_write_config(dev, PCIR_BRIDGECTL_1, 6054 dinfo->cfg.bridge.br_control, 2); 6055 break; 6056 case PCIM_HDRTYPE_CARDBUS: 6057 pci_write_config(dev, PCIR_SECLAT_2, 6058 dinfo->cfg.bridge.br_seclat, 1); 6059 pci_write_config(dev, PCIR_SUBBUS_2, 6060 dinfo->cfg.bridge.br_subbus, 1); 6061 pci_write_config(dev, PCIR_SECBUS_2, 6062 dinfo->cfg.bridge.br_secbus, 1); 6063 pci_write_config(dev, PCIR_PRIBUS_2, 6064 dinfo->cfg.bridge.br_pribus, 1); 6065 pci_write_config(dev, PCIR_BRIDGECTL_2, 6066 dinfo->cfg.bridge.br_control, 2); 6067 break; 6068 } 6069 pci_restore_bars(dev); 6070 6071 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 6072 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 6073 6074 /* 6075 * Restore extended capabilities for PCI-Express and PCI-X 6076 */ 6077 if (dinfo->cfg.pcie.pcie_location != 0) 6078 pci_cfg_restore_pcie(dev, dinfo); 6079 if (dinfo->cfg.pcix.pcix_location != 0) 6080 pci_cfg_restore_pcix(dev, dinfo); 6081 6082 /* Restore MSI and MSI-X configurations if they are present. */ 6083 if (dinfo->cfg.msi.msi_location != 0) 6084 pci_resume_msi(dev); 6085 if (dinfo->cfg.msix.msix_location != 0) 6086 pci_resume_msix(dev); 6087 6088 #ifdef PCI_IOV 6089 if (dinfo->cfg.iov != NULL) 6090 pci_iov_cfg_restore(dev, dinfo); 6091 #endif 6092 } 6093 6094 static void 6095 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6096 { 6097 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6098 struct pcicfg_pcie *cfg; 6099 int version, pos; 6100 6101 cfg = &dinfo->cfg.pcie; 6102 pos = cfg->pcie_location; 6103 6104 cfg->pcie_flags = RREG(PCIER_FLAGS); 6105 6106 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6107 6108 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6109 6110 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6111 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6112 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6113 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6114 6115 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6116 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6117 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6118 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6119 6120 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6121 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6122 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6123 6124 if (version > 1) { 6125 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6126 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6127 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6128 } 6129 #undef RREG 6130 } 6131 6132 static void 6133 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6134 { 6135 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6136 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6137 } 6138 6139 void 6140 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6141 { 6142 uint32_t cls; 6143 int ps; 6144 6145 /* 6146 * Some drivers apparently write to these registers w/o updating our 6147 * cached copy. No harm happens if we update the copy, so do so here 6148 * so we can restore them. The COMMAND register is modified by the 6149 * bus w/o updating the cache. This should represent the normally 6150 * writable portion of the 'defined' part of type 0/1/2 headers. 6151 */ 6152 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6153 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6154 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6155 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6156 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6157 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6158 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6159 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6160 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6161 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6162 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6163 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6164 case PCIM_HDRTYPE_NORMAL: 6165 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6166 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6167 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6168 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6169 break; 6170 case PCIM_HDRTYPE_BRIDGE: 6171 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6172 PCIR_SECLAT_1, 1); 6173 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6174 PCIR_SUBBUS_1, 1); 6175 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6176 PCIR_SECBUS_1, 1); 6177 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6178 PCIR_PRIBUS_1, 1); 6179 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6180 PCIR_BRIDGECTL_1, 2); 6181 break; 6182 case PCIM_HDRTYPE_CARDBUS: 6183 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6184 PCIR_SECLAT_2, 1); 6185 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6186 PCIR_SUBBUS_2, 1); 6187 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6188 PCIR_SECBUS_2, 1); 6189 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6190 PCIR_PRIBUS_2, 1); 6191 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6192 PCIR_BRIDGECTL_2, 2); 6193 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6194 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6195 break; 6196 } 6197 6198 if (dinfo->cfg.pcie.pcie_location != 0) 6199 pci_cfg_save_pcie(dev, dinfo); 6200 6201 if (dinfo->cfg.pcix.pcix_location != 0) 6202 pci_cfg_save_pcix(dev, dinfo); 6203 6204 #ifdef PCI_IOV 6205 if (dinfo->cfg.iov != NULL) 6206 pci_iov_cfg_save(dev, dinfo); 6207 #endif 6208 6209 /* 6210 * don't set the state for display devices, base peripherals and 6211 * memory devices since bad things happen when they are powered down. 6212 * We should (a) have drivers that can easily detach and (b) use 6213 * generic drivers for these devices so that some device actually 6214 * attaches. We need to make sure that when we implement (a) we don't 6215 * power the device down on a reattach. 6216 */ 6217 cls = pci_get_class(dev); 6218 if (!setstate) 6219 return; 6220 switch (pci_do_power_nodriver) 6221 { 6222 case 0: /* NO powerdown at all */ 6223 return; 6224 case 1: /* Conservative about what to power down */ 6225 if (cls == PCIC_STORAGE) 6226 return; 6227 /*FALLTHROUGH*/ 6228 case 2: /* Aggressive about what to power down */ 6229 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6230 cls == PCIC_BASEPERIPH) 6231 return; 6232 /*FALLTHROUGH*/ 6233 case 3: /* Power down everything */ 6234 break; 6235 } 6236 /* 6237 * PCI spec says we can only go into D3 state from D0 state. 6238 * Transition from D[12] into D0 before going to D3 state. 6239 */ 6240 ps = pci_get_powerstate(dev); 6241 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6242 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6243 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6244 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6245 } 6246 6247 /* Wrapper APIs suitable for device driver use. */ 6248 void 6249 pci_save_state(device_t dev) 6250 { 6251 struct pci_devinfo *dinfo; 6252 6253 dinfo = device_get_ivars(dev); 6254 pci_cfg_save(dev, dinfo, 0); 6255 } 6256 6257 void 6258 pci_restore_state(device_t dev) 6259 { 6260 struct pci_devinfo *dinfo; 6261 6262 dinfo = device_get_ivars(dev); 6263 pci_cfg_restore(dev, dinfo); 6264 } 6265 6266 static int 6267 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6268 uintptr_t *id) 6269 { 6270 6271 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6272 } 6273 6274 /* Find the upstream port of a given PCI device in a root complex. */ 6275 device_t 6276 pci_find_pcie_root_port(device_t dev) 6277 { 6278 struct pci_devinfo *dinfo; 6279 devclass_t pci_class; 6280 device_t pcib, bus; 6281 6282 pci_class = devclass_find("pci"); 6283 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6284 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6285 6286 /* 6287 * Walk the bridge hierarchy until we find a PCI-e root 6288 * port or a non-PCI device. 6289 */ 6290 for (;;) { 6291 bus = device_get_parent(dev); 6292 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6293 device_get_nameunit(dev))); 6294 6295 pcib = device_get_parent(bus); 6296 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6297 device_get_nameunit(bus))); 6298 6299 /* 6300 * pcib's parent must be a PCI bus for this to be a 6301 * PCI-PCI bridge. 6302 */ 6303 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6304 return (NULL); 6305 6306 dinfo = device_get_ivars(pcib); 6307 if (dinfo->cfg.pcie.pcie_location != 0 && 6308 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6309 return (pcib); 6310 6311 dev = pcib; 6312 } 6313 } 6314 6315 /* 6316 * Wait for pending transactions to complete on a PCI-express function. 6317 * 6318 * The maximum delay is specified in milliseconds in max_delay. Note 6319 * that this function may sleep. 6320 * 6321 * Returns true if the function is idle and false if the timeout is 6322 * exceeded. If dev is not a PCI-express function, this returns true. 6323 */ 6324 bool 6325 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6326 { 6327 struct pci_devinfo *dinfo = device_get_ivars(dev); 6328 uint16_t sta; 6329 int cap; 6330 6331 cap = dinfo->cfg.pcie.pcie_location; 6332 if (cap == 0) 6333 return (true); 6334 6335 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6336 while (sta & PCIEM_STA_TRANSACTION_PND) { 6337 if (max_delay == 0) 6338 return (false); 6339 6340 /* Poll once every 100 milliseconds up to the timeout. */ 6341 if (max_delay > 100) { 6342 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6343 max_delay -= 100; 6344 } else { 6345 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6346 C_HARDCLOCK); 6347 max_delay = 0; 6348 } 6349 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6350 } 6351 6352 return (true); 6353 } 6354 6355 /* 6356 * Determine the maximum Completion Timeout in microseconds. 6357 * 6358 * For non-PCI-express functions this returns 0. 6359 */ 6360 int 6361 pcie_get_max_completion_timeout(device_t dev) 6362 { 6363 struct pci_devinfo *dinfo = device_get_ivars(dev); 6364 int cap; 6365 6366 cap = dinfo->cfg.pcie.pcie_location; 6367 if (cap == 0) 6368 return (0); 6369 6370 /* 6371 * Functions using the 1.x spec use the default timeout range of 6372 * 50 microseconds to 50 milliseconds. Functions that do not 6373 * support programmable timeouts also use this range. 6374 */ 6375 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6376 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6377 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6378 return (50 * 1000); 6379 6380 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6381 PCIEM_CTL2_COMP_TIMO_VAL) { 6382 case PCIEM_CTL2_COMP_TIMO_100US: 6383 return (100); 6384 case PCIEM_CTL2_COMP_TIMO_10MS: 6385 return (10 * 1000); 6386 case PCIEM_CTL2_COMP_TIMO_55MS: 6387 return (55 * 1000); 6388 case PCIEM_CTL2_COMP_TIMO_210MS: 6389 return (210 * 1000); 6390 case PCIEM_CTL2_COMP_TIMO_900MS: 6391 return (900 * 1000); 6392 case PCIEM_CTL2_COMP_TIMO_3500MS: 6393 return (3500 * 1000); 6394 case PCIEM_CTL2_COMP_TIMO_13S: 6395 return (13 * 1000 * 1000); 6396 case PCIEM_CTL2_COMP_TIMO_64S: 6397 return (64 * 1000 * 1000); 6398 default: 6399 return (50 * 1000); 6400 } 6401 } 6402 6403 void 6404 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6405 { 6406 struct pci_devinfo *dinfo = device_get_ivars(dev); 6407 const char *s; 6408 int aer; 6409 uint32_t r, r1; 6410 uint16_t rs; 6411 6412 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6413 s = "Correctable"; 6414 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6415 s = "Uncorrectable (Non-Fatal)"; 6416 else 6417 s = "Uncorrectable (Fatal)"; 6418 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6419 if (aerp) { 6420 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6421 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6422 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6423 } else { 6424 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6425 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6426 } 6427 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6428 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6429 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6430 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6431 printf(" severity 0x%08x first %d\n", 6432 r, rs & 0x1f); 6433 } else 6434 printf("\n"); 6435 } 6436 6437 /* As kind of recovery just report and clear the error statuses. */ 6438 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6439 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6440 if (r != 0) { 6441 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6442 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6443 } 6444 6445 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6446 if (r != 0) { 6447 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6448 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6449 } 6450 } 6451 if (dinfo->cfg.pcie.pcie_location != 0) { 6452 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6453 PCIER_DEVICE_STA, 2); 6454 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6455 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6456 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6457 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6458 PCIER_DEVICE_STA, rs, 2); 6459 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6460 } 6461 } 6462 } 6463 6464 /* 6465 * Perform a Function Level Reset (FLR) on a device. 6466 * 6467 * This function first waits for any pending transactions to complete 6468 * within the timeout specified by max_delay. If transactions are 6469 * still pending, the function will return false without attempting a 6470 * reset. 6471 * 6472 * If dev is not a PCI-express function or does not support FLR, this 6473 * function returns false. 6474 * 6475 * Note that no registers are saved or restored. The caller is 6476 * responsible for saving and restoring any registers including 6477 * PCI-standard registers via pci_save_state() and 6478 * pci_restore_state(). 6479 */ 6480 bool 6481 pcie_flr(device_t dev, u_int max_delay, bool force) 6482 { 6483 struct pci_devinfo *dinfo = device_get_ivars(dev); 6484 uint16_t cmd, ctl; 6485 int compl_delay; 6486 int cap; 6487 6488 cap = dinfo->cfg.pcie.pcie_location; 6489 if (cap == 0) 6490 return (false); 6491 6492 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6493 return (false); 6494 6495 /* 6496 * Disable busmastering to prevent generation of new 6497 * transactions while waiting for the device to go idle. If 6498 * the idle timeout fails, the command register is restored 6499 * which will re-enable busmastering. 6500 */ 6501 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6502 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6503 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6504 if (!force) { 6505 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6506 return (false); 6507 } 6508 pci_printf(&dinfo->cfg, 6509 "Resetting with transactions pending after %d ms\n", 6510 max_delay); 6511 6512 /* 6513 * Extend the post-FLR delay to cover the maximum 6514 * Completion Timeout delay of anything in flight 6515 * during the FLR delay. Enforce a minimum delay of 6516 * at least 10ms. 6517 */ 6518 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6519 if (compl_delay < 10) 6520 compl_delay = 10; 6521 } else 6522 compl_delay = 0; 6523 6524 /* Initiate the reset. */ 6525 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6526 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6527 PCIEM_CTL_INITIATE_FLR, 2); 6528 6529 /* Wait for 100ms. */ 6530 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6531 6532 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6533 PCIEM_STA_TRANSACTION_PND) 6534 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6535 return (true); 6536 } 6537 6538 /* 6539 * Attempt a power-management reset by cycling the device in/out of D3 6540 * state. PCI spec says we can only go into D3 state from D0 state. 6541 * Transition from D[12] into D0 before going to D3 state. 6542 */ 6543 int 6544 pci_power_reset(device_t dev) 6545 { 6546 int ps; 6547 6548 ps = pci_get_powerstate(dev); 6549 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6550 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6551 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6552 pci_set_powerstate(dev, ps); 6553 return (0); 6554 } 6555 6556 /* 6557 * Try link drop and retrain of the downstream port of upstream 6558 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6559 * cause Conventional Hot reset of the device in the slot. 6560 * Alternative, for PCIe, could be the secondary bus reset initiatied 6561 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6562 */ 6563 int 6564 pcie_link_reset(device_t port, int pcie_location) 6565 { 6566 uint16_t v; 6567 6568 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6569 v |= PCIEM_LINK_CTL_LINK_DIS; 6570 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6571 pause_sbt("pcier1", mstosbt(20), 0, 0); 6572 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6573 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6574 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6575 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6576 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6577 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6578 } 6579 6580 static int 6581 pci_reset_post(device_t dev, device_t child) 6582 { 6583 6584 if (dev == device_get_parent(child)) 6585 pci_restore_state(child); 6586 return (0); 6587 } 6588 6589 static int 6590 pci_reset_prepare(device_t dev, device_t child) 6591 { 6592 6593 if (dev == device_get_parent(child)) 6594 pci_save_state(child); 6595 return (0); 6596 } 6597 6598 static int 6599 pci_reset_child(device_t dev, device_t child, int flags) 6600 { 6601 int error; 6602 6603 if (dev == NULL || device_get_parent(child) != dev) 6604 return (0); 6605 if ((flags & DEVF_RESET_DETACH) != 0) { 6606 error = device_get_state(child) == DS_ATTACHED ? 6607 device_detach(child) : 0; 6608 } else { 6609 error = BUS_SUSPEND_CHILD(dev, child); 6610 } 6611 if (error == 0) { 6612 if (!pcie_flr(child, 1000, false)) { 6613 error = BUS_RESET_PREPARE(dev, child); 6614 if (error == 0) 6615 pci_power_reset(child); 6616 BUS_RESET_POST(dev, child); 6617 } 6618 if ((flags & DEVF_RESET_DETACH) != 0) 6619 device_probe_and_attach(child); 6620 else 6621 BUS_RESUME_CHILD(dev, child); 6622 } 6623 return (error); 6624 } 6625 6626 const struct pci_device_table * 6627 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6628 { 6629 bool match; 6630 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6631 6632 vendor = pci_get_vendor(child); 6633 device = pci_get_device(child); 6634 subvendor = pci_get_subvendor(child); 6635 subdevice = pci_get_subdevice(child); 6636 class = pci_get_class(child); 6637 subclass = pci_get_subclass(child); 6638 revid = pci_get_revid(child); 6639 while (nelt-- > 0) { 6640 match = true; 6641 if (id->match_flag_vendor) 6642 match &= vendor == id->vendor; 6643 if (id->match_flag_device) 6644 match &= device == id->device; 6645 if (id->match_flag_subvendor) 6646 match &= subvendor == id->subvendor; 6647 if (id->match_flag_subdevice) 6648 match &= subdevice == id->subdevice; 6649 if (id->match_flag_class) 6650 match &= class == id->class_id; 6651 if (id->match_flag_subclass) 6652 match &= subclass == id->subclass; 6653 if (id->match_flag_revid) 6654 match &= revid == id->revid; 6655 if (match) 6656 return (id); 6657 id++; 6658 } 6659 return (NULL); 6660 } 6661 6662 static void 6663 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6664 { 6665 const char *dev_name; 6666 device_t dev; 6667 6668 dev = dinfo->cfg.dev; 6669 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6670 dinfo->cfg.slot, dinfo->cfg.func); 6671 dev_name = device_get_name(dev); 6672 if (dev_name != NULL) 6673 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6674 } 6675 6676 void 6677 pci_print_faulted_dev(void) 6678 { 6679 struct pci_devinfo *dinfo; 6680 device_t dev; 6681 int aer, i; 6682 uint32_t r1, r2; 6683 uint16_t status; 6684 6685 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6686 dev = dinfo->cfg.dev; 6687 status = pci_read_config(dev, PCIR_STATUS, 2); 6688 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6689 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6690 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6691 if (status != 0) { 6692 pci_print_faulted_dev_name(dinfo); 6693 printf(" error 0x%04x\n", status); 6694 } 6695 if (dinfo->cfg.pcie.pcie_location != 0) { 6696 status = pci_read_config(dev, 6697 dinfo->cfg.pcie.pcie_location + 6698 PCIER_DEVICE_STA, 2); 6699 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6700 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6701 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6702 pci_print_faulted_dev_name(dinfo); 6703 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6704 pci_read_config(dev, 6705 dinfo->cfg.pcie.pcie_location + 6706 PCIER_DEVICE_CTL, 2), 6707 status); 6708 } 6709 } 6710 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6711 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6712 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6713 if (r1 != 0 || r2 != 0) { 6714 pci_print_faulted_dev_name(dinfo); 6715 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6716 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6717 r1, pci_read_config(dev, aer + 6718 PCIR_AER_UC_MASK, 4), 6719 pci_read_config(dev, aer + 6720 PCIR_AER_UC_SEVERITY, 4), 6721 r2, pci_read_config(dev, aer + 6722 PCIR_AER_COR_MASK, 4), 6723 pci_read_config(dev, aer + 6724 PCIR_AER_CAP_CONTROL, 4)); 6725 for (i = 0; i < 4; i++) { 6726 r1 = pci_read_config(dev, aer + 6727 PCIR_AER_HEADER_LOG + i * 4, 4); 6728 printf(" HL%d: 0x%08x\n", i, r1); 6729 } 6730 } 6731 } 6732 } 6733 } 6734 6735 #ifdef DDB 6736 DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db) 6737 { 6738 6739 pci_print_faulted_dev(); 6740 } 6741 6742 static void 6743 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6744 { 6745 device_t dev; 6746 int aer; 6747 uint32_t r; 6748 6749 dev = dinfo->cfg.dev; 6750 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6751 PCIER_DEVICE_STA, 2); 6752 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6753 PCIER_DEVICE_STA, r, 2); 6754 6755 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6756 return; 6757 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6758 if (r != 0) 6759 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6760 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6761 if (r != 0) 6762 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6763 } 6764 6765 DB_COMMAND(pci_clearerr, db_pci_clearerr) 6766 { 6767 struct pci_devinfo *dinfo; 6768 device_t dev; 6769 uint16_t status, status1; 6770 6771 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6772 dev = dinfo->cfg.dev; 6773 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 6774 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6775 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6776 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6777 if (status1 != 0) { 6778 status &= ~status1; 6779 pci_write_config(dev, PCIR_STATUS, status, 2); 6780 } 6781 if (dinfo->cfg.pcie.pcie_location != 0) 6782 db_clear_pcie_errors(dinfo); 6783 } 6784 } 6785 #endif 6786