1 /*- 2 * Copyright (c) 2015, 2020 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2014 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Semihalf under 7 * the sponsorship of the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Generic ECAM PCIe driver */ 32 33 #include <sys/cdefs.h> 34 #include "opt_platform.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/rman.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcib_private.h> 48 #include <dev/pci/pci_host_generic.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include "pcib_if.h" 54 55 #if defined(VM_MEMATTR_DEVICE_NP) 56 #define PCI_UNMAPPED 57 #define PCI_RF_FLAGS RF_UNMAPPED 58 #else 59 #define PCI_RF_FLAGS 0 60 #endif 61 62 63 /* Forward prototypes */ 64 65 static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, 66 u_int func, u_int reg, int bytes); 67 static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, 68 u_int func, u_int reg, uint32_t val, int bytes); 69 static int generic_pcie_maxslots(device_t dev); 70 static int generic_pcie_read_ivar(device_t dev, device_t child, int index, 71 uintptr_t *result); 72 static int generic_pcie_write_ivar(device_t dev, device_t child, int index, 73 uintptr_t value); 74 75 int 76 pci_host_generic_core_attach(device_t dev) 77 { 78 #ifdef PCI_UNMAPPED 79 struct resource_map_request req; 80 struct resource_map map; 81 #endif 82 struct generic_pcie_core_softc *sc; 83 uint64_t phys_base; 84 uint64_t pci_base; 85 uint64_t size; 86 int error; 87 int rid, tuple; 88 89 sc = device_get_softc(dev); 90 sc->dev = dev; 91 92 /* Create the parent DMA tag to pass down the coherent flag */ 93 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 94 1, 0, /* alignment, bounds */ 95 BUS_SPACE_MAXADDR, /* lowaddr */ 96 BUS_SPACE_MAXADDR, /* highaddr */ 97 NULL, NULL, /* filter, filterarg */ 98 BUS_SPACE_MAXSIZE, /* maxsize */ 99 BUS_SPACE_UNRESTRICTED, /* nsegments */ 100 BUS_SPACE_MAXSIZE, /* maxsegsize */ 101 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ 102 NULL, NULL, /* lockfunc, lockarg */ 103 &sc->dmat); 104 if (error != 0) 105 return (error); 106 107 if ((sc->quirks & PCIE_CUSTOM_CONFIG_SPACE_QUIRK) == 0) { 108 rid = 0; 109 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 110 PCI_RF_FLAGS | RF_ACTIVE); 111 if (sc->res == NULL) { 112 device_printf(dev, "could not allocate memory.\n"); 113 error = ENXIO; 114 goto err_resource; 115 } 116 #ifdef PCI_UNMAPPED 117 resource_init_map_request(&req); 118 req.memattr = VM_MEMATTR_DEVICE_NP; 119 error = bus_map_resource(dev, SYS_RES_MEMORY, sc->res, &req, 120 &map); 121 if (error != 0) { 122 device_printf(dev, "could not map memory.\n"); 123 return (error); 124 } 125 rman_set_mapping(sc->res, &map); 126 #endif 127 } 128 129 sc->has_pmem = false; 130 sc->pmem_rman.rm_type = RMAN_ARRAY; 131 sc->pmem_rman.rm_descr = "PCIe Prefetch Memory"; 132 133 sc->mem_rman.rm_type = RMAN_ARRAY; 134 sc->mem_rman.rm_descr = "PCIe Memory"; 135 136 sc->io_rman.rm_type = RMAN_ARRAY; 137 sc->io_rman.rm_descr = "PCIe IO window"; 138 139 /* Initialize rman and allocate memory regions */ 140 error = rman_init(&sc->pmem_rman); 141 if (error) { 142 device_printf(dev, "rman_init() failed. error = %d\n", error); 143 goto err_pmem_rman; 144 } 145 146 error = rman_init(&sc->mem_rman); 147 if (error) { 148 device_printf(dev, "rman_init() failed. error = %d\n", error); 149 goto err_mem_rman; 150 } 151 152 error = rman_init(&sc->io_rman); 153 if (error) { 154 device_printf(dev, "rman_init() failed. error = %d\n", error); 155 goto err_io_rman; 156 } 157 158 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 159 phys_base = sc->ranges[tuple].phys_base; 160 pci_base = sc->ranges[tuple].pci_base; 161 size = sc->ranges[tuple].size; 162 if (phys_base == 0 || size == 0) 163 continue; /* empty range element */ 164 switch (FLAG_TYPE(sc->ranges[tuple].flags)) { 165 case FLAG_TYPE_PMEM: 166 sc->has_pmem = true; 167 error = rman_manage_region(&sc->pmem_rman, 168 pci_base, pci_base + size - 1); 169 break; 170 case FLAG_TYPE_MEM: 171 error = rman_manage_region(&sc->mem_rman, 172 pci_base, pci_base + size - 1); 173 break; 174 case FLAG_TYPE_IO: 175 error = rman_manage_region(&sc->io_rman, 176 pci_base, pci_base + size - 1); 177 break; 178 default: 179 continue; 180 } 181 if (error) { 182 device_printf(dev, "rman_manage_region() failed." 183 "error = %d\n", error); 184 goto err_rman_manage; 185 } 186 } 187 188 return (0); 189 190 err_rman_manage: 191 rman_fini(&sc->io_rman); 192 err_io_rman: 193 rman_fini(&sc->mem_rman); 194 err_mem_rman: 195 rman_fini(&sc->pmem_rman); 196 err_pmem_rman: 197 if (sc->res != NULL) 198 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); 199 err_resource: 200 bus_dma_tag_destroy(sc->dmat); 201 return (error); 202 } 203 204 int 205 pci_host_generic_core_detach(device_t dev) 206 { 207 struct generic_pcie_core_softc *sc; 208 int error; 209 210 sc = device_get_softc(dev); 211 212 error = bus_generic_detach(dev); 213 if (error != 0) 214 return (error); 215 216 rman_fini(&sc->io_rman); 217 rman_fini(&sc->mem_rman); 218 rman_fini(&sc->pmem_rman); 219 if (sc->res != NULL) 220 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); 221 bus_dma_tag_destroy(sc->dmat); 222 223 return (0); 224 } 225 226 static uint32_t 227 generic_pcie_read_config(device_t dev, u_int bus, u_int slot, 228 u_int func, u_int reg, int bytes) 229 { 230 struct generic_pcie_core_softc *sc; 231 uint64_t offset; 232 uint32_t data; 233 234 sc = device_get_softc(dev); 235 if ((bus < sc->bus_start) || (bus > sc->bus_end)) 236 return (~0U); 237 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || 238 (reg > PCIE_REGMAX)) 239 return (~0U); 240 if ((sc->quirks & PCIE_ECAM_DESIGNWARE_QUIRK) && bus == 0 && slot > 0) 241 return (~0U); 242 243 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg); 244 245 switch (bytes) { 246 case 1: 247 data = bus_read_1(sc->res, offset); 248 break; 249 case 2: 250 data = le16toh(bus_read_2(sc->res, offset)); 251 break; 252 case 4: 253 data = le32toh(bus_read_4(sc->res, offset)); 254 break; 255 default: 256 return (~0U); 257 } 258 259 return (data); 260 } 261 262 static void 263 generic_pcie_write_config(device_t dev, u_int bus, u_int slot, 264 u_int func, u_int reg, uint32_t val, int bytes) 265 { 266 struct generic_pcie_core_softc *sc; 267 uint64_t offset; 268 269 sc = device_get_softc(dev); 270 if ((bus < sc->bus_start) || (bus > sc->bus_end)) 271 return; 272 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || 273 (reg > PCIE_REGMAX)) 274 return; 275 276 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg); 277 278 switch (bytes) { 279 case 1: 280 bus_write_1(sc->res, offset, val); 281 break; 282 case 2: 283 bus_write_2(sc->res, offset, htole16(val)); 284 break; 285 case 4: 286 bus_write_4(sc->res, offset, htole32(val)); 287 break; 288 default: 289 return; 290 } 291 } 292 293 static int 294 generic_pcie_maxslots(device_t dev) 295 { 296 297 return (31); /* max slots per bus acc. to standard */ 298 } 299 300 static int 301 generic_pcie_read_ivar(device_t dev, device_t child, int index, 302 uintptr_t *result) 303 { 304 struct generic_pcie_core_softc *sc; 305 306 sc = device_get_softc(dev); 307 308 if (index == PCIB_IVAR_BUS) { 309 *result = sc->bus_start; 310 return (0); 311 } 312 313 if (index == PCIB_IVAR_DOMAIN) { 314 *result = sc->ecam; 315 return (0); 316 } 317 318 if (bootverbose) 319 device_printf(dev, "ERROR: Unknown index %d.\n", index); 320 return (ENOENT); 321 } 322 323 static int 324 generic_pcie_write_ivar(device_t dev, device_t child, int index, 325 uintptr_t value) 326 { 327 328 return (ENOENT); 329 } 330 331 static struct rman * 332 generic_pcie_rman(struct generic_pcie_core_softc *sc, int type, int flags) 333 { 334 335 switch (type) { 336 case SYS_RES_IOPORT: 337 return (&sc->io_rman); 338 case SYS_RES_MEMORY: 339 if (sc->has_pmem && (flags & RF_PREFETCHABLE) != 0) 340 return (&sc->pmem_rman); 341 return (&sc->mem_rman); 342 default: 343 break; 344 } 345 346 return (NULL); 347 } 348 349 int 350 pci_host_generic_core_release_resource(device_t dev, device_t child, int type, 351 int rid, struct resource *res) 352 { 353 struct generic_pcie_core_softc *sc; 354 struct rman *rm; 355 int error; 356 357 sc = device_get_softc(dev); 358 359 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 360 if (type == PCI_RES_BUS) { 361 return (pci_domain_release_bus(sc->ecam, child, rid, res)); 362 } 363 #endif 364 365 rm = generic_pcie_rman(sc, type, rman_get_flags(res)); 366 if (rm != NULL) { 367 KASSERT(rman_is_region_manager(res, rm), ("rman mismatch")); 368 if (rman_get_flags(res) & RF_ACTIVE) { 369 error = bus_deactivate_resource(child, type, rid, res); 370 if (error) 371 return (error); 372 } 373 return (rman_release_resource(res)); 374 } 375 376 return (bus_generic_release_resource(dev, child, type, rid, res)); 377 } 378 379 static int 380 generic_pcie_translate_resource_common(device_t dev, int type, rman_res_t start, 381 rman_res_t end, rman_res_t *new_start, rman_res_t *new_end) 382 { 383 struct generic_pcie_core_softc *sc; 384 uint64_t phys_base; 385 uint64_t pci_base; 386 uint64_t size; 387 int i, space; 388 bool found; 389 390 sc = device_get_softc(dev); 391 /* Translate the address from a PCI address to a physical address */ 392 switch (type) { 393 case SYS_RES_IOPORT: 394 case SYS_RES_MEMORY: 395 found = false; 396 for (i = 0; i < MAX_RANGES_TUPLES; i++) { 397 pci_base = sc->ranges[i].pci_base; 398 phys_base = sc->ranges[i].phys_base; 399 size = sc->ranges[i].size; 400 401 if (start < pci_base || start >= pci_base + size) 402 continue; 403 404 switch (FLAG_TYPE(sc->ranges[i].flags)) { 405 case FLAG_TYPE_MEM: 406 case FLAG_TYPE_PMEM: 407 space = SYS_RES_MEMORY; 408 break; 409 case FLAG_TYPE_IO: 410 space = SYS_RES_IOPORT; 411 break; 412 default: 413 space = -1; 414 continue; 415 } 416 417 if (type == space) { 418 *new_start = start - pci_base + phys_base; 419 *new_end = end - pci_base + phys_base; 420 found = true; 421 break; 422 } 423 } 424 break; 425 default: 426 /* No translation for non-memory types */ 427 *new_start = start; 428 *new_end = end; 429 found = true; 430 break; 431 } 432 433 return (found ? 0 : ENOENT); 434 } 435 436 static int 437 generic_pcie_translate_resource(device_t bus, int type, 438 rman_res_t start, rman_res_t *newstart) 439 { 440 rman_res_t newend; /* unused */ 441 442 return (generic_pcie_translate_resource_common( 443 bus, type, start, 0, newstart, &newend)); 444 } 445 446 struct resource * 447 pci_host_generic_core_alloc_resource(device_t dev, device_t child, int type, 448 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 449 { 450 struct generic_pcie_core_softc *sc; 451 struct resource *res; 452 struct rman *rm; 453 454 sc = device_get_softc(dev); 455 456 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 457 if (type == PCI_RES_BUS) { 458 return (pci_domain_alloc_bus(sc->ecam, child, rid, start, end, 459 count, flags)); 460 } 461 #endif 462 463 rm = generic_pcie_rman(sc, type, flags); 464 if (rm == NULL) 465 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 466 type, rid, start, end, count, flags)); 467 468 if (bootverbose) { 469 device_printf(dev, 470 "rman_reserve_resource: start=%#jx, end=%#jx, count=%#jx\n", 471 start, end, count); 472 } 473 474 res = rman_reserve_resource(rm, start, end, count, flags, child); 475 if (res == NULL) 476 goto fail; 477 478 rman_set_rid(res, *rid); 479 480 if (flags & RF_ACTIVE) 481 if (bus_activate_resource(child, type, *rid, res)) { 482 rman_release_resource(res); 483 goto fail; 484 } 485 486 return (res); 487 488 fail: 489 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 490 "start=%016jx, end=%016jx, count=%016jx, flags=%x\n", 491 __func__, type, *rid, start, end, count, flags); 492 493 return (NULL); 494 } 495 496 static int 497 generic_pcie_activate_resource(device_t dev, device_t child, int type, 498 int rid, struct resource *r) 499 { 500 rman_res_t start, end; 501 int res; 502 503 if ((res = rman_activate_resource(r)) != 0) 504 return (res); 505 506 start = rman_get_start(r); 507 end = rman_get_end(r); 508 res = generic_pcie_translate_resource_common(dev, type, start, end, 509 &start, &end); 510 if (res != 0) { 511 rman_deactivate_resource(r); 512 return (res); 513 } 514 rman_set_start(r, start); 515 rman_set_end(r, end); 516 517 return (BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type, 518 rid, r)); 519 } 520 521 static int 522 generic_pcie_deactivate_resource(device_t dev, device_t child, int type, 523 int rid, struct resource *r) 524 { 525 int res; 526 527 if ((res = rman_deactivate_resource(r)) != 0) 528 return (res); 529 530 switch (type) { 531 case SYS_RES_IOPORT: 532 case SYS_RES_MEMORY: 533 case SYS_RES_IRQ: 534 res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child, 535 type, rid, r); 536 break; 537 default: 538 break; 539 } 540 541 return (res); 542 } 543 544 static int 545 generic_pcie_adjust_resource(device_t dev, device_t child, int type, 546 struct resource *res, rman_res_t start, rman_res_t end) 547 { 548 struct generic_pcie_core_softc *sc; 549 struct rman *rm; 550 551 sc = device_get_softc(dev); 552 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 553 if (type == PCI_RES_BUS) 554 return (pci_domain_adjust_bus(sc->ecam, child, res, start, 555 end)); 556 #endif 557 558 rm = generic_pcie_rman(sc, type, rman_get_flags(res)); 559 if (rm != NULL) 560 return (rman_adjust_resource(res, start, end)); 561 return (bus_generic_adjust_resource(dev, child, type, res, start, end)); 562 } 563 564 static bus_dma_tag_t 565 generic_pcie_get_dma_tag(device_t dev, device_t child) 566 { 567 struct generic_pcie_core_softc *sc; 568 569 sc = device_get_softc(dev); 570 return (sc->dmat); 571 } 572 573 static device_method_t generic_pcie_methods[] = { 574 DEVMETHOD(device_attach, pci_host_generic_core_attach), 575 DEVMETHOD(device_detach, pci_host_generic_core_detach), 576 577 DEVMETHOD(bus_read_ivar, generic_pcie_read_ivar), 578 DEVMETHOD(bus_write_ivar, generic_pcie_write_ivar), 579 DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource), 580 DEVMETHOD(bus_adjust_resource, generic_pcie_adjust_resource), 581 DEVMETHOD(bus_activate_resource, generic_pcie_activate_resource), 582 DEVMETHOD(bus_deactivate_resource, generic_pcie_deactivate_resource), 583 DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource), 584 DEVMETHOD(bus_translate_resource, generic_pcie_translate_resource), 585 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 586 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 587 588 DEVMETHOD(bus_get_dma_tag, generic_pcie_get_dma_tag), 589 590 /* pcib interface */ 591 DEVMETHOD(pcib_maxslots, generic_pcie_maxslots), 592 DEVMETHOD(pcib_read_config, generic_pcie_read_config), 593 DEVMETHOD(pcib_write_config, generic_pcie_write_config), 594 595 DEVMETHOD_END 596 }; 597 598 DEFINE_CLASS_0(pcib, generic_pcie_core_driver, 599 generic_pcie_methods, sizeof(struct generic_pcie_core_softc)); 600