1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * PCI:PCI bridge support. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 47 #include <machine/resource.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcib_private.h> 52 53 #include "pcib_if.h" 54 55 static int pcib_probe(device_t dev); 56 57 static device_method_t pcib_methods[] = { 58 /* Device interface */ 59 DEVMETHOD(device_probe, pcib_probe), 60 DEVMETHOD(device_attach, pcib_attach), 61 DEVMETHOD(device_detach, bus_generic_detach), 62 DEVMETHOD(device_shutdown, bus_generic_shutdown), 63 DEVMETHOD(device_suspend, bus_generic_suspend), 64 DEVMETHOD(device_resume, bus_generic_resume), 65 66 /* Bus interface */ 67 DEVMETHOD(bus_print_child, bus_generic_print_child), 68 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 69 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 70 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 71 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 72 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 73 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 74 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 75 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 76 77 /* pcib interface */ 78 DEVMETHOD(pcib_maxslots, pcib_maxslots), 79 DEVMETHOD(pcib_read_config, pcib_read_config), 80 DEVMETHOD(pcib_write_config, pcib_write_config), 81 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 82 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 83 DEVMETHOD(pcib_release_msi, pcib_release_msi), 84 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 85 DEVMETHOD(pcib_remap_msix, pcib_remap_msix), 86 DEVMETHOD(pcib_release_msix, pcib_release_msix), 87 88 { 0, 0 } 89 }; 90 91 static devclass_t pcib_devclass; 92 93 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 94 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 95 96 /* 97 * Is the prefetch window open (eg, can we allocate memory in it?) 98 */ 99 static int 100 pcib_is_prefetch_open(struct pcib_softc *sc) 101 { 102 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 103 } 104 105 /* 106 * Is the nonprefetch window open (eg, can we allocate memory in it?) 107 */ 108 static int 109 pcib_is_nonprefetch_open(struct pcib_softc *sc) 110 { 111 return (sc->membase > 0 && sc->membase < sc->memlimit); 112 } 113 114 /* 115 * Is the io window open (eg, can we allocate ports in it?) 116 */ 117 static int 118 pcib_is_io_open(struct pcib_softc *sc) 119 { 120 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 121 } 122 123 /* 124 * Generic device interface 125 */ 126 static int 127 pcib_probe(device_t dev) 128 { 129 if ((pci_get_class(dev) == PCIC_BRIDGE) && 130 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 131 device_set_desc(dev, "PCI-PCI bridge"); 132 return(-10000); 133 } 134 return(ENXIO); 135 } 136 137 void 138 pcib_attach_common(device_t dev) 139 { 140 struct pcib_softc *sc; 141 uint8_t iolow; 142 143 sc = device_get_softc(dev); 144 sc->dev = dev; 145 146 /* 147 * Get current bridge configuration. 148 */ 149 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 150 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 151 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 152 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 153 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 154 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 155 156 /* 157 * Determine current I/O decode. 158 */ 159 if (sc->command & PCIM_CMD_PORTEN) { 160 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 161 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 162 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 163 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 164 } else { 165 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 166 } 167 168 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 169 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 170 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 171 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 172 } else { 173 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 174 } 175 } 176 177 /* 178 * Determine current memory decode. 179 */ 180 if (sc->command & PCIM_CMD_MEMEN) { 181 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 182 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 183 sc->pmembase = PCI_PPBMEMBASE(pci_read_config(dev, PCIR_PMBASEH_1, 4), 184 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 185 sc->pmemlimit = PCI_PPBMEMLIMIT(pci_read_config(dev, PCIR_PMLIMITH_1, 4), 186 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 187 } 188 189 /* 190 * Quirk handling. 191 */ 192 switch (pci_get_devid(dev)) { 193 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 194 { 195 uint8_t supbus; 196 197 supbus = pci_read_config(dev, 0x41, 1); 198 if (supbus != 0xff) { 199 sc->secbus = supbus + 1; 200 sc->subbus = supbus + 1; 201 } 202 break; 203 } 204 205 /* 206 * The i82380FB mobile docking controller is a PCI-PCI bridge, 207 * and it is a subtractive bridge. However, the ProgIf is wrong 208 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 209 * happen. There's also a Toshiba bridge that behaves this 210 * way. 211 */ 212 case 0x124b8086: /* Intel 82380FB Mobile */ 213 case 0x060513d7: /* Toshiba ???? */ 214 sc->flags |= PCIB_SUBTRACTIVE; 215 break; 216 217 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 218 case 0x00dd10de: 219 { 220 char *cp; 221 222 if ((cp = getenv("smbios.planar.maker")) == NULL) 223 break; 224 if (strncmp(cp, "Compal", 6) != 0) { 225 freeenv(cp); 226 break; 227 } 228 freeenv(cp); 229 if ((cp = getenv("smbios.planar.product")) == NULL) 230 break; 231 if (strncmp(cp, "08A0", 4) != 0) { 232 freeenv(cp); 233 break; 234 } 235 freeenv(cp); 236 if (sc->subbus < 0xa) { 237 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 238 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 239 } 240 break; 241 } 242 } 243 244 if (pci_msi_device_blacklisted(dev)) 245 sc->flags |= PCIB_DISABLE_MSI; 246 247 /* 248 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 249 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 250 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 251 * This means they act as if they were subtractively decoding 252 * bridges and pass all transactions. Mark them and real ProgIf 1 253 * parts as subtractive. 254 */ 255 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 256 pci_read_config(dev, PCIR_PROGIF, 1) == 1) 257 sc->flags |= PCIB_SUBTRACTIVE; 258 259 if (bootverbose) { 260 device_printf(dev, " secondary bus %d\n", sc->secbus); 261 device_printf(dev, " subordinate bus %d\n", sc->subbus); 262 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 263 if (pcib_is_nonprefetch_open(sc)) 264 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 265 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 266 if (pcib_is_prefetch_open(sc)) 267 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 268 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 269 else 270 device_printf(dev, " no prefetched decode\n"); 271 if (sc->flags & PCIB_SUBTRACTIVE) 272 device_printf(dev, " Subtractively decoded bridge.\n"); 273 } 274 275 /* 276 * XXX If the secondary bus number is zero, we should assign a bus number 277 * since the BIOS hasn't, then initialise the bridge. 278 */ 279 280 /* 281 * XXX If the subordinate bus number is less than the secondary bus number, 282 * we should pick a better value. One sensible alternative would be to 283 * pick 255; the only tradeoff here is that configuration transactions 284 * would be more widely routed than absolutely necessary. 285 */ 286 } 287 288 int 289 pcib_attach(device_t dev) 290 { 291 struct pcib_softc *sc; 292 device_t child; 293 294 pcib_attach_common(dev); 295 sc = device_get_softc(dev); 296 if (sc->secbus != 0) { 297 child = device_add_child(dev, "pci", sc->secbus); 298 if (child != NULL) 299 return(bus_generic_attach(dev)); 300 } 301 302 /* no secondary bus; we should have fixed this */ 303 return(0); 304 } 305 306 int 307 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 308 { 309 struct pcib_softc *sc = device_get_softc(dev); 310 311 switch (which) { 312 case PCIB_IVAR_BUS: 313 *result = sc->secbus; 314 return(0); 315 } 316 return(ENOENT); 317 } 318 319 int 320 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 321 { 322 struct pcib_softc *sc = device_get_softc(dev); 323 324 switch (which) { 325 case PCIB_IVAR_BUS: 326 sc->secbus = value; 327 break; 328 } 329 return(ENOENT); 330 } 331 332 /* 333 * We have to trap resource allocation requests and ensure that the bridge 334 * is set up to, or capable of handling them. 335 */ 336 struct resource * 337 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 338 u_long start, u_long end, u_long count, u_int flags) 339 { 340 struct pcib_softc *sc = device_get_softc(dev); 341 const char *name, *suffix; 342 int ok; 343 344 /* 345 * Fail the allocation for this range if it's not supported. 346 */ 347 name = device_get_nameunit(child); 348 if (name == NULL) { 349 name = ""; 350 suffix = ""; 351 } else 352 suffix = " "; 353 switch (type) { 354 case SYS_RES_IOPORT: 355 ok = 0; 356 if (!pcib_is_io_open(sc)) 357 break; 358 ok = (start >= sc->iobase && end <= sc->iolimit); 359 360 /* 361 * Make sure we allow access to VGA I/O addresses when the 362 * bridge has the "VGA Enable" bit set. 363 */ 364 if (!ok && pci_is_vga_ioport_range(start, end)) 365 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 366 367 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 368 if (!ok) { 369 if (start < sc->iobase) 370 start = sc->iobase; 371 if (end > sc->iolimit) 372 end = sc->iolimit; 373 if (start < end) 374 ok = 1; 375 } 376 } else { 377 ok = 1; 378 #if 1 379 if (start < sc->iobase && end > sc->iolimit) { 380 start = sc->iobase; 381 end = sc->iolimit; 382 } 383 #endif 384 } 385 if (end < start) { 386 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 387 end, start); 388 start = 0; 389 end = 0; 390 ok = 0; 391 } 392 if (!ok) { 393 device_printf(dev, "%s%srequested unsupported I/O " 394 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 395 name, suffix, start, end, sc->iobase, sc->iolimit); 396 return (NULL); 397 } 398 if (bootverbose) 399 device_printf(dev, 400 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 401 name, suffix, start, end); 402 break; 403 404 case SYS_RES_MEMORY: 405 ok = 0; 406 if (pcib_is_nonprefetch_open(sc)) 407 ok = ok || (start >= sc->membase && end <= sc->memlimit); 408 if (pcib_is_prefetch_open(sc)) 409 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 410 411 /* 412 * Make sure we allow access to VGA memory addresses when the 413 * bridge has the "VGA Enable" bit set. 414 */ 415 if (!ok && pci_is_vga_memory_range(start, end)) 416 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 417 418 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 419 if (!ok) { 420 ok = 1; 421 if (flags & RF_PREFETCHABLE) { 422 if (pcib_is_prefetch_open(sc)) { 423 if (start < sc->pmembase) 424 start = sc->pmembase; 425 if (end > sc->pmemlimit) 426 end = sc->pmemlimit; 427 } else { 428 ok = 0; 429 } 430 } else { /* non-prefetchable */ 431 if (pcib_is_nonprefetch_open(sc)) { 432 if (start < sc->membase) 433 start = sc->membase; 434 if (end > sc->memlimit) 435 end = sc->memlimit; 436 } else { 437 ok = 0; 438 } 439 } 440 } 441 } else if (!ok) { 442 ok = 1; /* subtractive bridge: always ok */ 443 #if 1 444 if (pcib_is_nonprefetch_open(sc)) { 445 if (start < sc->membase && end > sc->memlimit) { 446 start = sc->membase; 447 end = sc->memlimit; 448 } 449 } 450 if (pcib_is_prefetch_open(sc)) { 451 if (start < sc->pmembase && end > sc->pmemlimit) { 452 start = sc->pmembase; 453 end = sc->pmemlimit; 454 } 455 } 456 #endif 457 } 458 if (end < start) { 459 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 460 end, start); 461 start = 0; 462 end = 0; 463 ok = 0; 464 } 465 if (!ok && bootverbose) 466 device_printf(dev, 467 "%s%srequested unsupported memory range %#lx-%#lx " 468 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 469 name, suffix, start, end, 470 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 471 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 472 if (!ok) 473 return (NULL); 474 if (bootverbose) 475 device_printf(dev,"%s%srequested memory range " 476 "0x%lx-0x%lx: good\n", 477 name, suffix, start, end); 478 break; 479 480 default: 481 break; 482 } 483 /* 484 * Bridge is OK decoding this resource, so pass it up. 485 */ 486 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 487 count, flags)); 488 } 489 490 /* 491 * PCIB interface. 492 */ 493 int 494 pcib_maxslots(device_t dev) 495 { 496 return(PCI_SLOTMAX); 497 } 498 499 /* 500 * Since we are a child of a PCI bus, its parent must support the pcib interface. 501 */ 502 uint32_t 503 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 504 { 505 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 506 } 507 508 void 509 pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width) 510 { 511 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 512 } 513 514 /* 515 * Route an interrupt across a PCI bridge. 516 */ 517 int 518 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 519 { 520 device_t bus; 521 int parent_intpin; 522 int intnum; 523 524 /* 525 * 526 * The PCI standard defines a swizzle of the child-side device/intpin to 527 * the parent-side intpin as follows. 528 * 529 * device = device on child bus 530 * child_intpin = intpin on child bus slot (0-3) 531 * parent_intpin = intpin on parent bus slot (0-3) 532 * 533 * parent_intpin = (device + child_intpin) % 4 534 */ 535 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 536 537 /* 538 * Our parent is a PCI bus. Its parent must export the pcib interface 539 * which includes the ability to route interrupts. 540 */ 541 bus = device_get_parent(pcib); 542 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 543 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 544 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 545 pci_get_slot(dev), 'A' + pin - 1, intnum); 546 } 547 return(intnum); 548 } 549 550 /* Pass request to alloc MSI messages up to the parent bridge. */ 551 int 552 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 553 { 554 struct pcib_softc *sc = device_get_softc(dev); 555 device_t bus; 556 557 if (sc->flags & PCIB_DISABLE_MSI) 558 return (ENXIO); 559 bus = device_get_parent(pcib); 560 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 561 irqs)); 562 } 563 564 /* Pass request to release MSI messages up to the parent bridge. */ 565 int 566 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 567 { 568 device_t bus; 569 570 bus = device_get_parent(pcib); 571 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 572 } 573 574 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 575 int 576 pcib_alloc_msix(device_t pcib, device_t dev, int index, int *irq) 577 { 578 struct pcib_softc *sc = device_get_softc(dev); 579 device_t bus; 580 581 if (sc->flags & PCIB_DISABLE_MSI) 582 return (ENXIO); 583 bus = device_get_parent(pcib); 584 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, index, irq)); 585 } 586 587 /* Pass request to remap an MSI-X message up to the parent bridge. */ 588 int 589 pcib_remap_msix(device_t pcib, device_t dev, int index, int irq) 590 { 591 device_t bus; 592 593 bus = device_get_parent(pcib); 594 return (PCIB_REMAP_MSIX(device_get_parent(bus), dev, index, irq)); 595 } 596 597 /* Pass request to release an MSI-X message up to the parent bridge. */ 598 int 599 pcib_release_msix(device_t pcib, device_t dev, int irq) 600 { 601 device_t bus; 602 603 bus = device_get_parent(pcib); 604 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 605 } 606 607 /* 608 * Try to read the bus number of a host-PCI bridge using appropriate config 609 * registers. 610 */ 611 int 612 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 613 uint8_t *busnum) 614 { 615 uint32_t id; 616 617 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 618 if (id == 0xffffffff) 619 return (0); 620 621 switch (id) { 622 case 0x12258086: 623 /* Intel 824?? */ 624 /* XXX This is a guess */ 625 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 626 *busnum = bus; 627 break; 628 case 0x84c48086: 629 /* Intel 82454KX/GX (Orion) */ 630 *busnum = read_config(bus, slot, func, 0x4a, 1); 631 break; 632 case 0x84ca8086: 633 /* 634 * For the 450nx chipset, there is a whole bundle of 635 * things pretending to be host bridges. The MIOC will 636 * be seen first and isn't really a pci bridge (the 637 * actual busses are attached to the PXB's). We need to 638 * read the registers of the MIOC to figure out the 639 * bus numbers for the PXB channels. 640 * 641 * Since the MIOC doesn't have a pci bus attached, we 642 * pretend it wasn't there. 643 */ 644 return (0); 645 case 0x84cb8086: 646 switch (slot) { 647 case 0x12: 648 /* Intel 82454NX PXB#0, Bus#A */ 649 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 650 break; 651 case 0x13: 652 /* Intel 82454NX PXB#0, Bus#B */ 653 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 654 break; 655 case 0x14: 656 /* Intel 82454NX PXB#1, Bus#A */ 657 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 658 break; 659 case 0x15: 660 /* Intel 82454NX PXB#1, Bus#B */ 661 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 662 break; 663 } 664 break; 665 666 /* ServerWorks -- vendor 0x1166 */ 667 case 0x00051166: 668 case 0x00061166: 669 case 0x00081166: 670 case 0x00091166: 671 case 0x00101166: 672 case 0x00111166: 673 case 0x00171166: 674 case 0x01011166: 675 case 0x010f1014: 676 case 0x02011166: 677 case 0x03021014: 678 *busnum = read_config(bus, slot, func, 0x44, 1); 679 break; 680 681 /* Compaq/HP -- vendor 0x0e11 */ 682 case 0x60100e11: 683 *busnum = read_config(bus, slot, func, 0xc8, 1); 684 break; 685 default: 686 /* Don't know how to read bus number. */ 687 return 0; 688 } 689 690 return 1; 691 } 692