1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 1997, Stefan Esser <se@freebsd.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef _PCIVAR_H_ 32 #define _PCIVAR_H_ 33 34 #include <sys/queue.h> 35 #include <sys/_eventhandler.h> 36 37 /* some PCI bus constants */ 38 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 39 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 40 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 41 42 typedef uint64_t pci_addr_t; 43 44 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */ 45 struct pcicfg_bridge { 46 uint8_t br_seclat; 47 uint8_t br_subbus; 48 uint8_t br_secbus; 49 uint8_t br_pribus; 50 uint16_t br_control; 51 }; 52 53 /* Interesting values for PCI power management */ 54 struct pcicfg_pp { 55 uint16_t pp_cap; /* PCI power management capabilities */ 56 uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 57 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 58 uint8_t pp_data; /* conf. space addr. of PM data reg */ 59 }; 60 61 struct pci_map { 62 pci_addr_t pm_value; /* Raw BAR value */ 63 pci_addr_t pm_size; 64 uint16_t pm_reg; 65 STAILQ_ENTRY(pci_map) pm_link; 66 }; 67 68 struct vpd_readonly { 69 char keyword[2]; 70 char *value; 71 int len; 72 }; 73 74 struct vpd_write { 75 char keyword[2]; 76 char *value; 77 int start; 78 int len; 79 }; 80 81 struct pcicfg_vpd { 82 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 83 char vpd_cached; 84 char *vpd_ident; /* string identifier */ 85 int vpd_rocnt; 86 struct vpd_readonly *vpd_ros; 87 int vpd_wcnt; 88 struct vpd_write *vpd_w; 89 }; 90 91 /* Interesting values for PCI MSI */ 92 struct pcicfg_msi { 93 uint16_t msi_ctrl; /* Message Control */ 94 uint8_t msi_location; /* Offset of MSI capability registers. */ 95 uint8_t msi_msgnum; /* Number of messages */ 96 int msi_alloc; /* Number of allocated messages. */ 97 uint64_t msi_addr; /* Contents of address register. */ 98 uint16_t msi_data; /* Contents of data register. */ 99 u_int msi_handlers; 100 }; 101 102 /* Interesting values for PCI MSI-X */ 103 struct msix_vector { 104 uint64_t mv_address; /* Contents of address register. */ 105 uint32_t mv_data; /* Contents of data register. */ 106 int mv_irq; 107 }; 108 109 struct msix_table_entry { 110 u_int mte_vector; /* 1-based index into msix_vectors array. */ 111 u_int mte_handlers; 112 }; 113 114 struct pcicfg_msix { 115 uint16_t msix_ctrl; /* Message Control */ 116 uint16_t msix_msgnum; /* Number of messages */ 117 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 118 uint8_t msix_table_bar; /* BAR containing vector table. */ 119 uint8_t msix_pba_bar; /* BAR containing PBA. */ 120 uint32_t msix_table_offset; 121 uint32_t msix_pba_offset; 122 int msix_alloc; /* Number of allocated vectors. */ 123 int msix_table_len; /* Length of virtual table. */ 124 struct msix_table_entry *msix_table; /* Virtual table. */ 125 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 126 struct resource *msix_table_res; /* Resource containing vector table. */ 127 struct resource *msix_pba_res; /* Resource containing PBA. */ 128 }; 129 130 struct pci_id_ofw_iommu { 131 uint32_t id; 132 uint32_t xref; 133 }; 134 135 /* Interesting values for HyperTransport */ 136 struct pcicfg_ht { 137 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 138 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 139 uint16_t ht_msictrl; /* MSI mapping control */ 140 uint64_t ht_msiaddr; /* MSI mapping base address */ 141 }; 142 143 /* Interesting values for PCI-express */ 144 struct pcicfg_pcie { 145 uint8_t pcie_location; /* Offset of PCI-e capability registers. */ 146 uint8_t pcie_type; /* Device type. */ 147 uint16_t pcie_flags; /* Device capabilities register. */ 148 uint16_t pcie_device_ctl; /* Device control register. */ 149 uint16_t pcie_link_ctl; /* Link control register. */ 150 uint16_t pcie_slot_ctl; /* Slot control register. */ 151 uint16_t pcie_root_ctl; /* Root control register. */ 152 uint16_t pcie_device_ctl2; /* Second device control register. */ 153 uint16_t pcie_link_ctl2; /* Second link control register. */ 154 uint16_t pcie_slot_ctl2; /* Second slot control register. */ 155 }; 156 157 struct pcicfg_pcix { 158 uint16_t pcix_command; 159 uint8_t pcix_location; /* Offset of PCI-X capability registers. */ 160 }; 161 162 struct pcicfg_vf { 163 int index; 164 }; 165 166 struct pci_ea_entry { 167 int eae_bei; 168 uint32_t eae_flags; 169 uint64_t eae_base; 170 uint64_t eae_max_offset; 171 uint32_t eae_cfg_offset; 172 STAILQ_ENTRY(pci_ea_entry) eae_link; 173 }; 174 175 struct pcicfg_ea { 176 int ea_location; /* Structure offset in Configuration Header */ 177 STAILQ_HEAD(, pci_ea_entry) ea_entries; /* EA entries */ 178 }; 179 180 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */ 181 182 /* config header information common to all header types */ 183 typedef struct pcicfg { 184 device_t dev; /* device which owns this */ 185 186 STAILQ_HEAD(, pci_map) maps; /* BARs */ 187 188 uint16_t subvendor; /* card vendor ID */ 189 uint16_t subdevice; /* card device ID, assigned by card vendor */ 190 uint16_t vendor; /* chip vendor ID */ 191 uint16_t device; /* chip device ID, assigned by chip vendor */ 192 193 uint16_t cmdreg; /* disable/enable chip and PCI options */ 194 uint16_t statreg; /* supported PCI features and error state */ 195 196 uint8_t baseclass; /* chip PCI class */ 197 uint8_t subclass; /* chip PCI subclass */ 198 uint8_t progif; /* chip PCI programming interface */ 199 uint8_t revid; /* chip revision ID */ 200 201 uint8_t hdrtype; /* chip config header type */ 202 uint8_t cachelnsz; /* cache line size in 4byte units */ 203 uint8_t intpin; /* PCI interrupt pin */ 204 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 205 206 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 207 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 208 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 209 210 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 211 uint8_t nummaps; /* actual number of PCI maps used */ 212 213 uint32_t domain; /* PCI domain */ 214 uint8_t bus; /* config space bus address */ 215 uint8_t slot; /* config space slot address */ 216 uint8_t func; /* config space function number */ 217 218 uint32_t flags; /* flags defined above */ 219 220 struct pcicfg_bridge bridge; /* Bridges */ 221 struct pcicfg_pp pp; /* Power management */ 222 struct pcicfg_vpd vpd; /* Vital product data */ 223 struct pcicfg_msi msi; /* PCI MSI */ 224 struct pcicfg_msix msix; /* PCI MSI-X */ 225 struct pcicfg_ht ht; /* HyperTransport */ 226 struct pcicfg_pcie pcie; /* PCI Express */ 227 struct pcicfg_pcix pcix; /* PCI-X */ 228 struct pcicfg_iov *iov; /* SR-IOV */ 229 struct pcicfg_vf vf; /* SR-IOV Virtual Function */ 230 struct pcicfg_ea ea; /* Enhanced Allocation */ 231 } pcicfgregs; 232 233 /* additional type 1 device config header information (PCI to PCI bridge) */ 234 235 typedef struct { 236 pci_addr_t pmembase; /* base address of prefetchable memory */ 237 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 238 uint32_t membase; /* base address of memory window */ 239 uint32_t memlimit; /* topmost address of memory window */ 240 uint32_t iobase; /* base address of port window */ 241 uint32_t iolimit; /* topmost address of port window */ 242 uint16_t secstat; /* secondary bus status register */ 243 uint16_t bridgectl; /* bridge control register */ 244 uint8_t seclat; /* CardBus latency timer */ 245 } pcih1cfgregs; 246 247 /* additional type 2 device config header information (CardBus bridge) */ 248 249 typedef struct { 250 uint32_t membase0; /* base address of memory window */ 251 uint32_t memlimit0; /* topmost address of memory window */ 252 uint32_t membase1; /* base address of memory window */ 253 uint32_t memlimit1; /* topmost address of memory window */ 254 uint32_t iobase0; /* base address of port window */ 255 uint32_t iolimit0; /* topmost address of port window */ 256 uint32_t iobase1; /* base address of port window */ 257 uint32_t iolimit1; /* topmost address of port window */ 258 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 259 uint16_t secstat; /* secondary bus status register */ 260 uint16_t bridgectl; /* bridge control register */ 261 uint8_t seclat; /* CardBus latency timer */ 262 } pcih2cfgregs; 263 264 extern uint32_t pci_numdevs; 265 extern int pci_enable_aspm; 266 267 /* 268 * The bitfield has to be stable and match the fields below (so that 269 * match_flag_vendor must be bit 0) so we have to do the endian dance. We can't 270 * use enums or #define constants because then the macros for subsetting matches 271 * wouldn't work. These tables are parsed by devmatch and others to connect 272 * modules with devices on the PCI bus. 273 */ 274 struct pci_device_table { 275 #if BYTE_ORDER == LITTLE_ENDIAN 276 uint16_t 277 match_flag_vendor:1, 278 match_flag_device:1, 279 match_flag_subvendor:1, 280 match_flag_subdevice:1, 281 match_flag_class:1, 282 match_flag_subclass:1, 283 match_flag_revid:1, 284 match_flag_unused:9; 285 #else 286 uint16_t 287 match_flag_unused:9, 288 match_flag_revid:1, 289 match_flag_subclass:1, 290 match_flag_class:1, 291 match_flag_subdevice:1, 292 match_flag_subvendor:1, 293 match_flag_device:1, 294 match_flag_vendor:1; 295 #endif 296 uint16_t vendor; 297 uint16_t device; 298 uint16_t subvendor; 299 uint16_t subdevice; 300 uint16_t class_id; 301 uint16_t subclass; 302 uint16_t revid; 303 uint16_t unused; 304 uintptr_t driver_data; 305 char *descr; 306 }; 307 308 #define PCI_DEV(v, d) \ 309 .match_flag_vendor = 1, .vendor = (v), \ 310 .match_flag_device = 1, .device = (d) 311 #define PCI_SUBDEV(sv, sd) \ 312 .match_flag_subvendor = 1, .subvendor = (sv), \ 313 .match_flag_subdevice = 1, .subdevice = (sd) 314 #define PCI_CLASS(x) \ 315 .match_flag_class = 1, .class_id = (x) 316 #define PCI_SUBCLASS(x) \ 317 .match_flag_subclass = 1, .subclass = (x) 318 #define PCI_REVID(x) \ 319 .match_flag_revid = 1, .revid = (x) 320 #define PCI_DESCR(x) \ 321 .descr = (x) 322 #define PCI_PNP_STR \ 323 "M16:mask;U16:vendor;U16:device;U16:subvendor;U16:subdevice;" \ 324 "U16:class;U16:subclass;U16:revid;" 325 #define PCI_PNP_INFO(table) \ 326 MODULE_PNP_INFO(PCI_PNP_STR, pci, table, table, \ 327 sizeof(table) / sizeof(table[0])) 328 329 const struct pci_device_table *pci_match_device(device_t child, 330 const struct pci_device_table *id, size_t nelt); 331 #define PCI_MATCH(child, table) \ 332 pci_match_device(child, (table), nitems(table)); 333 334 /* Only if the prerequisites are present */ 335 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 336 struct pci_devinfo { 337 STAILQ_ENTRY(pci_devinfo) pci_links; 338 struct resource_list resources; 339 pcicfgregs cfg; 340 struct pci_conf conf; 341 }; 342 #endif 343 344 #ifdef _SYS_BUS_H_ 345 346 #include "pci_if.h" 347 348 enum pci_device_ivars { 349 PCI_IVAR_SUBVENDOR, 350 PCI_IVAR_SUBDEVICE, 351 PCI_IVAR_VENDOR, 352 PCI_IVAR_DEVICE, 353 PCI_IVAR_DEVID, 354 PCI_IVAR_CLASS, 355 PCI_IVAR_SUBCLASS, 356 PCI_IVAR_PROGIF, 357 PCI_IVAR_REVID, 358 PCI_IVAR_INTPIN, 359 PCI_IVAR_IRQ, 360 PCI_IVAR_DOMAIN, 361 PCI_IVAR_BUS, 362 PCI_IVAR_SLOT, 363 PCI_IVAR_FUNCTION, 364 PCI_IVAR_ETHADDR, 365 PCI_IVAR_CMDREG, 366 PCI_IVAR_CACHELNSZ, 367 PCI_IVAR_MINGNT, 368 PCI_IVAR_MAXLAT, 369 PCI_IVAR_LATTIMER 370 }; 371 372 /* 373 * Simplified accessors for pci devices 374 */ 375 #define PCI_ACCESSOR(var, ivar, type) \ 376 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 377 378 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 379 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 380 PCI_ACCESSOR(vendor, VENDOR, uint16_t) 381 PCI_ACCESSOR(device, DEVICE, uint16_t) 382 PCI_ACCESSOR(devid, DEVID, uint32_t) 383 PCI_ACCESSOR(class, CLASS, uint8_t) 384 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 385 PCI_ACCESSOR(progif, PROGIF, uint8_t) 386 PCI_ACCESSOR(revid, REVID, uint8_t) 387 PCI_ACCESSOR(intpin, INTPIN, uint8_t) 388 PCI_ACCESSOR(irq, IRQ, uint8_t) 389 PCI_ACCESSOR(domain, DOMAIN, uint32_t) 390 PCI_ACCESSOR(bus, BUS, uint8_t) 391 PCI_ACCESSOR(slot, SLOT, uint8_t) 392 PCI_ACCESSOR(function, FUNCTION, uint8_t) 393 PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 394 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 395 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 396 PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 397 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 398 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 399 400 #undef PCI_ACCESSOR 401 402 /* 403 * Operations on configuration space. 404 */ 405 static __inline uint32_t 406 pci_read_config(device_t dev, int reg, int width) 407 { 408 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 409 } 410 411 static __inline void 412 pci_write_config(device_t dev, int reg, uint32_t val, int width) 413 { 414 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 415 } 416 417 /* 418 * Ivars for pci bridges. 419 */ 420 421 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 422 enum pcib_device_ivars { 423 PCIB_IVAR_DOMAIN, 424 PCIB_IVAR_BUS 425 }; 426 427 #define PCIB_ACCESSOR(var, ivar, type) \ 428 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 429 430 PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 431 PCIB_ACCESSOR(bus, BUS, uint32_t) 432 433 #undef PCIB_ACCESSOR 434 435 /* 436 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 437 * on i386 or other platforms should be mapped out in the MD pcireadconf 438 * code and not here, since the only MI invalid IRQ is 255. 439 */ 440 #define PCI_INVALID_IRQ 255 441 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 442 443 /* 444 * Convenience functions. 445 * 446 * These should be used in preference to manually manipulating 447 * configuration space. 448 */ 449 static __inline int 450 pci_enable_busmaster(device_t dev) 451 { 452 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 453 } 454 455 static __inline int 456 pci_disable_busmaster(device_t dev) 457 { 458 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 459 } 460 461 static __inline int 462 pci_enable_io(device_t dev, int space) 463 { 464 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 465 } 466 467 static __inline int 468 pci_disable_io(device_t dev, int space) 469 { 470 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 471 } 472 473 static __inline int 474 pci_get_vpd_ident(device_t dev, const char **identptr) 475 { 476 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 477 } 478 479 static __inline int 480 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr) 481 { 482 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr)); 483 } 484 485 /* 486 * Check if the address range falls within the VGA defined address range(s) 487 */ 488 static __inline int 489 pci_is_vga_ioport_range(rman_res_t start, rman_res_t end) 490 { 491 492 return (((start >= 0x3b0 && end <= 0x3bb) || 493 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 494 } 495 496 static __inline int 497 pci_is_vga_memory_range(rman_res_t start, rman_res_t end) 498 { 499 500 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 501 } 502 503 /* 504 * PCI power states are as defined by ACPI: 505 * 506 * D0 State in which device is on and running. It is receiving full 507 * power from the system and delivering full functionality to the user. 508 * D1 Class-specific low-power state in which device context may or may not 509 * be lost. Buses in D1 cannot do anything to the bus that would force 510 * devices on that bus to lose context. 511 * D2 Class-specific low-power state in which device context may or may 512 * not be lost. Attains greater power savings than D1. Buses in D2 513 * can cause devices on that bus to lose some context. Devices in D2 514 * must be prepared for the bus to be in D2 or higher. 515 * D3 State in which the device is off and not running. Device context is 516 * lost. Power can be removed from the device. 517 */ 518 #define PCI_POWERSTATE_D0 0 519 #define PCI_POWERSTATE_D1 1 520 #define PCI_POWERSTATE_D2 2 521 #define PCI_POWERSTATE_D3 3 522 #define PCI_POWERSTATE_UNKNOWN -1 523 524 static __inline int 525 pci_set_powerstate(device_t dev, int state) 526 { 527 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 528 } 529 530 static __inline int 531 pci_get_powerstate(device_t dev) 532 { 533 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 534 } 535 536 static __inline int 537 pci_find_cap(device_t dev, int capability, int *capreg) 538 { 539 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg)); 540 } 541 542 static __inline int 543 pci_find_next_cap(device_t dev, int capability, int start, int *capreg) 544 { 545 return (PCI_FIND_NEXT_CAP(device_get_parent(dev), dev, capability, start, 546 capreg)); 547 } 548 549 static __inline int 550 pci_find_extcap(device_t dev, int capability, int *capreg) 551 { 552 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 553 } 554 555 static __inline int 556 pci_find_next_extcap(device_t dev, int capability, int start, int *capreg) 557 { 558 return (PCI_FIND_NEXT_EXTCAP(device_get_parent(dev), dev, capability, 559 start, capreg)); 560 } 561 562 static __inline int 563 pci_find_htcap(device_t dev, int capability, int *capreg) 564 { 565 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg)); 566 } 567 568 static __inline int 569 pci_find_next_htcap(device_t dev, int capability, int start, int *capreg) 570 { 571 return (PCI_FIND_NEXT_HTCAP(device_get_parent(dev), dev, capability, 572 start, capreg)); 573 } 574 575 static __inline int 576 pci_alloc_msi(device_t dev, int *count) 577 { 578 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 579 } 580 581 static __inline int 582 pci_alloc_msix(device_t dev, int *count) 583 { 584 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 585 } 586 587 static __inline void 588 pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 589 { 590 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data); 591 } 592 593 static __inline void 594 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 595 { 596 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data); 597 } 598 599 static __inline void 600 pci_disable_msi(device_t dev) 601 { 602 PCI_DISABLE_MSI(device_get_parent(dev), dev); 603 } 604 605 static __inline int 606 pci_remap_msix(device_t dev, int count, const u_int *vectors) 607 { 608 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 609 } 610 611 static __inline int 612 pci_release_msi(device_t dev) 613 { 614 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 615 } 616 617 static __inline int 618 pci_msi_count(device_t dev) 619 { 620 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 621 } 622 623 static __inline int 624 pci_msix_count(device_t dev) 625 { 626 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 627 } 628 629 static __inline int 630 pci_msix_pba_bar(device_t dev) 631 { 632 return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev)); 633 } 634 635 static __inline int 636 pci_msix_table_bar(device_t dev) 637 { 638 return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev)); 639 } 640 641 static __inline int 642 pci_get_id(device_t dev, enum pci_id_type type, uintptr_t *id) 643 { 644 return (PCI_GET_ID(device_get_parent(dev), dev, type, id)); 645 } 646 647 /* 648 * This is the deprecated interface, there is no way to tell the difference 649 * between a failure and a valid value that happens to be the same as the 650 * failure value. 651 */ 652 static __inline uint16_t 653 pci_get_rid(device_t dev) 654 { 655 uintptr_t rid; 656 657 if (pci_get_id(dev, PCI_ID_RID, &rid) != 0) 658 return (0); 659 660 return (rid); 661 } 662 663 static __inline void 664 pci_child_added(device_t dev) 665 { 666 667 return (PCI_CHILD_ADDED(device_get_parent(dev), dev)); 668 } 669 670 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 671 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 672 device_t pci_find_device(uint16_t, uint16_t); 673 device_t pci_find_class(uint8_t class, uint8_t subclass); 674 device_t pci_find_class_from(uint8_t class, uint8_t subclass, device_t devfrom); 675 676 /* Can be used by drivers to manage the MSI-X table. */ 677 int pci_pending_msix(device_t dev, u_int index); 678 679 int pci_msi_device_blacklisted(device_t dev); 680 int pci_msix_device_blacklisted(device_t dev); 681 682 void pci_ht_map_msi(device_t dev, uint64_t addr); 683 684 device_t pci_find_pcie_root_port(device_t dev); 685 int pci_get_relaxed_ordering_enabled(device_t dev); 686 int pci_get_max_payload(device_t dev); 687 int pci_get_max_read_req(device_t dev); 688 void pci_restore_state(device_t dev); 689 void pci_save_state(device_t dev); 690 int pci_set_max_read_req(device_t dev, int size); 691 int pci_power_reset(device_t dev); 692 uint32_t pcie_read_config(device_t dev, int reg, int width); 693 void pcie_write_config(device_t dev, int reg, uint32_t value, int width); 694 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask, 695 uint32_t value, int width); 696 void pcie_apei_error(device_t dev, int sev, uint8_t *aer); 697 bool pcie_flr(device_t dev, u_int max_delay, bool force); 698 int pcie_get_max_completion_timeout(device_t dev); 699 bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay); 700 int pcie_link_reset(device_t port, int pcie_location); 701 702 void pci_print_faulted_dev(void); 703 704 #endif /* _SYS_BUS_H_ */ 705 706 /* 707 * cdev switch for control device, initialised in generic PCI code 708 */ 709 extern struct cdevsw pcicdev; 710 711 /* 712 * List of all PCI devices, generation count for the list. 713 */ 714 STAILQ_HEAD(devlist, pci_devinfo); 715 716 extern struct devlist pci_devq; 717 extern uint32_t pci_generation; 718 719 struct pci_map *pci_find_bar(device_t dev, int reg); 720 struct pci_map *pci_first_bar(device_t dev); 721 struct pci_map *pci_next_bar(struct pci_map *pm); 722 int pci_bar_enabled(device_t dev, struct pci_map *pm); 723 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev); 724 725 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000 726 #define VGA_PCI_BIOS_SHADOW_SIZE 131072 727 728 int vga_pci_is_boot_display(device_t dev); 729 void * vga_pci_map_bios(device_t dev, size_t *size); 730 void vga_pci_unmap_bios(device_t dev, void *bios); 731 int vga_pci_repost(device_t dev); 732 733 /** 734 * Global eventhandlers invoked when PCI devices are added or removed 735 * from the system. 736 */ 737 typedef void (*pci_event_fn)(void *arg, device_t dev); 738 EVENTHANDLER_DECLARE(pci_add_device, pci_event_fn); 739 EVENTHANDLER_DECLARE(pci_delete_device, pci_event_fn); 740 741 #endif /* _PCIVAR_H_ */ 742