xref: /freebsd/sys/dev/pms/RefTisa/sallsdk/spc/mpi.h (revision 2ff63af9)
14e1bc9a0SAchim Leubner /*******************************************************************************
24e1bc9a0SAchim Leubner *Copyright (c) 2014 PMC-Sierra, Inc.  All rights reserved.
34e1bc9a0SAchim Leubner *
44e1bc9a0SAchim Leubner *Redistribution and use in source and binary forms, with or without modification, are permitted provided
54e1bc9a0SAchim Leubner *that the following conditions are met:
64e1bc9a0SAchim Leubner *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
74e1bc9a0SAchim Leubner *following disclaimer.
84e1bc9a0SAchim Leubner *2. Redistributions in binary form must reproduce the above copyright notice,
94e1bc9a0SAchim Leubner *this list of conditions and the following disclaimer in the documentation and/or other materials provided
104e1bc9a0SAchim Leubner *with the distribution.
114e1bc9a0SAchim Leubner *
124e1bc9a0SAchim Leubner *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
134e1bc9a0SAchim Leubner *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
144e1bc9a0SAchim Leubner *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
154e1bc9a0SAchim Leubner *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
164e1bc9a0SAchim Leubner *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
174e1bc9a0SAchim Leubner *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
184e1bc9a0SAchim Leubner *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
194e1bc9a0SAchim Leubner *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
204e1bc9a0SAchim Leubner *
214e1bc9a0SAchim Leubner *
224e1bc9a0SAchim Leubner ********************************************************************************/
234e1bc9a0SAchim Leubner 
244e1bc9a0SAchim Leubner /*******************************************************************************/
254e1bc9a0SAchim Leubner /*! \file mpi.h
264e1bc9a0SAchim Leubner  *  \brief The file defines the MPI constants and structures
274e1bc9a0SAchim Leubner  *
284e1bc9a0SAchim Leubner  * The file defines the MPI constants and structures
294e1bc9a0SAchim Leubner  *
304e1bc9a0SAchim Leubner  */
314e1bc9a0SAchim Leubner /*******************************************************************************/
324e1bc9a0SAchim Leubner 
334e1bc9a0SAchim Leubner #ifndef __MPI_H__
344e1bc9a0SAchim Leubner #define __MPI_H__
354e1bc9a0SAchim Leubner 
364e1bc9a0SAchim Leubner /*******************************************************************************/
374e1bc9a0SAchim Leubner 
384e1bc9a0SAchim Leubner /*******************************************************************************/
394e1bc9a0SAchim Leubner /* CONSTANTS                                                                   */
404e1bc9a0SAchim Leubner /*******************************************************************************/
414e1bc9a0SAchim Leubner /*******************************************************************************/
424e1bc9a0SAchim Leubner #define MPI_QUEUE_PRIORITY_HIGHEST      0xFF  /**< Highest queue priority */
434e1bc9a0SAchim Leubner #define MPI_QUEUE_PRIORITY_LOWEST       0x00  /**< Lowest queue priority */
444e1bc9a0SAchim Leubner 
454e1bc9a0SAchim Leubner #define MPI_MAX_INBOUND_QUEUES          64     /**< Maximum number of inbound queues */
464e1bc9a0SAchim Leubner #define MPI_MAX_OUTBOUND_QUEUES         64     /**< Maximum number of outbound queues */
474e1bc9a0SAchim Leubner 
484e1bc9a0SAchim Leubner                                                /**< Max # of memory chunks supported */
494e1bc9a0SAchim Leubner #define MPI_MAX_MEM_REGIONS             (MPI_MAX_INBOUND_QUEUES + MPI_MAX_OUTBOUND_QUEUES) + 4
504e1bc9a0SAchim Leubner #define MPI_LOGSIZE                     4096  /**< default size */
514e1bc9a0SAchim Leubner 
524e1bc9a0SAchim Leubner #define MPI_IB_NUM_MASK                 0x0000FFFF /**< Mask of Inbound Queue Number */
534e1bc9a0SAchim Leubner #define MPI_OB_NUM_MASK                 0xFFFF0000 /**< Mask of Outbound Queue Number */
544e1bc9a0SAchim Leubner #define MPI_OB_SHIFT                    16         /**< bits shift for outbound queue number */
554e1bc9a0SAchim Leubner 
564e1bc9a0SAchim Leubner 
574e1bc9a0SAchim Leubner #define BAR0                            0x10
584e1bc9a0SAchim Leubner #define BAR1                            0x14
594e1bc9a0SAchim Leubner #define BAR2                            0x18
604e1bc9a0SAchim Leubner #define BAR3                            0x1C
614e1bc9a0SAchim Leubner #define BAR4                            0x20
624e1bc9a0SAchim Leubner #define BAR5                            0x24
634e1bc9a0SAchim Leubner 
644e1bc9a0SAchim Leubner /*******************************************************************************/
654e1bc9a0SAchim Leubner /*******************************************************************************/
664e1bc9a0SAchim Leubner /* ENUMERATIONS                                                                */
674e1bc9a0SAchim Leubner /*******************************************************************************/
684e1bc9a0SAchim Leubner 
694e1bc9a0SAchim Leubner /*******************************************************************************/
704e1bc9a0SAchim Leubner /*******************************************************************************/
714e1bc9a0SAchim Leubner /** \enum mpiMsgCategory_e,
724e1bc9a0SAchim Leubner  *  \brief MPI message categories
734e1bc9a0SAchim Leubner  */
744e1bc9a0SAchim Leubner /*******************************************************************************/
754e1bc9a0SAchim Leubner enum mpiMsgCategory_e
764e1bc9a0SAchim Leubner {
774e1bc9a0SAchim Leubner   MPI_CATEGORY_ETHERNET = 0,
784e1bc9a0SAchim Leubner   MPI_CATEGORY_FC,
794e1bc9a0SAchim Leubner   MPI_CATEGORY_SAS_SATA,
804e1bc9a0SAchim Leubner   MPI_CATEGORY_SCSI
814e1bc9a0SAchim Leubner };
824e1bc9a0SAchim Leubner 
834e1bc9a0SAchim Leubner typedef enum mpiMsgCategory_e mpiMsgCategory_t;
844e1bc9a0SAchim Leubner 
854e1bc9a0SAchim Leubner /*******************************************************************************/
864e1bc9a0SAchim Leubner /*******************************************************************************/
874e1bc9a0SAchim Leubner /* TYPES                                                                       */
884e1bc9a0SAchim Leubner /*******************************************************************************/
894e1bc9a0SAchim Leubner /*******************************************************************************/
904e1bc9a0SAchim Leubner 
914e1bc9a0SAchim Leubner 
924e1bc9a0SAchim Leubner /*******************************************************************************/
934e1bc9a0SAchim Leubner /*******************************************************************************/
944e1bc9a0SAchim Leubner /* DATA STRUCTURES                                                             */
954e1bc9a0SAchim Leubner /*******************************************************************************/
964e1bc9a0SAchim Leubner /*******************************************************************************/
974e1bc9a0SAchim Leubner 
984e1bc9a0SAchim Leubner /*******************************************************************************/
994e1bc9a0SAchim Leubner /** \struct mpiMem_s
1004e1bc9a0SAchim Leubner  *  \brief Structure that descibes memory regions
1014e1bc9a0SAchim Leubner  *
1024e1bc9a0SAchim Leubner  * The mpiMemoryDescriptor_t is used to describe the attributes for a memory
1034e1bc9a0SAchim Leubner  * region. Each element in the memory chunk has to be physically contiguous.
1044e1bc9a0SAchim Leubner  * Different elements in the memory chunk do not necessarily have to be
1054e1bc9a0SAchim Leubner  * contiguous to each other.
1064e1bc9a0SAchim Leubner  */
1074e1bc9a0SAchim Leubner /*******************************************************************************/
1084e1bc9a0SAchim Leubner struct mpiMem_s
1094e1bc9a0SAchim Leubner {
1104e1bc9a0SAchim Leubner   void*        virtPtr;       /**< Virtual pointer to the memory region */
1114e1bc9a0SAchim Leubner   void*        appHandle;     /**< Handle used for the application to free memory */
1124e1bc9a0SAchim Leubner   bit32        physAddrUpper; /**< Upper 32 bits of physical address */
1134e1bc9a0SAchim Leubner   bit32        physAddrLower; /**< Lower 32 bits of physical address */
1144e1bc9a0SAchim Leubner   bit32        totalLength;   /**< Total length in bytes allocated */
1154e1bc9a0SAchim Leubner   bit32        numElements;   /**< Number of elements */
1164e1bc9a0SAchim Leubner   bit32        elementSize;   /**< Size in bytes of an element */
1174e1bc9a0SAchim Leubner   bit32        alignment;     /**< Alignment in bytes needed. A value of one indicates */
1184e1bc9a0SAchim Leubner                               /**< no specific alignment requirement */
1194e1bc9a0SAchim Leubner   bit32        type;          /**< Memory type */
1204e1bc9a0SAchim Leubner   bit32        reserved;      /**< Reserved */
1214e1bc9a0SAchim Leubner };
1224e1bc9a0SAchim Leubner 
1234e1bc9a0SAchim Leubner typedef struct mpiMem_s mpiMem_t;
1244e1bc9a0SAchim Leubner 
1254e1bc9a0SAchim Leubner /*******************************************************************************/
1264e1bc9a0SAchim Leubner /** \struct mpiMemReq_s
1274e1bc9a0SAchim Leubner  *  \brief Describes MPI memory requirements
1284e1bc9a0SAchim Leubner  *
1294e1bc9a0SAchim Leubner  * The mpiMemRequirements_t  is used to specify the memory allocation requirement
1304e1bc9a0SAchim Leubner  * for the MPI. This is the data structure used in the mpiGetRequirements()
1314e1bc9a0SAchim Leubner  * and the mpiInitialize() function calls
1324e1bc9a0SAchim Leubner  */
1334e1bc9a0SAchim Leubner /*******************************************************************************/
1344e1bc9a0SAchim Leubner struct mpiMemReq_s
1354e1bc9a0SAchim Leubner {
1364e1bc9a0SAchim Leubner   bit32     count;                        /**< The number of element in the mpiMemory array */
1374e1bc9a0SAchim Leubner   mpiMem_t  region[MPI_MAX_MEM_REGIONS];  /**< Pointer to the array of structures that define memroy regions */
1384e1bc9a0SAchim Leubner };
1394e1bc9a0SAchim Leubner 
1404e1bc9a0SAchim Leubner typedef struct mpiMemReq_s mpiMemReq_t;
1414e1bc9a0SAchim Leubner 
1424e1bc9a0SAchim Leubner /*******************************************************************************/
1434e1bc9a0SAchim Leubner /** \struct mpiQCQueue_s
1444e1bc9a0SAchim Leubner  *  \brief Circular Queue descriptor
1454e1bc9a0SAchim Leubner  *
1464e1bc9a0SAchim Leubner  * This structure holds outbound circular queue attributes.
1474e1bc9a0SAchim Leubner  */
1484e1bc9a0SAchim Leubner /*******************************************************************************/
1494e1bc9a0SAchim Leubner struct mpiOCQueue_s
1504e1bc9a0SAchim Leubner {
1514e1bc9a0SAchim Leubner   bit32                     qNumber;      /**< this queue number */
1524e1bc9a0SAchim Leubner   bit32                     numElements;  /**< The total number of queue elements. A value 0 disables the queue */
1534e1bc9a0SAchim Leubner   bit32                     elementSize;  /**< The size of each queue element, in bytes */
1544e1bc9a0SAchim Leubner   bit32                     priority;     /**< The queue priority. Possible values for this field are */
1554e1bc9a0SAchim Leubner                                           /**< MPI_QUEUE_PRIORITY_HIGHEST and MPI_QUEUE_PRIORITY_LOWEST */
1564e1bc9a0SAchim Leubner   bit32                     CIPCIBar;     /**< PCI Bar */
1574e1bc9a0SAchim Leubner   bit32                     CIPCIOffset;  /**< PCI Offset */
1584e1bc9a0SAchim Leubner   bit32                     DIntTOffset;  /**< Dynamic Interrupt Coalescing Timeout offset */
1594e1bc9a0SAchim Leubner   void*                     piPointer;    /**< pointer of PI (virtual address)*/
1604e1bc9a0SAchim Leubner   mpiMem_t                  memoryRegion; /**< Queue's memory region descriptor */
1614e1bc9a0SAchim Leubner   bit32                     producerIdx;  /**< Copy of the producer index */
1624e1bc9a0SAchim Leubner   bit32                     consumerIdx;  /**< Copy of the consumer index */
1634e1bc9a0SAchim Leubner   bit32                     pcibar;       /**< CPI Logical Bar Number */
1644e1bc9a0SAchim Leubner   agsaRoot_t                *agRoot;      /**< Pointer of LL Layer structure */
1654e1bc9a0SAchim Leubner };
1664e1bc9a0SAchim Leubner 
1674e1bc9a0SAchim Leubner typedef struct mpiOCQueue_s mpiOCQueue_t;
1684e1bc9a0SAchim Leubner 
1694e1bc9a0SAchim Leubner /*******************************************************************************/
1704e1bc9a0SAchim Leubner /** \struct mpiICQueue_s
1714e1bc9a0SAchim Leubner  *  \brief Circular Queue descriptor
1724e1bc9a0SAchim Leubner  *
1734e1bc9a0SAchim Leubner  * This structure holds inbound circular queue attributes.
1744e1bc9a0SAchim Leubner  */
1754e1bc9a0SAchim Leubner /*******************************************************************************/
1764e1bc9a0SAchim Leubner struct mpiICQueue_s
1774e1bc9a0SAchim Leubner {
1784e1bc9a0SAchim Leubner   bit32                     qNumber;      /**< this queue number */
1794e1bc9a0SAchim Leubner   bit32                     numElements;  /**< The total number of queue elements. A value 0 disables the queue */
1804e1bc9a0SAchim Leubner   bit32                     elementSize;  /**< The size of each queue element, in bytes */
1814e1bc9a0SAchim Leubner   bit32                     priority;     /**< The queue priority. Possible values for this field are */
1824e1bc9a0SAchim Leubner                                           /**< MPI_QUEUE_PRIORITY_HIGHEST and MPI_QUEUE_PRIORITY_LOWEST */
1834e1bc9a0SAchim Leubner   bit32                     PIPCIBar;     /**< PCI Bar */
1844e1bc9a0SAchim Leubner   bit32                     PIPCIOffset;  /**< PCI Offset */
1854e1bc9a0SAchim Leubner   void*                     ciPointer;    /**< Pointer of CI (virtual Address) */
1864e1bc9a0SAchim Leubner   mpiMem_t                  memoryRegion; /**< Queue's memory region descriptor */
1874e1bc9a0SAchim Leubner   bit32                     producerIdx;  /**< Copy of the producer index */
1884e1bc9a0SAchim Leubner   bit32                     consumerIdx;  /**< Copy of the consumer index */
1894e1bc9a0SAchim Leubner #ifdef SA_FW_TEST_BUNCH_STARTS
1904e1bc9a0SAchim Leubner   bit32                     BunchStarts_QPending;     // un-started bunched IOs on queue
1914e1bc9a0SAchim Leubner   bit32                     BunchStarts_QPendingTick; // tick value when 1st IO is bunched
1924e1bc9a0SAchim Leubner #endif /* SA_FW_TEST_BUNCH_STARTS */
1934e1bc9a0SAchim Leubner   agsaRoot_t                *agRoot;      /**< Pointer of LL Layer structure */
1944e1bc9a0SAchim Leubner };
1954e1bc9a0SAchim Leubner 
1964e1bc9a0SAchim Leubner typedef struct mpiICQueue_s mpiICQueue_t;
1974e1bc9a0SAchim Leubner 
1984e1bc9a0SAchim Leubner struct mpiHostLLConfigDescriptor_s
1994e1bc9a0SAchim Leubner {
2004e1bc9a0SAchim Leubner   bit32 regDumpPCIBAR;
2014e1bc9a0SAchim Leubner   bit32 iQNPPD_HPPD_GEvent;                 /**< inbound Queue Process depth */
2024e1bc9a0SAchim Leubner         /* bit0-7   inbound normal priority process depth */
2034e1bc9a0SAchim Leubner         /* bit8-15  inbound high priority process depth */
2044e1bc9a0SAchim Leubner         /* bit16-23 OQ number to receive GENERAL_EVENT Notification */
2054e1bc9a0SAchim Leubner         /* bit24-31 reserved */
2064e1bc9a0SAchim Leubner   bit32 outboundHWEventPID0_3;              /**< outbound HW event for PortId 0 to 3 */
2074e1bc9a0SAchim Leubner         /* bit0-7   outbound queue number of SAS_HW event for PortId 0 */
2084e1bc9a0SAchim Leubner         /* bit8-15  outbound queue number of SAS_HW event for PortId 1 */
2094e1bc9a0SAchim Leubner         /* bit16-23 outbound queue number of SAS_HW event for PortId 2 */
2104e1bc9a0SAchim Leubner         /* bit24-31 outbound queue number of SAS_HW event for PortId 3 */
2114e1bc9a0SAchim Leubner   bit32 outboundHWEventPID4_7;              /**< outbound HW event for PortId 4 to 7 */
2124e1bc9a0SAchim Leubner         /* bit0-7   outbound queue number of SAS_HW event for PortId 4 */
2134e1bc9a0SAchim Leubner         /* bit8-15  outbound queue number of SAS_HW event for PortId 5 */
2144e1bc9a0SAchim Leubner         /* bit16-23 outbound queue number of SAS_HW event for PortId 6 */
2154e1bc9a0SAchim Leubner         /* bit24-31 outbound queue number of SAS_HW event for PortId 7 */
2164e1bc9a0SAchim Leubner   bit32 outboundNCQEventPID0_3;             /**< outbound NCQ event for PortId 0 to 3 */
2174e1bc9a0SAchim Leubner         /* bit0-7   outbound queue number of SATA_NCQ event for PortId 0 */
2184e1bc9a0SAchim Leubner         /* bit8-15  outbound queue number of SATA_NCQ event for PortId 1 */
2194e1bc9a0SAchim Leubner         /* bit16-23 outbound queue number of SATA_NCQ event for PortId 2 */
2204e1bc9a0SAchim Leubner         /* bit24-31 outbound queue number of SATA_NCQ event for PortId 3 */
2214e1bc9a0SAchim Leubner   bit32 outboundNCQEventPID4_7;             /**< outbound NCQ event for PortId 4 to 7 */
2224e1bc9a0SAchim Leubner         /* bit0-7   outbound queue number of SATA_NCQ event for PortId 4 */
2234e1bc9a0SAchim Leubner         /* bit8-15  outbound queue number of SATA_NCQ event for PortId 5 */
2244e1bc9a0SAchim Leubner         /* bit16-23 outbound queue number of SATA_NCQ event for PortId 6 */
2254e1bc9a0SAchim Leubner         /* bit24-31 outbound queue number of SATA_NCQ event for PortId 7 */
2264e1bc9a0SAchim Leubner   bit32 outboundTargetITNexusEventPID0_3;   /**< outbound target ITNexus Event for PortId 0 to 3 */
2274e1bc9a0SAchim Leubner         /* bit0-7   outbound queue number of ITNexus event for PortId 0 */
2284e1bc9a0SAchim Leubner         /* bit8-15  outbound queue number of ITNexus event for PortId 1 */
2294e1bc9a0SAchim Leubner         /* bit16-23 outbound queue number of ITNexus event for PortId 2 */
2304e1bc9a0SAchim Leubner         /* bit24-31 outbound queue number of ITNexus event for PortId 3 */
2314e1bc9a0SAchim Leubner   bit32 outboundTargetITNexusEventPID4_7;   /**< outbound target ITNexus Event for PortId 4 to 7 */
2324e1bc9a0SAchim Leubner         /* bit0-7   outbound queue number of ITNexus event for PortId 4 */
2334e1bc9a0SAchim Leubner         /* bit8-15  outbound queue number of ITNexus event for PortId 5 */
2344e1bc9a0SAchim Leubner         /* bit16-23 outbound queue number of ITNexus event for PortId 6 */
2354e1bc9a0SAchim Leubner         /* bit24-31 outbound queue number of ITNexus event for PortId 7 */
2364e1bc9a0SAchim Leubner   bit32 outboundTargetSSPEventPID0_3;       /**< outbound target SSP event for PordId 0 to 3 */
2374e1bc9a0SAchim Leubner         /* bit0-7   outbound queue number of SSP event for PortId 0 */
2384e1bc9a0SAchim Leubner         /* bit8-15  outbound queue number of SSP event for PortId 1 */
2394e1bc9a0SAchim Leubner         /* bit16-23 outbound queue number of SSP event for PortId 2 */
2404e1bc9a0SAchim Leubner         /* bit24-31 outbound queue number of SSP event for PortId 3 */
2414e1bc9a0SAchim Leubner   bit32 outboundTargetSSPEventPID4_7;       /**< outbound target SSP event for PordId 4 to 7 */
2424e1bc9a0SAchim Leubner         /* bit0-7   outbound queue number of SSP event for PortId 4 */
2434e1bc9a0SAchim Leubner         /* bit8-15  outbound queue number of SSP event for PortId 5 */
2444e1bc9a0SAchim Leubner         /* bit16-23 outbound queue number of SSP event for PortId 6 */
2454e1bc9a0SAchim Leubner         /* bit24-31 outbound queue number of SSP event for PortId 7 */
2464e1bc9a0SAchim Leubner   bit32 ioAbortDelay;   /* was reserved */                 /**< io Abort delay MPI_TABLE_CHANGE */
2474e1bc9a0SAchim Leubner   bit32 custset;                          /**< custset */
2484e1bc9a0SAchim Leubner   bit32 upperEventLogAddress;               /**< Upper physical MSGU Event log address */
2494e1bc9a0SAchim Leubner   bit32 lowerEventLogAddress;               /**< Lower physical MSGU Event log address */
2504e1bc9a0SAchim Leubner   bit32 eventLogSize;                       /**< Size of MSGU Event log, 0 means log disable */
2514e1bc9a0SAchim Leubner   bit32 eventLogOption;                     /**< Option of MSGU Event log */
2524e1bc9a0SAchim Leubner         /* bit3-0 log severity, 0x0 Disable Logging */
2534e1bc9a0SAchim Leubner         /*                      0x1 Critical Error */
2544e1bc9a0SAchim Leubner         /*                      0x2 Minor Error    */
2554e1bc9a0SAchim Leubner         /*                      0x3 Warning        */
2564e1bc9a0SAchim Leubner         /*                      0x4 Information    */
2574e1bc9a0SAchim Leubner         /*                      0x5 Debugging      */
2584e1bc9a0SAchim Leubner         /*                      0x6 - 0xF Reserved */
2594e1bc9a0SAchim Leubner   bit32 upperIOPeventLogAddress;           /**< Upper physical IOP Event log address */
2604e1bc9a0SAchim Leubner   bit32 lowerIOPeventLogAddress;           /**< Lower physical IOP Event log address */
2614e1bc9a0SAchim Leubner   bit32 IOPeventLogSize;                   /**< Size of IOP Event log, 0 means log disable */
2624e1bc9a0SAchim Leubner   bit32 IOPeventLogOption;                 /**< Option of IOP Event log */
2634e1bc9a0SAchim Leubner         /* bit3-0 log severity, 0x0 Disable Logging */
2644e1bc9a0SAchim Leubner         /*                      0x1 Critical Error */
2654e1bc9a0SAchim Leubner         /*                      0x2 Minor Error    */
2664e1bc9a0SAchim Leubner         /*                      0x3 Warning        */
2674e1bc9a0SAchim Leubner         /*                      0x4 Information    */
2684e1bc9a0SAchim Leubner         /*                      0x5 Debugging      */
2694e1bc9a0SAchim Leubner         /*                      0x6 - 0xF Reserved */
2704e1bc9a0SAchim Leubner   bit32 FatalErrorInterrupt;               /**< Fatal Error Interrupt enable and vector */
2714e1bc9a0SAchim Leubner         /* bit0     Fatal Error Interrupt Enable   */
2724e1bc9a0SAchim Leubner         /* bit1     PI/CI Address                  */
2734e1bc9a0SAchim Leubner         /* bit5     enable or disable outbound coalesce   */
2744e1bc9a0SAchim Leubner         /* bit7-6  reserved */
2754e1bc9a0SAchim Leubner         /* bit15-8  Fatal Error Interrupt Vector   */
2764e1bc9a0SAchim Leubner         /* bit31-16 Reserved                       */
2774e1bc9a0SAchim Leubner   bit32 FatalErrorDumpOffset0;             /**< Fatal Error Register Dump Offset for MSGU */
2784e1bc9a0SAchim Leubner   bit32 FatalErrorDumpLength0;             /**< Fatal Error Register Dump Length for MSGU */
2794e1bc9a0SAchim Leubner   bit32 FatalErrorDumpOffset1;             /**< Fatal Error Register Dump Offset for IOP */
2804e1bc9a0SAchim Leubner   bit32 FatalErrorDumpLength1;             /**< Fatal Error Register Dump Length for IOP */
2814e1bc9a0SAchim Leubner   bit32 HDAModeFlags;                      /**< HDA Mode Flags */
2824e1bc9a0SAchim Leubner         /* bit1-0   Bootstrap pins */
2834e1bc9a0SAchim Leubner         /* bit2     Force HDA Mode bit */
2844e1bc9a0SAchim Leubner         /* bit3     HDA Firmware load method */
2854e1bc9a0SAchim Leubner   bit32 analogSetupTblOffset;              /**< Phy Calibration Table offset */
2864e1bc9a0SAchim Leubner         /* bit23-0  phy calib table offset */
2874e1bc9a0SAchim Leubner         /* bit31-24 entry size */
2884e1bc9a0SAchim Leubner   bit32 InterruptVecTblOffset;             /**< DW23 Interrupt Vector Table */
2894e1bc9a0SAchim Leubner         /* bit23-0  interrupt vector table offset */
2904e1bc9a0SAchim Leubner         /* bit31-24 entry size */
2914e1bc9a0SAchim Leubner   bit32 phyAttributeTblOffset;             /**< DW24 SAS Phy Attribute Table Offset */
2924e1bc9a0SAchim Leubner         /* bit23-0  phy attribute table offset */
2934e1bc9a0SAchim Leubner         /* bit31-24 entry size */
2944e1bc9a0SAchim Leubner   bit32 PortRecoveryTimerPortResetTimer;  /**< DW25 Port Recovery Timer and Port Reset Timer */
2954e1bc9a0SAchim Leubner   bit32 InterruptReassertionDelay;        /**< DW26 Interrupt Reassertion Delay 0:23 Reserved 24:31 */
2964e1bc9a0SAchim Leubner };
2974e1bc9a0SAchim Leubner 
2984e1bc9a0SAchim Leubner typedef struct mpiHostLLConfigDescriptor_s mpiHostLLConfigDescriptor_t;
2994e1bc9a0SAchim Leubner 
3004e1bc9a0SAchim Leubner /*******************************************************************************/
3014e1bc9a0SAchim Leubner /** \struct mpiInboundQueueDescriptor_s
3024e1bc9a0SAchim Leubner  *  \brief MPI inbound queue attributes
3034e1bc9a0SAchim Leubner  *
3044e1bc9a0SAchim Leubner  * The mpiInboundQueueDescriptor_t structure is used to describe an inbound queue
3054e1bc9a0SAchim Leubner  * attributes
3064e1bc9a0SAchim Leubner  */
3074e1bc9a0SAchim Leubner /*******************************************************************************/
3084e1bc9a0SAchim Leubner struct mpiInboundQueueDescriptor_s
3094e1bc9a0SAchim Leubner {
3104e1bc9a0SAchim Leubner   bit32                     numElements;     /**< The total number of queue elements. A value 0 disables the queue */
3114e1bc9a0SAchim Leubner   bit32                     elementSize;     /**< The size of each queue element, in bytes */
3124e1bc9a0SAchim Leubner   bit32                     priority;        /**< The queue priority. Possible values for this field are */
3134e1bc9a0SAchim Leubner                                               /**< MPI_QUEUE_PRIORITY_HIGHEST and MPI_QUEUE_PRIORITY_LOWEST */
3144e1bc9a0SAchim Leubner   bit32                     PIPCIBar;        /**< PI PCIe Bar */
3154e1bc9a0SAchim Leubner   bit32                     PIOffset;        /**< PI PCI Bar Offset */
3164e1bc9a0SAchim Leubner   void*                     ciPointer;       /**< Pointer of CI (virtual Address) */
3174e1bc9a0SAchim Leubner };
3184e1bc9a0SAchim Leubner 
3194e1bc9a0SAchim Leubner typedef struct mpiInboundQueueDescriptor_s mpiInboundQueueDescriptor_t;
3204e1bc9a0SAchim Leubner 
3214e1bc9a0SAchim Leubner /*******************************************************************************/
3224e1bc9a0SAchim Leubner /** \struct mpiOutboundQueueDescriptor_s
3234e1bc9a0SAchim Leubner  *  \brief MPI outbound queue attributes
3244e1bc9a0SAchim Leubner  *
3254e1bc9a0SAchim Leubner  * The mpiOutboundQueueDescriptor_t structure is used to describe an outbound queue
3264e1bc9a0SAchim Leubner  * attributes
3274e1bc9a0SAchim Leubner  */
3284e1bc9a0SAchim Leubner /*******************************************************************************/
3294e1bc9a0SAchim Leubner struct mpiOutboundQueueDescriptor_s
3304e1bc9a0SAchim Leubner {
3314e1bc9a0SAchim Leubner   bit32                     numElements;        /**< The total number of queue elements. A value 0 disables the queue */
3324e1bc9a0SAchim Leubner   bit32                     elementSize;        /**< The size of each queue element, in bytes */
3334e1bc9a0SAchim Leubner   bit32                     interruptDelay;     /**< Delay in microseconds before the interrupt is asserted */
3344e1bc9a0SAchim Leubner                                                  /**< if the interrupt threshold has not been reached */
3354e1bc9a0SAchim Leubner   bit32                     interruptThreshold; /**< Number of interrupt events before the interrupt is asserted */
3364e1bc9a0SAchim Leubner                                                  /**< If set to 0, interrupts for this queue are disablec */
3374e1bc9a0SAchim Leubner   bit32                     interruptVector;    /**< Interrupt vector assigned to this queue */
3384e1bc9a0SAchim Leubner   bit32                     CIPCIBar;           /**< offset 0x14:PCI BAR for CI Offset */
3394e1bc9a0SAchim Leubner   bit32                     CIOffset;           /**< offset 0x18:Offset address for outbound queue CI */
3404e1bc9a0SAchim Leubner   bit32                     DIntTOffset;        /**< Dynamic Interrupt Coalescing Timeout offset */
3414e1bc9a0SAchim Leubner   bit32                     interruptEnable;    /**< Interrupt enable flag */
3424e1bc9a0SAchim Leubner   void*                     piPointer;          /**< pointer of PI (virtual address)*/
3434e1bc9a0SAchim Leubner };
3444e1bc9a0SAchim Leubner 
3454e1bc9a0SAchim Leubner typedef struct mpiOutboundQueueDescriptor_s mpiOutboundQueueDescriptor_t;
3464e1bc9a0SAchim Leubner 
3474e1bc9a0SAchim Leubner /*******************************************************************************/
3484e1bc9a0SAchim Leubner /** \struct mpiPhyCalibration_s
3494e1bc9a0SAchim Leubner  *  \brief MPI Phy Calibration Table
3504e1bc9a0SAchim Leubner  *
3514e1bc9a0SAchim Leubner  * The mpiPhyCalibration_s structure is used to set Phy Calibration
3524e1bc9a0SAchim Leubner  * attributes
3534e1bc9a0SAchim Leubner  */
3544e1bc9a0SAchim Leubner /*******************************************************************************/
3554e1bc9a0SAchim Leubner struct mpiPhyCalibration_s
3564e1bc9a0SAchim Leubner {
3574e1bc9a0SAchim Leubner   bit32   spaReg0;            /* transmitter per port configuration 1 SAS_SATA G1 */
3584e1bc9a0SAchim Leubner   bit32   spaReg1;            /* transmitter per port configuration 2 SAS_SATA G1*/
3594e1bc9a0SAchim Leubner   bit32   spaReg2;            /* transmitter per port configuration 3 SAS_SATA G1*/
3604e1bc9a0SAchim Leubner   bit32   spaReg3;            /* transmitter configuration 1 */
3614e1bc9a0SAchim Leubner   bit32   spaReg4;            /* reveiver per port configuration 1 SAS_SATA G1G2 */
3624e1bc9a0SAchim Leubner   bit32   spaReg5;            /* reveiver per port configuration 2 SAS_SATA G3 */
3634e1bc9a0SAchim Leubner   bit32   spaReg6;            /* reveiver per configuration 1 */
3644e1bc9a0SAchim Leubner   bit32   spaReg7;            /* reveiver per configuration 2 */
3654e1bc9a0SAchim Leubner   bit32   reserved[2];        /* reserved */
3664e1bc9a0SAchim Leubner };
3674e1bc9a0SAchim Leubner 
3684e1bc9a0SAchim Leubner typedef struct mpiPhyCalibration_s mpiPhyCalibration_t;
3694e1bc9a0SAchim Leubner 
3704e1bc9a0SAchim Leubner #define ANALOG_SETUP_ENTRY_NO              10
3714e1bc9a0SAchim Leubner #define ANALOG_SETUP_ENTRY_SIZE            10
3724e1bc9a0SAchim Leubner 
3734e1bc9a0SAchim Leubner 
3744e1bc9a0SAchim Leubner /*******************************************************************************/
3754e1bc9a0SAchim Leubner /** \struct mpiConfig_s
3764e1bc9a0SAchim Leubner  *  \brief MPI layer configuration parameters
3774e1bc9a0SAchim Leubner  *
3784e1bc9a0SAchim Leubner  * The mpiConfig_s structure is used as a parameter passed in
3794e1bc9a0SAchim Leubner  * mpiGetRequirements() and mpiInitialize() to describe the MPI software
3804e1bc9a0SAchim Leubner  * configuration
3814e1bc9a0SAchim Leubner  */
3824e1bc9a0SAchim Leubner /*******************************************************************************/
3834e1bc9a0SAchim Leubner struct mpiVConfig_s
3844e1bc9a0SAchim Leubner {
3854e1bc9a0SAchim Leubner   mpiHostLLConfigDescriptor_t  mainConfig;                              /**< main part of configuration table */
3864e1bc9a0SAchim Leubner   mpiInboundQueueDescriptor_t  inboundQueues[MPI_MAX_INBOUND_QUEUES];   /**< mpiQueueDescriptor structures that provide initialization */
3874e1bc9a0SAchim Leubner                                                                         /**< attributes for the inbound queues. The maximum number of */
3884e1bc9a0SAchim Leubner                                                                         /**< inbound queues is MPI_MAX_INBOUND_QUEUES */
3894e1bc9a0SAchim Leubner   mpiOutboundQueueDescriptor_t outboundQueues[MPI_MAX_OUTBOUND_QUEUES]; /**< mpiQueueDescriptor structures that provide initialization */
3904e1bc9a0SAchim Leubner                                                                         /**< attributes for the outbound queues. The maximum number of */
3914e1bc9a0SAchim Leubner                                                                         /**< inbound queues is MPI_MAX_OUTBOUND_QUEUES */
3924e1bc9a0SAchim Leubner   agsaPhyAnalogSetupTable_t    phyAnalogConfig;
3934e1bc9a0SAchim Leubner   mpiInterruptVT_t             interruptVTable;
3944e1bc9a0SAchim Leubner   sasPhyAttribute_t            phyAttributeTable;
3954e1bc9a0SAchim Leubner   bit16   numInboundQueues;
3964e1bc9a0SAchim Leubner   bit16   numOutboundQueues;
3974e1bc9a0SAchim Leubner   bit16   maxNumInboundQueues;
3984e1bc9a0SAchim Leubner   bit16   maxNumOutboundQueues;
3994e1bc9a0SAchim Leubner   bit32   queueOption;
4004e1bc9a0SAchim Leubner };
4014e1bc9a0SAchim Leubner 
4024e1bc9a0SAchim Leubner /*******************************************************************************/
4034e1bc9a0SAchim Leubner /** \struct mpiConfig_s
4044e1bc9a0SAchim Leubner  *  \brief MPI layer configuration parameters
4054e1bc9a0SAchim Leubner  *
4064e1bc9a0SAchim Leubner  * The mpiConfig_s structure is used as a parameter passed in
4074e1bc9a0SAchim Leubner  * mpiGetRequirements() and mpiInitialize() to describe the MPI software
4084e1bc9a0SAchim Leubner  * configuration
4094e1bc9a0SAchim Leubner  */
4104e1bc9a0SAchim Leubner /*******************************************************************************/
4114e1bc9a0SAchim Leubner struct mpiConfig_s
4124e1bc9a0SAchim Leubner {
4134e1bc9a0SAchim Leubner   mpiHostLLConfigDescriptor_t  mainConfig;                              /**< main part of configuration table */
4144e1bc9a0SAchim Leubner   mpiInboundQueueDescriptor_t  inboundQueues[MPI_MAX_INBOUND_QUEUES];   /**< mpiQueueDescriptor structures that provide initialization */
4154e1bc9a0SAchim Leubner                                                                         /**< attributes for the inbound queues. The maximum number of */
4164e1bc9a0SAchim Leubner                                                                         /**< inbound queues is MPI_MAX_INBOUND_QUEUES */
4174e1bc9a0SAchim Leubner   mpiOutboundQueueDescriptor_t outboundQueues[MPI_MAX_OUTBOUND_QUEUES]; /**< mpiQueueDescriptor structures that provide initialization */
4184e1bc9a0SAchim Leubner                                                                         /**< attributes for the outbound queues. The maximum number of */
4194e1bc9a0SAchim Leubner                                                                         /**< inbound queues is MPI_MAX_OUTBOUND_QUEUES */
4204e1bc9a0SAchim Leubner   agsaPhyAnalogSetupTable_t    phyAnalogConfig;
4214e1bc9a0SAchim Leubner   bit16   numInboundQueues;
4224e1bc9a0SAchim Leubner   bit16   numOutboundQueues;
4234e1bc9a0SAchim Leubner   bit16   maxNumInboundQueues;
4244e1bc9a0SAchim Leubner   bit16   maxNumOutboundQueues;
4254e1bc9a0SAchim Leubner   bit32   queueOption;
4264e1bc9a0SAchim Leubner };
4274e1bc9a0SAchim Leubner 
4284e1bc9a0SAchim Leubner typedef struct mpiConfig_s  mpiConfig_t;
4294e1bc9a0SAchim Leubner 
4304e1bc9a0SAchim Leubner #define TX_PORT_CFG1_OFFSET                0x00
4314e1bc9a0SAchim Leubner #define TX_PORT_CFG2_OFFSET                0x04
4324e1bc9a0SAchim Leubner #define TX_PORT_CFG3_OFFSET                0x08
4334e1bc9a0SAchim Leubner #define TX_CFG_OFFSET                      0x0c
4344e1bc9a0SAchim Leubner #define RV_PORT_CFG1_OFFSET                0x10
4354e1bc9a0SAchim Leubner #define RV_PORT_CFG2_OFFSET                0x14
4364e1bc9a0SAchim Leubner #define RV_CFG1_OFFSET                     0x18
4374e1bc9a0SAchim Leubner #define RV_CFG2_OFFSET                     0x1c
4384e1bc9a0SAchim Leubner 
4394e1bc9a0SAchim Leubner /*******************************************************************************/
4404e1bc9a0SAchim Leubner /*******************************************************************************/
4414e1bc9a0SAchim Leubner /* FUNCTIONS                                                                   */
4424e1bc9a0SAchim Leubner /*******************************************************************************/
4434e1bc9a0SAchim Leubner /*******************************************************************************/
4444e1bc9a0SAchim Leubner /*******************************************************************************/
4454e1bc9a0SAchim Leubner void      mpiRequirementsGet(mpiConfig_t *config, mpiMemReq_t *memoryRequirement);
4464e1bc9a0SAchim Leubner FORCEINLINE bit32 mpiMsgFreeGet(mpiICQueue_t *circularQ, bit16 messageSize, void** messagePtr);
4474e1bc9a0SAchim Leubner FORCEINLINE bit32 mpiMsgProduce(mpiICQueue_t *circularQ, void* messagePtr,
4484e1bc9a0SAchim Leubner                         mpiMsgCategory_t category, bit16 opCode,
4494e1bc9a0SAchim Leubner                         bit8 responseQueue, bit8 hiPriority);
4504e1bc9a0SAchim Leubner #ifdef LOOPBACK_MPI
4514e1bc9a0SAchim Leubner GLOBAL bit32 mpiMsgProduceOQ(mpiOCQueue_t *circularQ, void *messagePtr,
4524e1bc9a0SAchim Leubner                              mpiMsgCategory_t category, bit16 opCode,
4534e1bc9a0SAchim Leubner                              bit8 responseQueue, bit8 hiPriority);
4544e1bc9a0SAchim Leubner GLOBAL bit32 mpiMsgFreeGetOQ(mpiOCQueue_t *circularQ, bit16 messageSize,
4554e1bc9a0SAchim Leubner                              void** messagePtr);
4564e1bc9a0SAchim Leubner #endif
4574e1bc9a0SAchim Leubner 
4584e1bc9a0SAchim Leubner #ifdef FAST_IO_TEST
4594e1bc9a0SAchim Leubner bit32     mpiMsgPrepare(mpiICQueue_t *circularQ, void* messagePtr,
4604e1bc9a0SAchim Leubner                         mpiMsgCategory_t category, bit16 opCode,
4614e1bc9a0SAchim Leubner                         bit8 responseQueue, bit8 hiPriority);
4624e1bc9a0SAchim Leubner 
4634e1bc9a0SAchim Leubner bit32     mpiMsgProduceSend(mpiICQueue_t *circularQ, void* messagePtr,
4644e1bc9a0SAchim Leubner                         mpiMsgCategory_t category, bit16 opCode,
4654e1bc9a0SAchim Leubner                         bit8 responseQueue, bit8 hiPriority, int sendFl);
4664e1bc9a0SAchim Leubner GLOBAL void mpiIBQMsgSend(mpiICQueue_t *circularQ);
4674e1bc9a0SAchim Leubner #define INQ(queueNum) (bit8)(queueNum & MPI_IB_NUM_MASK)
4684e1bc9a0SAchim Leubner #define OUQ(queueNum) (bit8)((queueNum & MPI_OB_NUM_MASK) >> MPI_OB_SHIFT)
4694e1bc9a0SAchim Leubner #endif
4704e1bc9a0SAchim Leubner 
4714e1bc9a0SAchim Leubner FORCEINLINE bit32 mpiMsgConsume(mpiOCQueue_t *circularQ, void** messagePtr1, mpiMsgCategory_t *pCategory, bit16* pOpCode, bit8 *pBC);
4724e1bc9a0SAchim Leubner FORCEINLINE bit32 mpiMsgFreeSet(mpiOCQueue_t *circularQ, void* messagePtr1, bit8 bc);
4734e1bc9a0SAchim Leubner 
4744e1bc9a0SAchim Leubner #endif /* __MPI_H__ */
4754e1bc9a0SAchim Leubner 
476