1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * 22 *******************************************************************************/ 23 /****************************************************************************** 24 25 Module Name: 26 lxcommon.h 27 Abstract: 28 TISA Initiator/target driver module constant define header file 29 Environment: 30 Kernel or loadable module 31 32 ******************************************************************************/ 33 34 35 #include <dev/pms/RefTisa/tisa/api/titypes.h> 36 37 38 #define LINUX_DMA_MEM_MAX 0x1ffe0 /* 128k - 32, real 128k - 24 */ 39 #define DEK_MAX_TABLE_ITEMS DEK_MAX_TABLE_ENTRIES // from tisa/api/titypes.h 40 41 /* 42 ** IP address length based on character. 43 */ 44 #ifdef AGTIAPI_IP6_SUPPORT 45 # define IP_ADDR_CHAR_LEN 64 46 #else 47 # define IP_ADDR_CHAR_LEN 16 48 #endif 49 50 #define MSEC_PER_TICK (1000/hz) /* milisecond per tick */ 51 #define USEC_PER_TICK (1000000/hz) /* microsecond per tick */ 52 #define AGTIAPI_64BIT_ALIGN 8 /* 64 bit environment alignment */ 53 54 /* 55 ** Max device supported 56 */ 57 #define AGTIAPI_MAX_CARDS 4 /* card supported up to system limit */ 58 #define AGTIAPI_TOO_MANY_CARDS -1 /* beyond defined max support */ 59 #define AGTIAPI_MAX_PORTALS 16 /* max portal per card */ 60 /* max device per portal */ 61 62 /* 63 ** Adjustable Parameter Options 64 */ 65 #define AGTIAPI_OPTION_ON 1 /* adjustable parameter available */ 66 #define AGTIAPI_KEY_MAX 64 /* max number of keys */ 67 #define AGTIAPI_STRING_MAX 512 /* max length for string */ 68 #define AGTIAPI_PARAM_MAX 256 /* max number of parameters */ 69 #ifdef TARGET_DRIVER 70 #define AGTIAPI_DMA_MEM_LIST_MAX 4096 /* max number of DMA memory list */ 71 #define AGTIAPI_CACHE_MEM_LIST_MAX 24 /* max number of CACHE memory list */ 72 #else /* INITIATOR_DRIVER */ 73 #define AGTIAPI_DMA_MEM_LIST_MAX 1024 /* max number of DMA memory list */ 74 #define AGTIAPI_CACHE_MEM_LIST_MAX 1024 /* max number of CACHE memory list */ 75 #endif 76 #ifndef AGTIAPI_DYNAMIC_MAX 77 #define AGTIAPI_DYNAMIC_MAX 4096 /* max unreleased dynamic memory */ 78 #endif 79 #define AGTIAPI_LOOP_MAX 4 /* max loop for init process */ 80 81 #define AGTIAPI_MAX_NAME 70 // Max string name length 82 #define AGTIAPI_MIN_NAME 10 // minimum space for SAS name string 83 #define AGTIAPI_MAX_ID 8 // Max string id length 84 85 /* 86 ** Card-port status definitions 87 */ 88 #define AGTIAPI_INIT_TIME 0x00000001 89 #define AGTIAPI_SOFT_RESET 0x00000002 90 #define AGTIAPI_HAD_RESET 0x00000004 // ### 91 #define AGTIAPI_DISC_DONE 0x00000008 92 #define AGTIAPI_INSTALLED 0x00000010 93 #define AGTIAPI_RESET 0x00000020 94 #define AGTIAPI_FLAG_UP 0x00000040 95 #define AGTIAPI_CB_DONE 0x00000080 96 #define AGTIAPI_DISC_COMPLETE 0x00000100 97 #define AGTIAPI_IOREGION_REQUESTED 0x00000200 98 #define AGTIAPI_IRQ_REQUESTED 0x00000400 99 #define AGTIAPI_SCSI_REGISTERED 0x00000800 100 #define AGTIAPI_NAME_SERVER_UP 0x00001000 101 #define AGTIAPI_PORT_INITIALIZED 0x00002000 102 #define AGTIAPI_PORT_LINK_UP 0x00004000 103 #define AGTIAPI_LGN_LINK_UP 0x00008000 104 #define AGTIAPI_PORT_PANIC 0x00010000 105 #define AGTIAPI_RESET_SUCCESS 0x00020000 106 #define AGTIAPI_PORT_START 0x00040000 107 #define AGTIAPI_PORT_STOPPED 0x00080000 108 #define AGTIAPI_PORT_SHUTDOWN 0x00100000 109 #define AGTIAPI_IN_USE 0x00200000 110 #define AGTIAPI_SYS_INTR_ON 0x00400000 111 #define AGTIAPI_PORT_DISC_READY 0x00800000 112 #define AGTIAPI_SIG_DOWN 0x01000000 113 #define AGTIAPI_SIG_UP 0x02000000 114 #define AGTIAPI_TASK 0x04000000 115 #define AGTIAPI_INITIATOR 0x08000000 116 #define AGTIAPI_TARGET 0x10000000 117 #define AGTIAPI_TIMER_ON 0x20000000 118 #define AGTIAPI_SHUT_DOWN 0x40000000 119 /* reserved for ccb flag TASK_MANAGEMENT 120 #define AGTIAPI_RESERVED 0x80000000 121 */ 122 #define AGTIAPI_RESET_ALL 0xFFFFFFFF 123 124 /* 125 ** PCI defines 126 */ 127 #ifndef PCI_VENDOR_ID_HP 128 #define PCI_VENDOR_ID_HP 0x103c 129 #endif 130 131 #ifndef PCI_VENDOR_ID_PMC_SIERRA 132 #define PCI_VENDOR_ID_PMC_SIERRA 0x11F8 133 #endif 134 135 #ifndef PCI_VENDOR_ID_AGILENT 136 #define PCI_VENDOR_ID_AGILENT 0x15bc 137 #endif 138 139 #ifndef PCI_VENDOR_ID_CYCLONE 140 #define PCI_VENDOR_ID_CYCLONE 0x113C 141 #endif 142 143 #ifndef PCI_VENDOR_ID_SPCV_FPGA 144 #define PCI_VENDOR_ID_SPCV_FPGA 0x1855 145 #endif 146 147 #ifndef PCI_VENDOR_ID_HIALEAH 148 #define PCI_VENDOR_ID_HIALEAH 0x9005 149 #endif 150 151 #define PCI_DEVICE_ID_HP_TS 0x102a 152 #define PCI_DEVICE_ID_HP_TL 0x1028 153 #define PCI_DEVICE_ID_HP_XL2 0x1029 154 #define PCI_DEVICE_ID_AG_DX2 0x0100 155 #define PCI_DEVICE_ID_AG_DX2PLUS 0x0101 156 #define PCI_DEVICE_ID_AG_QX2 0x0102 157 #define PCI_DEVICE_ID_AG_QX4 0x0103 158 #define PCI_DEVICE_ID_AG_QE4 0x1200 159 #define PCI_DEVICE_ID_AG_DE4 0x1203 160 #define PCI_DEVICE_ID_AG_XL10 0x0104 161 #define PCI_DEVICE_ID_AG_DX4PLUS 0x0105 162 #define PCI_DEVICE_ID_AG_DIXL 0x0110 163 #define PCI_DEVICE_ID_AG_IDX1 0x050A 164 #define PCI_DEVICE_ID_PMC_SIERRA_SPC 0x8001 165 #define PCI_DEVICE_ID_PMC_SIERRA_SPCV 0x8008 166 #define PCI_DEVICE_ID_PMC_SIERRA_SPCVE 0x8009 167 #define PCI_DEVICE_ID_PMC_SIERRA_SPCVPLUS 0x8018 168 #define PCI_DEVICE_ID_PMC_SIERRA_SPCVE_16 0x8019 169 #define PCI_DEVICE_ID_SPCV_FPGA 0xabcd 170 #define PCI_DEVICE_ID_PMC_SIERRA_SPCV12G 0x8070 171 #define PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G 0x8071 172 #define PCI_DEVICE_ID_PMC_SIERRA_SPCV12G_16 0x8072 173 #define PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G_16 0x8073 174 #define PCI_DEVICE_ID_HIALEAH_HBA_SPC 0x8081 175 #define PCI_DEVICE_ID_HIALEAH_RAID_SPC 0x8091 176 #define PCI_DEVICE_ID_HIALEAH_HBA_SPCV 0x8088 177 #define PCI_DEVICE_ID_HIALEAH_RAID_SPCV 0x8098 178 #define PCI_DEVICE_ID_HIALEAH_HBA_SPCVE 0x8089 179 #define PCI_DEVICE_ID_HIALEAH_RAID_SPCVE 0x8099 180 #define PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCV 0x8074 181 #define PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCVE 0x8075 182 #define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV 0x8076 183 #define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCVE 0x8077 184 #define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV_SATA 0x8006 185 186 187 #define PCI_SUB_VENDOR_ID_HP PCI_VENDOR_ID_HP 188 #define PCI_SUB_VENDOR_ID_AG PCI_VENDOR_ID_AGILENT 189 #define PCI_SUB_VENDOR_ID_MASK 0xFFFF 190 #define PCI_SUB_SYSTEM_ID_AG 0x0001 191 #define PCI_BASE_MEM_MASK (~0x0F) 192 193 #define PCI_DEVICE_ID_CYCLONE 0xB555 194 #define PCI_ENABLE_VALUE 0x0157 195 #ifdef PMC_SPC 196 #define PCI_NUMBER_BARS 6 197 #endif 198 #define IOCTL_MN_GET_CARD_INFO 0x11 199 /* 200 ** Constant defines 201 */ 202 #define _08B 8 203 #define _16B 16 204 #define _24B 24 205 #define _32B 32 206 #define _64B 64 207 #define _128B 128 208 #define _256B 256 209 #define _512B 512 210 211 #define _1K 1024 212 #define _2K 2048 213 #define _4K 4096 214 #define _128K (128*(_1K)) 215 216 // Card property related info. 217 typedef struct _ag_card_id { 218 U16 vendorId; /* pci vendor id */ 219 U16 deviceId; /* pci device id */ 220 S32 cardNameIndex; /* structure index */ 221 U16 membar; /* pci memory bar offset */ 222 U16 iobar1; /* pci io bar 1 offset */ 223 U16 iobar2; /* pci io bar 2 offest */ 224 U16 reg; /* pci memory bar number */ 225 } ag_card_id_t; 226 227 228 #define PCI_BASE_ADDRESS_0 PCIR_BAR(0) 229 #define PCI_BASE_ADDRESS_1 PCIR_BAR(1) 230 #define PCI_BASE_ADDRESS_2 PCIR_BAR(2) 231 #define PCI_BASE_ADDRESS_3 PCIR_BAR(3) 232 #define PCI_BASE_ADDRESS_4 PCIR_BAR(4) 233 234 235 ag_card_id_t ag_card_type[] = { 236 #ifdef AGTIAPI_ISCSI 237 {PCI_VENDOR_ID_AGILENTj, PCI_DEVICE_ID_AG_DIXL, 1, 238 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_0, 0}, 239 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_IDX1, 2, 240 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_0, 0}, 241 #endif 242 #ifdef AGTIAPI_FC 243 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_TS, 3, 244 PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3}, 245 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_TL, 4, 246 PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3}, 247 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_XL2, 5, 248 PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3}, 249 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX2, 6, 250 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 251 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX2PLUS, 7, 252 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 253 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX4PLUS, 8, 254 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 255 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QX2, 9, 256 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 257 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QX4, 10, 258 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 259 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DE4, 11, 260 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 261 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QE4, 12, 262 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 263 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_XL10, 13, 264 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 265 #endif 266 #ifdef AGTIAPI_SA 267 #ifdef PMC_SPC 268 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPC, 14, 269 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 270 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV, 15, 271 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 272 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE, 16, 273 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 274 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVPLUS, 17, 275 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 276 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE_16, 18, 277 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 278 {PCI_VENDOR_ID_SPCV_FPGA, PCI_DEVICE_ID_SPCV_FPGA, 19, 279 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 280 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV12G, 20, 281 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 282 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G, 21, 283 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 284 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV12G_16, 22, 285 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 286 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G_16, 23, 287 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 288 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPC, 24, 289 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 290 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPC, 25, 291 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 292 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPCV, 26, 293 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 294 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPCV, 27, 295 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 296 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPCVE, 28, 297 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 298 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPCVE, 29, 299 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 300 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCV, 30, 301 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 302 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCVE, 31, 303 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 304 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV, 32, 305 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 306 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCVE, 33, 307 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 308 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV_SATA, 34, 309 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 310 311 #endif 312 #endif //AGTIAPI_SA 313 }; 314 315 static char const * const ag_card_names[] = { 316 "Unknown", 317 "iSCSI DiXL Card", 318 "iSCSI iDX1 Card", 319 "Tachyon TS Fibre Channel Card", 320 "Tachyon TL Fibre Channel Card", 321 "Tachyon XL2 Fibre Channel Card", 322 "Tachyon DX2 Fibre Channel Card", 323 "Tachyon DX2+ Fibre Channel Card", 324 "Tachyon DX4+ Fibre Channel Card", 325 "Tachyon QX2 Fibre Channel Card", 326 "Tachyon QX4 Fibre Channel Card", 327 "Tachyon DE4 Fibre Channel Card", 328 "Tachyon QE4 Fibre Channel Card", 329 "Tachyon XL10 Fibre Channel Card", 330 #ifdef AGTIAPI_SA 331 #ifdef PMC_SPC 332 "PMC Sierra SPC SAS-SATA Card", 333 "PMC Sierra SPC-V SAS-SATA Card", 334 "PMC Sierra SPC-VE SAS-SATA Card", 335 "PMC Sierra SPC-V 16 Port SAS-SATA Card", 336 "PMC Sierra SPC-VE 16 Port SAS-SATA Card", 337 "PMC Sierra FPGA", 338 "PMC Sierra SPC-V SAS-SATA Card 12Gig", 339 "PMC Sierra SPC-VE SAS-SATA Card 12Gig", 340 "PMC Sierra SPC-V 16 Port SAS-SATA Card 12Gig", 341 "PMC Sierra SPC-VE 16 Port SAS-SATA Card 12Gig", 342 "Adaptec Hialeah 4/8 Port SAS-SATA HBA Card 6Gig", 343 "Adaptec Hialeah 4/8 Port SAS-SATA RAID Card 6Gig", 344 "Adaptec Hialeah 8/16 Port SAS-SATA HBA Card 6Gig", 345 "Adaptec Hialeah 8/16 Port SAS-SATA RAID Card 6Gig", 346 "Adaptec Hialeah 8/16 Port SAS-SATA HBA Encryption Card 6Gig", 347 "Adaptec Hialeah 8/16 Port SAS-SATA RAID Encryption Card 6Gig", 348 "Adaptec Delray 8 Port SAS-SATA HBA Card 12Gig", 349 "Adaptec Delray 8 Port SAS-SATA HBA Encryption Card 12Gig", 350 "Adaptec Delray 16 Port SAS-SATA HBA Card 12Gig", 351 "Adaptec Delray 16 Port SAS-SATA HBA Encryption Card 12Gig", 352 "Adaptec SATA Adapter", 353 354 #endif 355 #endif 356 }; 357 358 359 360 /* 361 ** Resource Info Structure 362 */ 363 typedef struct _ag_resource_info { 364 tiLoLevelResource_t tiLoLevelResource; // Low level resource required 365 tiInitiatorResource_t tiInitiatorResource; // Initiator resource required 366 tiTargetResource_t tiTargetResource; // Target resource required 367 tiTdSharedMem_t tiSharedMem; // Shared memory by ti and td 368 } ag_resource_info_t; 369 370 371 // DMA memory address pair 372 typedef struct _ag_dma_addr { 373 void *dmaVirtAddr; 374 vm_paddr_t dmaPhysAddr; 375 U32 memSize; 376 bit32 type; 377 bus_addr_t nocache_busaddr; 378 void *nocache_mem; 379 } ag_dma_addr_t; 380 381 382 typedef struct _CardInfo 383 { 384 U32 pciIOAddrLow; /* PCI IOBASE lower */ 385 U32 pciIOAddrUp; /* PCI IOBASE Upper */ 386 U32_64 pciMemBase; /* PCI MEMBASE, physical */ 387 U32_64 pciMemBaseSpc[PCI_NUMBER_BARS]; // PCI MEMBASE, physical 388 U16 deviceId; // PCI device id 389 U16 vendorId; // PCI Vendor id 390 U32 busNum; 391 U32 deviceNum; 392 }CardInfo_t; 393 394 // Card info. for all cards and drivers 395 typedef struct _ag_card_info { 396 struct mtx pmIOLock; 397 device_t pPCIDev; // PCI device pointer 398 void *pCard; // pointer to per card data structure 399 S32 cardNameIndex; 400 U32 cardID; // card system ID 401 U32 cardIdIndex; 402 U32 pciIOAddrLow; // PCI IOBASE lower 403 U32 pciIOAddrUp; // PCI IOBASE Upper 404 U32_64 pciMemBase; // PCI MEMBASE, physical 405 caddr_t pciMemVirtAddr; // PCI MEMBASE, virtual ptr 406 U32 pciMemSize; // PCI MEMBASE memory size 407 #ifdef AGTIAPI_SA 408 #ifdef FPGA_CARD 409 U32_64 pciMemBase0; // PCI MEMBASE, physical 410 caddr_t pciMemVirtAddr0; // PCI MEMBASE, virtual ptr 411 U32 pciMemSize0; // PCI MEMBASE memory size 412 #endif 413 #ifdef PMC_SPC 414 struct resource *pciMemBaseRscSpc[PCI_NUMBER_BARS]; 415 int pciMemBaseRIDSpc[PCI_NUMBER_BARS]; 416 U32_64 pciMemBaseSpc[PCI_NUMBER_BARS]; // PCI MEMBASE, physical 417 caddr_t pciMemVirtAddrSpc[PCI_NUMBER_BARS];//PCI MEMBASE, virt ptr 418 U32 pciMemSizeSpc[PCI_NUMBER_BARS]; // PCI MEMBASE memory size 419 #endif 420 #endif 421 U16 memBar; 422 U16 memReg; 423 U32 cacheIndex; 424 U32 dmaIndex; 425 ag_dma_addr_t tiDmaMem[AGTIAPI_DMA_MEM_LIST_MAX]; // dma addr list 426 427 // all (free and allocated) mem slots 428 ag_dma_addr_t dynamicMem[AGTIAPI_DYNAMIC_MAX]; 429 430 // ptr to free mem slots 431 ag_dma_addr_t *freeDynamicMem[AGTIAPI_DYNAMIC_MAX]; 432 433 U16 topOfFreeDynamicMem; // idx to the first free slot ptr 434 435 void *tiCachedMem[AGTIAPI_CACHE_MEM_LIST_MAX];// cached mem list 436 ag_resource_info_t tiRscInfo; /* low level resource requirement */ 437 U08 WWN[AGTIAPI_MAX_NAME]; /* WWN for this card */ 438 U08 WWNLen; 439 440 // #define MAX_MSIX_NUM_VECTOR 64 ## 441 #define MAX_MSIX_NUM_VECTOR 16 // 1 then 16 just for testing; 442 #define MAX_MSIX_NUM_DPC 64 // 16 443 #define MAX_MSIX_NUM_ISR 64 // 16 444 #ifdef SPC_MSIX_INTR 445 446 // ## use as a map instead of presirq 447 struct resource *msix_entries[MAX_MSIX_NUM_VECTOR]; 448 #endif 449 U32 maxInterruptVectors; 450 } ag_card_info_t; 451 452 /* 453 ** Optional Adjustable Parameters Structures. 454 ** Not using pointer structure for easy read and access tree structure. 455 ** In the future if more layer of key tree involved, it might be a good 456 ** idea to change the structure and program. 457 */ 458 typedef struct _ag_param_value{ 459 char valueName[AGTIAPI_MAX_NAME]; 460 char valueString[AGTIAPI_STRING_MAX]; 461 struct _ag_param_value *next; 462 } ag_value_t; 463 464 typedef struct _ag_param_key{ 465 char keyName[AGTIAPI_MAX_NAME]; 466 ag_value_t *pValueHead; 467 ag_value_t *pValueTail; 468 struct _ag_param_key *pSubkeyHead; 469 struct _ag_param_key *pSubkeyTail; 470 struct _ag_param_key *next; 471 } ag_key_t; 472 473 /* 474 ** Portal info data structure 475 */ 476 typedef struct _ag_portal_info { 477 U32 portID; 478 U32 portStatus; 479 U32 devTotal; 480 U32 devPrev; 481 tiPortInfo_t tiPortInfo; 482 tiPortalContext_t tiPortalContext; 483 #ifdef INITIATOR_DRIVER 484 void *pDevList[AGTIAPI_HW_LIMIT_DEVICE]; 485 #endif 486 } ag_portal_info_t; 487 488 #define MAP_TABLE_ENTRY(pC, c, d, l) (pC->encrypt_map + \ 489 (c * pC->devDiscover * AGTIAPI_MAX_LUN) + \ 490 (d * AGTIAPI_MAX_LUN) + \ 491 (l)) 492 493 #ifdef CHAR_DEVICE 494 /************************************************************************* 495 Purpose: Payload Wraper for ioctl commands 496 ***********************************************************************/ 497 typedef struct datatosendt{ 498 bit32 datasize; //buffer size 499 bit8 *data; //buffer 500 }datatosend; 501 /***********************************************************************/ 502 #define AGTIAPI_IOCTL_BASE 'x' 503 #define AGTIAPI_IOCTL _IOWR(AGTIAPI_IOCTL_BASE, 0,datatosend ) //receiving payload here// 504 #define AGTIAPI_IOCTL_MAX 1 505 #endif 506 507 #ifdef AGTIAPI_FLOW_DEBUG 508 #define AGTIAPI_FLOW(format, a...) printf(format, ## a) 509 #else 510 #define AGTIAPI_FLOW(format, a...) 511 #endif 512 513 #ifdef AGTIAPI_DEBUG 514 #define AGTIAPI_PRINTK(format, a...) printf(format, ## a) 515 #else 516 #define AGTIAPI_PRINTK(format, a...) 517 #endif 518 519 #ifdef AGTIAPI_INIT_DEBUG 520 #define AGTIAPI_INIT(format, a...) printf(format, ## a) 521 /* to avoid losing the logs */ 522 #define AGTIAPI_INIT_MDELAY(dly) mdelay(dly) 523 #else 524 #define AGTIAPI_INIT(format, a...) 525 #define AGTIAPI_INIT_MDELAY(dly) 526 #endif 527 528 #ifdef AGTIAPI_INIT2_DEBUG 529 #define AGTIAPI_INIT2(format, a...) printf(format, ## a) 530 #else 531 #define AGTIAPI_INIT2(format, a...) 532 #endif 533 534 #ifdef AGTIAPI_INIT_MEM_DEBUG 535 #define AGTIAPI_INITMEM(format, a...) printf(format, ## a) 536 #else 537 #define AGTIAPI_INITMEM(format, a...) 538 #endif 539 540 #ifdef AGTIAPI_IO_DEBUG 541 #define AGTIAPI_IO(format, a...) printf(format, ## a) 542 #else 543 #define AGTIAPI_IO(format, a...) 544 #endif 545 546 #ifdef AGTIAPI_LOAD_DELAY 547 #define AGTIAPI_INIT_DELAY(delay_time) \ 548 { \ 549 agtiapi_DelayMSec(delay_time); \ 550 } 551 #else 552 #define AGTIAPI_INIT_DELAY(delay_time) 553 #endif 554 555 /* 556 * AGTIAPI_KDB() will be used to drop into kernel debugger 557 * from driver code if kdb is involved. 558 */ 559 #ifdef AGTIAPI_KDB_ENABLE 560 #define AGTIAPI_KDB() KDB_ENTER() 561 #else 562 #define AGTIAPI_KDB() 563 #endif 564 565 #if (BITS_PER_LONG == 64) 566 //#if 1 567 #define LOW_32_BITS(addr) (U32)(addr & 0xffffffff) 568 #define HIGH_32_BITS(addr) (U32)((addr >> 32) & 0xffffffff) 569 #else 570 #define LOW_32_BITS(addr) (U32)addr 571 #define HIGH_32_BITS(addr) 0 572 #endif 573 574 #define AG_SWAP16(data) (((data<<8) & 0xFF00) | (data>>8)) 575 #define AG_SWAP24(data) (((data<<16) & 0xFF0000) | \ 576 ((data>>16) & 0xFF) | (data & 0xFF00)) 577 #define AG_SWAP32(data) ((data<<24) | ((data<<8) & 0xFF0000) | \ 578 ((data>>8) & 0xFF00) | (data>>24)) 579 580 #define AG_PCI_DEV_INFO(pdev) ( \ 581 AGTIAPI_PRINTK("vendor id 0x%x device id 0x%x, slot %d, function %d\n", \ 582 pdev->vendor, pdev->device, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)) \ 583 ) 584 585 #define COUNT(arr) (sizeof(arr) / sizeof(arr[0])) 586 587 #define PORTAL_CONTEXT_TO_PORTALDATA(pPortalContext) \ 588 ((ag_portal_data_t *)(((tiPortalContext_t *)pPortalContext)->osData)) 589 #define PORTAL_STATUS(pPortalData) (pPortalData->portalInfo.portStatus) 590 591 #if (defined(DEFINE_OSTI_PORT_EVENT_IN_IBE)) || \ 592 (defined(DEFINE_OSTI_PORT_EVENT_IN_TFE)) 593 #define TIROOT_TO_CARD(ptiRoot) \ 594 ((ag_card_t *)(((appRoot_t *)(ptiRoot->osData))->oscData)) 595 #define TIROOT_TO_CARDINFO(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->pCardInfo) 596 #define TIROOT_TO_PCIDEV(ptiRoot) (TIROOT_TO_CARDINFO(ptiRoot)->pPCIDev) 597 #else 598 599 #define TIROOT_TO_CARD(ptiRoot) ((struct agtiapi_softc *)(ptiRoot->osData)) 600 #define TIROOT_TO_CARDINFO(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->pCardInfo) 601 #define TIROOT_TO_PCIDEV(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->my_dev) 602 603 #endif 604 605 606 #define Is_ADP7H(pmsc) ((0x90058088 == (pmsc->VidDid))?1:\ 607 (0x90058089 == (pmsc->VidDid))?1:0) 608 #define Is_ADP8H(pmsc) ((0x90058074 == (pmsc->VidDid))?1:\ 609 (0x90058076 == (pmsc->VidDid))?1:0) 610 611 612 #define __cacheline_aligned __attribute__((__aligned__(CACHE_LINE_SIZE))) 613 614 /* 615 ** link data, need to be included at the start (offset 0) 616 ** of any structures that are to be stored in the link list 617 */ 618 typedef struct _LINK_NODE 619 { 620 struct _LINK_NODE *pNext; 621 struct _LINK_NODE *pPrev; 622 623 /* 624 ** for assertion purpose only 625 */ 626 struct _LINK_NODE * pHead; // track the link list the link is a member of 627 void * pad; 628 629 } LINK_NODE, * PLINK_NODE __cacheline_aligned; 630 631 632 /* 633 ** link list basic pointers 634 */ 635 typedef struct _LINK_LIST 636 { 637 PLINK_NODE pHead; 638 bit32 Count; 639 LINK_NODE Head __cacheline_aligned; // always one link to speed up insert&rm 640 } LINK_LIST, * PLINK_LIST __cacheline_aligned; 641 642 643 /******************************************************************** 644 ** MACROS 645 ********************************************************************/ 646 /******************************************************************************* 647 ** 648 ** MODULE NAME: comListInitialize 649 ** 650 ** PURPOSE: Initialize a link list. 651 ** 652 ** PARAMETERS: PLINK_LIST OUT - Link list definition. 653 ** 654 ** SIDE EFFECTS & CAVEATS: 655 ** 656 ** ALGORITHM: 657 ** 658 *******************************************************************************/ 659 #define comListInitialize(pList) {(pList)->pHead = &((pList)->Head); \ 660 (pList)->pHead->pNext = (pList)->pHead; \ 661 (pList)->pHead->pPrev = (pList)->pHead; \ 662 (pList)->Count = 0; \ 663 } 664 665 /******************************************************************************* 666 ** 667 ** MODULE NAME: comLinkInitialize 668 ** 669 ** PURPOSE: Initialize a link. 670 ** This function should be used to initialize a new link before it 671 ** is used in the linked list. This will initialize the link so 672 ** the assertion will work 673 ** 674 ** PARAMETERS: PLINK_NODE IN - Link to be initialized. 675 ** 676 ** SIDE EFFECTS & CAVEATS: 677 ** 678 ** ALGORITHM: 679 ** 680 *******************************************************************************/ 681 682 #define comLinkInitialize(pLink) { (pLink)->pHead = NULL; \ 683 (pLink)->pNext = NULL; \ 684 (pLink)->pPrev = NULL; \ 685 } 686 687 /******************************************************************************* 688 ** 689 ** MODULE NAME: comListAdd 690 ** 691 ** PURPOSE: add a link at the tail of the list 692 ** 693 ** PARAMETERS: PLINK_LIST OUT - Link list definition. 694 ** PLINK_NODE IN - Link to be inserted. 695 ** 696 ** SIDE EFFECTS & CAVEATS: 697 ** !!! assumes that fcllistInitialize has been called on the linklist 698 ** !!! if not, this function behavior is un-predictable 699 ** 700 ** ALGORITHM: 701 ** 702 *******************************************************************************/ 703 #define comListAdd(pList, pLink) { \ 704 (pLink)->pNext = (pList)->pHead; \ 705 (pLink)->pPrev = (pList)->pHead->pPrev; \ 706 (pLink)->pPrev->pNext = (pLink); \ 707 (pList)->pHead->pPrev = (pLink); \ 708 (pList)->Count ++; \ 709 (pLink)->pHead = (pList)->pHead; \ 710 } 711 712 /******************************************************************************* 713 ** 714 ** MODULE NAME: comListInsert 715 ** 716 ** PURPOSE: insert a link preceding the given one 717 ** 718 ** PARAMETERS: PLINK_LIST OUT - Link list definition. 719 ** PLINK_NODE IN - Link to be inserted after. 720 ** PLINK_NODE IN - Link to be inserted. 721 ** 722 ** SIDE EFFECTS & CAVEATS: 723 ** !!! assumes that fcllistInitialize has been called on the linklist 724 ** !!! if not, this function behavior is un-predictable 725 ** 726 ** ALGORITHM: 727 ** 728 *******************************************************************************/ 729 730 #define comListInsert(pList, pLink, pNew) { \ 731 (pNew)->pNext = (pLink); \ 732 (pNew)->pPrev = (pLink)->pPrev; \ 733 (pNew)->pPrev->pNext = (pNew); \ 734 (pLink)->pPrev = (pNew); \ 735 (pList)->Count ++; \ 736 (pNew)->pHead = (pList)->pHead; \ 737 } 738 739 /******************************************************************************* 740 ** 741 ** MODULE NAME: comListRemove 742 ** 743 ** PURPOSE: remove the link from the list. 744 ** 745 ** PARAMETERS: PLINK_LIST OUT - Link list definition. 746 ** PLINK_NODE IN - Link to delet from list 747 ** 748 ** SIDE EFFECTS & CAVEATS: 749 ** !!! assumes that fcllistInitialize has been called on the linklist 750 ** !!! if not, this function behavior is un-predictable 751 ** 752 ** !!! No validation is made on the list or the validity of the link 753 ** !!! the caller must make sure that the link is in the list 754 ** 755 ** 756 ** ALGORITHM: 757 ** 758 *******************************************************************************/ 759 #define comListRemove(pList, pLink) { \ 760 (pLink)->pPrev->pNext = (pLink)->pNext; \ 761 (pLink)->pNext->pPrev = (pLink)->pPrev; \ 762 (pLink)->pHead = NULL; \ 763 (pList)->Count --; \ 764 } 765 766 /******************************************************************************* 767 ** 768 ** MODULE NAME: comListGetHead 769 ** 770 ** PURPOSE: get the link following the head link. 771 ** 772 ** PARAMETERS: PLINK_LIST OUT - Link list definition. 773 ** RETURNS - PLINK_NODE the link following the head 774 ** NULL if the following link is the head 775 ** 776 ** SIDE EFFECTS & CAVEATS: 777 ** !!! assumes that fcllistInitialize has been called on the linklist 778 ** !!! if not, this function behavior is un-predictable 779 ** 780 ** ALGORITHM: 781 ** 782 *******************************************************************************/ 783 #define comListGetHead(pList) comListGetNext(pList,(pList)->pHead) 784 785 /******************************************************************************* 786 ** 787 ** MODULE NAME: comListGetTail 788 ** 789 ** PURPOSE: get the link preceding the tail link. 790 ** 791 ** PARAMETERS: PLINK_LIST OUT - Link list definition. 792 ** RETURNS - PLINK_NODE the link preceding the head 793 ** NULL if the preceding link is the head 794 ** 795 ** SIDE EFFECTS & CAVEATS: 796 ** 797 ** ALGORITHM: 798 ** 799 *******************************************************************************/ 800 #define comListGetTail(pList) comListGetPrev((pList), (pList)->pHead) 801 802 /******************************************************************************* 803 ** 804 ** MODULE NAME: comListGetCount 805 ** 806 ** PURPOSE: get the number of links in the list excluding head and tail. 807 ** 808 ** PARAMETERS: LINK_LIST OUT - Link list definition. 809 ** 810 ** SIDE EFFECTS & CAVEATS: 811 ** !!! assumes that fcllistInitialize has been called on the linklist 812 ** !!! if not, this function behavior is un-predictable 813 ** 814 ** ALGORITHM: 815 ** 816 *******************************************************************************/ 817 818 #define comListGetCount(pList) ((pList)->Count) 819 820 821 822 /******************************************************************************* 823 ** 824 ** MODULE NAME: comListGetNext 825 ** 826 ** PURPOSE: get the next link in the list. (one toward tail) 827 ** 828 ** PARAMETERS: PLINK_LIST OUT - Link list definition. 829 ** PLINK_NODE IN - Link to get next to 830 ** 831 ** return PLINK - points to next link 832 ** NULL if next link is head 833 ** 834 ** SIDE EFFECTS & CAVEATS: 835 ** !!! assumes that fcllistInitialize has been called on the linklist 836 ** !!! if not, this function behavior is un-predictable 837 ** 838 ** !!! No validation is made on the list or the validity of the link 839 ** !!! the caller must make sure that the link is in the list 840 ** 841 ** ALGORITHM: 842 ** 843 *******************************************************************************/ 844 845 #define comListGetNext(pList, pLink) (((pLink)->pNext == (pList)->pHead) ? \ 846 NULL : (pLink)->pNext) 847 848 849 /******************************************************************************* 850 ** 851 ** MODULE NAME: comListGetPrev 852 ** 853 ** PURPOSE: get the previous link in the list. (one toward head) 854 ** 855 ** PARAMETERS: PLINK_LIST OUT - Link list definition. 856 ** PLINK_NODE IN - Link to get prev to 857 ** 858 ** return PLINK - points to previous link 859 ** NULL if previous link is head 860 ** 861 ** SIDE EFFECTS & CAVEATS: 862 ** !!! assumes that fcllistInitialize has been called on the linklist 863 ** !!! if not, this function behavior is un-predictable 864 ** 865 ** !!! No validation is made on the list or the validity of the link 866 ** !!! the caller must make sure that the link is in the list 867 ** 868 ** ALGORITHM: 869 ** 870 *******************************************************************************/ 871 872 /*lint -emacro(613,fiLlistGetPrev) */ 873 874 #define comListGetPrev(pList, pLink) (((pLink)->pPrev == (pList)->pHead) ? \ 875 NULL : (pLink)->pPrev) 876 877 #define AGT_INTERRUPT IRQF_DISABLED 878 #define AGT_SAMPLE_RANDOM IRQF_SAMPLE_RANDOM 879 #define AGT_SHIRQ IRQF_SHARED 880 #define AGT_PROBEIRQ IRQF_PROBE_SHARED 881 #define AGT_PERCPU IRQF_PERCPU 882 883 884 #include "lxproto.h" 885 886